JP2553638B2 - Packet switching self-routing module - Google Patents

Description

The present invention relates to a packet switching self-routing module that is a basic unit switch of a self-routing switch that exchanges fixed-length packet information that is asynchronously transferred by packet header drive, and writes packet data to a queue buffer. / The purpose is to provide a packet switching self-routing module that reduces the number of queue buffers by enabling time-division access for read and at the same time eliminates the need for a contention arbitration circuit. In the routing module, phase adjusting means for synchronizing fixed-length packets input from a plurality of incoming paths, and one packet for each of the plurality of incoming paths, which is synchronized by the phase adjusting means, is converted into a parallel signal. And serial-parallel conversion means for time-division multiplexing the parallel signals, and Storage means for storing the packet group, which is divided and multiplexed, in the output corresponding area of each packet, and parallel signals corresponding to each of the packet groups stored in the storage means are read in a time division multiplex format to parallelize the packet groups. Parallel-serial conversion means for performing serial conversion and outputting to the output path, control means for controlling writing of packets from the serial-parallel conversion means to the storage means, and reading of packets from the storage means to the parallel-serial conversion means. Configure to prepare.

[Industrial applications]

The present invention relates to a packet switching system in a communication network for transferring packet type information, and more specifically, to a packet switching self-switch which is a basic unit switch of a self-routing switch for switching fixed length packet information transferred asynchronously by packet header drive. Regarding routing module.

Packet switching for effective use of communication lines in wide area networks is currently used in a wide range of fields. In a packet switching network, for example, packets from a sending terminal are temporarily stored in a temporary storage memory called a packet buffer and then distributed to receiving terminals. However, this memory switching requires time, and high-speed switching is not possible. Not suitable.

The self-routing method is suitable for high-speed packet switching. In this method, a correspondence table of the identification number (VCN) of each call and its outgoing line is created, and when a certain identification number arrives, the call is sent to the outgoing line designated by the corresponding table.

[Conventional technology]

FIG. 9 shows a conventional example of a self-routing module exchange in the above packet exchange system. In the figure, the main body of the exchange is a multi-stage self-routing network (MSR) in which a plurality of basic unit switches 1 called self-routing module (SRM) are connected.
N) 2. The figure shows the case where the number of switch stages is 2, but the basic operation principle is the same even when the number of stages is increased.

On the input highway 3 indicating an actual physical line, for example, as shown in FIG. 9, a packet data group to be transmitted from the same subscriber to different destinations has a virtual channel number (VC
N) is input to the virtual channel number converter VCC (VCN converter) 4 in a format in which each packet is added as a header. VCN converter (VCC) 4 is call processing 5
Control the virtual channel number of the packet data to VC.
Replace with N ', TA as data path information in MSRN2
Causes the packet to enter MSRN2 with G information. The reason why the virtual channel number (also called the logical link number) VCN is changed here is to reduce the number of bits of the packet header on the highway.

The packet data input to the self-routing module (SRM) 1 at the first stage is stored in the queue buffer memory 7 via the contention arbitration circuit 6 according to the route indicated by the TAG information, and then again through the contention arbitration circuit 6 to the next stage. Sent to SRM1. In the SRM 1 at the next stage, the packet data is also output to the output highway 8 connected to the partner terminal via the path according to the TAG information. The TAG information is used for routing in MSRN2 and is not output to the output highway 8.

As described above, the call processing 5 holds a correspondence table of outgoing lines for the VCN which is the identification number of each call.
At the same time that CN 'is created, the data path within MSRN2 is determined T
Generates AG information and controls VCC4. Further, the signal processing 9 receives the route information for the virtual channel number VCN of the packet data on the input highway 3 from the calling terminal by the outslot signaling 10 and outputs it to the call processing 5.

[Problems to be Solved by the Invention]

When exchanging fixed-length packets asynchronously transferred by the self-routing exchange as shown in FIG. 9,
Queue buffer for waiting in case of packet collision (Queue FIF
O) is required in large numbers. That is, in FIG. 9, a queue buffer 7 is provided for each basic unit switch, that is, for each cross point in the self routing module (SRM) 1. The optimal number of queue buffers installed to prevent packet loss is the number of switch ingress (n) × outgoing number (m). Further, each queue buffer 7 needs to operate independently of each other to accommodate packet data transferred asynchronously. Therefore, as the number of switch terminals increases, the required number of queue buffers rapidly increases, causing a problem of hardware enlargement.

Further, in the method of FIG. 9, for example, when the packet data is taken out from the queue buffer 7 and sent to the outgoing route, the contention arbitration circuit 6 between the plurality of queue buffers is required. As the processing speed increases and the scale increases, the contention arbitration circuit 6 becomes complicated and the control becomes difficult.

In view of the above problems, the present invention reduces the number of queue buffers by enabling time division access for writing / reading packet data to / from the queue buffer, and at the same time eliminates the need for a contention arbitration circuit. It is to provide a packet switching self-routing module.

[Means for solving the problem]

FIG. 1 is a block diagram of the principle of the present invention. In the figure, the phase adjusting means 11 synchronizes fixed length packets input from a plurality of incoming paths with a predetermined internal phase. The serial-parallel converter 12 serial-parallel converts one packet for each incoming path synchronized by the phase adjuster 11, and time-division multiplexes. The storage unit 13 is, for example, the queue buffer 7, classifies the time-division-multiplexed packet group according to the outgoing route of each packet, and stores it in the area corresponding to the outgoing route.
The parallel-serial conversion means 14 reads the data stored in the storage means 13 in a time division multiplexed format, parallel-serial converts the data, and outputs the data to the output path. The control means 15 is the storage means 13
Control the writing and reading of data to and from.

[Action]

In FIG. 1, fixed length packets input from each of a plurality of ingress routes to the self-routing module (SRM) 1 are synchronized with the internal phase of the SRM 1 by the phase adjusting means 11. Synchronized packets, one for each ingress, serial-parallel conversion means 12
Thus, for example, time division multiplexing is performed within a time equal to the fixed packet length. Storage means for time division multiplexed packet information
The data path information, that is, the TAG information, is stored inside the area 13 corresponding to the route from the SRM 1. The data write in this case is controlled by the control means 15. The data stored in the storage means 13 is read in a time division multiplexed format under the control of the control means 15, and the parallel / serial conversion means 14 is read.
Is output to the output route designated by the TAG information. Here, since the time-division multiplexing of data by the serial-parallel conversion means 12, the data write and read to the storage means 13, and the conversion by the parallel-serial conversion means 14 are all completed within that time with a fixed packet length as a time unit. , There is no problem in the switching process of the packets input one after another.

As described above, according to the present invention, it is possible to perform time division multiple access to the queue buffer that temporarily stores the packet information.

〔Example〕

FIG. 2 shows the overall structure of the speech path switch including the self-routing module SRM of the present invention. The figure shows the case where the number of switch stages is 3, and the basic operation principle does not change even if the number of stages increases. Note that 16 to 21 in the figure are basic unit switches, that is, SRMs, and have the same configuration. 22 and 23 are synchronization and virtual channel number (VCN) of packets input asynchronously from multiple packet input lines 24 and 25 (input highway 3)
Line interface unit (LIF) for changing over
The head position indicating signal lines 26 and 27 indicating the head position of the packet are also input to these. However, if the head position can be detected from the packet itself, the signal lines 26 and 27 do not exist. The line interface units (LIF) 22 and 23 are connected to the self-routing module, and the self-routing modules are connected by packet relay lines 28 to 33 and routing (TAG) information relay lines 34 to 39. Also, the exchanged packet information is output from the packet output lines 40 and 41 of the SRMs 20 and 21 at the final stage.

FIG. 3 is a schematic block diagram of the line interface unit (LIF). The figure shows the LIF 22 shown in FIG. 2, which is composed of a phase synchronization section 42, a header conversion section 43, and an interface line 44 connecting them.

In FIG. 3, a packet serially transferred at an arbitrary time phase flows into each input line 24. In the phase synchronization unit 42, each packet is placed on a time slot (time position) that matches a predetermined internal phase. The time slot length is set to accommodate one packet. The synchronized packet is input to the header conversion unit 43 through the interface line 44. The header conversion unit 43 uses the virtual channel number (VC
N) is converted into a new VCN 'and this packet information is sent out from the packet relay line 28. At the same time, the above-mentioned VCN is translated into routing information (TAG) in SRM, and this is sent to the routing information relay line 34 in synchronization with the packet information. At this time, between the packet relay lines 28 and the routing information relay line
The time slot phase between 34 is the same.

The above operation timings are shown in (a) to (c) of the time chart of FIG. As shown in FIG. 4A, the packets L10, L20, and LN0 (VCN) from each packet input line 24 are asynchronously input. These are synchronized by the phase synchronizer 42 and placed on the same time slot by the interface line 44 as shown in FIG. These packets have their VCNs converted into L11, L21, ... LN1 by the header conversion unit 43 and output from the packet relay line 28 as shown in FIG. Routing (TAG) information for each packet at the same time
R1, R2, ..., RN are also output from the routing information relay line 34.

FIG. 5 is a schematic block diagram of the self-routing module (SRM). In the figure, the information on the packet relay line 28 and the routing information relay line 34 is synchronized by the phase adjustment circuits 450 and 460 in the same manner as in the line interface unit 22 in order to cancel the phase difference due to the difference in transmission distance. After that, serial / parallel conversion is performed by the serial / parallel conversion circuits 45 and 46, respectively, and time division multiplexing is performed. Here, the packet is time-division multiplexed in the first half of the time slot that matches the fixed packet length, as shown in FIG. 4 (d), and is output to the parallel packet information input line 47.

On the other hand, of the parallelized routing information,
Only the portion 48 used in SRM is separated and input to the buffer control circuit 49. That is, the routing information includes
As shown in FIG. 6, valid / invalid of corresponding packet data
The flag indicating invalidity and the output path number in each stage SRM are accommodated for the number of stages. Here, the output route number of the first stage SRM is input to the buffer control circuit 49. The remaining portion 50 of the routing information is stored in the routing information buffer memory 51 for use in subsequent stages.

The packet information is stored in the packet buffer memory 52 via the parallel packet information input line 47. The internal areas of the two buffer memories 51 and 52 are divided and used according to the outgoing route of the SRM. The buffer control circuit 49 controls a read / write address pointer for each area in the buffer memories 51 and 52 corresponding to each outgoing route, and controls a read signal and a write signal. When the buffer control circuit 49 receives the valid flag in the routing information, it advances the write address pointer of the area corresponding to the output route number. According to this address pointer, the packet information and the routing information are written in the buffer memories 51 and 52.

On the other hand, reading is performed sequentially in the buffer memory.
The areas are sequentially read out from the areas corresponding to the outgoing routes in 51 and 52.
At this time, the read pointer for the area is incremented. Further, in order to prevent overflow and underflow of the buffer memories 51 and 52, the values of the read pointer and the write pointer are constantly compared, and the values are controlled so that they do not exceed their counterparts. The packet information on N in-phase time slots are all written and read in the same time as that time slot.

The packet information and the routing information read from the buffer memories 51 and 52 are serialized by the parallel-serial conversion circuits 56 and 57 and sent to the relay lines 30 and 36 corresponding to the next stage SRM. The route selection is uniquely determined in the order of input time to the serial-parallel conversion circuits 56 and 57. The SRMs in the next and subsequent stages perform the same operation.
In the time chart of FIG. 4, (e) of the figure shows a state in which the packet is read from the buffer memory 52, and (f) of the figure shows the packet on the packet relay line 30.

FIG. 7 is a block diagram of an embodiment of the line interface unit (LIF) 22.

In the figure, each packet input to the packet input line 24 is synchronized with the internal common phase in the phase adjustment circuit 58 in the phase synchronization unit 42 and accommodated in the time slot at the same time position. At this time, the input phase is given from the signal line 26 indicating the packet start position or the phase detection circuit 59 for detecting the start position from the packet itself. As the internal common phase for synchronization, the timing generation circuit 61 gives an optimum phase for internal processing.

The slotted packet information is transferred to the serial / parallel conversion circuit 63.
Serial-to-parallel conversion is carried out and input to the virtual channel number exchanging circuit 65 and the routing information generating circuit 66 in a time division multiple access format. The virtual channel number exchange circuit 65 has a function of converting the virtual channel (VCN) in the packet header into a new signal (VCN ') used in the next MSRN, and a table for searching VCN' from VCN. Similarly, the routing information generation circuit 66 has a function of converting VCN to routing information in the switch and a table for searching the routing information. These two search tables are connected to the upper CPU via the control circuit 67, and the contents are searched and updated by software control.

The packet information and the routing information output from the virtual channel number exchange circuit 65 and the routing information generation circuit 66 are time-division multiplexed, and the parallel-serial conversion circuits 70 and 71 are provided.
Is converted into a series by N, and N relay lines 28 and 3 corresponding to each SRM
It is distributed to 4 and sent out. At this time, the route of the relay line is
It is uniquely determined by the input time phase to the parallel-serial conversion circuits 70 and 71. Occasionally, the time slots of the packet information and the routing information on the trunk line have the same phase.

FIG. 8 is a block diagram of an embodiment of the self-routing module (SRM). Packets and routing information are input to the SRM at the first stage in FIG. 2, for example, 16 through the packet relay line 28 and the routing information relay line 34 from the line interface unit 22.

Each information is synchronized with the SRM internal phase in the phase adjustment circuits 450 and 460 in case of a phase difference due to the transmission distance or the like. The synchronized pieces of information are parallelized by the serial / parallel conversion circuits 45 and 46, and are sent to the buffer memories 51 and 52 in a time division multiplexed form. Buffer memory 51, 52
Is divided into areas corresponding to the outgoing routes. The individual queue buffer control circuit 72 manages each area.

The write request signal 73 of the buffer memory is the write request signal from the decoder 730 generated from the output path number for the SRM of the self-stage in the parallel routing information input 48 and the valid information flag and the write operation described later in the individual queue buffer control circuit 72. Prohibition signal 74
The condition that there is no condition occurs when both are detected in the write request detection circuit 75. The write request signal 73 is output from the N queue buffer control circuits 72 in total and input to the OR circuit 76, and the output thereof becomes the write enable signal 77. At the same time, the write request signal 73 triggers the write address counter 78 to count up. The output 79 of the counter 78 becomes a write address 80 for writing information to the buffer memories 51 and 52. At this time, the selector 81 selects the output path number of the SRM from among the outputs from the N write address counters 78 in total.

When the write enable signal 77 and its address 80 are complete, each piece of information 47, 50 is written in the buffer memories 52, 51. At this time, what is written in the buffer memory 51 is
It is only the SRM routing information for the next and subsequent stages.

On the other hand, the read request signal 82 is the decoder 84 of the selection signals 840 periodically sent from the timing generation circuit 83.
When the decode signal corresponding to the number (1 to N) of the queue buffer control circuit 72 to be decoded by and the condition that there is no read inhibit signal 85 described later are both detected, the read request detection circuit 86 outputs. This request signal 82 becomes a read enable signal 88 via the OR circuit 87, similarly to the write request signal 73. Further, the request signal 82 triggers the count-up of the read address counter 89. counter
The output 90 of 89 becomes the read address 92 of the information from the buffers 51 and 52 via the selector 91. At this time, a number corresponding to the selection signal 840 output from the timing generation circuit 83 is selected from the N counter outputs 90 in total.

Information is read from the buffer memories 51 and 52 when the read enable signal 88 and the address 92 are complete.

In order to prevent overflow and underflow of the buffer memories 51 and 52, the output values of the counters 78 and 89 are constantly compared by the address comparison circuit 93, and the write or read inhibit signal 7 is set before the values of the counters 78 and 89 exceed their counterparts.
Generates 4,85.

Packet information read from the buffer memories 52 and 51
The parallel information 54 and the routing information 55 are serialized by the parallel-serial conversion circuits 56 and 57 and sent to the output path corresponding to the next stage SRM.

The times of writing and reading to and from the buffer memories 51 and 52 do not overlap with each other, and the time required for writing and reading of the N queue buffers corresponds to the time of one time slot, that is, the fixed packet length. I shall.

The SRMs from the next stage onward also perform the same operation, and in the final stage SRM,
Only the packet information is sent out on the predetermined output highway 8 and the exchange is completed.

〔The invention's effect〕

As described above, according to the present invention, since the queue buffer for storing packet information is subjected to time division multiple access, contention at the time of writing and reading of information does not occur, and the contention arbitration circuit can be eliminated. it can. Also, the number of queue buffers can be reduced to one per self-routing module.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing an example of the overall structure of a speech path switch, FIG. 3 is a schematic block diagram of a line interface unit (LIF), and FIG. 4 is an operation of the speech path switch. Time chart, FIG. 5 is a schematic block diagram of the self-routing module (SRM), FIG. 6 is a diagram showing a configuration example of routing information, FIG. 7 is a block diagram of an embodiment of the line interface unit (LIF), and FIG. Is a block diagram of an embodiment of a self-routing module (SRM), and FIG. 9 is a diagram showing a conventional example of a self-routing packet switch. 1,16〜21 …… Self-routing module (SRM), 2 …… Multi-stage self-routing network (MS
RN), 4 ... Virtual channel number converter (VCC), 6 ... Competitive arbitration circuit, 7, 51, 52 ... Queue buffer memory, 22, 23 ... Line interface unit (LIF), 450, 460 ... Phase adjustment circuit, 45, 46 ... Series-parallel conversion circuit, 49 ... Buffer control circuit, 56, 57 ... Parallel-series conversion circuit.

Claims (1)

(57) [Claims] 1. A self-routing module used for packet switching, wherein phase adjustment means (11) for synchronizing fixed-length packets input from a plurality of input paths and synchronization by said phase adjustment means (11) are performed. , A serial / parallel conversion means (12) for converting one packet into a parallel signal for each of the plurality of routes and time-division-multiplexing the parallel signals, and outputting the packet group of the time-division-multiplexed packets to the route of each packet A storage means (13) for storing in the corresponding area and a parallel signal corresponding to each of the packet groups stored in the storage means (13) are read in parallel by a time division multiplexing method, and the packet group is parallel-serial converted. Parallel-serial conversion means (14) for serially outputting to the output as a serial signal, writing of packets from the serial-parallel conversion means (12) to the storage means (13), and the parallel-serial operation from the storage means (13). To conversion means (14) A packet switching self-routing module comprising a control means (15) for controlling packet reading.