JP2545936B2 - Bus interface unit - Google Patents

Description

The present invention relates to a bus interface unit connected to a high speed memory bus and a medium speed memory bus and an information processing system including the same, and particularly to a medium speed IO (input / output). The present invention relates to a bus interface unit that sends a partial write command of a bus to a small number of high-speed memory buses and an information processing system including the same.

[Prior Art] In a conventional bus interface unit, a partial write command sent from a medium speed IO is directly transferred to a high speed memory bus. A conventional system is shown in FIG.

When the data transfer is activated by the medium speed IO bus of d, the command decoder 1 distinguishes the transfer command. When a partial write command is instructed by the command decoder 1, the write enable signal line c input to the partial write command control circuit 4 outputs the partial write command on the high speed memory bus and at the same time outputs it as the write enable signal of the high speed memory bus. To be done. The partial write command on the medium-speed IO bus is output as it is as a partial write command on the high-speed memory bus, and when one cycle ends, EOC (END OF CYCL
E) The signal is output once. Read and full write commands on the medium speed IO bus are output to the high speed memory bus by the read command control circuit 2 and the write command control circuit 3.

[Problems to be Solved by the Invention] In the conventional system described above, when a partial write command is received from the medium speed IO bus, the same partial write command is issued to the high speed memory bus. There is a drawback in that a high-speed bus line having the same number of signal lines as that of is required.

[Means for Solving the Problems] A bus interface unit of the present invention is a bus interface unit connected to a high-speed bus and a medium-speed bus, and receives a command activated by the medium-speed bus, and the command is a partial command. Command decoder means for identifying whether or not the command is a write command; and a command identified by the command decoder means as a partial write command is decomposed into a plurality of continuous partial write commands, and the plurality of partial write commands are described above. And a write partial write control means for sending to the high speed bus.

EXAMPLES Next, the present invention will be described in detail with reference to the drawings.

In FIGS. 1 and 2, reference numeral 1 is a command decoder which decodes a command of the medium speed IO bus. Reference numeral 2 is a read command control circuit that performs a read command operation. Reference numeral 3 is a write command control circuit for performing all write operations. Reference numeral 4 is a partial write command control circuit for performing partial write as one cycle operation. Reference numeral 5 is a bus lock control circuit. Reference numeral 6 is a partial write command EOC control circuit that controls the EOC signal to perform partial writing. Reference numeral 7 is a write partial write control circuit that performs partial write a plurality of times according to an instruction from 6. Reference numeral 8 is a partial write lock control circuit for resetting the partial write lock flag of reference numeral 9 when the operation of the partial write command is completed.

The partial write command activated by the medium speed IO bus d is decoded by the command decoder 1, and the write partial write control circuit 7 takes in the write enable signal line c and generates an address including byte enable.
Further, the medium-speed IO bus partial write command is decomposed according to the partial write command of the high-speed memory bus, and the high-speed memory bus partial write command is executed a plurality of times for the medium-speed IO bus partial write command. As a result, the number of signal lines of the high speed memory bus can be reduced.

However, when such command division is performed, EOC
Since the signal is output at the end of each of the transmission of the divided commands to the high speed memory bus, an arbitration means (not shown) for adjusting the permission of use of the high speed memory bus is provided to another bus interface unit or the like. It is possible to issue a license. In this case, it takes extra time to send a command to the high-speed memory bus, so that the medium-speed IO bus does not delay the next command, and the bus usage efficiency decreases. In order to reduce this problem, the following configuration may be adopted.

First, assuming that a lock signal is used as shown in FIG. 1 as the first embodiment, when a partial write command from the medium speed IO bus is received, the partial write lock flag 9
A lock flag is set, a lock signal is output on the high-speed memory bus, and thereafter, arbitration means (not shown) for adjusting permission of use of the high-speed memory bus until the lock flag is reset by the partial write lock control circuit 8. The arbitration due to is suppressed, and during this period, only the disassembled partial write command is sent to the high speed bus memory. As a result, since the partial write operation is continuously performed on the high speed memory bus, the transfer capability does not drop extremely even on the medium speed IO bus. When the partial write command is completed, the lock flag is reset.

Further, as a second embodiment, as shown in FIG. 2, when a partial write command is received from the medium speed IO bus, the partial write command EOC control circuit 6 controls to output the EOC signal only for the last partial write command. As a result, the arbitration of the high-speed memory bus can be made to wait until all partial write operations are completed, and the high-speed memory bus can be exclusively occupied. As a result, since the partial write operation is continuously performed on the high speed memory bus, it is possible to minimize the deterioration of the transfer capability in the medium speed IO bus.

FIG. 3 shows an example of divided command signals generated by the write partial write control circuit.

[Effects of the Invention] As described above, the present invention reduces the number of bus lines of the high-speed memory bus by sending the partial write command from the medium-speed IO bus to the high-speed memory bus as a plurality of partial write commands. The effect of being able to do is exhibited.

Further, by suspending the transmission of the lock signal or the EOC signal to temporarily stop the high speed memory bus arbitration circuit at the time of the partial write command, it is possible to suppress the decrease in the transfer capability of the medium speed bus.

[Brief description of drawings]

1 and 2 show the first and second aspects of the present invention, respectively.
FIG. 3 is a block diagram showing an embodiment of FIG. 3, FIG. 3 is a diagram showing an example of a partial write command, and FIG. 4 is a block diagram showing a conventional system. 1 ... Command decoder, 2 ... Read command control circuit, 3 ... Write command control circuit, 4 ... Partial write command control circuit, 5 ... Bus lock control circuit, 6 ...
Partial write command EOC control circuit, 7 ... Write partial write control circuit, 8 ... Partial write lock control circuit, 9 ...
… Partial write lock flag, a Bus lock signal, b
...... EOC signal line, 9a …… Partial write lock signal line, 6b…
... partial write EOC signal line, c ... write enable signal line, d ... medium speed IO bus, e ... high speed memory bus.

Claims (3)

(57) [Claims] 1. A bus interface unit connected to a high speed bus and a medium speed bus, the command decoder receiving a command activated by the medium speed bus and identifying whether the command is a partial write command or not. Means and a write partial write control means for distributing the command identified as the partial write command by the command decoding means to a plurality of partial write commands and sending the plurality of partial write commands to the high speed bus. A bus interface unit characterized in that 2. An information processing system having a high-speed bus, a medium-speed bus, and the bus interface unit according to claim 1, which is connected to the high-speed bus, wherein the high-speed bus controls use permission of the high-speed bus. The bus interface has only the bus interface unit for the arbitration means while the write partial write control means sends all of the plurality of partial write commands to the high speed bus. An information processing system comprising: an arbitration means locking means for sending an instruction to give permission to use. 3. An information processing system having a high-speed bus, a medium-speed bus, and a bus interface unit according to claim 1, which is connected to the high-speed bus, wherein the high-speed bus controls use permission of the high-speed bus. The bus interface sends a command transmission end signal to the arbitration means only when the write partial write control means finishes sending all of the plurality of partial write commands to the high-speed bus. Command transmission end signal control means for transmitting, and the arbitration means gives permission to use the high-speed bus only to the bus interface unit until receiving the command transmission end signal transmitted by the command transmission end signal control means. An information processing system characterized by the above.