JP2543306B2 - Array processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array processor containing a plurality of pickets, and more particularly to a SIMD / MIMD array processor within a SIMD / MIMD array processor for executing programs by the array processor. A mechanism for grouping pickets.

Related Patent Application US Patent Application No. 6111594 (Japanese Patent Application No. 3-27890)
No. 0) describes a parallel associative processor system consisting of 100 to 1000 processing elements. However, this patent application does not describe any improvement of the present invention, including a dose latch.

Explanation of Terms ALU ALU is an arithmetic operation unit of each processing element.

Array An array is an array of elements in one or more dimensions. From the viewpoint of hardware of a massively parallel computer, an array is usually a set of structures (processing elements) having the same configuration. When performing parallel operations (arithmetic operations) on data, each processing element can perform these operations independently and in parallel when necessary, when the operations are assigned to each processing element. In general, an array can be thought of as a grid of processing elements.

Array Controller An array controller is a unit programmed as a controller for an array processor. The array controller performs the function of a master controller for grouping the processing elements located within the array processor.

Array Processors The two main architectures of array processors include Multiple Instruction Multiple Data Stream (MIMD) and
There is a single instruction multiple data stream (SIMD).
In the MIMD array processor, each processing element is
Executes its own unique instruction stream for its own data. On the other hand, in SIMD array processors, each processing element is restricted to the same instruction from a common instruction stream, but the data associated with each processing element is unique. The preferred array processor of the present invention is an advanced parallel array processor.
LelArray Processor: APAP) and has other characteristics.

Controller A controller is a device that directs the transmission of data and instructions over the links of an interconnection network.
Its operation is controlled by a program executed by the processor to which the controller is connected,
Alternatively, it is controlled by a program executed in the controller.

Link A link is a physical or logical element. A physical link is a physical connection for connecting a plurality of processing elements.

MIMD MIMD is the architecture of the array processor such that each processing element within the array processor itself to execute multiple data streams, one positioned for each processing element. , And thus, as a whole, a multi-instruction stream.

Module A module is a functional unit of hardware that is designed to be used with an individualized and identifiable program unit, or other component. A collection of processing elements contained within a single electronic chip is also called a module.

Node Generally, a node is a connection point of various links. In a general processing element (PE) array, one PE is one node. Each node is a PE called module
May include a set of. In the representative example, each node is preferably formed from eight processor memory elements (PMEs).

Node Array A collection of modules composed of PMEs, sometimes referred to as a node array, is an array of nodes composed of multiple modules. A single node array typically has more than a few PMEs.

Picket A picket is a component of an array processor.
A picket represents 1 / nth of an array processor and takes the form of a PME. Processor logic designed in accordance with the PME chip of the present invention may implement the picket logic described in the above-referenced related patent application or have the logic for an array processor formed as a node. . The term picket is similar to the term "processing element (PE)" commonly used in the field of array processors. The processing elements in the array processor corresponding to pickets preferably consist of processor elements and local memory combined to process multiple information bytes in bit parallel during one clock cycle. Picket in the typical example is 1
It consists of a byte-wide data flow processor (ALU + register), local memory with a capacity of 32 kilobytes or more, primitive control, and means for interconnecting the picket with other pickets.

Picket Processor A picket processor is an array of pickets, an interconnection network, an I / O system, and a SIMD controller consisting of a microprocessor, a storage routine processor, and a microcontroller that operates the array. It is a total system equipped with.

Picket Architecture The picket architecture is a preferred embodiment of the SIMD architecture, where it has features that accommodate several different types of problems. These issues include: -Set associative processing-Parallel numerical processing-Image-like physical array processing-PME The term PME is used to mean "processor memory element". One PME embeds one picket. A PME is 1 / nth of an array processor and consists of a processor element, its associated memory element, a control interface, and part of an interconnect network. A PME can have connectivity with a regular array, as in the case of a picket processor, or with a portion of a sub-array, as in the case of a PME node. .

Routing The routing is the allocation of the physical route by which a message reaches its destination. Data sources (sources) and destinations are associated with routing assignments.
These elements or addresses have a temporary relationship or similarity. Message routing is often based on keys, such as those obtained by looking up an assignment table. A destination in the network is any addressable processing element that is addressed as the destination for information sent by the routing address that identifies the link. The destination field in the message header identifies the applicable destination.

SIMD SIMD is the architecture of an array processor in which all the processing elements execute a single instruction stream, such that they execute multiple data streams, one for each processing element. It's like being commanded by a stream.

SIMD / MIMD SIMD / MIMD has the dual function of being able to switch from MIMD to SIMD during a certain period in order to process some complex instructions, Therefore, it is a term used to describe a computer having a dual operation mode. M
Thinking, as an input or output end of the IMD calculator
Machine Company's massively parallel computer "Connection Machine-2"
When (CM-2) ”is deployed, the programmer can activate dual modes of operation to perform different parts of one problem. These computers use a bus that interconnects the master control processor with other processors. This master control processor has the ability to interrupt the processing of other processors. Other processors are capable of executing independent program code. Means must be provided to checkpoint (close and save the current state of the controlled processor) during the interrupt.

SIMIMD SIMIMD is the architecture of an array processor in which all of the processing elements execute from a single instruction stream in order to execute multiple data streams, one for each processing element. It is like being ordered. In this architecture, the data dependent operations within each picket that mimic the execution of instructions are SIMD.
Controlled by the instruction stream. A SIMIMD computer is capable of ordering multiple instruction streams (one per picket) using a SIMD instruction stream and processing multiple data streams (one per picket). It is a single instruction stream computer. SIMIMD can be executed by the PME system.

Synchronous operation Synchronous operation in the MIMD computer is an operation mode in which each action is associated with one event. This event is usually a clock, but it may be a particular event that occurs regularly within a program sequence. When an operation is dispatched to multiple PEs,
These PEs proceed to perform their function independently. Control is not returned to the controller until this operation is complete. If the request is for an array of processing elements, then after the requests for the processing elements in the array have been generated by the controller, such processing elements complete their respective operations before control is returned to the controller. Must.

[0021]

In an endless quest for faster computers, engineers have paralleled hundreds to thousands of low-cost microprocessors to overcome the complex problems that plague today's computers. By linking to, we have started to build massively parallel computers. The present invention relates to a new technique for building a massively parallel computer. Many of the improvements of the present invention should be considered in the context of the prior art. There are systematic trade-offs required to choose the architecture that best fits a particular application, but until now there has been no satisfactory solution. The aim of the invention is to make it easier to provide a solution. That is, the present invention is applicable to SIMD and MIMD.
The present invention relates to an array processor capable of realizing operation.

The following is a summary of various US patents relating to SIMD computers. None of these U.S. patents discloses or suggests a mechanism in accordance with the present invention, i.e., for grouping pickets in SIMD and MIMD arrays for execution of a program by an array processor.

US Pat. No. 4,783,738 is directed to aspects of autonomy, and in particular,
When the SIMD controller issues one command to all processing elements (PEs) in the array processor, each P
It allows E to modify or insert bits within this command as a result of spatial or data dependent properties. For example, A
DD / SUB, SEND / RECEIVE and OPA /
Includes OPB generation. This feature is used to image multiple rows to define the boundaries of the image.
This U.S. Patent is similar to one of a number of autonomous functions (in which the present invention causes the ALU to perform a data dependent operation) which may be used in connection with the grouping of the present invention. However, the present invention does not contemplate modifying or inserting action bits as in this US patent. The present invention is
It does not consider that the U function is a particular function of spatial location within the array processor. This U.S. patent is similar to some of the features of the present invention in that it involves data dependent functions, but the present invention does not include DWIM (Do What).
I Mean: by implementing a function that does what I want) so that the data dependent part of one instruction sequence (such as a sign or condition code) simply forces the ALU to do something else. There is.

US Pat. No. 4,736,291 discloses data
The array conversion processor, which executes high-speed processing of the array, is described. This US patent has been optimized to implement an FFT (Fast Fourier Transform) algorithm in the field of seismic analysis. Central to this patent is a system control bus shared by bulk memory and up to 15 devices. Each device has a writable control store, a program memory, a control unit, and a device slave unit that provides unique characteristics to each of the 15 devices. On the other hand, the array conversion processor is not necessarily a parallel array processor in itself, nor is it mentioned in this US patent. Array conversion can also be performed by the system of the present invention. However, the processor described in this U.S. patent does not provide data in a complex and iterative order.
It has several subunits (stages) for processing the array. In contrast to this US patent, the SI of the present invention
In the MD array processor, the plurality of processing elements respectively take out the plurality of elements of the data array and process the data in parallel in these processing elements.

US Pat. No. 4,831,519 describes each one
Providing interprocessor connections extending from each PE to its left and right sides so that multiple processing elements (PEs) having a 6-bit width can be connected together to effectively accommodate different data formats. SIMD array
Describes the processor. For example, when processing a 64-bit floating point word by four PEs, one of these PEs (upper)
The exponent part (16 bits) of the floating point word is processed, and the fractional part (48 bits) of the floating point word is processed by the remaining three PEs connected together. Control of carry / borrow,
To achieve this, PEs can be bonded together. 16 PEs for data processing on one chip
And two PEs for address generation and two spare PEs
And can be installed. The I / O for this US patent is
By using a four-level signaling scheme, it is possible to combine two logic signals into one pin and generate one of four voltages depending on the logic conditions of these two lines. I have to. The device of this U.S. patent must provide the controller function, which is rarely described. The array processor of this U.S. patent includes a global MASK that defines how multiple PEs are grouped together to operate on data of various sizes, and a master P.
Local NEST propagating from E to the slave PE on its right
Control and is supplied. However, there is no mention in this US patent of determining which group a PE belongs to. In addition, the arbitrary processing is NE
Neither is there any description of local autonomy in the sense that it is performed based on the data being processed, not the ST control. This US patent describes multiple PEs adjacent to each other.
To describe a possible design for a horizontally expandable SIMD chip to operate as a single processor for processing 16, 32 and 48 bit wide data. However, in this US patent, how multiple processing elements can be combined, and the number of adjacent PEs that operate as a single processor, is 16, 32, or 48 bits wide. Regarding how to process the data of, and how to know or determine whether a processing element should participate in a given process, Not described or suggested at all. This U.S. patent has grouping dictated by the global control MASK. However, this US patent lacks local autonomy. This will become apparent upon a review of this U.S. patent after understanding the present invention.

US Pat. No. 4,783,782 is a SIMD described in US Pat. No. 4,831,519, cited above.
For separating up to two defective PEs in the array,
It describes the manufacturing test of SIMD chips.
Defective data is stored in the PROM section on this chip. Resources on this chip can be dynamically allocated after the defective data is read by the controller. Thus, the chip of this US patent
It has only limited autonomy of the processor.

US Pat. No. 4,748,585 describes a mechanism for assigning elements of a parallel processor to segments to accommodate data of varying lengths. This U.S. patent is also the above U.S. Pat.
Similar to No. 19, but this patent relates to combining multiple uniprocessors and grouping them together to handle words wider than the width of each uniprocessor. Each uniprocessor has a micro sequencer, ALU, registers, etc.
It is completed. A feature of this U.S. patent is that several uniprocessors may be operated in a staggered fashion to process wide data words. The segmentation control is performed by the global control using the combination code and the global condition code. As a MIMD array, this device cannot provide the capabilities of a SIMD array. In contrast, the present invention improves on multiple pickets rather than on controlling for a MIMD array to combine multiple uniprocessors together to build a wider processor as in this US patent. It relates to connecting in a different manner.

US Pat. No. 4,825,359 discloses data
Array processing, eg its Fast Fourier Transform (FFT)
Describes a processor for doing. The processor includes several processing operators, each of which can be programmed to perform one step during the calculation. This processor can be classified as a complex uniprocessor with some processing operators that act as a pipeline in executing complex processes. In this US patent, neither grouping nor autonomy is described at all. This US patent is only intended to make some modifications to accommodate a wide range of operators.

US Pat. No. 4,905,143 performs calculations on all combinations of variables of two types, and
An array processor for calculating a recursive function having a local data dependency using these calculation results is described. The results of these calculations are characterized by matching calculations based on the theory of dynamic time warping or dynamic programming as used in the case of pattern matching in the field of speech recognition. This processor is a kind of systolic MIMD
Intended to act as a table. The PEs are arranged in a ring and the next P in the ring
It passes intermediate results to E. Each PE is
It has its own instruction memory and other means. This US patent does not describe the autonomy of PEs in a SIMD array, but also describes grouping of PEs, except that they are physically arranged in a ring. I haven't.

US Pat. No. 4,910,665 describes each PE
Of the SIMD array processor so that it can directly access the eight elements adjacent to it.
Describes a dimensional interconnection network.
The communication medium is a dot-connected network where four adjacent elements are interconnected at each corner.
This U.S. patent also discloses a SIMD computer, but it is totally touched at whether or not local autonomy or grouping of PEs can or should be provided as in the present invention. Not not.

US Pat. No. 4,925,311 has nothing to do with implementing a mechanism similar to the present invention. In this patent, multiple processors within a multiprocessor system can be assigned as a group to solve one problem. In addition, each processor can add and remove messages, semaphores and other controls from other processors as well as add itself to and remove itself from the group. Due to its MIMD nature, this US patent is
Nothing is said about providing local autonomy at the PEs in the IMD array. Instead, each processor in this multiprocessor system has a RAM,
Microprocessor and certain functional units (disk,
A network interface controller, including a controller). Grouping is controlled by the network interface of each processor. The present invention does not require such precise task division.

US Pat. No. 4,943,912 describes NEWS.
It describes a MIMD array processor connected to a network. That is, the array controller loads the program into the memory of each PE in the array processor, and then issues one procedure start command to identify a plurality of PEs whose execution should be started. Each PE
Includes a register holding a plurality of task patterns and a comparing means for matching the task pattern of the PE with the global task pattern command. The result of this comparison is used to select a program start point within the PE or to put the PE into an idle state. However, this US patent does not suggest this for autonomy in PEs in SIMD arrays, like the present invention. The above-mentioned comparison means and the comparison result are used for a plurality of PEs for various parallel tasks.
Can be used to classify or group. In contrast, the present invention refines how multiple pickets in a SIMD environment are allowed to sort or group themselves. The effect is to isolate some of the pickets and make them active while a section of SIMD code is being executed. Thus, the computer of the present invention can proceed to activate other groups for processing.

US Pat. No. 4,967,340 describes a systolic array processor. Each processing element in the array processor consists of two registers, an adder, a multiplier and three programmable switches. To configure this array processor, the switches within each of its processing elements are set by the controller. The data is then used to create the desired result.
It is fed through these processing elements. This US patent does not suggest a system according to the present invention.

US Pat. No. 5,005,120 is directed to an array processor in the sense that multiple processors are present. However, this patent only describes a time compensation circuit used in aligning data in a bit serial signal array processor. Each processing element of the array processor consists of a four bit serial register which supplies data to the ALU. A time compensation circuit is placed in front of the first register. This array processor is SI
It has nothing to do with the MD calculator.

US Pat. No. 5020059 describes defective PE.
To a generalized interconnection scheme for array processors, where the array processor is reconfigured to eliminate tree and other topologies within the basic two-dimensional mesh. This U.S. patent does not describe or suggest array control architecture, grouping, or any aspect of the PE, and therefore no description of autonomy within the PE. However, the SI of the present invention
In the MD computer, each picket in the array processor performs exactly the same operation as before. The selective disabling and enabling of local autonomy of one or more pickets is a cornerstone of the present invention. Despite all the efforts of the prior art as mentioned above, executing SIMD, MIMD and SIMIMD processes by one computer has not been realized so far except for the related patent applications mentioned above. . In fact, the SIMIMD process,
The mechanisms required for floating point arithmetic and others have not been fully developed in the art.

US Pat. No. 5,045,995 describes a mechanism for enabling or disabling the function of each PE in a SIMD array based on the data conditions in each PE. When one global instruction is issued to all PEs, each PE
Samples a condition inside it and enables or disables the PE itself via a bit in the status register. Other global instructions effectively exchange the states of these PEs. Such a function is called IF / THEN / ELS
It can be used to realize E and WHILE / DO structures. In addition, this state can be stacked to support nested permit conditions.
Thus, this U.S. patent relates to the permit / prohibit function of the present invention. However, this US patent requires the following three conditions. 1. Initial test, load status bits, enable / disable based on status bits. 2. Instruction to flip all enable / disable bits to allow other sets of PEs. 3. A storage device for providing nesting. The aforementioned functionality of this US patent is unnecessarily complicated. In contrast, the mechanism of the present invention is capable of enabling / disabling functions without combining all three of the above conditions of this US patent. The present invention does not require the flip functionality described in this US patent, but can provide a wider range of capabilities to the system than the US patent provides. The SIMD computer of the present invention does not require any combination of IF and ELSE instruction functionality with other features of video processing.

In general, in accordance with the needs in the art and the technology aimed at by the present invention, the related patent application cited above describes a parallel array processor of 100 to 1000 pickets (PE). There are many reasons for grouping multiple pickets in some way so that processing can be performed by a selected group or groups of pickets. This selection process can be very cumbersome if, for example, the array processor contains more than one diverse job, or multiple highly diverse parts of the same job. Not only that, it will waste a lot of time. For example, si on geometrical problems
Some of the ne / cosine parts require processing SIN (x), while the other part of the problem is C
It may be necessary to process the OS (x). Thus, while calculating SIN, the group calculating COS is deactivated, and then while calculating COS, the group calculating SIN is deactivated.

However, recognizing that the values in the SIN or COS group are the result of the one angle just calculated, difficulties arise. Thus, SIN or CO
It is necessary to make the allocation to the S group extremely dynamic. Further, since multiple pickets may belong to more than one group, and these pickets may dynamically change their states so that they momentarily belong to different groups, For these pickets, it would be more efficient to reassign themselves in a dynamic fashion.

The knowledge of the present invention relating to this point is that array groups are re-assigned, or in order to know in real time which pickets belong to which group.
You shouldn't use a controller.

[0040]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a mechanism for effectively and dynamically grouping a plurality of pickets (PE).

[0041]

The present invention is a SIMD / M
The present invention relates to providing a mechanism for grouping a plurality of pickets in an IMD array, and more particularly, to a plurality of pickets (PE: processing) in a SIMD computer during execution of one SIMD or SIMIMD program. Element) grouping. While the related patent applications cited above describe aspects of the preferred embodiment, an improvement of the present invention is that the array functions performed in parallel by all active pickets in the array processor are: It includes a structure for assigning multiple pickets to multiple groups, and a mechanism for using grouping to select some pickets for which one group problem specific computation should be performed.

These improvements are achieved by providing the array processor with a mechanism for grouping multiple pickets in a SIMD / MIMD array. The array processor has an array controller and multiple pickets capable of functioning in SIMD mode of operation. Each picket has one ALU,
It has a number of registers and a local memory and is interconnected with other pickets during operation of the array processor. Each picket can dynamically assign itself to one or more groups in order to individually process the data in multiple pickets belonging to a group. Every picket in the array processor receives and executes one command from the array controller every clock cycle. In this case, certain commands can be interpreted within each picket to produce different actions, and during such actions, each picket can operate in SIMIMD operating mode. A unique function within a picket allows the picket to participate in the processing of the SIMD instruction stream as a result of SIMD commands from the array controller, or the picket processes the SIMD instruction stream. Prohibit participation in.

The array processor has a mechanism for local autonomy, a doze mode for preserving the picket's internal state, and a dose latch. This dose latch can be changed by the calculation result in one picket. This dose latch modifiable picket calculation is L for each data calculated or read from the picket's local memory.
It contains OAD / SET / RESET instructions.

According to the invention, the state of a picket is preserved by not allowing it to be stored in local memory within the picket. Also, other calculations, including reading local memory in the picket and arithmetic calculations, ensure that only valid results are moved to the dose latch.
This can be continued.

As a result of this grouping, groups of pickets within the array processor are divided by the type of problem they contain. Each picket has a means for assigning itself to one or more groups working on a problem.

By creating new chips and systems designed in accordance with the novel concepts of the present invention, new techniques for building massively parallel and other computers are provided. The present invention is directed to such a system.

In this specification, a picket processor and
A highly parallel array processor (APAP) is described. It is interesting that the picket processor can utilize one PME (processor memory element). Picket processors are particularly useful in military applications where very small array processors are desired. In this context, the picket processor is a highly parallel array processor (APAP).
Is slightly different from the embodiment of the present invention relating to. However, because of the commonality between both processors, the aspects and features provided in accordance with the present invention can be utilized in both processors.

A picket represents the 1 / nth element of an array processor as it is formed from processor and memory elements and interconnect elements. This picket concept can also be applied to 1 / nth of APAP.

Comparing the picket processor and APAP, both processors may differ in data width, memory size and number of registers,
In an implementation of a massively parallel computer, which is an alternative to APAP, the former is conn
ectivity), whereas the latter PME in the APAP is part of a sub-array. Both systems are capable of performing SIMIMD. But the picket processor
Since it is configured as a SIMD computer having a MIMD type PE, SIMIMD can be directly executed, whereas an APAP configured as a MIMD computer is controlled by the MIMD emulated SIMD. By using the type PE, SIMI
MD can be executed. Both computers use PME.

Both systems consist of n PEs and their Ps.
It can be configured as a parallel array processor, consisting of an interconnection network for interconnecting Es. In this case, 1 / n of the array processor consists of a PE, its associated memory, a control bus interface and part of the interconnection network.

Since this parallel array processor has a dual mode of operation,
It can be commanded to operate in either of two modes for SIMD and MIMD operation and to transition freely between these two modes. That is, if the mode for SIMD operation is selected, the processing unit may instruct each PE to execute its own instructions in SIMIMD mode. On the other hand, when the mode for MMD operation is selected, the processing unit determines that the selected PE is MIM.
Simulating the execution of D can be synchronized. This is called MIMD-SIMD.

The interconnection network provided by the parallel array processors in both systems has a path for passing information between PEs. Regarding the movement of information, 2
There are different ways. In the first method, the array controller commands all messages to move in the same direction at the same time because the moving data does not define its destination. In the second method, each message is self-routed according to the destination defined by the header at the beginning of each message.

A segment of this parallel array processor has multiple copies of a processing unit provided on a single semiconductor chip. Each segment has a portion of the interconnection network associated with it, a buffer, a multiplexer, and that segment is seamlessly connected to other segments to extend the interconnection network. And a control unit for enabling the above.

A control bus from the controller is provided for each processing unit. This control bus extends to each PE and controls its operation.

Each processing element segment of a parallel array processor has multiple copies of the processing memory elements contained within a single semiconductor chip and control of the array segments contained within that chip. It includes a portion of the array control bus and register buffers to support communication.

Both can perform mesh moves or routed moves. APAP is usually 2
Realize a heavy interconnection structure. That is, on the one hand, eight PEs (or PMEs) on a semiconductor chip are related to each other, and on the other hand, a plurality of semiconductor chips are related to each other.
Generally, on-chip programmable routing establishes links between PEs (or PMEs), as described above, but multiple nodes are associated in other ways. The usual topology on the chip is a 2x4 mesh,
The interconnection of the nodes in this case can be routed. Both systems have an interconnection network between PEs (or PMEs), thus allowing a matrix to consist of multiple point-to-point networks.

[0057]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 illustrates an improvement of the present invention for grouping multiple pickets within a SIMD computer during execution of a SIMD or SIMID program. More specifically, FIG. 1 illustrates a replicatable processing element within an array processor, commonly referred to as a PE.
This replicable element is one processor element (ALU +
A plurality of registers), a local memory, and means for interconnecting the replicable processing element with other replicable processing elements in the array processor. These replicable processing elements are controlled by an array controller in SIMD mode. The array controller is for controlling the function of a set of replicable processing elements that make up the array processor. Each of the replicable processing elements is a node of the array processor. In some systems, each node consists of a group of chips.
In the preferred embodiment of the present invention, each node can be thought of as consisting of a set of pickets, as described in the related patent applications cited above. Also, each picket is one of a set of processing elements mounted on a single chip. These one set of processing elements is S
Although it is possible to receive common control in the IMD mode, it can also function in the MIMD mode.
In less sophisticated systems, these sets of processing elements can be individual processor elements (ALUs, registers, memory, I / O). In that case, these individual processor elements may be mounted on a single chip with external communication means or may be duplicated as independent chip elements. It is particularly advantageous to utilize the grouping concept of the present invention when a set of processing elements are mounted on a single chip. The present invention can be used in a massively parallel array processor.

While the related patent application cited above describes aspects of the preferred embodiment, an improvement of the present invention is that the array functions performed in parallel by all active pickets in the array processor. , A structure for assigning multiple pickets to multiple groups, and a mechanism for using grouping to select some pickets to perform a computation specific to one group problem.
FIG. 1 shows a concept for controlling grouping of a plurality of pickets from each picket. At one memory location assigned to each group, each picket sets or resets a bit to indicate participation in the group. This memory location is preferably part of local memory, where it is directly associated with an individual picket. This memory location preferably forms part of the replicable picket, but in systems where one part of shared memory is allocated as global memory and the other part as local memory, the latter local memory part Corresponds to this memory location. Initially, a group is constructed from all the pickets with a certain commonality. There are many reasons why the present invention attempts to group multiple pickets in some way. 1
One example is when an array processor contains more than one diverse job, or a very diverse portion of the same job.

Pickets can assign themselves to one or more of several groups, and processing can proceed based on these groupings. The more pickets that are computing at a given time, the better, but for some actions it may be necessary to work with a subset group of pickets. Local autonomy is a tool for doing this task, which we have already discussed.

Next, we will describe an interesting way in which pickets can themselves belong to groups without the array controller needing to know which pickets belong to which group. .

Even though SIMD computers have a high degree of local autonomy, at some point they need to work on a set of similar problems. While the active (participating) pickets in an array processor are working on a problem, the inactive (non-participating) pickets of the array processor are placed in the doze state. Each picket placed in the doze mode is restricted in its activity so that the problems and data in the picket are not disturbed. A picket placed in doze mode can still read its local memory, and can do most of the same operations as other pickets do, but does store to that local memory or register. I can't. With the exception of this, the dose bit can be stored in the status word. Thus, one picket can load the dose bit to calculate a new state and restart (wake up) the picket.

An important feature of the grouping according to the invention is that the picket makes a decision as to whether each picket belongs to a group or a plurality of groups. Therefore, this allocation and reallocation process is one parallel operation, and many pickets can perform the same operation in parallel. The array controller does not even need to know which pickets belong to which groups. However, if such information is needed, the array controller can read the status from each picket. Thus, the functions of such an array controller are located in the registers associated with each picket, labeled "run / dose" in FIG. This register is provided inside the picket and its contents can be read by the array controller.

To establish separate groups,
Inside each picket, one memory location is reserved for each group. The memory location "xx1" inside all pickets is group 1 as shown in FIG.
Hold the dose control bit corresponding to. This dose
The calculated value as loaded into the bit is first stored in the memory location corresponding to the appropriate group in each picket. This value is then put into the dose bit to change the state of the picket.
According to the invention, in order to identify and set several groups prior to individual processing, the appropriate binary pattern (1/0) is placed in the memory locations corresponding to these groups.
To load. One group can be identified by examining the carry output and / or zero condition of one operation and loading that value into the one group. There are the following methods to set groups.

Group all pickets where they have a carry output of 1. Group all pickets where the content of the selected memory location is positive.
Group all pickets where the contents of the selected memory location is equal to a particular broadcast value.

If one picket belongs to group 2, memory location "xx2" in the picket.
Holds a logical one, otherwise it holds a logical zero. To change the dose bit, three commands (LO
AD / SET / RESET) can be used. The first command, "LOAD DOZE," causes the active group to change to a group of all pickets that hold a logical one at each memory location (eg, xx3). A picket that was previously in the on state but holds a logic 0 in its memory location "xx3" is turned off. The second command “SET DOZE” is
Add all pickets that hold a logical one at each memory location (eg xx4) to the active group. In this case, no picket can be turned off. The third command, "RESET DOZE," removes from the active group all pickets that hold a logic one at each memory location (eg, xx4).

These commands, namely LOAD, SET (A
With ND) and RESET (OR), the logical functions for building a new group can be effectively used based on the logical relationships of existing groups.
Also, using set theory, one new group can be constructed by logically merging existing groups within this picket data flow.

To this point, the array controller is aware of the existence of multiple groups. Because
The array controller is concerned with processing with these groups and has caused active processing to change between groups. However, the array controller knows nothing about which pickets belong to which groups, or whether a particular group is actually empty (no pickets).

The array controller can read information on individual pickets by using other functions as needed. The result of these functions is to provide the address of the picket of interest. Below, three examples are given. Find the picket with the latest value in a given group. Find the picket with the lowest address in a given group. Finding pickets within a given group that have values that appear to be closest to each other.

In each of these cases, the array
The controller, through executing a series of instructions,
Pickets with the desired values must be separated.
Various inter-picket instructions can be used to separate the desired pickets. At this point, the desired picket is the only picket that is still awake. The array controller requests that address,
Data can be read from or loaded into the local memory.

The grouping function within the array processor is a powerful tool not only in SIMD, but also in other modes such as SIMIMD.

[0071]

As described above, according to the present invention, it is possible to provide a mechanism for effectively and dynamically grouping a plurality of pickets (PE).

[Brief description of drawings]

FIG. 1 is a diagram showing a control concept for grouping a plurality of pickets from each picket. At one memory location assigned to each group, each picket sets or resets a bit to indicate participation in the group. This memory location is preferably part of local memory, where it is directly associated with an individual picket.

 ─────────────────────────────────────────────────── ————————————————————————————————————————————————————————————————————————————————————————————————————————————————–——————————————————————————————————————— D. 3-17 Inerator James Warren DeFender Far United States 13827, Ougo, New York Front Street 396 (72) Inventor Peter Michael Codge United States 13760, New York Endicott, Dorchester Drive 7 (56) ) Reference US Patent 4831519 (US, A)

Claims (3)

(57) [Claims] 1. An array processor comprising an array controller and a plurality of processing elements operating in a SIMD operating mode, each processing element comprising an arithmetic operation element, a plurality of registers, a local memory, and The array processor comprises pickets including means for interconnecting with other processing elements, each picket being interconnected during operation of the array processor, and each picket having a group of pickets (hereinafter "picket
(Referred to as a "group") to process the data individually within the picket itself.
Means for dynamically assigning to a group, all pickets in the array processor receiving and executing a command from the array controller on each clock cycle; Of the local memory has a memory location corresponding to each of the picket groups, and the state of the memory location indicates whether or not the picket participates in the picket group corresponding to the memory location. Array processor. 2. Each picket has a dose mode means and a dose latch for storing the internal state of the picket, the contents of the dose latch being changed according to the result of the calculation in the picket. The array processor according to claim 1, wherein 3. To store the internal state of each picket, storing in the local memory within the picket so that only the results of calculations affecting the state of the picket are loaded into the dose latch. 3. The array processor of claim 2, wherein the array processor is prohibited and allowed to continue other operations, including reading of the local memory and arithmetic operations in the picket.