JP2542933B2 - Time axis correction circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a time axis correction circuit, and in particular, a memory is used as a kind of variable delay line, and an A / D converter and a D / A converter are provided before and after the memory. The present invention relates to a time axis correction circuit in which a converter is arranged.

[Prior art]

FIG. 5 shows an example of a time axis correction circuit including the memory 1 and the A / D converter 2 and the D / A converter 3 arranged before and after the memory 1. Then, the write clock and the read clock of the memory 1 are operated asynchronously. That is, the A / D converter 2 that is created by, for example, a PLL (Phase Locked Loop) that follows a signal including a time axis error input to the A / D converter 2 and that has the same time axis error as the input signal And the write clock of the memory 1.
In addition, for example, a reference clock that is configured by a crystal oscillator and that is created by an oscillation circuit and does not include a time axis error is used as a memory 1
Read clock and D / A converter 3 for reading from memory
Used as the sampling clock of. The phase relationship between the read reset signal and the write reset signal, which are obtained by dividing the read clock and the write clock by the same dividing value by a read address counter and a write address counter (not shown), respectively, is Since it changes according to the frequency relationship with the write clock, the memory 1 functions as a kind of variable delay line, and the time base error contained in the input signal is corrected by it.

At this time, what is important is the phase relationship between the read reset signal and the write reset signal when the write clock follows the time axis error of the input signal and the time axis correction is performed. FIG. 6 shows a general frequency relationship when the read clock and the write clock follow the input signal. The time-axis error period is constant with respect to the read clock that does not include the time-axis error and always has a constant frequency. Shows the relationship with the write clock having frequency deviation.

At points A, E and I in FIG. 6, the frequency of the read clock (indicated by R in FIG. 6) is the write clock (shown in FIG.
The frequency of the write clock is higher than the frequency of the read clock during the period of points A to E, which is the point corresponding to the frequency of (indicated by W in the figure). Therefore, in this period, the read reset signal and the write reset signal obtained by dividing the read clock and the write clock by the same dividing value are the write reset signal based on the read reset signal as shown in FIG. 7A. Moves in the advance direction. On the other hand, in the period of points E to I, conversely, the frequency of the write clock is lower than the frequency of the read clock. Therefore, when the read reset signal is used as a reference, the write reset signal moves in the lag direction as shown in FIG. 7B.

[Problems to be Solved by the Invention]

Conventionally, in the initial state when the write clock follows the input signal, the write clock follows the input signal because there is no means for determining the time point in FIG. 6 where the frequency relationship between the write clock and the read clock is. If not, as shown in FIG. 8, the read reset signal and the write read signal are aligned in phase near the midpoint of each period (T: 1H memory becomes 1H memory), and this phase relationship is initialized. I was in a state. If the read reset signal and the write reset signal are matched in the initial phase by this method, the time axis can be corrected only with a half capacity of the memory 1 used as the variable delay line in the time axis correction circuit. For example, if a 1H line memory is used as the memory, the time axis correction range will be 0.5H or ± 0.25H. That is, the conventional method has a drawback that the memory cannot be effectively used.

Therefore, a main object of the present invention is to provide a time axis correction circuit that can effectively use a memory and can expand the maximum possible delay amount.

[Means for solving the problem]

Briefly, the present invention provides an A / D converter which receives an input signal and converts the input signal into digital data in response to a conversion clock, and a digital clock which converts the digital data converted by the A / D converter. Memory that writes in response to a read clock and that reads in response to a read clock, a D / A converter that converts digital data read from the memory into an analog signal in response to a conversion clock, and its input based on an input signal A PLL means adapted to generate a signal that changes in response to the signal and a reference oscillator generating an independent reference signal are provided, and the signal from the PLL means is converted into an A / D converter clock and a memory is written. PLL means in the time axis correction circuit, which is used as a clock and uses the signal from the reference oscillator as the conversion clock of the D / A converter and the read clock of the memory. When these signals do not follow the input signal, the switching means that switches to give the signal from the reference oscillator as the conversion clock of the A / D converter and the write clock of the memory, the signal from the PLL means follows the input signal. The overwriting detection means for detecting that the write reset signal of the memory correlated with the write clock overtakes the read reset signal of the memory correlated with the read clock, and the write reset signal is detected when the overtaking is detected. The time axis correction circuit is characterized by comprising output means for outputting as a read reset signal.

[Action]

Before the PLL means follows the input signal, the switching means provides the signal from the reference oscillator, that is, the read clock, as the conversion clock and the write clock. Therefore, in this period, the frequencies of the write clock and the read clock match, so that the read reset signal and the write reset signal have a constant phase relationship.

When the PLL means follows the input signal, the write reset signal starts moving when the read reset signal is used as a reference,
If the time point followed by the PLL means corresponds to the point A or I in FIG. 6, then the write reset signal starts moving in the phase advance direction. If the time point when the PLL means follows is point E in FIG. 6, the write reset signal then starts moving in the slow phase direction. At this time, the overtaking detection means detects that the write reset signal overtakes the read reset signal, and accordingly, the output means outputs the write reset signal as the read reset signal. Therefore, the time at which the PLL means starts to follow is always set so as to correspond to point E in FIG. 6, and therefore the write reset signal moves in the phase lag direction from the time at which the PLL means starts to follow, for example, the sixth point. After passing the point I in the figure, it moves again in the phase advance direction.

In this way, when the write reset signal overtakes the read reset signal in the phase advance direction, the write reset signal is output as the read reset signal, so the write reset signal moves only in the phase delay region of the read reset signal. Therefore, a delay corresponding to the maximum delay amount determined by the memory capacity is possible.

〔The invention's effect〕

According to the present invention, the amount of delay determined by the capacity of the memory can be utilized to the maximum, and therefore even if the memory capacity is the same as the conventional one, it is possible to correct a larger time axis error than the conventional one.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

〔Example〕

Referring to FIG. 1, the time base correction circuit 10 of this embodiment.
Includes an input terminal 12, to which a composite video signal, for example, is input as an input signal from a signal source (not shown). This input composite video signal is converted into digital data by the A / D converter 14 and written in the line memory 16. Then, the digital data is read from the line memory 16, converted again into an analog signal in the D / A converter 18, and output to the output terminal 20 as a video signal in which the time axis error is corrected.

The sync signal extracted by the sync separation circuit 22 from the composite video signal is input to the phase comparator 30 together with the signal frequency-divided by the frequency divider 28 from the voltage controlled oscillator (VCO) 26 constituting the PLL 24. The phase comparator 30 compares the phases of the two input signals and outputs the phase difference signal.
It is applied as a control voltage for VCO 26 via LPF32. this
When the PLL 24 locks, the VCO 26 output will follow the input composite video signal.

Further, the output of the VCO 26 is frequency-divided by the frequency divider 34, and is input to the synchronization determination circuit 36 together with the synchronization signal extracted by the above-mentioned synchronization separation circuit 22. The synchronization determination circuit 36 determines whether or not the PLL 24 is locked based on the phase of the input 2 signal, and outputs a high level (“1”) when the PLL 24 is in the locked state. The output of this synchronization determination circuit 36 is
When applied to the select gate 38, it is also applied to the reset signal generation circuit 40.

The select gate 38 selects the output of the VCO 26 or the output from the reference oscillator 42 depending on the high level or low level of the output of the synchronization determination circuit 36, and the line memory 16
The write clock and the sampling clock of the A / D converter 14 are given. That is, when the output of the synchronization determination circuit 36 is “0”, that is, when the PLL 24 is not locked, the select game 38 selects the output of the oscillation circuit 42,
When the output of the synchronization determination circuit 36 is "1", that is, the PLL 24
Selects the output of VCO 26 when is following the input signal.

The output of the oscillation circuit 42 is always given as the read clock of the line memory 16 and the sampling clock of the D / A converter 18.

The reset signal generation circuit 40 receives the write clock from the select gate 38 and the output of the oscillation circuit 42, that is, the read clock, and supplies the line memory 16 with the write reset signal and the read reset signal. That is, the reset signal generating circuit 40, as shown in FIG.
It includes a write reset counter 401 that receives a write clock, and this write reset counter 401 divides the supplied write clock by 1H, that is, 1/910. The output of this light reset counter is
The phase shifter 4
It is given to one input of the select gate 403 via 02. Similarly, the read reset counter 404 that receives the read clock divides the read clock by 1/910, and the output of this read reset counter 404 is the select gate 4
It is given to the other input of 03.

The synchronization determination signal from the synchronization determination circuit 36 is the AND gate 40.
5 is given to one input, and the output of the AND gate 405 is given as a select signal (switching signal) of the select gate 403.

The output of the write reset counter 401 and the output of the select gate 403 are given to the line memory 16 as a write reset signal and a read reset signal, respectively. The line reset signal and the read reset signal are given to the overtaking detection circuit 406. This overtaking detection circuit 406 outputs a high level (“1”) when the write reset signal moves from the initial phase to the advance direction with respect to the read reset signal, and the output of this overtaking detection circuit 406 is It is applied to the other input of the AND gate 405 described above.

The output of the select gate 403, that is, the read reset signal is also given as the reset signal of the read reset counter 404.

In operation, when the PLL 24 does not follow the input signal, the synchronization determination circuit 36 outputs a signal of "0".
Therefore, the select gate 38 selects and gives the output of the oscillation circuit 42 as the write clock and the sampling clock of the A / D converter 14. Therefore, in this state, the same write clock as the read clock is given, and therefore the frequencies of both are exactly the same. At this time, the select gate 403 of the reset signal generation circuit 40 selects the signal from the phase shifter 402 by the output of “0” from the AND gate 405. At this time, the phase shifter 402
Assuming that the phase shift amount is set to zero, the write reset signal and the read reset signal are both output from the write reset counter 401. Therefore, until PLL24 follows the input signal,
As shown in FIG. 3, the signals are output while maintaining a constant phase relationship (determined by the phase shift amount of the phase shifter 402). Therefore, if this phase shift amount is zero, the write reset signal and the read reset signal are output at exactly the same timing. Note that “PS” in FIG. 3 is the phase shift amount in the phase shifter 402 and can be variably set.

When the PLL 24 follows the input signal and is locked, "1" is output from the synchronization determination circuit 36, and the write clock and
As the sampling clock of the A / D converter 14, the output of the VCO 26 is given instead of the output of the oscillation circuit 42 up to that point. At this time, since the output of the AND gate 405 becomes “1”, the output of the read reset counter 404 is selected by the select gate 403 as the read reset signal.

When the write clock from the VCO 26 is input to the reset signal generating circuit 42, the write reset signal starts to move as shown in FIG. 6 if the read reset signal is used as a reference based on the frequency. But, as mentioned above,
If the phase of the read reset signal and the phase of the write reset signal are matched in the initial phase matching, at this time, the delay Td1 (FIG. 4) corresponding to the maximum delay amount determined by the capacity of the memory 16 is generated. It will be done.

After that, as shown in FIG. 4, if the write reset signal moves in the phase advancing direction, the data written by the write reset signal at timing T1 is not read by the read reset signal at timing T3, and at this timing T3, timing T2 The newly written data is read by the write reset signal. That is, the write reset signal will overtake the read reset signal at this point. Therefore, what has been the maximum delay amount Td1 up to now suddenly changes to the delay amount of Td2 and a large skew is generated, and further, data between the timing T1 and the timing T2 is lost.

Therefore, when the write reset signal overtakes the read reset signal in the overtaking detection circuit 406 (FIG. 2), "0" is output from the circuit 406. Therefore,
At this point, the output of the AND gate 405 becomes “0”, and the select gate 403 selects the output of the phase shifter 402, that is, the output of the write reset counter 401 again as the read reset signal. Therefore, the write reset signal and the read reset signal are output again at the same timing.
After that, the output of the AND gate 405 switches to "1", and the select gate 403 selects the output of the read reset counter 404 as the read reset signal. Then, the write reset signal again moves in the phase advance direction, and the overtaking detection circuit 406 detects the overtaking. Therefore, the initial state, that is, the read reset signal and the write reset signal are output again at the same timing.
By repeating such an operation, as a result, the point E shown in FIG. 6 can always be set as the initial phase. Therefore, if the read reset signal is used as a reference, the write reset signal is always delayed. Will move in the direction. Therefore, the amount of time axis error from point E to point I in FIG. 6 is the maximum delay amount Td1 (fourth point) determined by the line memory 16.
If the figure is not exceeded, the jitter can be controlled within that range. After passing the point I in FIG. 6, the write reset signal moves in the advancing direction, but the write reset signal moves in the lagging direction first, so if there is no special abnormal state, the write reset signal is It does not overtake the read reset signal and operates normally thereafter. Then, at the point J in FIG. 6, the state returns to the initial state where the phases of the read reset signal and the write reset signal match again.

By such an operation, the time axis of the input composite video signal including the time axis error is corrected, and the video signal without the time axis error appears at the output terminal 20. At this time, since the 1H line memory is used as the line memory 16, the time axis correction range by the time axis correction circuit 10 is the maximum delay amount of 1H, that is, ± 0.5H.

It should be noted that the capacity of the memory 16 may be appropriately changed as necessary and configured as a frame memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing in detail the reset signal generating circuit of the embodiment shown in FIG. FIG. 3 is a timing chart showing the relationship between the read reset signal and the write reset signal in the state where the PLL does not follow the input signal in the embodiment of FIGS. 1 and 2. FIG. 4 is a timing chart showing the relationship between the read reset signal and the write reset signal when the PLL follows the input signal in the embodiment of FIGS. 1 and 2. FIG. 5 is a block diagram showing a conventional general time axis correction circuit. FIG. 6 is a graph showing the frequency relationship between the write clock and the read clock. 7A and 7B are timing charts showing the direction in which the write reset signal moves with respect to the read reset signal. FIG. 8 is a timing chart for explaining the conventional initial phase adjustment. In the figure, 10 is a time axis correction circuit, 14 is an A / D converter, 16
Is a line memory, 18 is a D / A converter, 24 is a PLL, 36 is a synchronization determination circuit, 38 and 403 are select gates, 40 is a reset signal generation circuit, 42 is a reference oscillation circuit, 401 is a line reset counter, and 402 is a phase shift 404, read reset counter, 40
5 is an AND gate, and 406 is an overtaking detection circuit.

Claims (1)

(57) [Claims] 1. An A / D converter that receives an input signal and converts the input signal into digital data in response to a conversion clock; and a digital data converted by the A / D converter in response to a write clock. A memory for writing and reading in response to a read clock, a D / A converter for converting digital data read from the memory into an analog signal in response to a conversion clock, and an input signal based on the input signal PLL means adapted to generate a signal that changes in accordance with the above, and a reference oscillator generating an independent reference signal, the signal from the PLL means
In the time axis correction circuit, which is used as the conversion clock of the D / D converter and the write clock of the memory, and uses the signal from the reference oscillator as the conversion clock of the D / A converter and the read clock of the memory. When the signal from the PLL means does not follow the input signal, a switching means that switches to give a signal from the reference oscillator as the conversion clock of the A / D converter and the write clock of the memory, An overtaking detection that detects when a signal from the PLL means follows the input signal and that the write reset signal of the memory that correlates to the write clock overtakes the read reset signal of the memory that correlates to the read clock. And the write reset signal when the overtaking is detected. Characterized in that it comprises an output means for outputting a signal, the time base corrector.