JP2540844B2 - Data transfer control method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control method between an arithmetic and control unit and a main memory unit.

〔Overview〕

According to the present invention, in a method in which an arithmetic and control unit obtains required data from a main memory device by a block read request at a time, transfer data in block units divided into a plurality of blocks is transferred from a transfer segment data on an accessed address to a block. By transferring the data up to the transfer partition data located at the end of the boundary to the arithmetic and control unit and canceling the transfer of the remaining transfer partition data, it is possible to prevent the deterioration of the data transfer efficiency caused by transferring unnecessary data to the arithmetic and control unit. It was made possible.

This application is patent application 4 (Showa 62)
(February 10, 2012 application)

[Conventional technology]

In large-scale information processing systems, high-speed data processing is required in both the fields of office calculation and scientific calculation, and a high-speed buffer memory having a copy of a part of the data in the main memory in the memory controller. Is provided.

In order to obtain the data required by the arithmetic and control unit, the buffer memory in the memory control unit is first indexed, the required data is transferred from the buffer memory to the arithmetic and control unit when the required data exists, and the main memory unit when it does not exist. A block data transfer request is made to the memory controller, and the block data having the required data at the beginning is transferred to the memory control device several times. In the memory controller, this block data is written in the buffer memory and the required data at the beginning is directly transferred to the arithmetic and control unit.

Here, in order to collectively obtain the data required by the arithmetic and control unit, a block data transfer request is made to the memory control unit (hereinafter, a block data transfer request made by the arithmetic and control unit to the memory control unit is block read). It may be called a request). In this case, in the conventional data transfer control method, when the required data exists in the buffer memory in the memory control device, the required block data in the buffer memory is divided into a plurality of sections, and the transfer section on the accessed address is divided. All the required block data is transferred to the arithmetic and control unit by dividing the data into several times. If it does not exist, a block data transfer request is issued to the main memory device, the required block data read from the main memory device is divided into multiple sections, and the transfer section data at the accessed address is the first and divided into several times. Transfer to the memory controller. In the memory control unit, write this block data in the buffer memory and transfer all the required block data directly to the arithmetic and control unit in several times starting from the transfer section data on the accessed address. Was in control.

[Problems to be solved by the invention]

By the way, there is an array operation process as an example in which block read requests are frequently made for the purpose of collectively obtaining data required by the operation control device. In the field of scientific and technical computing, it is desired to perform the same processing at high speed on a large amount of array data that is regularly arranged in memory, and the data can be transferred at high speed to the arithmetic unit in the arithmetic and control unit. Therefore, the arithmetic and control unit collectively reads out necessary data by the block read request.

In this case, in the above-described conventional data transfer control method, all block data is transferred starting with the transfer division data on the accessed address. For example, if one block data is 64 bytes, as shown in FIG. 4, the block data of 64 bytes is determined by the data transfer width between the arithmetic control unit and the memory control unit (in this case, 8 bytes). ), And all block data is transferred to the arithmetic and control unit in eight times. Here, this 64-byte block data is word number 0 from the beginning of the block boundary to the end of the block boundary.
7 and the array data required by the arithmetic and control unit are continuously arranged in the memory from the address position of word number 3 in the address increasing direction, the array data required by the arithmetic and control unit by the block read request. In order to obtain all of the block data at once, a block read request is sent to the memory control device at the address corresponding to the array data 0, and it is not said that this array data 0 exists in the buffer memory in the memory control device. Regardless of the above, in the conventional data transfer control method, the transfer control data of the word number 3 of the array data 0 is set to the head of the operation control device, and subsequently the word numbers 4 to 7 (array data 0 to 4) and the word numbers All block data 0 to 2 (unnecessary data) is transferred.

At this time, the transfer division data of word numbers 0 to 2 is unnecessary data that the arithmetic control unit does not need, and the data of word numbers 0 to 2 of this unnecessary data is read from the buffer memory or the main memory device in the memory control device. However, there are drawbacks such as an increase in wasteful memory access time caused by the transfer to the arithmetic and control unit, and a process of separating necessary data from unnecessary data in the arithmetic and control unit.

Furthermore, if the required data does not exist in the buffer memory in the memory controller and the required block data is read from the main memory device, the read block data is stored in the buffer memory in the memory controller. In this case, while the block data is being written to the buffer memory, the processing of the request newly sent from the arithmetic and control unit is kept waiting in the memory control unit. Become. That is, in the arithmetic and control unit, it is expected that a block read request for reading the next continuous block data will be performed in order to continuously obtain the continuous array data after the array data 4 (array data 5, 6, ...). The processing of the new block read request is delayed because the block data including the unnecessary data is written in the buffer memory, and the efficiency of use of the buffer memory is reduced.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a data transfer control method capable of improving the data transfer efficiency by prohibiting transfer of unnecessary data to the arithmetic and control unit.

[Means for solving problems]

According to the present invention, the block data held in the buffer memory is divided into a plurality of sections by an arithmetic control unit that issues a block transfer request via a buffer memory that holds a part of the data stored in the main memory device in block units. In the data transfer control method of sequentially transferring the data of a plurality of sections having the request section among the sections divided into, when the data related to the block transfer request exists in the buffer memory, it is stored in this buffer memory. The data up to the last division of the block boundary starting from the request division among the plurality of divisions are transferred to the arithmetic control means, and when the data requested by the block transfer request is not in the buffer memory, Read the data from the main memory device up to the last partition on the block boundary starting with the requested partition and Transferred to, whereas prohibits the storage into the buffer memory of the data thus read out, continue to and storing the data in the block unit of a predetermined number of subsequent to the read data in the buffer memory.

[Action]

When the data required by the arithmetic and control unit is continuously arranged from the middle of the block boundary and the required data is obtained collectively, the transfer of the data from the beginning of the required data to the end of the block boundary And the subsequent data transfer is terminated. In addition, when the required data does not exist in the buffer memory in the memory control device and the required block data is read from the main memory device, it is prohibited to write the block data including the unnecessary data in the buffer memory, and Following the transfer up to the last data on the block boundary, consecutive n blocks of data are stored in the buffer memory.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment system of the present invention. FIG. 2 is a conceptual diagram showing a memory data format of various memories in the embodiment system of the present invention. In FIG. 2, the young address is located on the left side, and word numbers 0 to 15 indicate word identification every 8 bytes. A 64-byte boundary indicates an address position where the address is divisible by 64. Similarly, a 128-byte boundary indicates an address position where the address is divisible by 128.

First, the configuration of this embodiment system will be described with reference to FIG. This embodiment system includes a main memory device 1, a memory control device 2, and an arithmetic control device 3. Here, the main memory device 1 includes a memory unit 10 that stores instruction words, operand data, and the like, and a memory unit that is sent from the memory control device 2.
Address register holding the address to access 10
11, a data register 12 that holds the data read from the memory unit 10, and a data selection circuit 13 that selects the data transmission order of the data read to the data register 12 to the memory control device 2.

FIG. 3 shows a configuration example of the address register 11 in FIG. In the example of FIG. 3, the 0th bit is used as an instruction bit and the 1st bit and subsequent bits are used as address data. In the system of this embodiment, the 0th instruction bit is always set to "0" in a normal request, and the characteristic operation of the present invention, that is, 1 in the address register 11 at the time of reading block data from the memory unit 10. The data from the address indicated by the bit and subsequent bits to the last data on the block boundary are read, the reading of the remaining data in the block is suppressed, and the subsequent n block data (n = 1 in this embodiment) is read. "1" is set when instructing the operation of performing.

Next, the memory control device 2 holds a buffer memory 20 for holding a part of the data read from the memory unit 10 in the main memory device 1, and a request for processing various requests instructed by the arithmetic and control unit 3. A processing circuit 21, a data register 22 for holding data sent from the main memory device 1, a data selection circuit 23 for selecting the first half data and the second half data of the data register 22, and a buffer memory.
A data selection circuit 24 for selecting the data read from 20 and the data selected by the data selection circuit 23, a memory address of the data required by the arithmetic and control unit 3, and a request designation for instructing the content of the request. A request address receiving register 25 and a request designating unit receiving register 26, which respectively hold a section and a section. Arithmetic control device 3
Although not shown in the figure, it has the same configuration as that of a known arithmetic and control unit, and is also provided with a unit such as an input / output unit that needs to read data from the main memory unit. In addition, the main memory device 1, the memory control device 2, and the arithmetic control device 3
Are connected by interface lines 100 to 104.

Next, the operation of the apparatus of this embodiment will be described with reference to FIGS.

First, the data width of the data transfer path 101 from the main memory device 1 to the memory control device 2 is 16 bytes, and the data width of the data transfer path 104 from the memory control device 2 to the arithmetic and control device 3 is 8 bytes. The block size of 20 is 64 bytes, and the block size of the memory unit 10 is 12 bytes.
8 bytes. That is, the data for one block at the time of transferring the block data from the buffer memory 20 and the memory unit 10 is 64 bytes data from the 64-byte boundary in the buffer memory 20 and 12 bytes in the memory unit 10, respectively.
128-byte data from 8-byte boundary. Further, the circuit element of the main memory device 1 is slower than the circuit elements of the memory control device 2 and the arithmetic control device 3, and its machine cycle time is set to double. That is, the data transfer from the main memory device 1 is 2 when viewed from the memory control device 2.
16 bytes per machine cycle.

Now, it is assumed that the arithmetic and control unit 3 needs to fetch an instruction or an operand and sends a memory request to the memory control unit 2. Here, the arithmetic and control unit 3
A case where a normal block request is transmitted for the purpose of collectively obtaining block data including data required by the above will be described. The arithmetic and control unit 3 sends a memory address of the required data and a request designation section for designating a normal block read request to the memory control unit 2, and the contents of each are set in the request address receiving register 25 and the request designation section receiving register 26, respectively. To be done. next,
The contents of the request address receiving register 25 and the request designation unit receiving register 26 are transmitted to the request processing circuit 21. The request processing circuit 21, which has received the memory address of the required data and the contents of the request designating section for designating a normal block read request, first indexes the buffer memory 20 with the memory address of the required data. When the required data exists in the buffer memory 20, the required data is read out, and subsequently the block data is sequentially read out. That is, the block data of 64 bytes is divided into eight transfer section data of every 8 bytes, the eight transfer section data starting from the required data of 8 bytes are sequentially read out, and the arithmetic and control unit 3 is operated through the data selection circuit 24. Sent to.

If the required data does not exist in the buffer memory 20,
The request processing circuit 21 sends a block data transfer request to the main memory device 1 together with the memory address of the required data, and the memory address of the required data is stored in the address register 11.
It is set in the first bit and after. At this time, the request processing circuit 21 simultaneously sets the 0th instruction bit of the address register 11 to "0". In the main memory device 1, 128 including the required data on the memory address indicated by the first and subsequent bits of the address register 11 from the memory unit 10
128-byte data is read from the byte boundary and set in the data register 12. The block data read out to the data register 12 is passed through the data selection circuit 13 to 16
It is sent to the memory control device 2 in 8 times for each byte.

By the way, the data transfer order of the 128-byte block data to the memory control device 2 at this time is, for example, if the memory address of the required data from the operation control device 3 indicates the position corresponding to the word number 3, first the word The first 64 bytes of data are transferred in the order of numbers 3 to 7 and 0 to 2, followed by the word numbers 8 to 15 in the latter half.
64-byte data transfer is performed. That is, in the transmission order, the heads are word numbers 3 and 4 of the required data,
The second is word number 5 and 6, the third is word number 7
And 0, 4th are word numbers 1 and 2, and 5th to 8th are word numbers 8 to 15
Are sequentially transmitted in groups of two words. The block data from the memory unit 10 is sent to the memory control device 2 in this order. The memory control device 2 can send the 64-byte block data including the required data requested by the arithmetic and control unit 1 to the arithmetic and control unit 1 without time loss. Further, by sending the continuous 64-byte data to the memory control device 2 following the 64-byte data requested by the arithmetic and control unit 1, highly established data required for the subsequent access is previously stored in the buffer memory. It becomes possible to take in 20.

In the memory control device 2, each 16-byte data sent from the main memory device 1 is set in the data register 22 and selected by the data selection circuit 23 in the order of the first 8 bytes and the second 8 bytes, and the first 64 bytes are selected. The byte data is directly sent to the arithmetic and control unit 3 via the data selection circuit 24 and is written in the buffer memory 20. The latter 64 bytes of data sent from the main memory device 1 are not sent to the arithmetic and control unit 3 and are stored in the buffer memory 20.
Is written to. The above is the operation of a normal block read request.

Next, the characteristic operation of the data transfer control system of the present invention will be described. Here, it is assumed that the arithmetic and control unit 3 performs the array data processing, and the required array data is continuously arranged in the memory from the address position of the word number 3 in the address increasing direction as shown in FIG. The arithmetic and control unit 3 sends a block read request to the memory control unit 2 for the purpose of prefetching array data in order to perform high-speed processing of array data. In this case, if the above-mentioned normal block read request is sent out, in addition to the required data of word numbers 3 to 7, word number 0
Since unnecessary data up to 2 is transferred to the arithmetic and control unit 3, unnecessary memory access time is increased by reading and transferring the unnecessary data, and necessary and unnecessary data are separated in the arithmetic and control unit 3. Processing occurs. Therefore, the arithmetic and control unit 3 sends a block read request (hereinafter referred to as a block boundary block read request) instructing to terminate the data transfer at the block boundary.
That is, the arithmetic and control unit 3 sends a memory address indicating array data 0 and a request designating section for designating a block boundary block read request to the memory control unit 2, and the memory address and request designating section use the request address receiving register 25 and the request. Designated register
Set to 26 each. The contents of the request address receiving register 25 and the request designating unit receiving register 26 are transmitted to the request processing circuit 21, and the request processing circuit 21 first indexes the buffer memory 20 with the received memory address. When the required data exists in the buffer memory 20, the required data is read out, and subsequently the block data is sequentially read out. At this time, the request processing circuit 21 follows the instruction of the request designation unit that designates the received block boundary block read request,
Control is performed to read out the transfer section data up to the last transfer section data on the block boundary starting from the required data of 8 bytes out of the byte block data, and suppressing the subsequent reading of the transfer section data. In the case of this example, the transfer section data up to the word numbers 3 to 7 corresponding to the array data 0 to 4 is read out, and the transfer section data up to the word numbers 0 to 2 which is unnecessary data thereafter is not read out. . Buffer memory
The transfer section data of the word numbers 3 to 7, that is, the array data 0 to 4 read out from 20, is sent to the arithmetic and control unit 3 via the data selection circuit 24.

When the required data does not exist in the buffer memory 20, the request processing circuit 21 sends a block data transfer request to the main memory device 1 together with the memory address of the required data, and the memory address of the required data is the address register.
It is set after the 1st bit of 11. At this time, the request processing circuit 21 simultaneously sets the 0th instruction bit of the address register 11 to "1". Main memory device 1
Then, from the memory section 10 to the required data on the memory address indicated by the first bit and subsequent bits of the address register 11
128-byte data is read from the 8-byte boundary and set in the data register 12. In the data transfer to the memory control device 2, first, the required data expected by the memory control device 2 is transferred to the top, and the data is transferred to the last data on the block boundary determined by the block size of the buffer memory 20. In other words, the 12 read out to the data register 12
Each of word numbers 3 and 4, word numbers 5 and 6, and word numbers 7 and 0 in the first 64 bytes of 8-byte data
16 bytes of data are sequentially selected by the data selection circuit 13,
It is sent to the memory control device 2. The data of word numbers 1 and 2 containing only unnecessary data is not read from the data register 12 and is not sent to the memory control device 2.
Further, since the data required by the arithmetic and control unit 3 is the data of word numbers 3 to 7, when the data paired with the data of word number 7 becomes unnecessary data as in this embodiment, the data is Any data may be used. In the memory control device 2, each 16-byte data sent from the main memory device 1 is set in the data register 22 and is selected by the data selection circuit 23 in the order of the first half 8 bytes and the second half 8 bytes. The data transfer to the arithmetic and control unit 3 is performed by the request processing circuit 21 according to the instruction of the request designating unit designating the block boundary block read request.
Based on the control of 1., only the last transfer section data on the block boundary starting with the required data, that is, the transfer section data up to word numbers 3 to 7 (array data 0 to 4) is passed through the data selection circuit 24 and the arithmetic and control unit 3 Unnecessary data (data of word number 0 in the present embodiment) sent together with the data of word number 7 (array data 4).
Is not sent. The data in the buffer memory 20 is managed in units of one block data, and the data sent from the main memory device 1 is less than one block data. Therefore, the buffer memory 20 is controlled by the request processing circuit 21. Writing to is prohibited. When the main memory device 1 finishes reading the data of the word number 7 (array data 4) in the first half 64-byte data from the data register 12, the next block data following the block data requested by the arithmetic and control unit 3 continues. The latter half 64 bytes of data in the data register 12, which is the block data corresponding to, are sequentially arranged as 16-byte data of word numbers 8 and 9, word numbers 10 and 11, word numbers 12 and 13, and word numbers 14 and 15. It is selected by the data selection circuit 13 and sent to the memory control device 2 (n = 1). The latter 64 bytes of data are not sent to the arithmetic and control unit 3 as in the case of a normal block read request, and the buffer memory 20
When only the data is written to and the arithmetic and control unit 3 continuously requires the continuous array data after the array data 4 (array data 5, 6, ...), the necessary data is supplied at high speed from the buffer memory 20. It becomes possible to do.

The above is the operation of the block boundary block read request when n = 1 in the data transfer control method of the present invention.
Only the array data 0 to 4 required by the arithmetic and control unit 3 are sent to the arithmetic and control unit 3.

The above is the case where the head of the data required by the arithmetic and control unit 3 corresponds to the word number 3. For example, the head of the data required by the arithmetic and control unit 3 is the word number.
If it corresponds to 14, the data transfer from the main memory device 1 to the memory control device 2 by the block boundary block read request is performed only for the 16-byte data of word numbers 14 and 15 and the remaining word numbers. The unnecessary data of 0 to 13 is not transferred. This case corresponds to n = 0.

The value of n is determined by the configuration of the data processing device used, and the configuration of this embodiment corresponds to the case of n = 0 and n = 1. To perform the case of n ≧ 2, block data may be read from the memory unit 10 a desired number of times and written to the buffer memory 20.

〔The invention's effect〕

The present invention, as described above, when processing data in which data required by the arithmetic and control unit is continuously arranged from the middle of a block boundary, for example, when processing array data, In response to a block read request used to collectively obtain data required by the arithmetic and control unit, the arithmetic and control unit is read from the beginning of the required data to the last data of the block boundary from the buffer memory or the main memory unit. Since the function to transfer to the arithmetic and control unit is added, the unnecessary access time that occurs when the unnecessary data is read from the buffer memory or the main memory unit and transferred to the arithmetic and control unit and the data necessary and unnecessary in the arithmetic and control unit There is an effect that it is possible to reduce unnecessary processing and the like that occur in the division.

Further, if the required data does not exist in the buffer memory in the memory control device and it is necessary to read the required data from the main memory device, following the end of the transfer from the required data to the last data on the block boundary, Since immediately consecutive n blocks of data are stored in the buffer memory, there is an effect that a read request for data that has a high probability of being continuously used by the arithmetic and control unit can be promptly dealt with.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment system of the present invention. FIG. 2 is a conceptual diagram showing a memory data format. FIG. 3 is a block diagram of the address register 11 shown in FIG. FIG. 4 is an array diagram of array data. 1 ... Main memory device, 2 ... Memory control device, 3 ... Arithmetic control device, 10 ... Memory unit, 11 ... Address register, 12, 22 ... Data register, 13, 23, 24 ... Data selection Circuit, 20 …… Buffer memory, 21 …… Request processing circuit, 25 …… Request address receiving register, 26 ……
Request specification block receiving register.

Claims (1)

(57) [Claims] 1. A plurality of block data held in the buffer memory is sent to an arithmetic control unit that issues a block transfer request via a buffer memory that holds a part of data stored in a main memory device in block units. In the data transfer control method for sequentially transferring the data of a plurality of sections having the request section among the sections divided into sections, when the data related to the block transfer request is in the buffer memory, the data is stored in this buffer memory. Data is transferred to the operation control means from the request section to the last section of the block boundary among the plurality of sections being provided, and when the data requested by the block transfer request is not on the buffer memory, Data from the main memory device up to the last division of the block boundary starting from the request division is read out, and the arithmetic control is performed. Means for transferring the read data to the buffer memory,
A data transfer control method, characterized in that a predetermined number of block units of data following the read data are stored in the buffer memory.