JP2537280B2 - Device for designing circuit block layout in integrated circuit - Google Patents

Description

The present invention relates to a circuit block layout design device in an integrated circuit, and is particularly suitable for performing a circuit block layout design in a PLD with a CAD device, Further, the present invention relates to a device capable of designing a circuit block arrangement having a minimum total wiring length in a short time.

[Prior Art] A programmable logic device (PLD) is known as an IC in which a user can freely program internal wiring to realize a desired logical operation.

As shown in FIG. 2, this PLD is provided with a plurality of various logic elements, and includes a programmable logic element (PLE) 2 which is a circuit block having an input / output pin 1 and a switching element (eg MOSFET). The station (SS) is a highly-integrated circuit that has a structure in which regular stations are arranged in advance in a regular grid pattern, and the circuit can be written and rewritten.

In order to realize a desired logic by using such a PLD, the user turns on a predetermined switching element in a predetermined SS to appropriately determine the wiring direction in the SS and realize the desired logic. A wiring path is formed between the I / O pins required between PLE.

So how to place this PLE on the PLD
It is necessary to design the layout (layout) of the circuit blocks by forming a wiring path via SS between PLEs.

By the way, in order to reduce the delay time of signal transmission, it is necessary to minimize the total wiring length inside the PLD. For this purpose, it is necessary to design the layout of PLE in advance so that the total wiring length is minimized.

Therefore, there is a conventional example in which the layout of PLE can be automatically designed.

As such a conventional example, there is, for example, the simulated annealing method described on page 289 of Nikkei Electronics 1986, 7, 28 (NO 400).

In this simulated annealing method, the circuit block layout is designed so that the circuit block pair exchange is continued and the total wiring length is shortened while determining whether the circuit block pair exchange is performed by the following judgment formula. It is designed.

exp [− (E ₂ −E ₁ ) / T] ≧ R E ₁ is the evaluation function before the exchange and E ₂ is the evaluation function when the exchange is performed. T
Is a parameter and takes a value of 0 to ∞. R is a uniform random number and is 0
Takes a value of ~ 1. When Expression (1) is established, the circuit blocks are exchanged for a pair. If it does not hold, no such exchange is made.

[Problems to be Solved by the Invention]

However, in the simulated annealing method, it is determined for each circuit block based on the above formula whether or not the pair of circuit blocks should be exchanged. Therefore, the design until the final layout of the circuit block is determined. There was a problem that the time was long.
For example, it took 4.6 hours to determine the layout when the PLD has 36 circuit blocks.

In addition, if the coupling degree between PLEs is strong, it is possible to directly connect the PLEs with a dedicated line that does not pass through SS, and to configure macro circuit blocks of various sizes that reduce the wiring length and prevent delay time. It is preferable from the top. However, in the simulated annealing method, since the block arrangement is optimized by exchanging pairs of short circuit blocks having the same or almost the same size, for example, the length or width is different from each other, the size of the different sizes is different. For example, it is difficult to automatically perform the optimization of a short block layout having different vertical and horizontal lengths. Also, to reduce the wiring length on the interactive graphics screen of computer-aided design (CAD) equipment,
Manually arranging macro circuit blocks of various sizes by trial and error increases the time required for design, and if this design is performed by trial and error by manual operation, the minimum wiring length requirement may be broken. .

Therefore, in order to solve such an unsolved problem, the invention according to this application can design the layout of a circuit block for further shortening the final total wiring length of an integrated circuit in a short time. A first object of the present invention is to provide a device for designing a circuit block arrangement in an integrated circuit. Further, even when forming a plurality of circuit blocks of various sizes having different sizes, the total wiring length is shortened, and A second object is to provide a designing device that can perform layout design in a short time.

[Means for solving the problem]

In order to achieve such an object, the invention according to the present application, as shown in the basic configuration diagram of FIG. 1 (1), is an apparatus capable of designing the arrangement of circuit blocks in an integrated circuit, and wiring between the circuit blocks. The initial placement means for initially placing the circuit block by using a mass-type spring model having an attractive force according to the number, and the spring model having a reaction force according to the overlapping amount of the circuit blocks are initially placed. The rearrangement means for rearranging the circuit blocks and the rearranged circuit blocks are fitted one-to-one to the nearest reference circuit block among the regularly arranged reference circuit blocks so that the circuit blocks do not overlap. By
And an adjusting and arranging unit for adjusting and arranging the rearranged circuit blocks so that the circuit blocks are arranged regularly.

In order to achieve the second object, the invention according to claim (2) is, as shown in the basic configuration diagram of FIG. 1 (2), all or part of the circuit blocks existing in the integrated circuit. , Which is a macro circuit block in which a plurality of circuit blocks are aggregated, and circuit blocks in the macro circuit block are integrated to perform processing by the initial placement means, processing by the rearrangement means, and adjustment placement means. Integrated placement processing executing means for executing processing by
The design apparatus for circuit block arrangement in an integrated circuit according to claim 1, further comprising:

[Action]

The present invention intends to dynamically design the layout of a circuit block by using, for example, a spring model of a mass system as shown in FIG.

First, the initial arrangement of the circuit blocks is determined by utilizing the attractive force balance of the spring model of the mass system in which the attractive force is generated according to the number of wirings between the circuit blocks. This initial arrangement determines the relative position of the circuit block.

However, in this initial arrangement state, since an overlap (overlap) occurs between the circuit blocks due to attractive force, the reaction force balance of the spring model of the mass point system is used, in which the reaction force corresponding to the overlapping area is generated. Then, the overlap of the circuit blocks is removed.

Then, each of the rearranged circuit blocks is compared with each of the regularly arranged reference circuit blocks, and the rearranged circuit block is compared with the regularly arranged reference circuit blocks. The placement of the circuit blocks after the rearrangement is adjusted by fitting one-to-one to the nearest one.

When such a spring model is used, the circuit blocks in which a large number of wirings are formed are arranged closer to each other, so that the overall wiring length can be minimized.

Then, instead of individually evaluating and executing pair exchange between circuit blocks as in the simulated annealing method, the time required for layout design of circuit blocks is determined because the arrangement of all circuit blocks is dynamically determined. Can be significantly shortened. Moreover, since the geometrical adjustment is performed in the adjustment arrangement performed after the rearrangement, the arrangement of the finally obtained circuit blocks can be a desired regular arrangement.

In addition to this, the invention according to claim (2) has a high degree of coupling between the circuit blocks, that is, because many wirings are finally formed between the circuit blocks, they are arranged close to each other. A process by the initial placement means according to claim (1), wherein a plurality of circuit blocks whose powers are known before the layout design are collected before the layout design to form a macro circuit block, and the macro circuit blocks are integrated. The processing by the rearrangement means and the processing by the adjustment arrangement means are executed. As a result, the plurality of circuit blocks that form the macro circuit block are not separated from each other in the process of the placement process, so that the macro circuit blocks can be prevented from being separated from each other and the effect of reducing the total wiring length can be further enhanced. It will be possible.

〔Example〕

Next, an embodiment in which the present invention is applied to a PLD will be described in detail with reference to the accompanying drawings.

FIG. 4 shows a schematic system configuration diagram for realizing a circuit block layout design device in a PLD.

In FIG. 4, reference numeral 20 denotes a system bus composed of a data bus and a control bus. On this system bus, a database 21 holding position data of all circuit blocks on the PLD and a program for controlling the operation of the CPU are provided. A central processing unit (CPU) 23 that performs an operation for determining the optimum layout of the circuit blocks in forming the shortest wiring from the written ROM 22 and netlist data (wiring data between circuit blocks), a keyboard, Operating device 2 consisting of a mouse, etc.
4, a RAM 25 capable of storing the calculation result of the CPU, and a display device 26 such as a CRT capable of displaying a screen of a layout-designed circuit block on the screen even during the layout processing are connected.

In the present embodiment, in order to design the layout of the circuit blocks, a spring model is used in which the circuit blocks are connected by springs and an attractive force and a reaction force are assumed to work. As the spring model, for example, the third model is used. What is shown in the figure can be used.

A solid line A in FIG. 3 is an attractive force balance in which attractive force works according to the distance between the centers of the circuit blocks a1 and a2.
When the center distance between a1 and a2 is a _ij , both attractive force and reaction force are 0
Becomes This attractive force balance model is expressed by the following balance equation.

f = −c _ij (L−a _ij ) ... (1) In the formula (1) and the formulas (2) and later described below, f is an attractive force or reaction force acting between blocks, and c _ij is wiring between both blocks. The number a _ij corresponds to the center-to-center distance when the circuit blocks a ₁ and a _{2 contact} each other, that is, the diameter of the circuit block (the circuit block is represented by a circle as described later), and L is the distance between both blocks. Indicates the center-to-center distance. The value of a _ij is set in the RAM.

According to the attractive spring model shown by the solid line A, the larger the number of wirings between the two blocks is, the larger the attractive force is formed. The number of wires is obtained from the netlist data.

Next, the solid line B in FIG. 3 is a reaction force balance model in which only the reaction force acts between the blocks a1 and a2 according to the distance between the centers of the blocks.

This reaction force balance model is expressed by the following balance equation.

f = K _ij · a _ij ² / L ² (2) In the equation (2), K _ij is a constant obtained empirically. This K _{ij is} also preset in the RAM.

According to this reaction force balance model, the reaction force is inclined between both blocks, and in particular, when the center-to-center distance is smaller than the a _ij and an overlap occurs between both blocks,
It shows that a large reaction force is formed according to the overlap amount.

Further, a solid line C in the figure is an attractive force / reaction force balance model in which the solid lines A and B shown by the following equation (3) are added.

f = −c _ij (L−a _ij ) + K _ij · a _ij ² / L ² (3) Next, the operation of the embodiment of the invention described in claim (1) will be described with reference to the flowchart shown in FIG. .

In step, the CPU reads the netlist data temporarily stored in RAM. Next, ignoring the size of the circuit blocks and using the attractive force balance model represented by the solid line A in FIG. 3 between the circuit blocks having no size, for example, the initial arrangement of the circuit blocks as shown in FIG. Is performed as follows.

First, the number of wires in each circuit block is read from the netlist data (step). In step, the read number of wires (= corresponding to c _ij in the above formula) is substituted into the formula (1), and the attractive force (f) is calculated from the formula (1).
Is calculated.

Then, in step, the initial arrangement of the circuit blocks is completed by using the attractive force obtained in step to balance.

The initial arrangement shown in FIG. 6 is displayed on the screen of the display device. Then, the boundary condition of this initial arrangement is a free boundary. The numbers in the figure indicate the numbers of the circuit blocks.

According to this initial arrangement, an attractive force according to the number of wirings between the circuit blocks acts between the circuit blocks, so that the circuit blocks having a larger number of wirings are arranged closer to each other. As a result, the circuit blocks can be relatively arranged so that the final wiring distance becomes shorter.

It is also possible to give the circuit block a size and perform the initial layout without ignoring the size of the circuit block. However, since the initial placement of the circuit blocks is performed by using the attractive force balance, a large amount of overlap occurs between the circuit blocks, and as a result, the initial placement can be performed assuming that the circuit blocks are not large. It is suitable for making it easy to see.

Next, in order to remove the overlap between the circuit blocks that occurs in the layer in consideration of the size of the circuit blocks after the initial placement, balance is performed by the free boundary which is the rearrangement process of the initially placed circuit blocks. For this free boundary balance, the attractive force (balance equation given together with the reaction force) shown by the solid line C in FIG. 3 is used in which the reaction force acts according to the overlap amount (overlap amount). The rearrangement of the circuit blocks is obtained as shown in Fig. 7. This arrangement is displayed on the screen.In Fig. 7, the solid line between the centers of the circuit blocks indicates the wiring formed between the circuit blocks.

In this free boundary balance, the size of the circuit block is given by a circle (the actual shape of the circuit block is the second
As shown in the figure is short). The reason why the size of the circuit block is given by a circle in this way is that the circuit block on the display screen is easier to move than if it is in the short form, and if it is in the short form, the overlap between the circuit blocks will occur at the corners. This is because, while a circle is likely to occur, a circle does not have a corner portion and thus such an overlap can be prevented from occurring.
However, it does not prevent the free boundary balance processing and the subsequent processing from being performed in the short shape according to the actual shape of the circuit block.

This free boundary balancing procedure is performed as follows.

In the step, the center-to-center distance between the circuit blocks after the initial placement is calculated by the following equation (4).

(| X ₁ −X ₂ | ² + | Y ₁ −Y ₂ | ² ) ^1/2 (4) In equation (4), (X ₁ , Y ₁ ) and (X ₂ , Y ₂ ) are It is the center coordinates of the circuit block.

Then, the center-to-center distance, the diameter of the circuit block indicated by the a _ij , the number of wires between the circuit blocks indicated by the c _ij , and the empirically obtained characteristic value indicated by the k _ij are read ( (Step), these values are substituted into the formula (3) to calculate the attractive force or reaction force f, and the free boundary is balanced using this (step).

According to such a free boundary balance, the circuit blocks having a larger number of wirings are arranged closer to each other, so that the requirement for shortening the total wiring length is not broken and a reaction force corresponding to the overlap amount of the circuit blocks is given. Therefore, the overlap between the circuit blocks can be reduced.

By the way, in the rearrangement shape of the circuit blocks by the free boundary balance of the steps (Fig. 7), there is a large dead space where the circuit blocks do not exist, as shown by 100, and at the same time, the attraction springs cause an excess between the circuit blocks. The wrap remains. Therefore, in order to eliminate this dead space and the remaining overlap, circuit block layout is made compact (compaction).

First, in the step, the CPU displays 80 in FIG. 8 on the screen.
A short circumscribing frame that can be compressed or expanded by giving the deformation rate α shown in is displayed around the rearrangement circuit block after the free boundary balance. The circuit block also moves on the screen according to the movement of compression or expansion of the circumscribing frame.

Then, in step, the deformation rate α of the circumscribing frame is changed to the compression side. The deformation rate α can be set to different values in the X and Y directions.

In the step, the area of the dead space is calculated, and in the step, the dead space area M is compared with a predetermined value (M ₁ ). The dead space area is
CP is the area outside the circle that represents the circuit block on the screen.
It can be calculated by calculating U.

If it is determined in step that the dead space area is less than or equal to M ₁ , the dead space is considered to have been eliminated by the compaction process, and the process proceeds to the next step. In this compactification, the circuit blocks are balanced by using the balance equation of the attractive force / reaction force balance of the solid line C shown in FIG. At this time, the minimum total wiring length requirement is maintained. As a result, for example, an arrangement of circuit blocks as shown in FIG. 8 is obtained, and this is displayed on the screen.

On the other hand, in the step, the dead space area is M ₁
If it exceeds, the α is further changed to the compression side and the compacting is performed until the dead space area becomes M ₁ or less.

By the way, in this arrangement after compacting, the dead space can be eliminated, but the overlap due to the attraction spring remains, so that the overlap generated due to the attraction spring is cut immediately after the attraction spring to cut the third space. It is eliminated by the reaction force balance shown by the solid line B in the figure. Therefore, in the step, α of the circumscribing frame 80 is changed to the enlargement side, and in the step, the overlap amount between all the circuit blocks is calculated. This overlap amount ΔH is
When the radius of the circle that represents the circuit block is 1, ΔH = 2l-
It can be calculated by b _ij (b _ij is the distance between the centers of the circuit blocks). Next, at step, it is judged whether or not this overlap amount ΔH is less than or equal to a predetermined value H ₁ (for example, zero), and the reaction force spring is expanded while expanding the circumscribed frame until ΔH becomes less than or equal to the predetermined value H _1. Continue the balance used. This predetermined value
An appropriate value is selected for H ₁ as necessary, and for example, zero is usually selected.

Then, in step, when the arrangement of the circuit blocks is fixed at the time when the overlap is eliminated (ΔH = 0) and the circumscribing frame is removed, for example, the arrangement of the circuit blocks as shown in FIG. 9 is obtained, This can be shown on the display screen. The position data of the circuit block after completion of compaction is stored in the RAM.

With the compact processing described above, as shown in FIG. 9, it is possible to eliminate the dead space and overlap while maintaining the minimum requirement for the total wiring length of the circuit block.

In addition, in this free boundary balance and compactification,
Instead of using the equilibrium equation given with the attractive force / reaction force shown by the solid line C in FIG. 3, when the distance L between the circuit blocks a1 and a2 is equal to or greater than their contact position a _ij , the solid line A is used. An attractive spring model is used, and when the distance L = a _ij , it is on the broken line H, and when the distance L is less than a _ij , a reaction spring model according to a quadratic equation as shown by the solid line C is used. be able to.

Further, as another aspect of the compaction processing, after forming the circumscribing frame in the arrangement of the circuit blocks after the free boundary balance, the deformation rate α is set in the direction of compressing the circumscribing frame, and the arrangement of the circuit blocks at this time is set. It is also possible to eliminate the overlap and the dead space by executing the above with only the reaction force balance shown by the balance equation of the solid line B in FIG. In this case, since the calculation of the attractive force is not performed as compared with the compactification shown in the above-mentioned embodiment, the calculation time can be shortened, but the minimum total wiring length requirement may be broken.

Further, in the above-described embodiment, the gravitational force / reaction force balance is taken while compressing the circumscribing frame, but instead of this, the gravitational force / reaction force balance and the reaction force balance are alternately used when the circumscribing frame is compressed. It is also possible to eliminate the overlap caused by the attraction spring only by the reaction force balance by cutting the attraction spring immediately after that. In this case, since the attractive spring is cut immediately after that, the circuit block can be moved easily, and since the attractive force / reaction force balance is used, the dead space and overlap can be maintained without breaking the minimum total wiring length requirement. Can be eliminated. However, since the attraction spring is frequently cut and the reaction force balances each time, the calculation time increases accordingly.

After compaction, the circuit block arrangement is adjusted so that the circuit blocks have a regular grid shape.

The data space 21 stores absolute position data on the screen of the reference circuit blocks 110 arranged in a regular grid as shown in FIG. This grid-like arrangement corresponds to the setting position of PLE on PLD.

Therefore, in step, the CPU reads the position data of the reference circuit block of FIG. 10 from the database. The position data may include, for example, the center coordinates of a circle representing the reference circuit block.

Next, in step, the CPU reads the center coordinates on the screen of the circuit block (shown by a circle) after compaction shown in FIG. 9 for all the circuit blocks.

In the step, for each of the circuit blocks arranged in FIG. 9, calculation of the distance between the center coordinates with all of the reference circuit blocks arranged in a regular lattice shown in FIG. 10 is performed by the equation (4). Based on. Then, this calculation is executed for all the circuit blocks after compaction. Then, in step, for each of the circuit blocks after compaction shown in FIG. 9, the reference circuit block having the smallest center-to-center distance is selected from the reference circuit blocks shown in FIG. In other words, if the center-to-center distance between each circuit block after compaction and each of the regularly arranged reference circuit blocks shown in FIG. 10 is calculated, the circuit block after compaction is calculated as It can be applied to the nearest reference circuit block among the reference circuit blocks shown in FIG. 10 on a one-to-one basis. For example, 9th
Focusing on the circuit blocks 9 and 1 after compaction in the figure, the reference circuit block with the minimum center-to-center distance for 9 corresponds to B1 in FIG. 10, and the similar block for 1 is
Equivalent to B2.

Next, in step, the circuit block 1 of FIG. 9 is moved to the display position of the reference circuit block B1 of FIG. 10, and similarly the circuit block 9 is moved to the display position of B2 on the screen. If this process is executed for all the circuit blocks after compaction, the circuit blocks after compaction can be adjusted to have a grid-like arrangement. Then, as in the present embodiment, if the final arrangement of the circuit blocks is performed by the geometrical parallel movement on the screen, the circuit blocks can be arranged in a desired regular arrangement. If it is assumed that the final placement is performed using a dynamic model, the calculation will take a longer time than in the case of performing the geometrical parallel movement as in the present embodiment, and moreover, it is desired. In most cases, manual final adjustments will have to be made to ensure a regular arrangement of.

In the step, when moving the circuit block in the step, the circuit block shape is changed from a circle to a rectangle. As a result, a lattice-like arrangement of short circuit blocks is obtained as shown in FIG. 11, and this arrangement is displayed on the screen. The layout of the circuit blocks in FIG. 11 is a screen in which the display of the switching station (SS) is omitted and only the circuit blocks are emphasized.

Of course, the circuit blocks may be adjusted and arranged as they are in the form of circles, and finally the circuit blocks may be modified into a short shape.

By the above, all the processes for the layout design of the circuit block are completed.

In the subsequent steps, the circuit blocks are arranged as shown in FIG. 11 finally obtained, and after this arrangement,
The process of forming wiring between the circuit blocks arranged while determining the wiring direction in the SS existing on the PLD together with the circuit block is executed.

Next, an embodiment of the invention described in claim (2) will be described.

In this embodiment, a macro circuit block in which a plurality of circuit blocks existing in the PLD are aggregated is formed, and the macro circuit blocks are integrated, that is, the circuit blocks constituting the macro circuit block are initially arranged without being separated from each other. And so on.

Formation of such a macro circuit block is performed by connecting the circuit blocks in the X-axis and / or Y-axis directions under a multipoint constraint condition.

In this embodiment, the circuit block is constrained by 3 rows × 1 column.

It is possible to specify the circuit block to be restricted by the CPU and the direction of restriction via the operation device. In the macro circuit block, layout design is executed with other macro circuit blocks and / or unconstrained circuit blocks in a state in which the circuit blocks forming the macro circuit block are constrained so as not to be separated from each other.

FIG. 12 is a layout screen after free environment balance when three circuit blocks of the circuit blocks 5, 6, and 8 are constrained in 3 rows × 1 column to form a macro circuit block. The figure shows the layout screen after compaction processing. The initial placement, free environment balance, and compaction processing are the same as in the above embodiment.

In this free boundary balance and compaction,
Although it is balanced by attractive force / reaction force,
Under the constraint condition, the macro circuit block does not separate from the constrained direction even if the attraction force and the reaction force by the attraction spring and the reaction spring shown in FIG. Is balanced between.

Such restraint of the circuit block is executed by interrupt processing repeated every predetermined time as shown in FIG.

First, in step a, it is determined whether or not there is a binding request. In step b, the CPU is a circuit block
The X coordinates of the centers of 5, 6 and 8 are sequentially read, and in step c, the X coordinates of the center of the circuit block 6 and the circuit block are read.
A deviation from the X coordinate of the center of 5, 8 is calculated, and it is determined whether or not this deviation is zero (step d). When this deviation becomes zero, the processing is terminated and the processing of the next compaction is continued. On the other hand, if this deviation is not zero, the process moves to step e, and the circuit blocks 5 and 8 are moved so that the X coordinates of the circuit blocks 5 and 8 match the X coordinates of the circuit block 6. Although not shown in the drawing, the same restraint process is performed for the Y coordinate by the interrupt process as in the case of the X coordinate. However, in this embodiment, as is clear from FIG. 14, since the three circuit blocks 5, 6 and 8 with the constraint request are arranged in the vertical direction (the direction along the Y axis), Regarding the X coordinate, these three blocks match, so it is judged at step d in FIG. 15 whether or not the deviation is 0. Regarding the Y coordinate, the Y coordinate of the center of the adjacent circuit blocks 5 and 6 is determined. Is 2 × l (l is the radius of the circle), and the deviation of the Y coordinate of the center of the adjacent circuit blocks 6 and 8 is 2 × l. The deviation between the Y coordinate of the center of the block 6 and the Y coordinate of the center of the circuit blocks 5 and 8 is calculated, and a process of moving the circuit blocks 5 and 8 is executed so that the deviations match 2 × l.

This results in the circuit block as shown in Figures 12-14.
An arrangement in which 5,6,8 are constrained and moved as a unit is obtained.

Next, also in this embodiment, the adjustment arrangement after the completion of compaction is performed. Even in this process, the steps from
Is executed to adjust the circuit block layout after completion of compaction.

The arrangement after this adjustment arrangement is as shown in FIG.
By the way, in this arrangement, there are blank portions 170 and 171 in which circuit blocks are not arranged. It is preferable that this blank portion does not exist in order to shorten the total wiring length. This blank portion is generated by designing the layout by constraining the circuit blocks 5, 6, and 8. Therefore, in this embodiment, the circuit block after the adjustment and arrangement is readjusted in order to eliminate the blank portion. The procedure for this is shown in FIG.

After the step processing is completed, the CPU reads the position data of the circuit block after the adjustment arrangement shown in FIG. 16 (step). Then, in step, it is determined whether or not there is a blank portion. This determination can be performed as follows, for example.

The position data of the circuit block after the adjustment and arrangement is data in which the center coordinates of each unit lattice and the number of the circuit block have a one-to-one correspondence, and this content is stored in the RAM. Then, a unit lattice existing inside a blank portion of a circumscribing frame 173, which will be described later, and having no corresponding circuit block number is set as a blank portion.

In step, as shown in FIG. 16, a circumscribing frame is displayed on the screen after adjustment and arrangement. This circumscribed frame is compressible in the X-axis direction and / or the Y-axis direction.

In the step, the circuit blocks 5, 6,
Fix the position of 7 and compress the step circumscribed frame.
At this time, none of the circuit blocks move due to the compression of the circumscribing frame in the Y-axis direction. On the other hand, due to the compression of the circumscribing frame in the X-axis direction, the circuit blocks 4 and 7 move and the blank portion 1
70 is filled and the circuit block 12 moves to fill the blank portion 171.

Then, in step, it is determined whether or not there is a blank portion, and the readjustment process is continued until there is no blank portion. If it is determined that there is no blank portion, in step, the circuit block The layout is fixed and the position data of the circuit block is updated and stored in the RAM. As a result, the first
As shown in FIG. 8, a circuit block layout after readjustment is obtained in which no blank portion exists. With this arrangement, even when a macro circuit block is formed by constraining a plurality of circuit blocks, a layout design with a minimum total wiring length is possible.

Next, a second embodiment of the invention described in claim (2) will be described.

In this embodiment, the circuit blocks 6, 7, 8 and 10 are constrained by 2 rows × 2 columns. However, unlike the previous embodiment, the circuit block
Display 6,7,8,10 as a big circle. This is because the reaction force shown in FIG. 3 is weak in the vicinity of the contact points between the circuit blocks, and during free boundary balance and compaction, other circuit blocks enter this part and restrain the circuit blocks. It can be destroyed. Therefore, each of the circuit blocks 6, 7, 8, 10 shown in FIG. 19 (1) is given a great circle shape as shown in (2). As a result, an overlap occurs between the circuit blocks, and a gap into which another circuit block enters is eliminated, so that the constraint of the circuit block is not destroyed,
Layout design can be performed.

Then, initial placement, free boundary balance, compaction, and adjustment placement are executed for these circuit blocks in the same manner as in each of the above-described embodiments. FIG. 20 is a layout drawing after free boundary balancing, and FIGS. 21 and 22 are layout drawings after completion of compaction. The initial placement, free boundary balance, and compaction processing in this embodiment are executed in the same manner as in the previous embodiment. Then, the adjustment arrangement is performed by the same method as the processing shown in FIG. The circuit block after adjustment and arrangement is shown in FIG.

By the way, since the layout design is done with the circuit blocks 6, 7, 8 and 10 being constrained, after adjustment placement,
The circuit blocks 4 and 12 correspond to one unit cell, and the circuit blocks 10 and 2 are also the same. That is, the circuit blocks overlap.

Therefore, after the processing of the above steps is completed, it is determined whether or not the circuit block overlaps. This judgment is
This is executed depending on whether the circuit block shown in FIG. 22 corresponds to one circuit block shown in FIG.

If it is determined that there is circuit block overlap,
In order to remove the duplication of the circuit blocks, the circuit blocks are moved to the blank portion adjacent to the overlapping circuit block position.
In this embodiment, the circuit block 12 is moved separately from the circuit block 4, and the circuit block 2 is moved separately from the circuit block 10. At this time, it is necessary to distinguish between the circuit block that is moved and the circuit block that is not moved.
Are adjacent to the circuit block 11, they can be distinguished by giving priority to the circuit block 4. Further, since the circuit block 10 is constrained to the circuit blocks 6, 7, and 8, it is possible to give priority to the circuit block 10 and move the circuit block 2 separately from the circuit block 10.

This circuit block is moved to a blank unit cell in the direction of the center of gravity of the circuit block after the adjustment and arrangement in order to minimize the wiring length. As a result, as shown in FIG. 24, it is possible to obtain an arrangement in which overlapping circuit blocks are moved.

After that, in order to eliminate the blank portion, the processing for filling the blank unit cell is performed similarly to the processing in FIG. As a result, finally, since the overlapping circuit block and the blank unit cell do not exist, the layout of the adjustment arrangement can be obtained as shown in FIG. 25 when the wiring length is minimized.

In the present embodiment, the spring model shown in FIG. 3 is used, but the present invention is not limited to this, and it is also possible to balance forces by other balance equations. For example, as the reaction force balance, the reciprocal relation of the quadratic equation of L (f = K _ij · a _ij ² / L ² ) is used in FIG. 3, but the reciprocal relation of the cubic and quartic equations may be used. In addition, the constant K _ij can be changed appropriately.

In addition, as a balance of attractive force, a linear expression [f = -c
_ij (L−a _ij )] is used, but a non-linear expression can also be used, and c _ij can be defined as a variable that increases according to the number of wirings instead of the number of wirings between circuit blocks. .

Further, in the present embodiment, the size of the circuit block is represented by a circle in the processing after the initial placement of the circuit block, but the present invention is not limited to this, and the layout design can be performed by making the circuit block into a short shape which is the actual shape. It is also possible to execute from the initial placement.

Further, although the circuit block represented by the circle after the adjustment arrangement after the completion of the compaction is corrected to the short shape, it is also possible to perform the adjustment arrangement after the completion of the adjustment arrangement after the completion of the compaction and to execute the adjustment arrangement thereafter.

Further, it is also possible to set the number of wirings between each circuit block and the IO pad to execute the placement process such as the initial placement.

Although the circuit blocks in the initial arrangement, free boundary balance, compaction and adjustment arrangement are constrained in the embodiment of claim (2), the circuit blocks in the macro circuit block may be constrained at least after the free boundary balance. .

Further, in the present embodiment, some of the plurality of circuit blocks existing in the PLD are macro circuit blocks. However, all the circuit blocks are set to some sets of macro circuit blocks, and the macro circuit blocks are locked with other macro circuit blocks. It is also possible to perform a layout design with the macro circuit block.

In the embodiment of the multipoint constraint described above, the circuit blocks are indicated by circles, but it is needless to say that the present invention can be applied to the case where the circuit blocks are expressed in a short form and the circuit blocks in the short form are restricted. is there. In this case, the size of the constrained short macro circuit block does not necessarily have to be an integral multiple of the unconstrained circuit block, and the size of the constrained short macro circuit block can be appropriately selected. is there.

Further, in the above embodiments, the case where the present invention can be applied to the PLD has been described, but the present invention is not limited to this, and there is a problem of layout design of basic cells (comprising a plurality of unit cells) such as a gate array, SOG, and standard cells. Of course, the present invention can also be applied to this.

〔The invention's effect〕

As described above, according to the invention described in claim (1), a circuit block layout design can be designed in which the total wiring length can be made shorter and a desired regular circuit block layout can be designed in a short time. A device can be provided.

According to the invention as set forth in claim (2), even when forming macro circuit blocks of a plurality of circuit blocks of different sizes, the total wiring length can be made shorter and the layout design can be performed in a short time. A block layout design device can be provided.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a schematic configuration diagram of a PLD, FIG. 3 is a spring model diagram of a mass diameter, FIG. 4 is a schematic system configuration diagram for realizing the present invention, and FIG. A flowchart for explaining the operation of the invention described in claim (1), FIGS. 6 to 9 and 11 are layout diagrams of circuit blocks subjected to layout processing according to the invention described in claim (1), and FIG. The layout of the circuit blocks arranged in a regular grid, and FIGS. 12 to 14 and 16 are layouts of the circuit blocks arranged according to the second embodiment of the invention described in claim (2). FIG. 15 is a flow chart showing an operation capable of executing the constraint processing of the circuit block, FIG. 17 is a flow chart showing a procedure for filling a blank portion after the adjustment arrangement of the circuit block, and FIG.
Arrangement drawing of the circuit block after readjustment arrangement obtained by the process of FIG. 19, FIG. 19 is an explanatory view showing the concept of constraint of 2 rows × 2 columns, and FIGS. 20 to 25 are claims (2) FIG. 8 is a layout diagram of circuit blocks subjected to layout processing according to the second embodiment of the invention. In the figure, 1 is an input / output pin of a circuit block, 2 is a circuit block, 20 is a system bus, 21 is a database, 22 is a ROM, 2
3 is a CPU, 24 is an operating device, 25 is a RAM, and 26 is a display device.

Claims (2)

(57) [Claims] 1. An apparatus for designing the arrangement of circuit blocks in an integrated circuit, comprising: initial placement means for initially placing the circuit blocks using a mass-type spring model having an attractive force according to the number of wirings between the circuit blocks. Using a spring model having a reaction force corresponding to the overlapping amount of the circuit blocks, the rearranging means for rearranging the initially arranged circuit blocks so as to eliminate the overlapping of the initially arranged circuit blocks, and the circuit block after the rearrangement. , By applying one-to-one to the nearest reference circuit block among the regularly arranged reference circuit blocks, adjusting and arranging means for adjusting and arranging so that the arrangement of the circuit blocks after the rearrangement becomes regular, An apparatus for designing a circuit block arrangement in an integrated circuit, comprising: 2. A macro circuit block forming means for integrating all or some of the circuit blocks existing in an integrated circuit into a macro circuit block, and a circuit block in the macro circuit block. An integrated circuit processing execution means for implementing the processing by the initial arrangement means, the processing by the rearrangement means, and the processing by the adjustment arrangement means by implementing the integrated arrangement processing execution means. Circuit block layout design device.