JP2535823B2 - Hierarchical pattern layout method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pattern layout method, that is, a layout and wiring method for performing automatic diagrams such as logic diagrams and electronic circuit diagrams, or printed wiring board designs. In particular, the present invention relates to a hierarchical pattern layout method that can be suitably used when there are various patterns or restrictions in the arrangement direction, mutual position, etc. between arrangement elements.

[Conventional technology]

Conventionally, for example, in an automatic diagram system such as a logic diagram,
Limit the positions where logic elements etc. can be arranged to the positions of the grids that are assumed on the drawing, and draw the drawing symbols of the logic elements etc. from one end of the drawing in a certain direction (for example, from input terminal side to output terminal side). First, the arrangement is sequentially determined according to the connection relation between the symbols.

The procedure for determining the layout is as follows. First, each drawing symbol is divided into levels (“columns” for layout) according to the wiring relationship, starting from the input terminal, and then the front row (level) whose position has already been determined. The positioning of the drawing symbols in each column is sequentially performed by a method of minimizing the intersection of the wirings with the drawing symbols, or a method of minimizing the total length of all the wirings.

However, the above-mentioned positioning is not always performed once, and normally, the sequential determination from the input terminal side to the output terminal side and the reverse sequential determination from the output terminal side to the input terminal side are performed. By repeating it, a better arrangement is determined.

In this way, after each drawing symbol arrangement is determined,
For the first time, it is customary to determine the wiring of the connection by the line segment search method or the maze method.

Note that examples related to the above-mentioned system include, for example, Proceedings of the 30th National Congress of the Information Processing Society of Japan (first half of 1985), pages 191-1904 and 1973-1974.

[Problems to be solved by the invention]

In the arrangement and wiring of the connection between the symbols and the symbols, the above-mentioned conventional technique is, for example, that a plurality of symbols (logical elements or the like) forming a specific function such as a logical function are arranged according to a fixed arrangement pattern, or No consideration was given to the strength or weakness of the connection between the arrangement symbols, or the arrangement of the symbols according to restrictions, and for this reason, there were the following problems.

(1) Since the arrangement symbols and the connection lines between them are only treated as the relation between nodes (nodes) and arcs (branches) in the graph, the contents (functions) of logical diagrams are easy to understand. Can't understand. That is, there is a problem in viewability of the drawings.

(2) The arrangement is such that all the arrangement symbols are oriented in a fixed direction (for example, from the input terminal side to the output terminal side).

(3) Since what should be originally processed as a wiring, such as a confluence of wiring connections, is represented by a symbol such as a connection logic symbol, a redundant arrangement / wiring with a lot of blank portions results.

(4) When deciding the arrangement of the arrangement symbols, a method of setting a certain kind of objective function (evaluation function) and optimizing this is adopted, but it is possible to set a sufficiently satisfactory objective function as this objective function. Since it is difficult, it is necessary to determine the placement once and then improve the placement using another objective function.

(5) No consideration is given to speeding up by parallel processing.

An object of the present invention is to solve the above-mentioned problems in the conventional automatic layout technique, and to provide a fixed pattern in the arrangement direction or mutual position of each arrangement element such as arrangement and wiring in a logic circuit. Or, to provide an automatic layout method that makes it possible to perform placement / wiring in which the strengths and weaknesses of the connections between placement elements are present, as well as placement / wiring using an existing CAD system of skilled personnel. is there.

[Means for solving the problem]

In order to achieve the above-mentioned object, a hierarchical pattern layout method of the present invention is a process of dividing a pattern composed of a plurality of layout elements into a plurality of blocks into blocks, and further dividing each of the divided blocks into a plurality of blocks. Is a hierarchical pattern layout method in which the pattern is hierarchically divided into blocks, the placement of placement elements in each block in each hierarchy is determined, and the pattern is reconfigured. The layout element group for obtaining the function is stored as a layout pattern group in a predetermined priority order, and among the functions obtained by the arrangement of each layout element in each block in each layer, the function of the layout pattern stored in advance is Whether or not there is a match is determined in a predetermined priority order, and each allocation in each block in each hierarchy is determined. Extracting a layout pattern that matches features obtained an element arrangement of a functional arrangement of placement element in the block matching, and replaces the layout pattern above extraction.

[Action]

In the present invention, instead of placing and wiring the entire circuit,
To some extent, by limiting the placement and wiring in a narrow range,
By using a pattern in which layout elements such as logic elements and electronic parts are arranged as knowledge, layout and wiring of the entire circuit such as logic circuits and electronic circuits are performed. In other words, using the pattern in which layout elements such as logic elements and electronic parts are arranged as knowledge,
When arranging / wiring an entire circuit such as a logic circuit or an electronic circuit, each pattern corresponding to the arrangement / wiring of each circuit must be prepared, and the number of patterns to be stored in the knowledge base is huge. Becomes In addition, depending on the circuit, it is difficult to pattern the entire layout and wiring as it is. Therefore, in practice, it is difficult to place and wire the entire circuit by using the pattern as knowledge. However, it is effective to use the pattern as knowledge when the arrangement and wiring of the entire circuit are limited to a certain extent in a narrow range rather than the arrangement and wiring of the entire circuit. Therefore, in the present invention, the entire layout / wiring pattern is divided (blocked) into several blocks, each of these blocks is further divided into blocks (sub-blocks), and this block formation is repeated, thereby Arrange and wire patterns hierarchically into blocks. Then, a corresponding pattern (layout pattern) is prepared for each block in each layer and used as knowledge. As described above, in the present invention, by preparing a pattern (layout pattern) for each block, it is possible to easily perform layout / wiring using the pattern as knowledge.

That is, a set having a specific pattern can be extracted from the set of placement elements, and their placement can be laid out according to the placement pattern. Therefore, when a human recognizes an object, considering that it is recognized by various patterns obtained empirically, the problem (1)
It is considered that (3) to (3) can be solved to a large extent by the arrangement and wiring using the layout pattern.

Regarding the problem (4), there is no problem because it is not necessary to set an objective function by performing layout and wiring using a layout pattern as knowledge.
As for the problem (5), the hierarchical arrangement /
By wiring, it is possible to process the placement and wiring in parallel for each block.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In this embodiment, particularly in logic synthesis (Logic Synthisis) for generating gate logic from functional logic blocks,
Netlist information generated on the basis of the functional logic block and placement / wiring information of each logic element (placement element) obtained from the functional logic block (a connection information table 200, a placement table 210 in FIGS. Wiring table 22
The case where the arrangement and wiring of the combined gate logic circuit are determined based on the above (0) will be described as an example.

FIG. 2 is a functional block diagram of an automatic layout apparatus showing an embodiment of the present invention. In the figure, 3 is a layout processing unit, 6 is a layout pattern storage unit, 7 is an input unit,
Reference numeral 8 indicates an output unit.

 The functions of the above units will be described in detail below.

The layout processing unit 3 is a central processing unit (CP) of the computer.
U), which will be realized in the input unit 7 described later.
A structure registered in the layout / pattern storage unit 6, which will be described later, is extracted from the structure description input from
It is a function of performing layout processing of drawing elements according to a layout pattern corresponding to the structure.

The layout / pattern storage unit 6 is realized by a storage device such as a magnetic disk device, and is a portion (knowledge base) that stores various patterns regarding layout as knowledge.

The input unit 7 is a storage device such as a magnetic disk device, a magnetic tape device, a keyboard, a tablet,
This is a part for inputting the netlist of the placement / wiring target and the placement / wiring information of the original block diagram from the input device such as a card reader to the layout processing unit 3, and performs the layout process from the input device or the storage device. It has a function of inputting a target structural description (for example, a netlist such as a logic diagram or an electronic circuit diagram).

The output unit 8 arranges the output result of the layout processing unit 3.
Outputs wiring information to a storage device such as a magnetic disk device or magnetic tape device, or draws a gate logic diagram, etc. on an output device such as a display, printer, plotter, etc. based on the layout / wiring information of the output result. It is the part to do.

FIG. 1 is a processing flowchart showing the layout method of this embodiment. This processing is performed by the layout processing unit 3 described above.
Is done by.

The process 10 is placement / wiring at the highest block level, and in the present embodiment, the placement / wiring information of the original block diagram input manually is used as it is for determination. In addition,
When the placement / wiring is performed without using the existing placement / wiring information because the original block diagram does not exist, the entire set of placement elements may be the top block. In other words, it is not necessary to consider the placement / wiring at the highest block level because there is only one block.

The process 20 is a part for performing the placement / wiring process in each block whose layout has been determined (actually, the relative positional relationship has been determined) by the process 10, and is a part which can be processed in parallel for each block.

In addition, the process 20 is the sub-block level layout 2
1, a layout 22 in the sub-block, a layout 23 in the sub-block embedded in the sub-block, and a rewiring process 24 in the block. Hereinafter, each processing will be described.

The process 21 is a part for determining the arrangement / wiring of the sub-blocks in the block by using the layout pattern group 50 registered in the layout pattern storage unit 6.

The process 22 is a part for performing the placement / wiring process in each sub-block whose layout has been determined (actually, the relative positional relationship has been determined) by the process 21, and is recursively processed. That is, in the processing by the processing 22, the same processing as the processing in which the block is replaced with the sub-block in the processing 20 is repeatedly executed.

However, when the sub-block is the arrangement target element (gate) itself, of course, for the sub-block,
The processing of processing 22 and 23 is not performed.

The process 23 is a process of embedding the inside of each sub-block whose placement / wiring has been determined in the process 22 in the corresponding sub-block whose placement has been determined in the process 21. At this time, depending on the layout and wiring conditions inside the sub-block,
Enlarge or reduce the size of the sub-block (frame).

The process 24 is a part for performing the rewiring process for improving the overlapping and redundant parts of the wiring that occur when the sub-blocks are embedded. To improve the redundant wiring, for example, the rewiring means proposed by the applicant of the present invention in Japanese Patent Application No. 60-233301 may be used.

Process 30 is a part to embed the inside of each block whose placement / wiring has been determined in the process 20 in the corresponding block whose placement has been determined in process 10, and is the same process as process 23 above. is there.

The process 40 is a part similar to the process 24, which is a part for improving the overlapping of wirings and the redundant wirings which occur when the respective blocks are embedded.

The processing procedure shown in FIG. 1 is an example of laying out in a top-down manner. However, at the time of laying out a block or a sub-block, the final size of the layout is not decided, and the inside is laid out. In order to perform this processing efficiently when it is decided for the first time, the present applicant has previously proposed the automatic layout method proposed by Japanese Patent Application No. 61-75051 (see Japanese Patent Application Laid-Open No. 62-231377). Use the layout method.

On the contrary, for bottom-up layout,
In FIG. 1, the process 10 may be moved between the process 30 and the process 40, and the process 21 may be moved between the process 23 and the process 24.

The processes 20 and 30, 22 and 23, etc. in FIG. 1 are recursive processes and can be performed in parallel.

The layout pattern group 50 in FIG. 1 stores the layout pattern corresponding to each block level of each hierarchy in the layout pattern storage unit 6.

FIG. 3 shows an example of the layout pattern group 50 stored in the layout pattern storage unit 6. Fig. 3 shows II L (Integrated Injection Log).
ic) is an example of a gate level layout pattern group. The above II L is basically an II L having inverter characteristics.
It is composed of an element and a connection logic showing AND characteristics.

The layout pattern 60 is such that when there is a set of gates indicating the function of the latch in the target block, that is, 2
There are two II L elements 61, 62, and one output 6 of the II L element 61
3 is connected to the input 66 of the II L element 62, and the 1 of the II L element 62 is connected.
If two outputs 64 are connected to the input 65 of the II L element 61, indicate that the II L elements 61 and 62 are arranged close to each other, and that the wiring is wired so that the two elements cross each other. There is.

In addition, the layout pattern 70, in the target block,
When there is a set of gates showing the exclusive OR function, two II L elements 71 and 72 are arranged close to each other, and their output lines are wired so as to be connected by the connection 75, and the remaining 2 The two II L elements 73 and 74 are arranged close to each other, and their output lines are connected by the connection, 76 and wired so as to be the input of the II L element 71. Is connected to the output of another II L element output 77b and II L element 73
It is shown that the input 78a of is connected to another output 78b of the II L element connected to the output at the connection point 79 and is wired so as to be the input of the II L element 72.

In addition, the layout pattern 80, in the target block,
When the AND function exists, that is, when the outputs of a plurality of elements are the same input of a certain element, it is indicated that the output lines are connected so that the front surface thereof is aligned with the wiring 81. .

Next, the layout process using the layout pattern will be described in detail.

FIG. 4 is a flowchart showing a detailed processing example of the processing 21 which is the layout at the sub-block level in FIG. Further, FIGS. 5, 6 and 7 show
It is an example of a table used in the processing shown in the figure.

The connection information table 200 in FIG. 5 is a table that stores information on floating terminals in a block, that is, the end points of interrupted wiring and terminals to which gates are not connected, when arranging and wiring in the block. Is an example. In the connection information table 200, the first column 201 is the node name (signal name) of the floating terminal, the second column 202 is information about whether the floating terminal is an input, and the third column 203 is the floating terminal. The layout pattern information (eg, rule number, that is, the number given to the pattern) to which the () belongs, and the fourth column 204, the positional information of the floating terminal (that is, the position coordinates or a variable, or Is it a pointer to them, etc.)
To store.

In the input / output information column 202, "in" (or "1") is input when the floating terminal is input, and "out" is output when the floating terminal is output.
(Or “2”), or if there is no input / output distinction,
Stores "both" (or "0").

The arrangement table 210 shown in FIG. 6 has gates (or blocks) arranged according to the layout pattern.
Stores the placement information of. First column 211 of book placement table 210
Is the type (that is, type) of the placed gate in the second column.
In 212, the proper name of the gate, in the third column 213, the position information of the gate (ie, position coordinates and variables, or pointers pointing to them, etc.), the fourth column 21.
4, the vertical and horizontal size of the gate, the fifth column 215, rotation information such as the angular stop of the rotation of the gate, and the sixth column 216, whether the gate is reversed. Inversion information indicating whether or not it is stored.

The wiring table 220 shown in FIG. 7 shows an example of a table that stores wiring information of connections between gates (or blocks) in line segment units (straight lines without branching or joining). The first column 221 of the wiring table 220 contains the node names of the line segments of the wiring, and the second column 222 contains the position information of the start points of the line segments (ie, position coordinates and variables, or pointers pointing to them). Etc.) in the third column 223,
The position coordinates of the end point of the line segment are stored.

Next, the operation of FIG. 4 will be described using each of these tables. The tables 200, 210, 220 are each cleared by an appropriate method before the processing of FIG. 4 is performed.

The process 110 collects a (partial) netlist belonging to the target block (that is, a gate or sub-block included in the target block and their relations) in a temporary storage area for working (working memory). It is a process of embedding.

The process 120 is a boundary information setting process of setting (registering) all information relating to the input or output of another block to the target block in the connection information table 200. Here, for example, if it is an input, the connection table
The first column 201 of 200 is the node name of the input, and the second column 202
To the output (out), in the fourth column 204 the relative position of that input,
Set each. If it is an output, enter the node name of the output in the first column 201, input (in) in the second column 202,
The relative positions of the outputs are set in the columns 204, respectively.

The process 130 is a step of setting the rule number N to the initial value "1".

The process 140 is a step of extracting a portion (function, etc.) that matches the Nth layout pattern from the netlist in the temporary work storage area (working memory). If not, the process 150 is performed.

The layout pattern group 50 used in this processing is
As illustrated in FIG. 3, each pattern is rule-numbered according to the priority order of the patterns.

The process 150 is a step of adding 1 to the rule number N, and is a pre-process for applying the next layout pattern in the process 140.

The layout pattern extraction performed by these series of processing 130, 140, 150 uses unification (unification) and backtracking (backtracking) when the logic language Prolog is used.
It can be easily realized by the function. Regarding the above Prolog, WFClocksin, CSMellish: Translated by Katsuhiko Nakamura "Prolog Programming", Micro Software ("Programmin
g in Prolog ", Springer-Verlag) et al.

The process 106 is a step of deleting the portion extracted in the process 140 from the temporary work storage area (working memory).

The process 170 is a step of updating the connection information table 200 for all the floating terminals when the parts extracted in the process 140 are arranged / wired according to the corresponding layout pattern, and have already been arranged / wired. Position relative to other parts.

An example of the method for updating the connection information table 200 is shown below.

(1) When the floating terminal to be updated is an input: In the connection information table 200, the node name in the first column 201 is the same name as the floating terminal, and the input / output information in the second column 202 is output (out). ) Exists, the portion to be placed / wired is positioned so that the position represented by the positional information in the fourth column 204 of the line and the position of the floating terminal are the same, The row is deleted from the connection information table 200. If there is no corresponding row, the node name of the floating terminal to be updated, input / output information input (in), layout pattern (that is, rule number N), and position information are additionally registered in the connection information table 200.

(2) When the floating terminal to be updated is an output: In the connection information table 200, the node name in the first column 201 is the same name as the floating terminal, and the input / output information in the second column 202 is input (in ) Exists, the portion to be placed / wired is positioned so that the position represented by the positional information in the fourth column 204 of the line and the position of the floating terminal are the same, The row is deleted from the connection information table 200. If there is no corresponding row, the node name of the floating terminal to be updated, the output (out) of the input / output information, the layout pattern (that is, the rule number N), and the position information are additionally registered in the connection information table 200.

The above-mentioned positioning, that is, the method of making the two position coordinates the same is described in Japanese Patent Application No. 61-75051 by the present applicant, for example.
This can be easily realized by utilizing the automatic layout system proposed by the "Automatic layout system" (see Japanese Patent Laid-Open No. 62-231377).

The process 108 is according to the Nth layout pattern.
This is the step of arranging and wiring the matched parts, gates or sub-blocks and their wiring.
The wiring result is stored in the layout table 210 and the wiring table 220.
To each, additionally register.

The process 109 determines whether the connection information table 200 is empty, that is, no information is registered, or whether the netlist corresponding to the target block does not exist on the temporary working memory (working memory). It is a step, and if it is empty or does not exist, the processing ends,
If not, the process proceeds to step 140 to continue the iterative process.

Note that such repetitive processing can be easily realized by recursive processing by using, for example, a logic language Prolog.

The above is the description of the processing contents of the layout processing unit 3 of the present embodiment. This layout processing unit 3 also uses the logical language Pr
It can be easily achieved using olog.

In the above embodiment, the block division of the system to be laid out was not particularly described,
The block division may be performed by a skilled person, or may be performed by an automated method such as performing free extraction using a pattern as shown in FIG.

 According to this embodiment, there are the following effects.

(1) A person accumulates layout patterns in a knowledge base in advance as knowledge, so that layout / wiring based on those layout patterns can be easily realized.

(2) By registering an appropriate layout pattern in the knowledge base, each logical function is arranged and wired in a fixed pattern that is predetermined for each function, so each function in the logical diagram can be easily recognized. This makes it possible to create a logical diagram that is easy to see.

(3) Since the arrangement / wiring information of the original functional logic block is used for the arrangement / wiring of the highest level block, the reproduced logical diagram and the original functional block diagram can be easily associated with each other.
The debug efficiency of the logic diagram is improved.

(4) Since the placement / wiring is hierarchically divided by the hierarchical block formation, the processing efficiency is high, and the placement / wiring processing in a plurality of blocks in the same hierarchy can be performed in parallel, which is high speed. Automatic layout system can be realized.

(5) From the above description, it is possible to significantly reduce the man-hours conventionally required for drawing an easy-to-read logical diagram, and improve the design efficiency.

〔The invention's effect〕

As described above, according to the present invention, the arrangement and wiring can be facilitated by the hierarchical block formation, and the arrangement and wiring in the block can be performed according to the layout pattern according to the knowledge of the expert. Therefore, the following effects can be obtained. be able to.

(1) Arrangement / wiring having various patterns or restrictions in the arrangement direction or mutual position can be efficiently performed between the arrangement elements.

(2) It is possible to automate the layout and wiring similar to that of a skilled person.

(3) The processing efficiency is significantly improved by the division processing by the hierarchical layout / wiring and the layout / wiring by the layout pattern.

(4) The placement and wiring processes can be performed in parallel, and a high-speed automatic layout system can be realized.

[Brief description of drawings]

FIG. 1 is an operation flowchart showing an embodiment of a layout method according to the present invention, FIG. 2 is a block diagram showing an example of a system configuration for realizing the embodiment, and FIG. 3 is a layout pattern group used in the embodiment. FIG. 4 shows an example, FIG. 4 is a flow chart showing an example of a layout process using a layout pattern, and FIGS. 5, 6, and 7 are connection information tables and arrangements used in the layout process according to the pattern of FIG. It is a figure which shows an example of a table and a wiring table. 3: Layout processing unit, 6: Layout pattern storage unit, 7:
Input section, 8: Output section, 10: Block level layout processing, 20: Block layout processing, 30: Block embedding processing, 40: Rewiring processing between blocks, 50: Layout pattern group, 200: Connection information Table, 210: Placement table, 220: Wiring table.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Fumihiko Mori 1099 Ozenji, Aso-ku, Kawasaki City, Hitachi Systems Development Laboratory (72) Inventor Noboru Horie 111 Nishiyokotemachi, Takasaki City Takasaki Plant, Hitachi Ltd. (72) Inventor Takaaki Ito 111 Nishiyokote-cho, Takasaki City Takasaki Plant, Hitachi, Ltd. (56) References JP 61-45364 (JP, A) JP 57-128952 (JP, A)

Claims (1)

(57) [Claims] 1. A pattern comprising a plurality of arrangement elements is divided into a plurality of blocks to form a block, and each divided block is further divided into a plurality of blocks, and the above-mentioned (a) and (b) are provided. ), The pattern is hierarchically divided into blocks, the arrangement of the arrangement elements is determined for each block in each layer, and the pattern is reconfigured, which is a hierarchical pattern layout method, Arrangement of arrangement elements for obtaining a predetermined function in advance is stored as a layout pattern group in a predetermined priority order, and among the functions obtained by the arrangement of each arrangement element in each block in each hierarchy, the above-mentioned storage is performed in advance. Whether or not there is a function that matches the function of the layout pattern is determined in the above-mentioned predetermined priority order, and each layout in each block in each hierarchy is determined. Extracting a layout pattern that matches features obtained an element placement, placement of placement elements in said block matching in said functional, hierarchical pattern layout method characterized by replacing in the layout pattern above extraction.