JP2535718B2 - Multiprocessor system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a computer system having an interrupt controller for each processor module.

[0002]

2. Description of the Related Art In a conventional multiprocessor system, there is a first method by which an input / output (I / O) interface (device) interrupts a processor so that the I / O interface can supply an interrupt signal to an arbitrary processor. . In this method, an input / output (I / O) interface designates one processor, and the designated processor is supplied with an interrupt signal.

There is a second method in which the processor and the I / O interface are connected in advance by special hardware (communication circuit or the like), and each I / O interface can supply an interrupt signal only to a predetermined processor. .

In either method, the processor is provided with a one-to-one interrupt controller. Each interrupt controller outputs an interrupt signal to the corresponding processor when the I / O interface generates an interrupt request.

[0005]

However, in the first method, I
If the processor designated by the / O interface cannot accept the interrupt, the interrupt request from the I / O interface becomes a standby state, and the processing is delayed. On the other hand, in the second method, the processor and the I / O interface are connected in advance by special hardware.
Therefore, interrupt control is quite different from interrupt control in single processor systems. Therefore, it is necessary to significantly change and use the software for the single processor system.

The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the efficiency of interrupt processing.

Another object of the present invention is to provide a multiprocessor system in which when one processor cannot accept an interrupt, another processor can accept an interrupt request.

[0008]

According to the present invention, when the interrupt right control means holds the interrupt right, it outputs the interrupt signal from the corresponding interrupt controller to the corresponding processor and stops the transfer of the interrupt right. Control. Further, the interrupt temporary masking means sets a mask for an interrupt request signal from the input / output interface to the interrupt controller when the processor accesses the input / output interface, and the interrupt from the interrupt right control means when the interrupt request signal is generated. Reset the mask depending on the transfer of power.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a tightly coupled multiprocessor system according to the first embodiment of the present invention. The tightly coupled multiprocessor system includes a plurality of processor modules 1-1 to 1-n interconnected by a system bus 6. The system bus 6 has a keyboard I / O1 and a local area network (LA).
N) I / O2, floppy desk device (FDD) I / O
3. Input / output (I / O) interfaces (devices) such as hard disk drive (HDD) I / Om are connected.

Each processor module 1-1 to 1-n has a C
PU (central processing unit) 2-1 to 2-n, interrupt right control circuit 3
-1 to 3-n, interrupt controllers 4-1 to 4-n, temporary interrupt mask circuits 5-1 to 5-n, and control ports R1 to Rn.

Each of the CPUs 2-1 to 2-n has a cache memory therein as shown in FIG.
It operates in synchronization with a 33 MHz clock signal. CPU
2-1 to 2-n are controlled by a common OS (operating system) and access a shared I / O interface. Each of the CPUs 2-1 to 2-n receives the interrupt signal IA from the corresponding interrupt right control circuit 3-1 to 3-n. The CPUs 2-1 to 2-n are connected to the ports R1 to Rn and can read / write the contents of the ports R1 to Rn.

Only one of the interrupt right control circuits 3-1 to 3-n accepts an interrupt request from the I / O interface at a certain time point, and sends an interrupt signal (request) to the corresponding CPU.
Supply. The right to accept an interrupt request from the I / O interface and supply an interrupt signal to the CPU is called an "interrupt right". Interrupt right control circuit 3 having an interrupt right
-1 to 3-n supplies the interrupt signal IA to the interrupt terminals INT of the corresponding CPUs 2-1 to 2-n if there is an interrupt request from the interrupt controllers 4-1 to 4-n, and if there is no interrupt request. After a lapse of a certain time after the acquisition of the interrupt right, the interrupt right transfer signal ID is output to the interrupt right control circuits 3-2 to 3-1 of the processor modules 1-2 to 1-1 in the next stage. Interrupt right control circuits 3-1 to 3 which output the interrupt right transfer signal ID
-n loses the interrupt right, and the interrupt right control circuits 3-2 to 3-1 receiving the interrupt right transfer signal ID acquire the interrupt right. The last-stage interrupt right control circuit 3-n outputs an interrupt right transfer signal ID to the first-stage interrupt right control circuit 3-1.

The interrupt controllers 4-1 to 4-n are PICs
(Programmable interrupt controller),
Mask control, level control, priority control, vector generation, etc. for interrupt processing are performed. Although not shown in the drawing, each interrupt controller 4-1 to 4-n is connected to all the CPUs 2-1 to 2-n, and all the CPUs 2-1 to
It can be controlled by 2-n. Interrupt controller 4-1 ~
As 4-n, for example, i8259A-5 manufactured by Intel can be used.

The interrupt temporary masking circuits 5-1 to 5-n mask the interrupt signal from the I / O device in response to the interrupt right transfer signal ID.

The ports R1 to Rn are control signals for controlling the interrupt right control circuits 3-1 to 3-n and the interrupt temporary mask circuits 4-1 to 4-n, for example, signals IG and
CPU2 to make IH, SM1 to SMm active
-1 to 2-n write, interrupt right control circuit 3-1 to 3
The ports are read by the CPUs 2-1 to 2-n to detect the interrupt right instruction signal IE output from -n.

Next, the internal configuration of the interrupt right control circuit, the interrupt controller, and the interrupt mask circuit will be described.

As shown in FIG. 3, the interrupt right control circuit 3-1.
3 to 3-n are interrupt signals IB from the interrupt controllers 4-1 to 4-n, a clock CL from a clock generator (not shown), and an interrupt right transfer signal from the interrupt right control circuits 3-n to 3- (n-1). The interrupt right stop signal IG, the clear signal IH, and the initial reset signal RE from the power supply reset circuit are supplied from the ID and the ports R1 to Rn. Interrupt right control circuit 3-1
~ 3-n outputs the interrupt signal IA to the CPUs 2-1 to 2-n, and transfers the interrupt right transfer signal I to the interrupt right control circuits 3-2 to 3-1.
Output D.

The clock CL is, for example, a basic operation clock of 8 MHz. The interrupt right set signal IF is set to 1 when the system power is turned on or when the system is reset.
This is a signal for granting an interrupt right to one of the interrupt right control circuits 3-1 to 3-n, and is generated using hardware such as a pull-down / pull-up resistor. For example, the signal IF supplied to the interrupt right control circuit 3-1 is set to the active level,
The signals IF supplied to the interrupt right control circuits 3-2 to 3-n are made inactive. As a result, in the initial state, the interrupt right control circuit 3-1 acquires the interrupt right.

The interrupt right stop signal IG is a signal for stopping the transfer of the interrupt right, and is activated by the CPUs 2-1 to 2-n via the corresponding ports R1 to Rn.
When the interrupt right stop signal IG is activated, the interrupt right control circuit 3-1 stops outputting the interrupt right transfer signal ID to the interrupt right control circuit 3-2. Therefore, the interrupt right is stopped by the interrupt right control circuit 3-1 and the other interrupt right control circuit 3
-Do not move to 2-3-n. When the interrupt signal IA is output to the CPUs 2-1 to 2-n, the interrupt right control circuit automatically stops the transfer of the interrupt right.

The clear signal IH is a signal for ending the state in which the interrupt right is held, and the CPUs 2-1 to 2-n that receive the interrupt signal activate it via the corresponding ports R1 to Rn.

The initial reset signal RE is a reset signal of this circuit and becomes active when the power is turned on by the reset circuit.

The interrupt right instruction signal IE is a signal for instructing that the interrupt right is held, and the CPUs 2-1 to 2-1.
-n is a signal for confirming whether or not the processor module 1-1 to 1-n to which it belongs has the interrupt right by reading the corresponding port R1 to Rn.

The configurations of the interrupt right control circuits 3-1 to 3-n are represented by the following logical expressions (1) to (4).

IA: = IE * IB * / RE (1) IE: = input ID * / RE + IE * IB * / RE + IE * IP * / RE + IF * RE (2) IP: = IE * IB * / RE + IG * / RE + IP * / IH * / RE + IF * RE (3) ID (output): = IE * / ID (input) * / IP * / RE (4) where ": =" Is a symbol indicating the Q output of the D-type flip-flop, the left side indicates the Q output, and the right side indicates the D input. “*” Indicates a logical product (AND). “+” Indicates a logical sum (OR). “/” Indicates negation (inverter).

The clock CL is supplied to the clock inputs of the flip-flops shown in the equations (1) to (4).

Expression (1) is a logical expression showing the operation of the flip-flop for setting the interrupt signal IA. That is, when the interrupt right instruction signal IE is set and the interrupt signal IB from the corresponding interrupt controller 4-1 to 4-n becomes active, the interrupt signal IA is set in the flip-flop. At other times, the flip-flop is cleared.

Expression (2) is a logical expression showing the operation of the flip-flop which sets the interrupt right instruction signal IE and outputs it to the ports R1 to Rn. The logic circuit corresponding to the equation (2) is configured as shown in FIG. This logic circuit has a flip-flop 10, AND circuits 11 a to 11 d, an OR circuit 12, and an inverter 13. In the logic circuit of FIG. 3, when the interrupt right transfer signal ID from the previous stage becomes active, the AND circuit 11a and the OR circuit 12
The flip-flop 10 latches the active level and outputs the active level interrupt right instruction signal IE. The flip-flop 10 maintains the set state only while the interrupt signal IB is active or the signal IP is output.

The signal IP is a signal for holding the interrupt right in the interrupt right control circuits 3-1 to 3-n as shown in the equation (3), and the interrupt right control circuit is in the active level period of the signal IP. 3-1 to 3-n hold the interrupt right without yielding it to others.

Expression (3) is a logical expression showing the operation of the flip-flop for setting the signal IP. That is, when the interrupt right instruction signal IE is set and the interrupt signal IB from the corresponding interrupt controller 4-1 to 4-n becomes active or the interrupt right stop signal IG becomes active, the signal IP Is set. The flip-flop maintains the set state until the clear signal IH becomes active. The logic circuit corresponding to the equation (3) is configured as shown in FIG. This logic circuit includes a flip-flop 30, AND circuits 31a to 31d, and an OR circuit 3.
2 and inverters 33a and 33b.

Expression (4) is a logical expression showing the operation of the flip-flop for setting the interrupt right transfer signal ID. That is, the interrupt right instruction signal IE is set, and the interrupt signal IB from the corresponding interrupt controller 4-1 to 4-n.
Is inactive and the interrupt right stop signal IP is at the inactive level, the interrupt right transfer signal ID is set.

When both the interrupt right set signal IF and the reset signal RE are active, the interrupt right instruction signal IE
And the interrupt right stop signal IG becomes active. On the other hand, when the interrupt right set signal IF is inactive and the initial reset signal RE is active, the interrupt right control circuits 3-1 to 3-n.
All of the four flip-flops constituting each of the above are cleared.

FIG. 6 shows input / output signals of the interrupt temporary mask circuits 5-1 to 5-n. The interrupt temporary mask circuits 5-1 to 5-n receive the interrupt request signals IR1 to IRm, the clock CL, the interrupt right transfer signal ID, the initial reset signal RE, and the temporary mask set signals SM1 to SMm, and the corresponding interrupt controller 4- The interrupt signals IM1 to IMm are output to 1 to 4-n.

The interrupt request signals IR1 to IRm are supplied from the I / O interface via the system bus 6. In the example of FIG. 1, the interrupt signal IR1 is the keyboard I
The interrupt signal from / O1 and the interrupt signal IR2 are LANI
The interrupt signal and the interrupt signal IR3 from / O2 are the interrupt signal and the interrupt signal I from the floppy desk device I / O3.
Rm corresponds to an interrupt signal from the hard disk device I / Om. Temporary mask set signals SM1 to SM
m is a signal for setting a temporary mask of the interrupt signals IR1 to IRm, respectively, and CPUs 2-1 to 2-n
It becomes active by accessing ports R1 to Rn.

The respective configurations of the interrupt temporary mask circuits 5-1 to 5-n are represented by logical expressions (5) to (10).

IM1 = IR1 * / MS1 (5) IM2 = IR2 * / MS1 (6) ... IMm = IRm * / MS1 (7) MS1: = SM1 * / R + MS1 * / IR1 * / R + MS1 * / ID * / R (8) MS2: = SM2 * / R + MS2 * / IR2 * / R + MS2 * / ID * / R (9) ..................... MSm: = SMm * / R + MSm * / IRm * / R + MSm * / ID * / R (10) Here, “: =” is a symbol indicating the Q output of the D-type flip-flop, the left side indicates the Q output, and the right side indicates the D input. “*” Indicates a logical product (AND). “+” Indicates a logical sum (OR). “/” Indicates negation (inverter).

As shown in equations (5) to (7), the interrupt request signals IR1 to IRm are active and the corresponding interrupt temporary mask flip-flops MS1 to MSm are provided.
Interrupt signals IM1 to IMm when is cleared
Becomes active.

Expressions (8) to (10) are logical expressions showing the operation of the interrupt temporary mask flip-flops MS1 to MSm. That is, the flip-flops MS1 to MSm are set when the temporary mask set signals SM1 to SMm are active, and both the interrupt request signals IR1 to IRm from the I / O interface and the interrupt right transfer signal ID to the next stage are active. Maintain the set state until. When the initial reset signal RE is active, all the flip-flops MS1 to MSm are cleared.

FIG. 7 shows a specific example of the logic circuit corresponding to the logical expressions (5) and (8). This logic circuit has a flip-flop 20, AND circuits 21a to 21d, an OR circuit 22, and inverters 23a to 23c. The flip-flop MS1 is set through the AND circuit 21b and the OR circuit 22 when the temporary mask set signal SM1 becomes active. When both the interrupt request signal IR1 and the interrupt right transfer signal ID become active, the flip-flop 20 is reset and the AND circuit 21a outputs the interrupt signal IM1 to the interrupt controller 4-1.

Next, referring to FIG. 8, CPUs 2-1 to 2-1
-n interrupt operation is explained. When the CPUs 2-1 to 2-n receive the interrupt signal IA, the transfer of the interrupt right is stopped by the corresponding interrupt right control circuit (step P1). Next, the CPUs 2-1 to 2-n have the interrupt controllers 4-1 to 4
-n is accessed and the content of the interrupt is specified (step P
1).

Next, the CPUs 2-1 to 2-n access the port R of the other processor module and set the temporary mask set signal SM for temporarily masking the interrupt from the I / O interface (step P2). ). For example, when the CPU 2-1 receives an interrupt from the floppy desk device I / O3, another processor module 1
The ports R2 to Rn of -2 to 1-n are accessed, and the temporary mask set signal SM3 for temporarily masking the interrupt request IR3 from the floppy desk device I / O3 is set.
This is because interrupt requests from the same I / O interface are accepted by the same processor module as much as possible, and the stored contents of the cache memory in the CPU are effectively used.

Next, the CPUs 2-1 to 2-n perform interrupt processing (step P3). When the interrupt processing is completed, the clear signal IH is set to the active level (step P4).
Then, the interrupt right transfer signal ID becomes the active level, and the interrupt right is transferred to the interrupt right control circuits 3-1 to 3-n in the next stage.

When the interrupt request from the I / O for which the temporary mask is set becomes active and the interrupt right goes around, the temporary mask is reset. That is, the interrupt to the CPU for which the temporary mask is not set is prioritized while the interrupt right goes around after the interrupt request is generated.

Next, the operation of the interrupt right control circuits 3-1 to 3-n will be described with reference to the flowchart of FIG. As shown in step S1, the interrupt right control circuits 3-1 to 3-n output the interrupt right transfer signal ID to the interrupt right control circuit of the next stage at regular time intervals. When the interrupt right transfer signal ID supplied from the previous stage becomes active, the interrupt right instruction signal IE is set according to the condition of the logical expression (2), and the interrupt transfer signal ID to the next stage according to the condition of the logical expression (4). Becomes active. As a result, the interrupt right is sequentially transferred to the interrupt right control circuits 3-1, 3-2, ..., 3-n, 3-1 ,.

When the interrupt right control circuits 3-1 to 3-n hold the interrupt right, the corresponding interrupt controller 4
When the interrupt signal IB is input from -1 to 4-n (YES in step S2, YES in S3), the interrupt signal IA is output to the corresponding CPU 2-1 to 2-n (step S4). That is, according to the logical expression (1), when the interrupt right instruction signal IE is set and the interrupt signal IB from the interrupt controllers 4-1 to 4-n becomes active, the corresponding C
An interrupt signal IA is output to PU2-1 to 2-n.

At this time, the interrupt right control circuits 3-1 to 3-n stop transferring the interrupt right and continue to hold the interrupt right (step S5). That is, according to the logical expression (3), at the same time that the interrupt signal IA becomes active, the signal IP is set, the interrupt right transfer signal ID is fixed at the non-active level, and transfer of the interrupt right to the next stage is stopped.

When the CPUs 2-1 to 2-n end the interrupt processing by accessing the I / O interface or the like, C
PU2-1 to 2-n set the clear signal IH to the active level. Then, the input D of the flop flop becomes the non-active level, and the signal IP becomes the non-active level. As a result, the interrupt right transfer signal ID becomes the active level, and the interrupt right is transferred to the interrupt right control circuits 3-1 to 3-n in the next stage (YES in step S6).

Next, the operation of the interrupt temporary mask circuits 5-1 to 5-n will be described with reference to FIG. Interrupt request signal IR1 from I / O interface I / O1 to I / On
When ~ IRm is output (YE in step S12)
S), each of the interrupt temporary mask circuits 5-1 to 5-n outputs the interrupt request signals IR1 to IRm as they are unless the corresponding temporary mask set signals SM1 to SMm are set. Supply to. On the other hand, if the corresponding temporary mask set signals SM1 to SMm are set, the interrupt request signals IR1 to IRm are not supplied to the interrupt controller. For example, the temporary mask set signal S
In the state where the temporary mask is set by M1, even if the interrupt request signal IR1 is supplied, it is not supplied to the interrupt controller (YES in step S13).

At this time, if the interrupt right is transferred to the processor module of the next stage (YES in step S14),
The set temporary mask set signal SM is reset (step S15). At this point, step S1
The interrupt request signal IM blocked in 3 is supplied to the interrupt controller (step S16).

Next, the operation of the interrupt controller will be described. When the interrupt request signals IR1 to IRm are received, they are compared with the interrupt level set in the controller. If the interrupt level specified by the interrupt request signals IR1 to IRm is lower than the set interrupt level, the interrupt request is ignored. If the interrupt level specified by the interrupt request signals IR1 to IRm is higher than the set interrupt level, an interrupt vector or the like is generated based on the interrupt request signal and the interrupt signal IB is output.

Next, the operation of the entire multiprocessor system of this embodiment will be described with reference to FIGS.

First, when the system power is turned on, the CPU
An initial reset signal RE is supplied to 2-1 to 2-n, interrupt controllers 4-1 to 4-n, interrupt temporary mask circuits 5-1 to 5-n, and ports R1 to Rn, and these circuits are initially reset. It

On the other hand, one of the interrupt right control circuits 3-1 to 3-n (assuming the interrupt right control circuit 3-1) receives an active level interrupt right set signal IF together with the initial reset signal RE. Supplied. Therefore, the interrupt right instruction signal IE becomes the active level. The other interrupt right control circuits 3-2 to 3-n are supplied with the initial reset signal RE and the non-active level interrupt right set signal IF, and the interrupt right instruction signal IE becomes the non-active level. By the above operation, the interrupt right control circuit 3-1 holds the interrupt right in the initial state.

In synchronization with the rising of the clock CL, the interrupt right transfer signal ID output from the interrupt right control circuit 3-1 becomes active level, and the interrupt right control circuit 3-2 acquires the interrupt right. After that, the interrupt right is sequentially transferred in response to the clock CL.

It is assumed that the LAN I / O2 issues an interrupt request IR2 while the interrupt right control circuit 3-1 holds the interrupt right. The interrupt request IR2 is supplied to all the interrupt temporary mask circuits 5-1 to 5-n. Assuming that the temporary mask set signals SM1 to SMm are not set at this point, the mask circuits 5-1 to 5-n commonly supply the interrupt request IM2 to the interrupt controllers 4-1 to 4-n.

The interrupt controllers 4-1 to 4-n are LAN
Receives interrupt request IR2 from I / O2, controls the level,
Performs mask control, interrupt vector generation, etc.

For example, when the interrupt request mask is set in the interrupt controller 4-4, the interrupt controller 4-4 masks all input interrupt requests. Also, the priority level of the interrupt request is 3, and the interrupt permission level set in the interrupt controller 4-3 has a priority level of 4.
In case of (higher than priority 3), interrupt controller 4-3
Ignores the interrupt request. For example, when the priority of the interrupt request is 3 and the interrupt allowable level set in the interrupt controller 4-1 is priority 2 (lower than priority 3), the interrupt controller 4-1 sends the interrupt signal IB to the interrupt right. The control circuit 3-1 is reached. As described above, since the interrupt right control circuit 3-1 has the interrupt right, the interrupt right control circuit 3-1 supplies the interrupt signal IA to the CPU 2-1.

The other interrupt right control circuits 3-2 to 3-n also have a possibility of receiving the interrupt signal IB, but since they do not have the interrupt right, the interrupt signal IA is sent to the CPU.
Do not output to 2-2 to 2-n.

In response to the interrupt signal IA, the CPU 2-1
Is a temporary mask set signal S through the ports R2 to Rn.
Activate M2. As a result, the other processor modules 1-2 to 1-n cannot receive the interrupt request from the LAN I / O2. Next, CPU2-1
Accesses LAN I / O2 to execute interrupt processing, and then activates the clear signal IH through the port R1. As a result, again, the interrupt right is sequentially transferred through the interrupt control circuit.

It is assumed that the LAN I / O2 reissues the interrupt request IR2 when the interrupt right control circuit 3-2 has the interrupt right. In this case, as described above, port R
Since the active level temporary masks are set in 2 to Rn, this interrupt request IR2 is blocked by the interrupt temporary mask circuit 5-2. At the time when the interrupt right control circuit 3-2 outputs the interrupt right transfer signal ID, the temporary mask set signal SM2 set in the port R2 is reset and the signal IM2 is supplied to the interrupt controller 4-2. However, at this point of time, the interrupt right control circuit 3-2 does not have the interrupt right, so that it cannot receive the interrupt request from the LAN I / O2. The same operation is repeated in the processor modules 1-3 to 1-n, and when the interrupt right control circuit 3-1 has the interrupt right, this interrupt request is accepted. The CPU 2-1 makes effective use of the data in the cache memory to execute interrupt processing. If the allowable level priority set in the interrupt controllers 4-1 to 4-n is higher than the interrupt priority of LAN I / O2, the other CPUs 2-2 to 2-n are LA
An interrupt from NI / O2 will be accepted.

Further, regardless of whether the CPU requests an interrupt,
When accessing the interrupt controller or the interrupt temporary mask circuit, the interrupt right stop signal IG of the interrupt right control circuit of its own stage is activated, and then the interrupt right instruction signal IE is confirmed to be active. Can access interrupt resources such as an interrupt controller including other modules and an interrupt temporary mask circuit.

According to this embodiment, when an interrupt request from the I / O interface occurs, the processor that can accept the interrupt can immediately accept the interrupt request. Further, by controlling the transfer of the interrupt right of the interrupt right control circuits 3-1 to 3-n, the interrupt related resources (each circuit necessary for interrupt processing) can be exclusively processed. Therefore, the conflict of interrupt access by each processor can be resolved.

Further, the processor that has accepted the interrupt request can preferentially accept the next interrupt request by setting the temporary mask set signal in the interrupt temporary mask circuit of another processor module.

The present invention is not limited to the above embodiment. For example, in the first embodiment, the interrupt temporary mask circuit 5
Resets the temporary mask set signal when transferring the interrupt right to the processor module of the next stage. The present invention is not limited to this, and for example, the temporary mask set signal may be reset when the interrupt right makes two or three cycles through the interrupt right control circuit, or the temporary mask set signal becomes constant after being activated. The temporary mask set signal may be reset after a lapse of time.

(Second Embodiment) In the first embodiment, the processors (CPU) 2-1 to 2-n are used.
Can mask interrupt requests by programming the interrupt controllers 4-1 to 4-n. On the other hand, the processors 2-1 to 2-n can quickly inhibit all external interrupts without controlling the interrupt controller by using the interrupt inhibit instruction provided in the CPU itself.

In the multiprocessor system of FIG. 1, when the external interrupt prohibition instruction of the processor itself is used, the CPU does not accept the interrupt signal in the state where the interrupt signal IA is supplied from the interrupt right control circuit to the CPU. However, even if another CPU can process the interrupt request, the interrupt request is made to wait. In order to solve this problem, it is necessary to program the interrupt controller to disable interrupts from all I / O external interfaces even when the CPU uses its own external interrupt disable instruction.

Moreover, in a multitasking, multiuser operating system such as UNIX, the CPU
Although the period is short, all the external interrupts are disabled. Therefore, the configuration of the first embodiment may not provide the desired performance. Therefore, in the second embodiment of the present invention, by providing a mask circuit between the interrupt controller and the interrupt right control circuit, it is possible to prohibit all interrupts or release the prohibition.

FIG. 11 shows an example of the configuration of the processor module according to the second embodiment. In addition, in FIG.
The same reference numerals are attached to the portions corresponding to the configuration of FIG.

In FIG. 11, the CPU 2 executes C shown in FIG.
The function is basically the same as the PU configuration, but disables all external interrupts or cancels the interrupt disabled state.
It also has a function of setting signals SETMASK and CLRMASK, which will be described later. The configurations of the interrupt right transfer control circuit and the temporary mask circuit are the same as those in FIG.

As shown in FIG. 12, the mask circuit 100 receives the clock signal CL, the interrupt signal IB output from the interrupt controller 4, the mask setting signal SETMASK, the mask release signal CLMASK and the reset signal RE,
The interrupt signal IB ′ is supplied to the interrupt control circuit 3. Mask setting signal SETMASK and mask release signal CLMAS
K is supplied from the port R, for example. The mask setting signal SETMASK is set to an active level by the CPU 2 itself when the CPU 2 prohibits all external interrupts by the interrupt prohibition instruction. Mask release signal CLR
MASK is set to an active level by the CPU 2 itself when the CPU 2 releases the interrupt disabled state.

The mask circuit 100 has a logical formula (1
1) and (12).

IB ′ = IB * / MASK (11) MASK: = SETMASK * / RE + MASK * / RE * / CLRMASK (12) Here, the left side of “=” indicates the logical output of the right side, and “ :
“=” Is a symbol indicating the Q output of the D-type flip-flop, the left side indicates the Q output, and the right side indicates the D input. "*"
Indicates a logical product (AND). “+” Indicates a logical sum (OR). “/” Indicates negation (inverter). The clock input of the D-type flip-flop is the clock signal CL.

The logic circuit corresponding to equations (11) and (12) is constructed as shown in FIG. In the second embodiment, the CPU 2 uses the mask setting signal SETMASK or the mask release signal CL when the external interrupt is prohibited or canceled by the interrupt prohibition instruction or the cancellation instruction.
Set RMASK. Mask setting signal SETMASK
Is set, the interrupt signal IB is blocked by the mask circuit 100 and does not reach the CPU 2.

According to this embodiment, all the interrupts can be prohibited and the interrupt prohibited state can be canceled by a simple operation.
When the CPU 2 is operating under an operating system such as UNIX that frequently sets "a state in which all interrupts are prohibited", the present invention is very effective for appropriately processing interrupt requests. Further, in a multiprocessor system, an interrupt function between processors is frequently required. If one processor interrupts another, it must have all external interrupts disabled. Therefore, the configuration of this embodiment is very effective in a multiprocessor system.

[0075]

As described above in detail, according to the present invention, I
The interrupt request from the / O interface is greatly reduced in waiting state, and the efficiency of interrupt processing is improved. Further, since the processor and the I / O interface are not connected by special hardware, the software for interrupt control of the multiprocessor system can be developed by slightly changing the software for the single processor. Further, even if the processor itself has a function of prohibiting all external interrupts, the interrupt request can be appropriately processed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a CPU.

FIG. 3 is a diagram for explaining input / output signals of an interrupt right control circuit.

FIG. 4 is a circuit diagram illustrating a configuration of an interrupt right control circuit.

FIG. 5 is a circuit diagram for explaining a configuration of an interrupt right control circuit.

FIG. 6 is a diagram for explaining input / output signals of an interrupt mask circuit.

FIG. 7 is a circuit diagram illustrating a configuration of an interrupt mask circuit.

FIG. 8 is a flowchart for explaining the operation of the CPU.

FIG. 9 is a flowchart for explaining the operation of the interrupt right control circuit.

FIG. 10 is a flowchart for explaining the operation of the interrupt mask circuit.

FIG. 11 is a block diagram of a processor module according to a second embodiment of the present invention.

FIG. 12 is a diagram for explaining input / output signals of a mask circuit.

FIG. 13 is a logic circuit diagram showing a configuration of a mask circuit.

[Explanation of symbols]

1-1 to 1-n ... Processor module, 2 and 2-1 to 2-n ...
CPU 3, 3-1 to 3-n ... Interrupt right control circuit 4, 4-1
... 4-n ... Interrupt controller 5, 5-1-5-n ... Interrupt mask circuit, 6 ... System bus, I / O1 ... Keyboard, I / O2 ... LAN, I / O3 ... Floppy desk device, I / Om … Hard desk device, 100… mask circuit.

Claims (2)

(57) [Claims] 1.Each processor module has an input / output interface
Multi that receives the interrupt signal output from the face
In the processor system, Each of the processor modules is A processor, Interrupt signal output from the input / output interface
Of the types specified by the processor.
The output of the embedded signal is temporarily masked and not masked.
An interrupt temporary masking means for outputting an embedded signal, The interrupt is output from the interrupt temporary masking means.
An interrupt controller that receives a signal and outputs an interrupt signal
Laura, Interrupt right to other processor modules at regular intervals
When delegating and holding the interrupt right,
The interrupt signal output from the interrupt controller
Output to the processor and transfer of the interrupt right
And an interrupt right control means for stopping.
Multiprocessor system to do. (2)Each processor module has an input / output interface
Multi that receives the interrupt signal output from the face
In the processor system, Each of the processor modules is Means to accept external interrupt signals and disable external interrupts
A processor having instructions and Interrupt signal output from the input / output interface
Of the types specified by the processor.
The output of the embedded signal is temporarily masked and not masked.
An interrupt temporary masking means for outputting an embedded signal, The interrupt output from the interrupt temporary masking means
Only the interrupt signal that receives the interrupt signal and outputs the interrupt signal.
With a trawler The processor executes the external interrupt disable instruction
Set by the interrupt controller
Masking means for masking output of input interrupt signal
When, Interrupt right to other processor modules at regular intervals
When delegating and holding the interrupt right,
The interrupt signal output from the mask means is sent to the processor.
Output to the server and stop the transfer of the interrupt right.
A multi-unit, which is equipped with a right to control
Processor system.