JP2526287B2 - Arithmetic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Concerning an arithmetic circuit for performing arithmetic operations such as cumulative multiplication, it is possible to perform continuous cumulative arithmetic processing to speed up the arithmetic speed and to execute rounding processing with a small circuit configuration. For the purpose of making it possible, the accumulator, the shifter that shifts the bit position of the accumulated value accumulated in the accumulator, and the initial value for the predetermined rounding processing according to the shift number of the shifter are set to the shift number of the shifter. Depending on the initial value generating section, the selecting section that selects and outputs the cumulative value from the accumulator or the initial value from the initial value generating section, the input value and the output value of the selecting section are added, and the addition result is displayed. And an adder for storing in the accumulator, and the selection unit selects the initial value from the initial value generation unit instead of the accumulated value from the accumulator and outputs it to the adder. Is configured as follows.

[Field of Industrial Application] The present invention relates to an arithmetic circuit for performing arithmetic operations such as cumulative multiplication.

This kind of arithmetic circuit is used, for example, in a cumulative multiplication process between pixel blocks in an image signal processor or the like or in a DCT.
It is used to perform cumulative multiplication processing between the difference pixel and the coefficient such as (discrete cosine transform).

In image signal processing, n × n for motion compensation
(N = 4,8 ...) Cumulative addition for matching processing of pixel block and predetermined pattern block, or DC
The product-sum operation of the difference pixel and a predetermined coefficient is required for T processing, etc., but with the recent demand for high-speed pixel signal processing, these operation processes can be performed at high speed by a digital signal processing circuit. In addition, it is necessary to be able to realize with a small circuit scale.

[Prior Art] FIG. 6 shows a conventional arithmetic circuit for performing cumulative arithmetic operation of this kind of image signal processing. In the figure, a value (image data) D and a value (pattern data) C to be multiplied are set in a register 1 and a register 2, respectively, and are multiplied by a multiplier 3 in the next clock cycle to obtain the multiplied value C × D. Are stored in the register 4. Next, the value C × D of the register 4 is added by the adder 5 with the cumulative addition value Σ (C · D) of the accumulator (register) 61, and the addition result value Σ (C · D)
D) is stored again in the accumulator 61. That is, Is calculated. By performing such arithmetic processing for each pixel of the n × n pixel block in n × n clock cycles, the cumulative addition value is obtained as the final result. Is found. The cumulative addition value is further input to the shifter 8 and shifted by the desired number of bits set in the shift number setting register 9 to obtain data of a predetermined word length. Rounding processing (usually 1/2 LSB when making data of this predetermined word length
If "1" is not rounded off, it will cause a flicker of the reproduced image. Therefore, after the rounding processing circuit 11 performs the rounding processing, the result is stored in the register 10.

The calculation timing of this conventional circuit is shown in the timing chart of FIG. As can be seen from this figure, the cumulative addition value of a certain pixel block stored in the accumulator 61 is cleared by the clear clock for the cumulative addition of the next pixel block during the processing between that pixel block and the next pixel block. Must be cleared according to CLRC.

[Problems to be Solved by the Invention] In an arithmetic circuit having a conventional configuration, a clock cycle for clearing the contents of the accumulator 61 requires one cycle in addition to the cycle for accumulative arithmetic processing. Is lost and an extra time is required for the one cycle, so that the calculation speed is reduced.

Further, when the cumulative operation result is rounded, the rounding processing circuit 11 is required as independent hardware, but since the rounding processing circuit 11 is generally configured to include an adding circuit, its circuit scale becomes large. There is a problem.

Therefore, an object of the present invention is to enable continuous cumulative calculation processing to increase the calculation speed and also to execute rounding processing with a small circuit configuration.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention.

The arithmetic circuit according to the present invention includes an accumulator 21, a shifter 24 that shifts the bit position of the accumulated value accumulated in the accumulator 21, and an initial value for a predetermined rounding process that corresponds to the shift number of the shifter. , An input value and an output value of the selection unit 22 are added, and a selection unit 22 that selects and outputs the accumulated value from the accumulator 21 or the initial value from the initial value generation unit is added. The adder 23 stores the addition result in the accumulator 21, and the selector 22 selects the initial value from the initial value generator in place of the accumulated value from the accumulator in response to the initialization signal and outputs the result to the adder 23. It is configured to output.

[Operation] When the cumulative addition value of one cumulative operation cycle is obtained, the initialization signal is input to the selection circuit 22 at the beginning of the cumulative operation, whereby the selection circuit 22 selects the initial value and outputs it to the adder 23. The adder 23 adds the initial value (normally zero when the data shift is not performed by the shifter 24) and the input value, and stores the addition result in the accumulator 21.

After that, the selection circuit 22 selects the cumulative value from the accumulator 21 and performs cumulative addition with the input value. This eliminates the need for an independent clock cycle for clearing the accumulated value of the accumulator 21, so that continuity of operations is maintained and the operation speed is increased.

When the shifter 24 shifts the accumulated result data to make the data length a predetermined length, the selection circuit 22 selects an initial value for rounding processing according to the number of shifts in the shifter 24. As a result, rounding processing can be performed equivalently on the accumulated value after data shift, and a dedicated hardware circuit for rounding processing can be eliminated.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an arithmetic circuit as an embodiment of the present invention. In the figure, the circuits designated by the same reference numerals as those of the arithmetic circuit of FIG. 6 described above indicate circuits having the same function.

The difference is that in the circuit of this embodiment, the accumulator (register) 6 does not have a clear function, and the accumulated value from the accumulator 6 is input to the adder 5 via the initialization circuit 7. The set shift number NSF is input from the shift number setting register 9 to the initialization circuit 7. The circuit of this embodiment does not have the rounding circuit 11.

A configuration example of the initialization circuit 7 is shown in FIG. As shown in the figure, the initialization circuit 7 includes a selector 71 and a decoder 72. The selector 71 normally selects and outputs the cumulative value Σ from the accumulator 6, but when the initialization clock INIC is input, the decoder 71 It is configured to selectively output the initial value INI from 72. The decoder 72 changes the output initial value INI according to the set shift number NSF from the shift number setting register 9, and FIG. 4 shows the relationship between the shift number NSF and the output initial value INI. That is, the number of shifts N
When SF is zero, the initial value INI is also zero, but when the 1-bit right shift is executed by the shifter 8, the initial value INI is LSB only "1" and other bits are all "0" data and shift When the number is "l", only the "l" th bit from the lower order is "1" and the others are all "0".

The operation of the circuit of this embodiment will be described below with reference to the operation timing chart of FIG.

Now, as a new operation cycle, the data D ₁ and C ₁ set in the registers 1 and 2 are multiplied by the multiplier 3,
The multiplication result value (C / D) ₁ is stored in the register 4, and the accumulator 6 has the final cumulative addition value of the previous operation cycle. Is stored, and the initialization clock INIC is input to the initialization circuit 7 in this state.

Then, in the initialization circuit 7, the selector 71 selects the initial value INI from the decoder 72 and outputs it to the adder 5. This initial value INI is a value corresponding to the shift number NSF as shown in FIG. 4, but the shift number is now zero and the initial value INI
Is also zero. Therefore, the signal input to the adder 5 is “0” and (C · D) ₁ and the addition result Are stored in the accumulator 6.

After that, the initialization clock is turned off, so that the initialization circuit 7 selects the cumulative addition value Σ from the accumulator 6 and inputs it to the adder 5 to sequentially perform cumulative addition. By performing such an operation, a separate and independent one clock cycle for clearing the contents of the accumulator 6 becomes unnecessary, so that it is possible to realize continuity of operation and to increase the operation speed. Become.

When the shifter 8 performs a bit shift to make the cumulative addition value Σ stored in the accumulator 6 into a predetermined word length data, the shift number setting register 9 sets the shift number NSF.
Is also sent to the initialization circuit 7, and the initial value INI according to FIG. 4 is multiplied by the adder 5 at the beginning of the calculation (C / D).
Is incremented by ₁ . As a result, since the rounding process that was conventionally performed after the final result was obtained was performed at the start, the conventional rounding circuit 11 as dedicated hardware becomes unnecessary. In this case, the apparatus of the embodiment requires the selector 71 and the decoder 72 to perform the rounding process, but the circuit scale of these is significantly smaller than that of the rounding process circuit 11 which requires the conventional adder. Can be converted.

[Advantages of the Invention] According to the present invention, it is possible to increase the calculation speed while performing continuous cumulative calculation processing. Further, rounding processing can be executed with a small circuit configuration.

When the arithmetic circuit of the present invention is used in, for example, an image signal processing system, by adding an initialization circuit having a simple configuration to the conventional circuit configuration, pixel block processing that needs to be performed at high speed and effectively, This can be performed while realizing high-speed cumulative addition, normalization processing, and effective rounding processing.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a block diagram showing an arithmetic circuit as one embodiment of the present invention, FIG. 3 is a block diagram showing an initialization circuit in the embodiment circuit, and FIG. Is a setting table of initial value data in the initialization circuit, FIG. 5 is a time chart showing the operation timing of the embodiment circuit, FIG. 6 is a block diagram showing a conventional operation circuit, and FIG. 7 is an operation of the conventional circuit. It is a time chart which shows timing. In the figure, 1,2,4,10 register 3 multiplier 5 adder 6,61 accumulator 7 initialization circuit 8 shifter 9 shift number setting circuit 11 rounding Processing circuit

Claims (1)

(57) [Claims] 1. An accumulator, a shifter for shifting the bit position of the accumulated value accumulated in the accumulator, and an initial value for a predetermined rounding process according to the shift number of the shifter, according to the shift number of the shifter. An initial value generation unit that generates, a selection unit that selects and outputs a cumulative value from the accumulator or an initial value from the initial value generation unit, and an addition result of an input value and an output value of the selection unit Is stored in the accumulator, and the selector selects the initial value from the initial value generator instead of the accumulated value from the accumulator according to the initialization signal and outputs the selected value to the adder. Arithmetic circuit configured as.