JP2526269B2 - Master slice method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A master slice slicing method for a transistor array in which basic cells composed of a p-channel transistor and an n-channel transistor are arranged, and a turnaround time is shortened and a fabrication area of the transistor array is also reduced. And two p-type impurity regions as a source / drain of a p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes, Of the n-channel transistor formed between the gate electrodes and on both sides of these gate electrodes as a common gate electrode.
An n-type impurity region as a drain, an isolation region for insulatingly separating the p-type impurity region and the n-type impurity region, and a p-type impurity region and an n-type impurity region on both sides for drawing out the gate electrode to the outside. A cell having four gate electrode lead-out regions provided at the ends and two gate electrode lead-out regions provided on the isolation region is used as a basic cell, and the basic cells are arranged in parallel in axial symmetry. In a transistor array in which the two basic cells are arranged as a basic block and a large number of the basic blocks are arranged, the basic cell includes at least three wiring channels parallel to the gate electrode and 14 or 16 wirings in a direction perpendicular to the wiring channels. It has a channel, a contact hole, a first wiring layer, and a via hole are appropriately created in advance, and the first hole is formed through the via hole according to the required circuit function.
A second wiring layer is formed to electrically connect the wiring layers.

[Industrial applications]

The present invention relates to a master slice method for a transistor array in which basic cells composed of p-channel transistors and n-channel transistors are arranged.

[Conventional technology]

FIG. 14 is a basic cell pattern of a master slice method for a semiconductor device having a CMOS structure. In the figure, 158 is a basic cell, which is composed of two p-channel transistors and two n-channel transistors. One p-channel transistor consists of a poly-Si gate electrode 159 and source / drain regions 160 and 161 (p-type impurity regions), and the other p-channel transistor is a poly-Si gate electrode.
162 and source / drain regions 161,163 (p-type impurity region)
It consists of In addition, one n-channel transistor has a poly-Si gate electrode 159 and source / drain regions 164 and 165.
(N-type impurity region), and the other n-channel transistor has a poly-Si gate electrode 162 and a source / drain region 1
65,166 (n-type impurity region). Then, an insulating film (first interlayer insulating film) is formed thereon in order to protect these regions.

The semiconductor device manufactured up to this point is stocked, contact holes are opened in the insulating film according to the required circuit function, then the first wiring film (Al film) is formed, and then the second wiring film is formed.
Forming an insulating film (second interlayer insulating film), forming a via hole in the second insulating film, and further forming a second wiring film connected to the first wiring film through the via hole.

In this way, by changing each of the four patterns of the contact hole, the first-layer Al wiring, the via hole, and the second-layer Al wiring, a circuit having a predetermined function can be freely formed. Further, it is possible to shorten the manufacturing process.

[Problems to be Solved by the Invention]

By the way, according to the conventional master slicing method, at least four pattern masks of a contact hole pattern mask, a first layer Al wiring pattern mask, a via hole pattern mask and a second layer Al wiring pattern mask are required. .

If these change pattern masks can be reduced, the turnaround time can be further shortened as compared with the conventional case.

The present invention was created in view of the above conventional problems, and provides a master slice method for a semiconductor device capable of reducing the turnaround time by reducing the change pattern mask to only the wiring pattern mask of the second layer. With the goal.

[Means for solving the problem]

The first master slice method of the present invention is shown in FIGS.
As shown in the figure, two gate electrodes 2 and 3 extending in parallel
And p-type impurity regions 4 to 6 as source / drain of a p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes, and the two gate electrodes 2 and 3 as a common gate electrode. , N-type impurity regions 7 to 9 as the source / drain of the n-channel transistor formed between these gate electrodes and on both sides of these gate electrodes, and the p-type impurity regions 4 to 6 and the n-type impurity region 7. Isolation regions 10 for insulating and isolating the gate electrodes 9 to 9 from each other, and four gate electrode lead-out regions provided at the ends of the p-type impurity regions 4 and 6 and the n-type impurity regions 7 and 9 to lead the gate electrodes to the outside. A cell having the parts 11 to 14 and two gate electrode lead-out region parts 15 and 16 provided on the isolation region is used as a basic cell, and two basic cells are arranged in parallel in axial symmetry. Basic Bro In the transistor array comprising arranging a large number of the basic block as click 1A, the basic cell of at least 3 parallel to the gate electrodes 2 and 3
There are 14 wiring channels and 14 wiring channels in a direction perpendicular to the wiring channels, and the first interlayer insulating film on each of the gate electrode lead-out region portions 11 to 14 and the first interlayer insulating film on each of the impurity regions 4 to 9 are formed. Each interlayer insulating film has at least one contact hole 17 to
And forming at least one via hole 27 to 30 adjacent to contact holes (17) to (20) in the same region in the second interlayer insulating film on each gate electrode lead-out region portion, At least three via holes 31 to 33 are formed adjacent to each other in the second interlayer insulating film on each impurity region on both sides of the electrode.
Further, at least 4 is formed on the second interlayer insulating film on the isolation region.
One via hole 34 to 37 is formed, a first wiring layer 38 connecting the contact hole and the via hole is formed in the gate electrode lead-out region, and one via hole on the impurity regions on both sides of the gate electrode is connected to each other. Contact the first wiring layer 39 and the first wiring layer 40, which is used mainly as a power line by connecting another via hole on the impurity regions on both sides with the via hole on the same impurity region. The first wiring layer 41 connecting the holes to each other, the first wiring layer 42 connecting the contact hole in the impurity region between the gate electrodes and one via hole in the isolation region, to the isolation region. A first wiring layer 43 for connecting another via hole in the inside and another via hole in the isolation region of the basic cell which is axially symmetrical is formed in advance, and the first wiring layer 43 is formed according to the required circuit function. It is characterized by forming a second wiring layer for electrically connecting the first wiring layer through a via hole formed in the insulating film.

The second master slice method of the present invention is shown in FIGS.
As shown in the figure, two gate electrodes 2 and 3 extending in parallel
A p-type impurity region 4 to 6 as a source / drain of a p-type channel transistor formed between the gate electrodes and on both sides of these gate electrodes, and the two gate electrodes 2 and 3 as a common gate electrode. The n-type impurity regions 7 to 9 as the source / drain of the n-type channel transistor formed between these gate electrodes and on both sides of these gate electrodes, the p-type impurity regions 4 to 6 and the n-type impurities. Isolation region 10 that insulates and isolates regions 7 to 9, and four gate electrodes provided at the ends of p-type impurity regions 4 and 6 and n-type impurity regions 7 and 9 for drawing out the gate electrode to the outside. Two cells in which cells having lead-out region portions 11 to 14 and two gate electrode lead-out region portions 15 and 16 provided on the isolation region are used as basic cells, and the basic cells are arranged in parallel in axial symmetry. One basic In the transistor array comprising arranging a large number of the basic block as the lock 1A, the basic cell of at least 3 parallel to the gate electrodes 2 and 3
A plurality of wiring channels and 14 wiring channels in a direction perpendicular to the wiring channels, and at least one wiring channel region parallel to the gate electrode is provided between the basic cells. At least one contact hole 44-47 in the first interlayer insulating film, at least one contact hole 48, 49 in the first insulating film on the impurity regions on both sides of the gate electrode, and the impurity region between the gate electrodes. At least two contact holes 50, 51 are formed in the upper first insulating film, and at least one via hole 52, adjacent to the contact hole is formed in the second interlayer insulating film on each gate electrode lead-out region. 53, at least three via holes 54, 55, 56 adjacent to each other in the second interlayer insulating film on the impurity region on one side of the gate electrode on both sides of the gate electrode. , Two via holes 57, 58 on both sides of the contact hole in the second interlayer insulating film on the other impurity region, and at least two via holes 59, 60 in the second interlayer insulating film on the isolation region. At least two via holes 61, 62 are formed on one wiring channel region between the basic cells, and a first wiring layer 63 connecting a contact hole and a via hole is formed in the gate electrode lead-out region portion, A first wiring layer 64 connecting one via hole on one region of the impurity region on both sides of the electrode and a contact hole in the impurity region between the gate electrodes is formed on the impurity region on both sides of the gate electrode. The first wiring layer 65 which connects two via holes to each other and is mainly used as a power line is connected to another via hole on the impurity regions on both sides and a contact hole in the same region. Continuing first wiring layer 66,6
7, a first wiring layer 68 for connecting another contact hole 51 in the impurity region between the gate electrodes and a via hole 59 in the isolation region, and a first wiring layer 68 on the wiring channel between the basic cells. The wiring layer 69 is formed in advance, and a second wiring layer which electrically connects the first wiring layer through the via hole formed in the second insulating film is formed according to the required circuit function. It is characterized by that.

The third master slice method of the present invention is shown in FIGS.
As shown in the figure, two gate electrodes 2 and 3 extending in parallel
And p-type impurity regions 4 to 6 as source / drain of a p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes, and the two gate electrodes 2 and 3 as a common gate electrode. , N-type impurity regions 7 to 9 as the source / drain of the n-channel transistor formed between these gate electrodes and on both sides of these gate electrodes, and the p-type impurity regions 4 to 6 and the n-type impurity region 7. Isolation regions 10 for insulating and isolating the gate electrodes 9 to 9 from each other, and four gate electrode lead-out regions provided at the ends of the p-type impurity regions 4 and 6 and the n-type impurity regions 7 and 9 to lead the gate electrodes to the outside. A cell having the parts 11 to 14 and two gate electrode lead-out region parts 15 and 16 provided on the isolation region is used as a basic cell, and two basic cells are arranged in parallel in axial symmetry. Basic Bro In the transistor array in which a large number of the basic blocks are arranged as 1A, the basic cell has at least three wiring channels parallel to the gate electrode and 14 wiring channels in a direction perpendicular to the wiring channel. There is at least one wiring channel region parallel to the gate electrode, at least one contact hole 70 in the first interlayer insulating film on each gate electrode lead-out region portion, and impurity regions on both sides of the gate electrode. At least one contact hole 71, 72 is formed in the upper first insulating film, and at least two contact holes 73, 74 are formed in the first insulating film on the impurity region between the gate electrodes. At least one via hole 75 adjacent to the contact hole is formed in the second interlayer insulating film on the region portion, and one via hole 75 on both sides of the gate electrode is formed. At least three via holes 76 to 78 are adjacent to each other on the second interlayer insulating film on the pure region, and on both sides of the contact hole in the second interlayer insulating film on the other impurity region on both sides of the gate electrode. Two via holes 79 and 80 in the second interlayer insulating film on the isolation region, and at least two via holes 8 in the isolation region.
At least four via holes 83 to 86 are formed on one wiring channel region between the basic cells 1, 82, and a first wiring layer 87 connecting the contact hole and the via hole is formed in the gate electrode lead-out region portion. The first wiring layer 88 for connecting one via hole 76 on one of the impurity regions on both sides of the gate electrode and the contact hole 73 in the impurity region between the gate electrodes to the two wirings of the two basic cells. One via hole 77, 79 on the impurity regions on both sides of the gate electrode is continuously connected on the same channel to use the first wiring layer 89 which is mainly used as a power supply line for another via on the impurity regions on both sides. A first wiring layer 90 connecting one via hole to a contact hole in the same region is connected to another contact hole in the impurity region between the gate electrodes and a via hole in the isolation region. The first wiring layer 91, the via holes on the wiring channel between the first contact so as not to basic cell and the wiring layer 89 for the power supply line 83 to the
A first wiring layer 92 for intermittently connecting 86 is formed in advance, and the first wiring layer is electrically connected through a via hole formed in the second insulating film according to a required circuit function. It is characterized in that a second wiring layer for connection is formed.

A fourth master slice method of the present invention is shown in FIGS.
As shown in the figure, two gate electrodes 2 and 3 extending in parallel
And p-type impurity regions 4 to 6 as source / drain of a p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes, and the two gate electrodes 2 and 3 as a common gate electrode. , N-type impurity regions 7 to 9 as the source / drain of the n-channel transistor formed between these gate electrodes and on both sides of these gate electrodes, and the p-type impurity regions 4 to 6 and the n-type impurity region 7. Isolation regions 10 for insulating and isolating the gate electrodes 9 to 9; A cell having the parts 11 to 14 and two gate electrode lead-out region parts 15 and 16 provided on the isolation region is used as a basic cell, and two basic cells are arranged in parallel in axial symmetry. Basic Bro 1A is a transistor array in which a large number of the basic blocks are arranged, the basic cell has at least three wiring channels parallel to the gate electrode and 16 wiring channels in a direction perpendicular to the wiring electrode, and the basic cell At least one wiring channel region parallel to the gate electrode is provided therebetween, at least one contact hole 93 is formed in the first interlayer insulating film on each gate electrode lead-out region portion, and on the impurity regions on both sides of the gate electrode. At least one contact hole 94, 95 is formed in the first insulating film, and at least two contact holes 96, 97 are formed in the first insulating film on the impurity region between the gate electrodes. At least one adjacent to the contact hole 93 in the second interlayer insulating film above
The two via holes 98 are adjacent to the second interlayer insulating film on one of the impurity regions on both sides of the gate electrode, 99 and 100 are adjacent to each other, and the other 101 is at least 3 with a space for one wiring channel region. One via hole, one on each side of the contact hole in the same region in the second interlayer insulating film on the other impurity region on both sides of the gate electrode, 102 is adjacent to the contact hole, and the other is 103. Are two via holes at a distance corresponding to one wiring channel region in the contact hole, at least two via holes 104 and 105 in the second interlayer insulating film on the isolation region, and one wiring channel between the basic cells. At least four via holes 106 to 109 are formed in the region, and a first wiring layer 110 connecting the contact hole and the via hole is formed in the gate electrode lead-out region portion on both sides of the gate electrode. The first wiring layer 111 for connecting one via hole on one of the impurity regions of the two basic cells to the contact hole in the impurity region between the gate electrodes is formed on the impurity regions on both sides of the gate electrodes of the two basic cells. The first wiring layer 112, which is mainly used as a power supply line by continuously connecting two via holes to each other on the same channel, is connected to another one via hole on the impurity regions on both sides and a contact hole in the same region. The first wiring layers 113 and 114 for connecting the first wiring layer 115 for connecting another contact hole in the impurity region between the gate electrodes and the via hole in the isolation region to the first wiring layer for the power supply line. A first wiring layer 116 for intermittently connecting each via hole on the wiring channel between the basic cells so as not to come into contact with the layer 112 is formed in advance, and the second insulating layer is formed according to the required circuit function. It is characterized by forming a second wiring layer for electrically connecting the first wiring layer through a contact hole formed.

The fifth master slice method of the present invention is shown in FIGS.
As shown in the figure, two gate electrodes 2 and 3 extending in parallel
And p-type impurity regions 4 to 6 as source / drain of a p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes, and the two gate electrodes 2 and 3 as a common gate electrode. , N-type impurity regions 7 to 9 as the source / drain of the n-channel transistor formed between these gate electrodes and on both sides of these gate electrodes, and the p-type impurity regions 4 to 6 and the n-type impurity region 7. Isolation regions 10 for insulating and isolating the gate electrodes 9 to 9 from each other, and four gate electrode lead-out regions provided at the ends of the p-type impurity regions 4 and 6 and the n-type impurity regions 7 and 9 to lead the gate electrodes to the outside. A cell having the parts 11 to 14 and two gate electrode lead-out region parts 15 and 16 provided on the isolation region is used as a basic cell, and two basic cells are arranged in parallel in axial symmetry. Basic Bro In the transistor array in which a large number of the basic blocks are arranged as 1A, the basic cell has at least three wiring channels parallel to the gate electrode and 14 wiring channels in a direction perpendicular to the wiring channel. At least one wiring channel region parallel to the gate electrode is provided therebetween, at least one contact hole 117 is formed in the first interlayer insulating film on each gate electrode lead-out region portion, and impurity regions on both sides of the gate electrode. At least one contact hole 118, 119 is formed in the upper first insulating film, and at least one contact hole 120 is formed in the first insulating film on the impurity region between the gate electrodes. At least one via hole 121 is formed in the second interlayer insulating film adjacent to the contact hole in the same region, on both sides of the gate electrode. In the second interlayer insulating film on one impurity region, one 122 is adjacent to the contact hole and the other 123 is one wiring channel region from the contact hole centering on the contact hole in the same region. Two via holes spaced apart from each other are provided in the second interlayer insulating film on the other impurity region on both sides of the gate electrode, one on one side of the contact hole in the same region and one adjacent to the contact hole. The other one 125 is a second via hole that is spaced from the via hole by one wiring channel region, and is the second via hole on the isolation region.
At least two via holes 126 and 127 are formed in the interlayer insulating film, and at least four via holes 128 to 131 are formed on one wiring channel region between the basic cells, and a contact hole and a via hole are formed in the gate electrode lead-out region. The first wiring layer 132 for connecting to and is connected mainly to one via hole on the impurity regions on both sides of the gate electrodes of the two basic cells and via holes in the impurity region between the gate electrodes are continuously connected to each other mainly as a power supply line. The first wiring layer 133 used as the first wiring layer 134, 135 connecting the contact hole in one region of the impurity regions on both sides of the gate electrode to another via hole, and the impurity region between the gate electrodes. The first wiring layer 136 connecting the contact hole in the inside and the via hole in the isolation region is not in contact with the first wiring layer for the power supply line. First wiring layer 137 for intermittently connecting each via hole on the wiring channel between the basic cells is formed in advance, and via the via hole formed in the second insulating film according to the required circuit function. And forming a second wiring layer electrically connecting the first wiring layer.

The sixth master slice method of the present invention is shown in FIGS.
As shown in the figure, two gate electrodes 2 and 3 extending in parallel
And p-type impurity regions 4 to 6 as source / drain of a p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes, and the two gate electrodes 2 and 3 as a common gate electrode. , N-type impurity regions 7 to 9 as the source / drain of the n-channel transistor formed between these gate electrodes and on both sides of these gate electrodes, and the p-type impurity regions 4 to 6 and the n-type impurity region 7. Isolation regions 10 for insulating and isolating the gate electrodes 9 to 9 from each other, and four gate electrode lead-out regions provided at the ends of the p-type impurity regions 4 and 6 and the n-type impurity regions 7 and 9 to lead the gate electrodes to the outside. A transistor array in which a cell having parts 11 to 14 and two gate electrode lead-out region parts 15 and 16 provided on an isolation region is used as a basic block, and a large number of the basic blocks are arranged. The basic cell has at least three wiring channels parallel to the gate electrode and 14 wiring channels in a direction perpendicular to the wiring channel, and at least one wiring channel region parallel to the gate electrode is provided between the basic cells. Providing at least one contact hole 138 in the first interlayer insulating film on each gate electrode lead-out region,
At least one contact hole 139, 140 is formed in the first insulating film on the impurity regions on both sides of the gate electrode, and at least one contact hole 141 is formed in the first insulating film on the impurity region between the gate electrodes. At least one via hole 142 is formed adjacent to a contact hole in the same region in the second interlayer insulating film on the gate electrode lead-out region portion, and the second interlayer insulating film is formed on the gate electrode impurity region. In the second interlayer insulating film, one via hole 143 is formed adjacent to the contact hole in the same region, and the impurity regions on both sides of the gate electrode on the same vertical wiring channel adjacent to the via hole and the impurity region between the gate electrodes are formed. One via hole in each, 144,145,146
At least four via holes 147 to 150 are formed on one horizontal wiring channel region between the basic cells, and a first wiring layer 151 connecting the contact hole and the via hole is formed in the gate electrode lead-out region portion. A first wiring layer 15 for continuously connecting one via hole on the impurity regions on both sides of the gate electrode and using it as a power supply line
2, first wiring layers 153 and 154 connecting the contact holes in the same region of the impurity regions on both sides of the gate electrode with other via holes, and the contact holes in the impurity region between the gate electrodes and the contacts. A first wiring layer 155 connecting the via hole adjacent to the hole,
A first wiring layer 156 for connecting another via hole in the p-type impurity region between the gate electrodes and another via hole in the n-type impurity region between the gate electrodes is formed with a first wiring layer 156 for the power supply line. The first wiring layer 15 which connects each via hole on the wiring channel between the basic cells intermittently so as not to contact the wiring layer 15
7 is formed in advance, and a second wiring layer for electrically connecting the first wiring layer through the via hole formed in the second insulating film is formed according to the required circuit function. It has a feature.

[Action]

According to the first invention, as shown in FIG. 2, the contact hole, the first wiring layer and the via hole are formed in advance at predetermined positions. Then, according to the required circuit function, a second wiring layer is formed as shown in FIG.

Although FIG. 3 shows only a circuit having a basic function, those skilled in the art can also use a circuit having another basic function and a circuit having a complicated function by changing the pattern of the second wiring layer. It can be easily created.

According to the second invention, as in the first invention, as shown in FIG. 5, circuits having various functions can be created by changing only the pattern of the second wiring layer.

Comparing the second invention (FIG. 4) with the first invention (FIG. 2), in the second invention, an inter-cell wiring channel region is provided and via holes 61, 62,
The difference is that the first wiring layer 69 is provided. As a result, the first wiring layer 69 can be used, for example, in the case of passing a signal line in the horizontal direction, so that a large-scale circuit can be easily created.

According to the third invention, as shown in FIG. 7, circuits having various functions can be created by changing the pattern of the second wiring layer as in the other inventions.

Comparing the third invention (FIG. 6) with the second invention (FIG. 4), in the third invention, four via holes 83 to 86 are provided in the inter-cell wiring channel region to provide the first horizontal direction. Wiring layer 92
The first wiring layer 92 as a power supply line is prevented from short-circuiting. Further, since the first wiring layer 92 is continuously wired without passing through the contact hole, it is possible to form a high-quality power supply line with a small voltage drop.

According to the fourth invention, as shown in FIG. 9, circuits of various functions can be created by changing the second wiring layer pattern as in the other inventions.

Comparing the fourth invention (FIG. 8) with the third invention (FIG. 6), the fourth invention has 16 wiring channels in the vertical direction. As a result, the via hole 107 in the inter-cell wiring channel region can be offset from the via hole 101 in the cell by one vertical wiring channel. Therefore, in particular, two transmission gates connected in series as shown in FIG. 9 are formed on one basic cell. It becomes possible to do.

According to the fifth invention, as shown in FIG. 11, circuits having various functions can be created by changing the second wiring layer pattern as in the other inventions.

Comparing the fifth invention (Fig. 10) with the fourth invention (Fig. 8), the fifth invention shows that, as shown in Fig. 11, even if there are 14 wiring lines in the vertical direction, they are connected in series. It is possible to create the two transmission gates that are formed on one basic cell.

According to the sixth invention, as shown in FIG. 13, like the other inventions, circuits having various functions can be created by changing the second wiring layer pattern.

Comparing the sixth invention (Fig. 12) and the fifth invention (Fig. 10), two basic cells are used as one basic block in the fifth invention, so only the lower basic cell is used. If the basic cell on the upper side is wasted, the basic cell on the lower side may be wasted if only the basic cell on the upper side is used, but in the sixth invention, one basic cell is Since it is one basic block, the use efficiency of the basic cell is improved.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory diagram of basic blocks of the master slice method of the first to fifth inventions. In the figure, basic block 1A
Is composed of a pair of basic cells 1, and one basic cell 1 is composed of two p-channel transistors connected in series and two n-channel transistors connected in series. One p-channel transistor is composed of a gate electrode 2 and p-type impurity regions 4 and 5 for source / drain, and the other p-channel transistor is a gate electrode 3.
And p-type impurity regions 5 and 6 for source / drain. One n-channel transistor is composed of a gate electrode 2 and n-type impurity regions 7 and 8 for source / drain, and the other n-channel transistor is a gate electrode 3.
And n-type impurity regions 8 and 9 for source / drain.

Reference numeral 10 is a region that separates a p-channel transistor formation region and an n-channel transistor formation region, and gate electrode lead-out region portions 11 to 16 are provided on the separation region and at the end of the nuclear transistor. The gate electrode lead-out region portions 11 to 16 and the gate electrodes 2 and 3 are made of, for example, poly-Si.

(A) Description of the master slice method of the first invention FIG. 2 is a common pattern diagram explaining the master slice method of the first invention. In the figure, the black squares are contact holes formed in the first insulating film, the thin solid lines are the first wiring layer, and the unfilled squares are formed in the second insulating film. It is a beer hole.

To describe the order of formation in the wafer process, after forming the gate electrode and the source / drain impurity regions, a first insulating film (for example,
CVD-SiO ₂ film) is formed. Next, after forming a contact hole in the first insulating film, a first wiring layer is formed.
Then, after depositing a second insulating film (for example, a CVD-PSG film), a via hole is formed in the second insulating film. The pattern diagram of FIG. 2 is formed in this manner. Hereinafter, the pattern diagrams of FIGS. 4, 6, 8, 10, and 12 are also formed by the same wafer process.

Next, each pattern arrangement of the contact hole, the first wiring layer, and the via hole of the first invention will be described with reference to FIG. The basic cell is formed on a region formed by three horizontal wiring channels and 14 vertical wiring channels intersecting the horizontal wiring channels.
The wiring layer and the via hole are formed at positions determined by these wiring channels.

In the gate electrode lead-out region 11, contact holes 17
And the via hole 27 are connected by the first wiring layer 38. This allows the gate electrode 2 to be drawn out through the via hole 27. The other gate electrode lead-out regions 12 to 14 have the same pattern arrangement.

In the p-type impurity region 4, three via holes 31 to 33 and one contact hole are formed on the four vertical wiring channels.
21 are arranged in succession.

Further, with respect to the p-type impurity region 6 and the n-type impurity regions 7 and 9, contact holes and via holes (number omitted) are arranged at positions symmetrical to the p-type impurity region 4, respectively.

In the p-type impurity region 5 and the n-type impurity region 8 between the gate electrodes 2 and 3, one contact hole 22, 25 is formed at symmetrical positions. Two via holes 35 and 37 are formed in the gate electrode lead-out region 16 of the isolation region 10, and via holes 34 and 36 are formed in the isolation region 10 where there is no gate electrode lead-out region.

The via hole 31 on the p-type impurity region 4 is connected to the via hole on the p-type impurity region 6 which is symmetrical to this via the first wiring layer 39. The via hole 32 is also connected to the via hole on the impurity region symmetrical to this via the first wiring layer 40, and the first wiring layer 40 is extended and connected to the via hole of the adjacent basic cell. Used as a line (V _DD ). Further, the contact hole 21 and the via hole 33 are connected by the first wiring layer 41, and the contact hole 22 and the via hole 34 are connected by the first wiring layer 42. Further, the via holes 35 and 37 are connected to the via holes of the adjacent basic cells located symmetrically to the via holes by the first wiring layer 43.

As shown in FIG. 2, the patterns of the contact hole, the first wiring layer, and the via hole are arranged in point symmetry with respect to the center of the basic block 1A.

FIG. 3 shows a second invention of the first invention for forming various logic circuits.
FIG. 4 is a wiring layer pattern diagram in which the thick solid line is the second wiring layer. As described above, based on the common pattern up to the via hole in FIG. 2, a predetermined logic circuit can be appropriately obtained only by changing the second wiring layer, so that the turnaround time can be shortened. Becomes

(B) Description of the mataster rice method of the second invention FIG. 4 is a common pattern diagram for explaining the master slice method of the invention of FIG. The transistor array on the substrate has the same arrangement as the transistor array in FIG.

In the gate electrode lead-out region, the contact hole 44 and the via hole 52 are connected by the first wiring layer 63, and the contact hole 50 in the p-type impurity region 5 is connected to the via hole 54 in the p-type impurity region 4 and the first wiring. Connected by layer 64. The via holes 55 and 57 in the p-type impurity regions 4 and 6 are connected to each other by the first wiring layer 65. The contact hole 48 and the via hole 56 in the p-type impurity region 4 are formed by the first wiring layer 66, and the contact hole 49 and the via hole 58 in the p-type impurity region 6 are formed by the first wiring layer 67. The contact hole 51 in the region 5 and the via hole 59 in the isolation region 10 have the first wiring layer 68.
Connected by.

As shown in the figure, the respective patterns of the contact hole, the first wiring layer and the via hole are arranged at symmetrical positions with respect to the center of the basic block. A wiring channel region is provided between the basic cells, and the first wiring layer 69
The via holes 61 and 62 connected by are formed.

FIG. 5 shows a second invention of the second invention for forming various logic circuits.
FIG. 4 is a wiring layer pattern diagram in which the thick solid line is the second wiring layer. As described above, based on the fixed common pattern up to the via hole in FIG. 4, a predetermined logic circuit can be appropriately obtained only by changing the second wiring layer. Therefore, similar to the master slice of the first invention. It is possible to shorten the turnaround time.

Further, in the second invention, the wiring channel region is provided between the cells, and the via holes 61, 62 and the first wiring layer 69 are provided in the inter-cell wiring channel region. Since the first wiring layer 69 can be used as a horizontal signal line, connections between cells in the horizontal direction are facilitated and a large-scale circuit can be created. The power supply lines (V _DD , V _SS ) connect the cells in the vertical direction by the second wiring layer as shown in FIG. 5, so that the signal lines (the first wiring layer) between the cells in the horizontal direction are connected. ) Is not short-circuited with.

(C) Description of the master slice method of the third invention FIG. 6 is a common pattern diagram for explaining the master slice method of the third invention. In the figure, 70 to 74 are contact holes, 75 to 86 are via holes, 87 to 92 are patterns of the first wiring layer, and each pattern is symmetrical with respect to the center of the basic block. In the present invention, unlike the above-mentioned second invention, the V _DD power supply line 89 (first wiring layer) extends in the vertical direction without passing through the contact hole (the same applies to the V _SS power supply line). Therefore, the voltage drop when a current flows through the power supply line can be reduced, and the circuit operation speed can be further increased.

FIG. 7 is a diagram in which various logic circuits are formed only by the second wiring layer (thick solid line) based on the common pattern up to the first wiring layer in FIG.

(D) Description of Master Slice Method of Fourth Invention FIG. 8 is a common pattern diagram for explaining the master slice method of the fourth invention. In the figure, 93 to 97 are contact holes, 98 to 109 are via holes, and 110 to 116 are patterns of the first wiring layer, and similarly have a symmetrical structure with respect to the center of the basic block.

FIG. 9 shows various logic circuits formed by changing only the pattern of the second wiring layer based on the common pattern diagram of FIG.

Particularly, in the present invention, as shown in FIG. 9 (part 4), two transmission gates arranged in series can be formed on one basic cell (half of the basic block). When configuring a circuit, it is possible to achieve higher circuit integration.

(E) Description of Master Slice Method of Fifth Invention FIG. 10 is a common pattern diagram for explaining the master slice method of the fifth invention. In the figure, 117 to 120 are contact holes, 121 to 131 are via holes, and 132 to 137 are patterns of the first wiring layer, which are symmetrical with respect to the center of the basic block.

FIG. 11 shows various logic circuits formed by changing only the second wiring layer based on the common pattern diagram of FIG.

Similarly to the fourth aspect of the invention, the fifth aspect of the invention can form two serial transmission gates on a single basic cell (FIG. 11 (part 4)), but the fifth aspect of the invention is the fourth aspect.
It is advantageous in that the pattern formation area can be reduced as compared with the invention of (1). That is, FIG. 8 (fourth invention)
10 and the common pattern diagram of FIG. 10 (fifth invention), 16 vertical wiring channels are required in FIG. 8, whereas 14 vertical wiring channels are required in FIG. Can be formed with.

(F) Description of the master slice method of the sixth invention FIG. 12 is a common pattern diagram for explaining the master slice method of the sixth invention. In the figure, 138 to 141 are contact holes, 142 to 150 are via holes, and 151 to 157 are patterns of the first wiring layer. In the present invention, unlike other inventions, a basic block is composed of one basic cell. Each pattern is arranged in a symmetrical position with respect to the center of the basic cell. The basic cells are formed on three horizontal wiring channels, inter-cell wiring channels and 14 vertical wiring channels.

FIG. 13 shows various logic circuits formed by changing only the second wiring layer based on the common pattern diagram of FIG.

The present invention is particularly significant in that one basic cell is used as a basic block for forming a logic circuit. That is,
In another invention, two basic cells are used as one basic block. Therefore, when a logic circuit is created using only the lower basic cells, the upper basic cells are wasted, and conversely, the upper basic cells are used. When the logic circuit is created using only the lower basic cell, it is wasted. In this respect, according to the present invention, it is possible to create a predetermined logic circuit by using any of the basic cells, so that the usage efficiency of the basic cells is improved and the circuit can be highly integrated.

〔The invention's effect〕

As described above, according to any of the first to sixth inventions, various logic circuits can be created by changing only the second wiring layer, so that the turnaround time can be shortened. It is possible to plan.

In the second invention, since the inter-cell wiring channel region is provided, the signal line can be passed in the lateral direction.
The connection between the logic circuits becomes easier as compared with the invention described above.

In the third invention, the via hole is formed in the inter-cell wiring channel region, and the power supply line is formed by the first wiring layer. Therefore, as compared with the second aspect of the invention, the voltage drop in the power supply line when a current flows through the power supply line can be reduced, so that the circuit operation can be speeded up.

In the fourth invention, it is possible to form two transmission gates connected in series on one basic cell. Therefore, when a circuit including two serial transmission gates such as a flip-flop circuit and a counter circuit is formed, the formation area can be reduced.

In the fifth invention, as in the fourth invention, two transmission gates connected in series can be formed on one basic cell. In particular, in the fifth invention, the number of wiring channels in the vertical direction can be reduced from 16 to 14,
The area can be further reduced.

In the sixth aspect, two transmission gates connected in series and other various logic circuits can be formed by using one basic cell as a basic block. Therefore, the formation of the logic circuit becomes easier than in the first to fifth inventions.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a transistor array of a basic block of the first to fifth inventions, FIG. 2 is a common pattern explanatory diagram of the first invention, and FIG. 3 is a second wiring pattern diagram of the first invention. FIG. 4 is a common pattern explanatory view of the second invention, FIG. 5 is a second wiring pattern diagram of the second invention, FIG. 6 is a common pattern explanatory view of the third invention, and FIG. 3 is a second wiring pattern diagram of the invention, FIG. 8 is a common pattern explanatory diagram of the fourth invention, FIG. 9 is a second wiring pattern diagram of the fourth invention, and FIG. 10 is a fifth invention. Common pattern explanatory diagram, FIG. 11 is a second wiring pattern diagram of the fifth invention, FIG. 12 is a common pattern explanatory diagram of the sixth invention, and FIG. 13 is a second wiring pattern diagram of the sixth invention. FIG. 14 is an explanatory diagram of a master slice basic cell. (Explanation of symbols) In FIG. 1, 1 ... Basic cell, 1A ... Basic block, 2, 3 ... Gate electrode, 4-6 ... P-type impurity region,
7-9 ... n-type impurity region, 10 ... isolation region, 11-16 ...
... gate electrode lead-out region portion, in FIG. 2 (first invention), 17 to 26 ... contact hole, 27 to 37 ... via hole, 38 to 43 ... first wiring layer, in FIG. 2 invention), 44-51 …… contact hole, 52-62 ……
Via holes, 63 to 69 ... First wiring layer, in FIG. 6 (third invention), 70 to 74 ... Contact holes, 75 to 86
...... Via hole, 87 to 92 ...... First wiring layer, in Fig. 8 (4th invention), 93 to 97 ...... Contact hole, 98
~ 109 …… Beer hole, 110 ～ 116 …… First wiring layer, first
In FIG. 0 (fifth invention), 117-120 ... contact holes, 121-131 ... via holes, 132-137 ... first wiring layer, in FIG. 12 (sixth invention), 138-141. ......
Contact hole, 142-150 …… Beer hole, 151-157
...... First wiring layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinji Sato 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) Reference JP 62-263653 (JP, A) JP 61-111564 (JP, A)

Claims (6)

(57) [Claims] 1. Two gate electrodes (2) extending in parallel
(3) and the source of the p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes.
The p-type impurity regions (4) to (6) as drains and the two gate electrodes (2) and (3) are used as a common gate electrode, and are formed between these gate electrodes and on both sides of these gate electrodes. Source of the selected n-channel transistor
N-type impurity regions (7) to (9) as drains, the p-type impurity regions (4) to (6) and the n-type impurity region (7)
Isolation region (10) for insulating and isolating the gate electrode from p-type impurity region (4),
(6) and four gate electrode lead-out region portions (11) to (1) provided at the ends of the n-type impurity regions (7) and (9).
4) and two gate electrode lead-out region parts (15) and (16) provided on the isolation region are used as basic cells, and the basic cells are arranged in parallel in axial symmetry. In a transistor array in which a large number of basic blocks are arranged as one basic block 1A, the basic cell includes at least three wiring channels parallel to the gate electrodes (2) and (3) and 14 wiring channels in a direction perpendicular to the wiring channels. The first interlayer insulating film on each of the gate electrode lead-out region portions (11) to (14) and the first interlayer insulating film on each of the impurity regions (4) to (9). At least one contact hole (17) to (26) is formed, and the second interlayer insulating film on each gate electrode lead-out region is adjacent to the contact holes (17) to (20) in the same region. At least one via (27) - (30),
At least three via holes (3) are formed adjacent to each other in the second interlayer insulating film on each impurity region on both sides of the gate electrode.
1) to (33), at least four via holes (34) to (37) are formed in the second interlayer insulating film on the isolation region, and contact holes and via holes are formed in the gate electrode lead-out region. The first wiring layer (38) connecting the first wiring layer (39) connecting the via holes on the impurity regions on both sides of the gate electrode to each other, and another wiring layer on the impurity regions on the both sides. A first wiring layer (40) which connects two via holes to each other and is mainly used as a power supply line, and a first wiring layer (41) which connects the via hole and the contact hole on the same impurity region to each other, A first wiring layer (42) connecting the contact hole in the impurity region between the gate electrodes and one via hole in the isolation region,
A first wiring layer (43) for connecting another via hole in the isolation region and another via hole in the isolation region of the basic cell, which is axially symmetrical, is formed in advance, and the first wiring layer (43) is formed according to the required circuit function. A master slicing method, comprising forming a second wiring layer electrically connecting the first wiring layer through a via hole formed in the second insulating film. 2. Two gate electrodes (2) extending in parallel,
(3) and the source of the p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes.
The p-type impurity regions (4) to (6) as drains and the two gate electrodes (2) and (3) are used as a common gate electrode, and are formed between these gate electrodes and on both sides of these gate electrodes. N-type impurity regions (7) to (9) as source / drain of the formed n-type channel transistor,
Isolation region (10) for insulating and isolating the p-type impurity regions (4) to (6) from the n-type impurity regions (7) to (9).
And four gate electrode lead-out region portions (1) provided at the ends of the p-type impurity regions (4) and (6) and the n-type impurity regions (7) and (9) to lead out the gate electrode to the outside.
A cell having 1) to (14) and two gate electrode lead-out area portions (15) and (16) provided on the isolation area is used as a basic cell, and the basic cells are arranged in parallel in axial symmetry. In the transistor array in which the two basic cells are arranged as a basic block 1A and a large number of the basic blocks are arranged, the basic cell is composed of at least three wiring channels parallel to the gate electrodes (2) and (3) and perpendicular to the wiring channels. Direction, and at least one wiring channel region parallel to the gate electrode is provided between the basic cells and at least one is formed in the first interlayer insulating film on each gate electrode lead-out region portion. Contact holes (44)-(47)
And at least one contact hole (48), (4) in the first insulating film on the impurity regions on both sides of the gate electrode.
9), at least two contact holes (50) and (51) are formed in the first insulating film on the impurity region between the gate electrodes, and the second interlayer insulating film on each gate electrode lead-out region portion is formed. At least one via hole (52), (53) adjacent to the contact hole, and at least three via holes adjacent to the second interlayer insulating film on one of the impurity regions on both sides of the gate electrode. Beer holes (54), (55), (56)
The second impurity region on the other impurity region on both sides of the gate electrode.
In the interlayer insulating film, two via holes (57) and (58) on both sides of the contact hole, and at least two via holes (59) and (6) in the second interlayer insulating film on the isolation region.
0), at least two via holes (61), (62) are formed on one wiring channel region between the basic cells, and a contact hole and a via hole are connected in the gate electrode lead-out region portion. A first wiring layer (64) for connecting one via hole on one of the impurity regions on both sides of the gate electrode to a contact hole in the impurity region between the gate electrodes. A first wiring layer (65) for connecting one via hole on the impurity regions on both sides of the gate electrode and mainly used as a power supply line to the same region as another via hole on the impurity regions on both sides. First to connect with the contact hole inside
Wiring layers (66) and (67) of the first wiring layer (68) for connecting another contact hole (51) in the impurity region between the gate electrodes and a via hole (59) in the isolation region. )
The first wiring layer (69) is formed in advance on the wiring channel between the basic cells, and the first wiring layer (69) is formed through the via hole formed in the second insulating film according to the required circuit function. A master slicing method, which comprises forming a second wiring layer for electrically connecting the wiring layers. 3. Two gate electrodes (2) extending in parallel,
(3) and the source of the p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes.
The p-type impurity regions (4) to (6) as drains and the two gate electrodes (2) and (3) are used as a common gate electrode, and are formed between these gate electrodes and on both sides of these gate electrodes. Source of the selected n-channel transistor
N-type impurity regions (7) to (9) as drains, the p-type impurity regions (4) to (6) and the n-type impurity region (7)
Isolation region (10) for insulating and isolating the gate electrode from p-type impurity region (4),
(6) and four gate electrode lead-out region portions (11) to (1) provided at the ends of the n-type impurity regions (7) and (9).
4) and two gate electrode lead-out region parts (15) and (16) provided on the isolation region are used as basic cells, and the basic cells are arranged in parallel in axial symmetry. In a transistor array in which a large number of basic blocks are arranged as one basic block 1A, the basic cell has at least three wiring channels parallel to a gate electrode and 14 wiring channels in a direction perpendicular to the wiring channels, And at least one wiring channel region parallel to the gate electrode between the basic cells, at least one contact hole (70) in the first interlayer insulating film on each gate electrode extraction region portion, and the gate electrode At least one contact hole (71), (72) in the first insulating film on the impurity regions on both sides of the gate electrode, and at least two contact holes (71), (72) in the first insulating film on the impurity region between the gate electrodes. Contact holes (73), (74) are formed, and at least one via hole (75) adjacent to the contact hole is formed in the second interlayer insulating film on each gate electrode lead-out region, At least three via holes (76) to (78) adjacent to the second interlayer insulating film on one impurity region on both sides of the second interlayer insulating film on the other impurity region on both sides of the gate electrode. Two via holes (79), (8
0), at least two via holes (81), (82) in the second interlayer insulating film on the isolation region, and at least four via holes (83) on one wiring channel region between the basic cells. (86) is formed, and a first wiring layer (87) for connecting a contact hole and a via hole is formed in the gate electrode lead-out region, and one via hole is formed on one region of the impurity regions on both sides of the gate electrode. A first wiring layer (88) connecting the (76) and the contact hole (73) in the impurity region between the gate electrodes.
Is a first wiring layer mainly used as a power supply line by continuously connecting one via hole (77), (79) on the impurity regions on both sides of the gate electrodes of two basic cells on the same channel. 89) to another 1 on the impurity regions on both sides
A first wiring layer (90) connecting one via hole to a contact hole in the same region, and a first wiring layer (90) connecting another contact hole in the impurity region between the gate electrodes and a via hole in the isolation region. Connecting the via layer (91) of each of the via holes (83) to (86) on the wiring channel between the basic cells so as not to come into contact with the first wiring layer (89) for the power supply line. A second wiring for electrically connecting the first wiring layer through a via hole formed in the second insulating film in accordance with a required circuit function by forming a first wiring layer (92) in advance. A master slicing method, which comprises forming layers. 4. Two gate electrodes (2) extending in parallel,
(3) and the source of the p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes.
The p-type impurity regions (4) to (6) as drains and the two gate electrodes (2) and (3) are used as a common gate electrode, and are formed between these gate electrodes and on both sides of these gate electrodes. Source of the selected n-channel transistor
N-type impurity regions (7) to (9) as drains, the p-type impurity regions (4) to (6) and the n-type impurity region (7)
Isolation region (10) for insulating and isolating the gate electrode from p-type impurity region (4),
(6) and four gate electrode lead-out region portions (11) to (1) provided at the ends of the n-type impurity regions (7) and (9).
4) and two gate electrode lead-out region parts (15) and (16) provided on the isolation region are used as basic cells, and the basic cells are arranged in parallel in axial symmetry. In a transistor array in which a large number of basic blocks are arranged as one basic block 1A, the basic cell has at least three wiring channels parallel to a gate electrode and 16 wiring channels in a direction perpendicular to the wiring channels, In addition, at least one wiring channel region parallel to the gate electrode is provided between the basic cells, at least one contact hole (93) is formed in the first interlayer insulating film on each gate electrode lead-out region, and the gate electrode At least one contact hole (94), (95) is formed in the first insulating film on the impurity regions on both sides, and at least two contact holes (94, 95) are formed in the first insulating film on the impurity region between the gate electrodes. Contact holes (96) and (97) are formed, and at least one via hole (98) adjacent to the contact hole (93) is formed in the second interlayer insulating film on each of the gate electrode lead-out regions. Two (99) on the second interlayer insulating film on one of the impurity regions on both sides of the gate electrode,
(100) are adjacent to each other, and the other (101) is at least three via holes spaced by one wiring channel region,
In the second interlayer insulating film on the other impurity region on both sides of the gate electrode, 1 is formed on both sides of the contact hole in the same region
One (102) is adjacent to the contact hole, and the other one (103) has two via holes at a distance of one wiring channel region in the contact hole, and a second interlayer on the isolation region. At least two via holes (104) and (105) in the insulating film, and at least four via holes (106) to (1) on one wiring channel region between the basic cells.
09) is formed, and a first wiring layer (110) for connecting a contact hole and a via hole is formed in the gate electrode lead-out region, and one via hole is formed on one region of the impurity regions on both sides of the gate electrode. The first wiring layer (111) connecting to the contact hole in the impurity region between the gate electrodes is continuously connected to one via hole on the impurity regions on both sides of the gate electrodes of the two basic cells on the same channel. A first wiring layer (112) for connecting the first wiring layer (112) connected and mainly used as a power supply line to another one via hole on the impurity regions on both sides and a contact hole in the same region.
3) and (114) are provided with a first wiring layer (115) for connecting another contact hole in the impurity region between the gate electrodes and a via hole in the isolation region to a first wiring layer for the power supply line.
The first wiring layer (116) for intermittently connecting the via holes on the wiring channels between the basic cells so as not to come into contact with the wiring layer (112) is formed in advance, and the first wiring layer (116) is formed according to the required circuit function. A master slicing method, comprising forming a second wiring layer electrically connecting the first wiring layer through a via hole formed in the second insulating film. 5. Two gate electrodes (2) extending in parallel,
(3) and the source of the p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes.
The p-type impurity regions (4) to (6) as drains and the two gate electrodes (2) and (3) are used as a common gate electrode, and are formed between these gate electrodes and on both sides of these gate electrodes. Source of the selected n-channel transistor
N-type impurity regions (7) to (9) as drains, the p-type impurity regions (4) to (6) and the n-type impurity region (7)
Isolation region (10) for insulating and isolating the gate electrode from p-type impurity region (4),
(6) and four gate electrode lead-out region portions (11) to (1) provided at the ends of the n-type impurity regions (7) and (9).
4) and two gate electrode lead-out region parts (15) and (16) provided on the isolation region are used as basic cells, and the basic cells are arranged in parallel in axial symmetry. In a transistor array in which a large number of basic blocks are arranged as one basic block 1A, the basic cell has at least three wiring channels parallel to a gate electrode and 14 wiring channels in a direction perpendicular to the wiring channels, Further, at least one wiring channel region parallel to the gate electrode is provided between the basic cells, at least one contact hole (117) is formed in the first interlayer insulating film on each gate electrode lead-out region portion, and the gate electrode At least one contact hole (118), (119) in the first insulating film on the impurity regions on both sides,
At least one contact hole (120) is formed in the first insulating film on the impurity region between the gate electrodes, and the contact hole in the same region is formed in the second interlayer insulating film on each gate electrode lead-out region. At least one via hole (121) adjacent to, and one (122) centering on a contact hole in the same region in the second interlayer insulating film on one of the impurity regions on both sides of the gate electrode. The other one (123) adjacent to the contact hole is spaced from the contact hole by one wiring channel region 2
One via hole is provided on one side of the contact hole in the same region of the second interlayer insulating film on the other impurity region on both sides of the gate electrode (124) adjacent to the contact hole and the other via hole. One (125) forms a second via hole with an interval of one wiring channel region in the via hole, and at least two via holes (126), (127) in the second interlayer insulating film on the isolation region. Then, at least four via holes (128) to (131) are formed on one wiring channel region between the basic cells, and a first wiring connecting the contact hole and the via hole in the gate electrode lead-out region portion. 2 layers (132)
A first wiring layer (133) mainly used as a power supply line by continuously connecting one via hole on the impurity regions on both sides of the gate electrode of one basic cell and via holes in the impurity region between the gate electrodes, First wiring layers (134), (135) for connecting a contact hole in one of the impurity regions on both sides of the gate electrode and another via hole
The first wiring layer (136) connecting the contact hole in the impurity region between the gate electrodes and the via hole in the isolation region is basically arranged so as not to come into contact with the first wiring layer for the power supply line. A first wiring layer (137) for intermittently connecting each via hole on a wiring channel between cells is formed in advance, and a via hole formed in the second insulating film is inserted in accordance with a required circuit function. Forming a second wiring layer for electrically connecting the first wiring layer with each other. 6. Two gate electrodes (2) extending in parallel,
(3) and the source of the p-channel transistor formed between the gate electrodes and on both sides of these gate electrodes.
The p-type impurity regions (4) to (6) as drains and the two gate electrodes (2) and (3) are used as a common gate electrode, and are formed between these gate electrodes and on both sides of these gate electrodes. Source of the selected n-channel transistor
N-type impurity regions (7) to (9) as drains, the p-type impurity regions (4) to (6) and the n-type impurity region (7)
Isolation region (10) for insulating and isolating the gate electrode from p-type impurity region (4),
(6) and four gate electrode lead-out region portions (11) to (1) provided at the ends of the n-type impurity regions (7) and (9).
In a transistor array in which a cell having 4) and two gate electrode lead-out area portions (15) and (16) provided on the isolation area is a basic block, and a large number of the basic blocks are arranged, Has at least three wiring channels parallel to the gate electrode and 14 wiring channels in a direction perpendicular to the wiring channel, and provides at least one wiring channel region parallel to the gate electrode between the basic cells. At least one contact hole (138) is formed in the first interlayer insulating film on the gate electrode lead-out region, and at least one contact hole (139) is formed in the first insulating film on the impurity regions on both sides of the gate electrode. (140)
At least one contact hole (141) is formed on the same vertical wiring channel in the first insulating film on the impurity region between the gate electrodes, and the second interlayer insulating film on each gate electrode lead-out region portion is formed. At least one via hole (142) is formed in the film adjacent to the contact hole in the same region, and a contact hole in the same region is adjacent to the second interlayer insulating film on the impurity region between the gate electrodes. One beer hole (143)
And one via hole (14 in each of the impurity regions on both sides of the gate electrode on the same vertical wiring channel adjacent to the via hole and in the impurity region between the gate electrodes).
4), (145), (146), at least four via holes (147) to (150) are formed on one horizontal wiring channel region between the basic cells, and contacts are formed in the gate electrode lead-out region portion. A first wiring layer (152) that uses a first wiring layer (151) connecting a hole and a via hole as a power supply line by continuously connecting one via hole on impurity regions on both sides of a gate electrode. First wiring layers (153) and (154) for connecting contact holes and other via holes in the same region of the impurity regions on both sides of the gate electrode to the inside of the impurity region between the gate electrodes. A first wiring layer (155) connecting the contact hole and a via hole adjacent to the contact hole is provided with an n-type impurity region between the gate electrode and another via hole in the p-type impurity region between the gate electrodes. A first wiring layer (156) for connecting to other via holes in the inside is connected intermittently to each via hole on the wiring channel between the basic cells so as not to come into contact with the first wiring layer for the power supply line. A first wiring layer (157) is formed in advance, and a second wiring for electrically connecting the first wiring layer through a via hole formed in the second insulating film according to a required circuit function. A master slicing method, which comprises forming layers.