JP2524733Y2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2524733Y2
JP2524733Y2 JP1991040971U JP4097191U JP2524733Y2 JP 2524733 Y2 JP2524733 Y2 JP 2524733Y2 JP 1991040971 U JP1991040971 U JP 1991040971U JP 4097191 U JP4097191 U JP 4097191U JP 2524733 Y2 JP2524733 Y2 JP 2524733Y2
Authority
JP
Japan
Prior art keywords
semiconductor device
view
metal
brazing material
metal connector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1991040971U
Other languages
Japanese (ja)
Other versions
JPH04113455U (en
Inventor
直由 尾島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP1991040971U priority Critical patent/JP2524733Y2/en
Publication of JPH04113455U publication Critical patent/JPH04113455U/en
Application granted granted Critical
Publication of JP2524733Y2 publication Critical patent/JP2524733Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/3701Shape
    • H01L2224/37011Shape comprising apertures or cavities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005Shape
    • H01L2224/4009Loop shape
    • H01L2224/40095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【考案の詳細な説明】[Detailed description of the invention]

【0001】[0001]

【産業上の利用分野】本考案は半導体装置の構造に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a semiconductor device.

【0002】[0002]

【従来の技術】従来、ダイオード等の半導体チップを用
いて半導体装置を構成する場合、例えば図1の断面構造
図に示すように、2の金属部材、3の金属板、1の半導
体チップ、及び4の金属接続子を順次載置して、5のろ
う材層にて相互間を固着している。4の金属接続子は回
路接続手段、機構的接続手段、熱疲労防止手段などに使
用され、電気抵抗が低く、且つ熱伝導度の高い銅などの
材料を用いている。しかしながら金属接続子4と半導体
チップ1の間のろう材層5に気泡6が発生し易い。これ
は金属接続子4のろう付けに於いて、ろう材のヌレ性を
よくする為に、フラックスを与え、加熱、冷却により固
着しているが、ろう材が溶融し固化する迄の間に、フラ
ックス等の気化物が残り、気泡6として残る。この気泡
は耐熱疲労性の低下を招くなど半導体装置の信頼性を悪
化する欠点である。
2. Description of the Related Art Conventionally, when a semiconductor device is formed by using a semiconductor chip such as a diode, for example, as shown in a sectional structural view of FIG. 1, two metal members, three metal plates, one semiconductor chip, and The metal connectors of No. 4 are sequentially placed, and are fixed to each other by a brazing material layer of No. 5. The metal connector No. 4 is used for circuit connection means, mechanical connection means, thermal fatigue prevention means and the like, and uses a material such as copper having low electric resistance and high thermal conductivity. However, bubbles 6 are easily generated in the brazing material layer 5 between the metal connector 4 and the semiconductor chip 1. In the brazing of the metal connector 4, a flux is applied to improve the wettability of the brazing material, and the brazing material is fixed by heating and cooling, but before the brazing material is melted and solidified. Vapors such as flux remain and remain as bubbles 6. These bubbles are disadvantageous in that the reliability of the semiconductor device is deteriorated, for example, the thermal fatigue resistance is lowered.

【0003】[0003]

【考案の目的】本考案は従来装置の前記欠点を解消し、
気泡の発生率を低減し、且つ、熱疲労寿命の長い半導体
装置を提供するものである。又、プリント配線板や放熱
フィンへ搭載した半導体装置をあわせて提供する。
The object of the present invention is to solve the above-mentioned disadvantages of the conventional device,
An object of the present invention is to provide a semiconductor device having a reduced bubble generation rate and a long thermal fatigue life. Further, the present invention also provides a semiconductor device mounted on a printed wiring board or a radiation fin.

【0004】[0004]

【実施例】図2は本考案の実施例の断面構造図であり、
図1と同一符号は同一部分を示す。2の金属部材は金属
板3及び半導体チップ1が収容できる凹部をもったアル
ミや銅の放熱フィンを構成する。又、金属接続子4は図
3(a)に側面図(b)に平面図、(c)を(a)の断
面構造図に示すように、4aなる貫通穴を形成してい
る。
FIG. 2 is a sectional structural view of an embodiment of the present invention.
1 denote the same parts. The second metal member constitutes a radiation fin made of aluminum or copper having a concave portion in which the metal plate 3 and the semiconductor chip 1 can be accommodated. The metal connector 4 has a through hole 4a as shown in FIG. 3A, a side view, FIG. 3B is a plan view, and FIG. 3C is a sectional structural view of FIG.

【0005】製造に於いては、金属部材2(放熱フィ
ン)の凹部に第1のろう材、金属板3、第2のろう材、
半導体チップ1、第3のろう材、金属接続子4を積層し
て収容し、加熱により、第1、第2、第3のろう材を溶
融し、その後冷却により固化させろう付けを成してい
る。
In manufacturing, a first brazing material, a metal plate 3, a second brazing material,
The semiconductor chip 1, the third brazing material, and the metal connector 4 are stacked and accommodated, and the first, second, and third brazing materials are melted by heating, and then solidified by cooling to perform brazing. I have.

【0006】ここに金属接続子4はろう付け部に貫通穴
4aを形成しているので、ろう材の溶融から固化までの
間に気泡の要因となるフラックス等の気化物は貫通穴4
aを通り、逃げやすくなり、ろう材層の固化後の気泡発
生は著しく低減した。
Here, since the metal connector 4 has a through hole 4a in the brazing portion, vaporized substances such as flux which cause air bubbles during the period from melting to solidification of the brazing material are not passed through the through hole 4a.
a, it became easy to escape, and the generation of bubbles after solidification of the brazing material layer was significantly reduced.

【0007】貫通穴4aは図3において円形を示した
が、楕円形、角形など設計の都合により任意に選択し得
る。貫通穴4aの直径は金属接続子4の厚さより大きく
選ぶことにより、プレス加工及び気泡発生の低減の面
で、特に、好結果を得た。又、貫通穴4aは必要に応じ
て、複数個設けてもよい。
Although the through hole 4a is shown as a circle in FIG. 3, it can be arbitrarily selected such as an oval or a square depending on the design. By selecting the diameter of the through hole 4a to be larger than the thickness of the metal connector 4, particularly good results were obtained in terms of press working and reduction of bubble generation. Further, a plurality of through holes 4a may be provided as necessary.

【0008】図4は本考案の他の実施例の断面構造図で
あり、図1、図2、図3と同一符号は同一部分を示す。
3の金属部材は凹形状とし半導体チップ1を収容できる
アルミや銅の放熱フィンで構成する。
FIG. 4 is a sectional structural view of another embodiment of the present invention, and the same reference numerals as those in FIGS. 1, 2 and 3 denote the same parts.
The metal member 3 is made of aluminum or copper radiating fins having a concave shape and capable of accommodating the semiconductor chip 1.

【0009】図5は本考案の他の実施例の断面構造図を
示し、3の金属部材はプリント配線板の基板7に配設し
た導電層である。プリント配線板は多種多様のものがあ
り、例えばセラミック基板、アルミ銅張板、ガラス、エ
ポキシ銅張積層板などが有る。本考案は、いずれのプリ
ント配線板にも適用できる。又、8は基板7上に設けた
他の電子部品であり、種々の複合又は混成集積回路装置
を構成する。図4、図5の実施例に於いても図2の実施
例で説明したと同様の作用、効果をしめす。
FIG. 5 is a sectional structural view of another embodiment of the present invention, and a metal member 3 is a conductive layer provided on a substrate 7 of a printed wiring board. There are various types of printed wiring boards, for example, a ceramic substrate, an aluminum copper-clad board, glass, and an epoxy copper-clad laminate. The present invention can be applied to any printed wiring board. Reference numeral 8 denotes another electronic component provided on the substrate 7, which constitutes various composite or hybrid integrated circuit devices. 4 and 5 show the same operations and effects as those described in the embodiment of FIG.

【0010】図6は図5に用いる金属接続子の構造図で
あり、(a)に平面図、(b)に側面図、(c)に断面
図を示す。
FIGS. 6A and 6B are structural views of the metal connector used in FIG. 5, wherein FIG. 6A is a plan view, FIG. 6B is a side view, and FIG.

【0011】図7は金属接続子4の他の実施例であり、
(a)に側面図、(b)に平面図(c)に断面図を示し
ている。金属接続子4の半導体チップ1とのろう付け部
(図7(a)の下面、図7(b)の面)を凸状とし、そ
の凸状部中央に貫通穴4aを設けるようにしている。
FIG. 7 shows another embodiment of the metal connector 4.
(A) is a side view, (b) is a plan view, and (c) is a cross-sectional view. The brazing portion of the metal connector 4 with the semiconductor chip 1 (the lower surface in FIG. 7A, the surface in FIG. 7B) is made convex, and a through hole 4a is provided at the center of the convex portion. .

【0012】このような金属接続子4の使用により、ろ
う材中の気泡はろう材の溶融中に貫通穴4aを上方に向
うものと、周辺に向うものの両方向に逃げて、ろう材中
の気泡低減を更に促進する。又、図6のごとき金属接続
子4に図7のごとく、ろう付け部を凸状として、同様の
効果を上げ得る。
With the use of the metal connector 4, air bubbles in the brazing material escape in both directions, that is, the air flowing upward through the through-hole 4a and the peripheral air during melting of the brazing material. Further promote reduction. Also, as shown in FIG. 7, a similar effect can be obtained by forming the brazing portion in a convex shape on the metal connector 4 as shown in FIG.

【0013】前記において、放熱フィンなる用語は放熱
効果を有する導電物を意味し、ケース状、板状、ひだ状
等など形状を特定するものではない。又、前記せる実施
例の各部形状変更や他の部品の付加等についても本考案
の要旨の範囲で、任意になし得るものである。
In the above description, the term "radiation fin" means a conductive material having a heat radiation effect, and does not specify a shape such as a case shape, a plate shape, and a pleated shape. Also, the shape of each part in the above-described embodiment and addition of other parts can be arbitrarily made within the scope of the present invention.

【0014】[0014]

【考案の効果】以上説明したように、本考案の半導体装
置は、ろう付け層内の気泡を低減し熱疲労性能の向上を
可能とし、放熱フィンやプリント配線板に搭載した半導
体装置として有効であり、電装品をはじめ高信頼性を要
求される各種の電子機器に利用して実用上の効果大なる
ものである。
As described above, the semiconductor device of the present invention reduces bubbles in the brazing layer, improves thermal fatigue performance, and is effective as a semiconductor device mounted on a radiation fin or a printed wiring board. It can be used in various electronic devices requiring high reliability, including electrical components, and has a large practical effect.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来の半導体装置の断面構造図FIG. 1 is a sectional structural view of a conventional semiconductor device.

【図2】本考案の実施例を示す断面構造図FIG. 2 is a sectional view showing an embodiment of the present invention.

【図3】図2に用いる金属接続子の構造図であり(a)
は側面図、(b)は平面図、(c)は(a)の断面図。
FIG. 3 is a structural view of a metal connector used in FIG. 2 (a).
3B is a side view, FIG. 3B is a plan view, and FIG. 3C is a cross-sectional view of FIG.

【図4】本考案の実施例を示す断面構造図FIG. 4 is a sectional structural view showing an embodiment of the present invention.

【図5】本考案の実施例を示す断面構造図FIG. 5 is a sectional structural view showing an embodiment of the present invention.

【図6】図5に用いる金属接続子の構造図であり(a)
は平面図(b)は側面図(c)は断面図
FIG. 6 is a structural view of a metal connector used in FIG. 5 (a).
Is a plan view, (b) is a side view, and (c) is a cross-sectional view.

【図7】金属接続子の他の実施例を示す構造図であり、
(a)は側面図(b)は平面図(c)は断面図
FIG. 7 is a structural view showing another embodiment of the metal connector;
(A) is a side view (b) is a plan view (c) is a cross-sectional view

【符号の説明】[Explanation of symbols]

1. 半導体チップ 2. 金属部材 3. 金属板 4 金属接続子 4a.金属接続子の貫通穴 5. ろう材層 6. 気泡 7. 基板 8. 他の電子部品 1. Semiconductor chip 2. Metal member 3. Metal plate 4 Metal connector 4a. 4. Through hole for metal connector Brazing material layer 6. Air bubbles 7. Substrate 8. Other electronic components

Claims (5)

(57)【実用新案登録請求の範囲】(57) [Scope of request for utility model registration] 【請求項1】 半導体チップの一面に金属板を、又、他
面に金属接続子をそれぞれ、ろう材を介して固着させ、
前記金属接続子の半導体チップとのろう付け部に貫通穴
を設け、該貫通穴にろう材の一部を入るようにしたこと
を特徴とする半導体装置。
1. A metal plate is fixed to one surface of a semiconductor chip and a metal connector is fixed to the other surface via a brazing material.
A semiconductor device, wherein a through hole is provided in a brazing portion of the metal connector to a semiconductor chip, and a part of a brazing material is inserted into the through hole.
【請求項2】 金属板をプリント配線板上の導電層とし
た請求項1の半導体装置。
2. The semiconductor device according to claim 1, wherein the metal plate is a conductive layer on the printed wiring board.
【請求項3】 金属板を放熱フィンとした請求項1の半
導体装置。
3. The semiconductor device according to claim 1, wherein said metal plate is a radiation fin.
【請求項4】 金属板を更に放熱フィンにろう材を介し
て固着した請求項1の半導体装置。
4. The semiconductor device according to claim 1, wherein the metal plate is further fixed to the radiation fin via a brazing material.
【請求項5】 金属接続子の半導体チップとのろう付け
部を金属板に向って凸状とし、かつ、その凸状部に貫通
穴を設けた請求項1、請求項2、請求項3又は、請求項
4の半導体装置。
5. The semiconductor device according to claim 1, wherein the brazing portion of the metal connector to the semiconductor chip is formed in a convex shape toward the metal plate, and the convex portion is provided with a through hole. The semiconductor device according to claim 4.
JP1991040971U 1991-03-20 1991-03-20 Semiconductor device Expired - Fee Related JP2524733Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991040971U JP2524733Y2 (en) 1991-03-20 1991-03-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991040971U JP2524733Y2 (en) 1991-03-20 1991-03-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH04113455U JPH04113455U (en) 1992-10-05
JP2524733Y2 true JP2524733Y2 (en) 1997-02-05

Family

ID=31921885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1991040971U Expired - Fee Related JP2524733Y2 (en) 1991-03-20 1991-03-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2524733Y2 (en)

Also Published As

Publication number Publication date
JPH04113455U (en) 1992-10-05

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