JP2520123B2 - Rotating head type digital audio playback device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital signal in which an audio signal is converted into a PCM signal and recorded as one diagonal track on a tape-shaped recording medium by a rotary head for each unit time. The present invention relates to a rotary head type digital audio reproducing device suitable for reproducing a.

[Technical background of the invention and its problems]

An R-DAT (rotary head type digital audio system) is used as a device for recording and reproducing an audio signal on a magnetic tape by forming a diagonal track on a magnetic tape by a helical scan type rotary head. A rotary head type digital audio recording / reproducing apparatus called a tape recorder has been considered.

The format of the track actually recorded in the R-DAT has a pattern as shown in FIG. 12 (a), and the SUB and PCM are composed of blocks as shown in FIG. 12 (b). The numerical values in FIG. 12 (a) represent the number of blocks occupied by each area.

Area of ATF-1 and ATF-2 (ATF: Automatic Track Fi
(nding) is for enabling the tracking control so that the rotary head properly scans the recording track during reproduction by the output of the rotary head without providing a special head.

That is, the pilot signal recorded in the ATF area is obtained by outputting the output of each rotary head when the recording track is reproduced by scanning the recording track by the rotary head whose scanning width is wider than the track width. It is used to control the tracking of the rotary head by the reproduction signal of the pilot signal from the adjacent track.

The track pattern for this ATF is defined as shown in Fig. 13, and ATF-1 and ATF-2 in the front part and the rear part of each track are used as a pilot signal for tracking and have a low azimuth effect. Frequency signal f ₁
This is used for detecting the level of the crosstalk level from both adjacent tracks during reproduction and obtaining the level difference of the crosstalk components of both adjacent tracks as a tracking error signal.

Further, in ATF-1 and ATF-2, a sync signal for discriminating the position where the pilot signal f ₁ is recorded is recorded. Since the on-track and the adjacent track cannot be distinguished from each other if there is crosstalk in the sync signal, a frequency having an azimuth effect and a pattern which does not exist in the PCM signal is selected. When the rotary head corresponding to + azimuth is A and the rotary head corresponding to −azimuth is B, the sync signals are different from each other in order to distinguish between the A rotary head and the B rotary head. The sync 1 signal f ₂ of frequency f _M / 18 (= 522KHz)
For the B head, the sync 2 signal f ₃ of frequency f _M / 12 (= 784 KHz) is recorded at a predetermined position.

In the R-DAT, an erasing head is not provided, and rewriting of a signal is performed by so-called overwriting in which data is overwritten on the previous recording. Therefore, the erase signal f ₄ having the frequency f _{M /} 6 (= 1.56 MHz) is recorded at a predetermined position for erasing the pilot signal f ₁ , sync 1 signal f _2, and sync 2 signal f ₃ of the previous recording. It

The positions of the ATF pilot signal are different on the on-track and on both adjacent tracks, and the level of the on-track pilot signal and the level of the pilot signal on both adjacent tracks are temporally different, and three types of levels are sampled respectively. Are arranged so that they can.

Five blocks are allocated to each of the ATF-1 and ATF-2 ATF areas, and the pilot signal f _{1 is} allocated to two of the blocks.
Is recorded. The sync signals f ₂ and f ₃ are one block from the center of the position where one adjacent track is recorded or
It is recorded using 0.5 blocks. The pilot signal f ₁ of the other adjacent track is recorded such that the center thereof is located two blocks after the beginning of the sync signal recorded on the on-track. The sync signal of one block is assigned to the odd frame and the sync signal of 0.5 block is assigned to the even frame.

As described above, in the ATF, the frequency of the sync signal differs depending on the A rotary head and the B rotary head, and the recording length of the sync signal differs between the odd frame and the even frame. Therefore, different ATFs are given to all four consecutive tracks, so that they can be distinguished. ATF as described above
The pattern is a 4-track complete type, which is repeated every 4 tracks.

By the way, when a magnetic tape recorded in a format as shown in FIG. 12 (a) is reproduced by a rotary head, an RF signal as shown in FIG. 14 (a) is obtained from the rotary head. If this RF signal is obtained, for example, by reproducing the odd frame track (A) in FIG. 13, 130 KHz
By passing the band pass filter (BPF) of
A pilot signal f ₁ as shown in (b) is obtained.

Section I is due to the on-track pilot signal,
The sections II and III are due to the crosstalk of the pilot signals of the (B) odd frame track and the (B) even frame track, respectively. When the rotary head is scanning on the track correctly, it should be
Envelope level of III, ie VII and VI of (c)
II should be equal, but if there is a track deviation, VII ≠ V
III, the amount and direction of displacement of the rotary head with respect to the on-track can be known from the size and polarity. Therefore, VII and V
The difference in III activates the capstan servo and fine-tunes the tape speed to allow the rotary head to run on track.

In order to perform the above-described operation, it is necessary to accurately detect the sync signal at the predetermined position and sample the VII and VIII levels. However, since the R-DAT does not have an erasing head as described above and performs the second and third recording by overwriting, the sync signal is accurately detected and VII and VIII are sampled to obtain the correct error. Sometimes it was not possible to generate a signal.

That is, in R-DAT, recording is ± from the center of the PCM area.
It is supposed to be done within 2 blocks. Also,
The recording level of the pilot signal f ₁ (= 130 KHz) is set to be slightly lower than the levels of other signals. The lower the frequency of the signal, the deeper the recording level on the tape,
Pilot signal f ₁ recorded before overwriting
Is to be erased by the erase signal f ₄ . However, when the level of the pilot signal f ₁ is lowered in this way, the previously recorded sync signal f ₂ or
When the pilot signal f ₁ is newly recorded at f _3, the previous sync signal may remain without being completely erased.

Specifically, when the later recording is performed earlier than the previous recording, the sync signal of the later recording always precedes the unerased sync signal of the previous recording on the track. Therefore, this does not cause a problem, but when the subsequent recording is shifted backward, the unerased sync signal precedes the sync signal of the subsequent recording. An example of this is the case where there is a shift within the range of 1 to 2 blocks later.
F-1 is an even frame, (A) an odd frame, ATF-2 is a (B) even frame, and (B) an odd frame, the sync signal f _{2 of the} previous recording is added to the pilot signal f _1. , f ₃ will be partially or entirely erased.

When this happens, the level of the frequency component of the pilot signal in the reproduced RF signal at that time is sampled according to the sync signal of the previous recording. This pilot signal should originally be at the crosstalk level of the sampling signal of one adjacent track, but the above-described frequency component to be sampled is the on-track pilot signal itself, and the level obtained by the sampling is a very large value. Becomes After that, the frequency component of the pilot signal in the reproduced RF signal after two blocks is sampled, the difference between this sampled value and the sampled value two blocks before is taken, and this level difference is used as the track deviation amount to control the capstan servo. However, since the sampled earlier is the on-track level, not the cross-talk level of the adjacent track, a very large level difference far from the actual track deviation amount can be obtained. If this happens, the capstan servo will be disturbed and the tape running will be adversely affected.

[Object of the Invention]

The present invention solves the above-mentioned problems and enables the tracking control to be performed normally without malfunction even if the sync signal of the previous recording is erased and left at a position preceding the sync signal of the subsequent recording by overwriting. It is an object of the present invention to provide a rotary head type digital audio reproducing device.

[Outline of Invention]

The present invention has been made in order to achieve the above-mentioned object, and a rotary head type digital audio reproducing apparatus has a structure in which a pilot signal of one adjacent track is crossed after a certain period of time predetermined according to a recording pattern according to detection of a pilot signal. The talk level is sampled and held, and after a certain period of time, a signal representing the amount of track deviation is formed by the held level and the crosstalk level of the pilot signal of the other adjacent track to control the capstan servo. And even if the false sync signal due to overwrite is in front of the true sync signal, correct tracking can be taken without malfunction.
In addition, since the detection sensitivity of the on-track pilot signal can be changed, more reliable tracking control is possible when driving stably, and faster pulling is possible when it is not.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a main part of a rotary head type digital audio reproducing apparatus.

In the figure, a portion A partitioned by a one-dot chain line shows an analog processing system, and a portion D shows a digital processing system.

First, the analog processing system A will be explained.
It is a 0 KHz bandpass filter (BPF), and an RF signal reproduced by a rotary magnetic head (not shown) is input to its input. The 130KHz BPFA1 passes only the pilot signal component of 130KHz from the RF signal and removes signals in other bands. A2 is an envelope detector circuit, whose input is 13
0KHzBPFA1 output is input. The envelope detection circuit A2 converts the vibration of the pilot signal of 130 KHz into a DC level, and supplies this to the input of the sample / hold (S / H) circuit A3 and one input of the addition circuit A3.

The S / H circuit A3 temporarily holds the output of the envelope detection circuit A2 in response to a sample pulse BP (described later) applied to its control input, and supplies this to the other input of the addition circuit A3. The adder circuit A3 adds the output of the envelope detection circuit A2 and the output of the S / H circuit A3, which are respectively supplied to its both inputs, and supplies this to the average value circuit A5.

The output of the envelope detection circuit A2 in each of the on-track pilot period, the pilot period of one adjacent track, and the pilot period of the other adjacent track is the S / H circuit A
3 is temporarily held at the timing of the sample pulse BP.
The sample pulse BP is envelope detected in the first half of each period.
This is for temporarily storing the first half value of the output of A2 in the S / H circuit A3. In the ideal case where the output of the envelope detection circuit A2 has no ripple and there is no interference due to the remaining pilot signal, the S / H circuit A3 is unnecessary, and the output of the envelope detection circuit A2 remains unchanged. S / H circuit A6 and S
The / H circuit A7 and the differential amplifier A9 may be connected to one side of the input.
However, in reality, it is impossible to make the output of the envelope detection circuit A2 to have no ripple, and if there is interference such as overwriting and unerased, there will be a large error when sampling at one point, Therefore, 2 in the same period
The error can be reduced by sampling at points and averaging. Circuits therefor are an S / H circuit A3, an adding circuit A4, and an average value circuit A5. Also, if there is a time margin, use 3 points or 4 points, or increase the sampling time in the first half and the second half of each period and take the peak value of that period,
The error can be further reduced by taking the average.

The S / H circuit A6 sets the level of the on-track pilot signal, the S / H circuit A7 sets the level of crosstalk on one adjacent track, and the S / H circuit A8 sets the level of crosstalk on the other adjacent track. Sample pulses OP, SP1 and from the controller and timing generator described later
Temporarily hold each by SP2. The details of the relationship between the sample pulse OP, SP1 and SP2 with respect to the sample pulse BP will be described later, but BP is generated in the first half of each period, OP is the on-pilot period, SP1 is the pilot period of one adjacent track and SP2 is It is generated in the latter half of each pilot period of the other adjacent track.

The outputs of the S / H circuits A7 and A8 are supplied to the + and-inputs of the differential amplifier A9, respectively. The differential amplifier A9 outputs a track shift amount which is the difference between the signals supplied to the both inputs, that is, the difference between the crosstalk of one adjacent track and the crosstalk of the other adjacent track. The output of the differential amplifier A9 is supplied to one input of the comparator A10 and the input of the S / H circuit A11. Differential amplifier A9 on one input
The output of the 1/2 circuit A12 is supplied to the other input of the comparator A10 to which the output of (1) is input. As a result, the output of the comparator A10 becomes H when the output level of the differential amplifier A9 is lower than the comparison reference. S / H circuit A11
Holds the output of the differential amplifier A9, that is, the track shift amount temporarily in response to the application of the sample pulse GP, and supplies this to the capstan servo as an ATF error signal.

The output of the S / H circuit A6 is supplied to the input of the 1/2 circuit A12. That is, the on-track pilot signal level held in the S / H circuit A6 is halved by the 1/2 circuit A12.
And is supplied as the reference input of the comparator A10.

SW1 and SW1 'are switches interlocking with each other, and operate so that when a control signal from an RS flip-flop, which will be described later, is L, it is on the a-contact side, and when it is H, it is on the b-contact side. + V _1ref and −V _1ref are provided on the a-contact side via resistors R ₁ and R ₂ , respectively, and resistors R ₃ and R ₄ are provided on the b-contact side.
+ V _2ref and -V _2ref are respectively connected via the respective _terminals, and ± V _2ref is supplied to the reference input of the comparator A14 when ± V _1ref is H when the control input is L. Note that there is a relationship of | V _1ref | <| V _2ref |.

The input of the comparator A14 is supplied with the 130 KHz component from the output of the 130 KHz BPFA1. As a result, the comparator A14 outputs a logic "1" when the amplitude of the 130 KHz component is larger on the + side than the + side reference level, a logic "0" when it is larger than the one side reference level on the one side, and an amplitude larger than the reference level. When is small, it works as a kind of hysteresis comparator that outputs an output that holds the previous logic. Moreover, there are two types of reference levels on the + and-sides, one of which can be switched by a control signal.
And SW1 '. When the switches SW1 and SW1 'are switched to the b contact side, the reference level is set so that the dead zone range becomes large.

The 130KHz component of the 130KHzBPFA1 output is also supplied to the input of the zero-cross comparator A16. Is supplied to the input via the contact point b side. That is, the comparators A14 and A16 are
130KHz BPFA1 130KHz component is converted to digital signal and output.

Next, the digital processing system D will be described. D1 is a crystal oscillator that generates a basic clock f _M for driving the system. The basic clock f _M from the output of the crystal oscillator D1 is
The clock (CK) terminal of the system counter 5, which will be described later, 13
It is supplied to the CK terminal of the 0 KHz detector 7 and the CK terminal of the controller and timing generator 8.

D2 is a head touch detector to which an RF signal is supplied to the input, and it is determined whether or not the RF signal is input, that is, whether or not the head and the tape are in contact, and when it is determined that they are in contact , System counter D4 and ATF-2
Reset the flag flip-flop (F / F) D6 to the initial state.

D3 is a data sync and block address detection circuit, which detects the data sync and block address of the subcode and PCM.
Is corrected. The data sync and block address detection circuit D3 actually includes a PCM equalizer, a zero detector, an 8/10 converter, etc., but the detailed description thereof is omitted here.

D4 is a system counter, which manages the outline of the contact period between the head and the tape to judge the recording position of the signal. D5 is a system controller and an ATF window generator, which decodes the output of the system counter D4 to form windows such as ATF and PCM, and pulse when approximately half the head-tape contact period has elapsed. To occur. Apply this pulse to the ATF-2 flag F / FD6 to set the ATF-2 flag F / FD6 and
Apply the F window to the 130KHz detector D7.

130KHz detector D7 is sample pulse BP and detection pulse DE
Although T is generated, its details will be described later. Comparator and timing generator D8 are counter, flag F /
A detection pulse DET from the 130KHz detector D7, a head switching pulse HSWP (A /) from the servo system that is H for A head and L for B head, and ATF-2.
The Q output of the flag F / FD6, the Q output from the F / FD11, and the clock signal from the crystal oscillator D1 are input. Controller and timing generator based on these inputs
D8 outputs sample pulses OP, SP1, SP2 and GP1 as well as UP and DOWN signals UP and DOWN.

The sample pulse OP is supplied to the control input of the S / H circuit A6, the sample pulse SP1 is supplied to the control input of the S / H circuit A7, and the sample pulse SP2 is supplied to the control input of the S / H circuit A8. These sample pulses are pulses generated in the latter half of each period as described above. The pilot signal level is held in the S / H circuit A3 at the first half point by the sample pulse BP from the 130KHz detector D7, and at the second half S / H circuit
The average value of the output of A3 and the output of the envelope detection circuit A2 is
S / H circuits A6, A7 and A8 with sample pulses OP, SP1 and SP2
Held by That is, the average value of the sample values of the first half and the second half of each period is held.

The sample pulse GP1 is, when it is determined that the on-track pilot signal can be detected digitally correctly,
That is, when 5 out of 10 waves are detected, it is a pulse output after a predetermined time after outputting the sample pulse SP2 as OK, which is supplied to the 3-input AND gate D13 and the 2-input AND gate D14, respectively. .

The up signal UP includes all internal flags that are turned on when the on-track pilot signal, the crosstalk of the pilot signals of one adjacent track, and the crosstalk of the pilot signals of the other adjacent track are detected digitally correctly. When it is turned on, one is output at the end of the ATF processing, and when this is input to the UPC terminal of the up / down counter D10, the up / down counter D10 counts up. On the other hand, the down signal DOWN is output when all of the above internal flags are not turned on and the up condition is not satisfied, and by inputting this to the DOWNC terminal of the up / down counter D10. The up / down counter D10 counts down.

D9 is a data memory that stores data indicating the center value of the up / down counter D10.
The data on D9 is used to set the up / down counter D10 to the midpoint when a carry or borrow occurs. The up-down counter D10 counts up when the pilot signals of the on-track and both adjacent tracks are correctly input as described above, and operates down-counting otherwise, and the signal from the carry output CY is RS.
The signal from the borrow output BR is input to the 3-input OR gate D12 and the 2-input OR gate D16, respectively, at the set (S) input terminal of the F / FD11. When the tracking is on-track, the pilot signals of on-track and both adjacent tracks are continuously detected, which causes the carry signal CY of the up / down counter D10 to output the carry signal and the Q output of RSF / FD11. Become H. The Q output of RSF / FD11 is applied to the AND gate D13, the controller and timing generator D8, and the switches SW1 and SW1 '. Switch S
W1 and SW1 'are switched to the b contact side by the Q output which is H of RSF / FD11.

D12 is a 3-input OR gate, and its input has a carry signal and a borrow signal from the up / down counter D10, a system controller and an ATF window generator D.
The reset signal RESET from 5 is input. The output of the OR gate D12 is applied to the load terminal L of the up / down counter D10. That is, when the carry signal or borrow signal is generated, the data from the data memory D9 is set in the up / down counter D10.

The 3-input AND gate D13 has the input of the output of the comparator A10, the controller and the timing generator D8.
The sample pulses GP1 and Q output of RSF / FD11 are applied, respectively, and the output is applied to the input of the 2-input OR gate D15. The 2-input AND gate D14 has at its input the sample pulse GP from the controller and timing generator D8.
The outputs of 1 and RSF / FD11 are applied respectively. Note that D
Reference numeral 15 is a 2-input OR gate to which the output of the 3-input AND gate D13 is applied to one input and the output of the 2-input AND gate D14 is applied to the other input. The output of the OR gate D15 is connected to the S / H circuit A11. A sample pulse GP applied to the control input of is generated.

D16 receives the borrow signal from the up / down counter D10 on one input and the system controller and AT on the other input.
A 2-input OR gate to which the reset signal RESET from the F window generator D5 is applied, and the OR gate D1
The output of 7 is connected to the reset (R) terminal of RSF / FD11. SW2 is a switch that is switched by the switching signal ON / from the controller and the timing generator D8.

Before explaining the operation of the above configuration, the relationship between the position of the ATF and the level of the pilot signal is shown in FIG. That is, the on-track pilot signal with the highest level is the ATF of the A head (+ azimuth).
-1 and B head (-azimuth) ATF-2 are at the front, and A head (+ azimuth) ATF-2 and B head (-azimuth) ATF-1 are at the back.

The position of the head with respect to the track is shown in FIG. 3, and the relationship between the track deviation and the output level of the pilot signal is as shown in FIG. That is, when the track deviates from the head by 45 ° or more, the level of the on-track decreases, and conversely, the level of the adjacent track increases. And the amount of track deviation is 180
Above 0 °, the output levels of the adjacent track and on-track are completely reversed. However, the pilot signal level of the adjacent track does not reach the level of the on-track. This is because azimuth is different and azimuth loss exists.

On the other hand, if the probability of track deviation and sync detection is shown,
It becomes like the figure. Since the sync indicating the position of the pilot signal is used to sample the level of the pilot signal of the adjacent track by its detection,
As can be seen from the figure, almost 100% of the sync can be detected even with a track shift of about 100 °, but almost no sync can be detected with a track shift of 130 ° or more.

By the way, when the envelope of the RF signal is schematically shown,
As shown in FIG. In the figure, the solid line shows the reproduced waveform at the time of on-track and the broken line shows the reproduced waveform at the time of 135 ° shift. Due to the 135 ° track shift, the RE signal level is 1/2
It becomes impossible to read the correct data.

Assuming that there is no track bending and that the sensitivities of the A and B heads do not vary, the levels of the pilot signals on the on-track and on both adjacent tracks with respect to the track shift are schematically shown in FIG. That is, when on-track, the crosstalk of pilot signals on both adjacent tracks is equal, and is 1/2 of on-track.
It is the following. With a track shift of 45 °, crosstalk between any one of the adjacent tracks disappears, and when the track shift increases further, the level difference between the on-track pilot signal and the crosstalk between the pilot signals of one adjacent track decreases. The level reverses around 135 °.

In short, when the track is shifted by 45 ° or more, either one of the adjacent tracks cannot be detected, and conversely, when the pilot signal for each period of the on-track and both adjacent tracks can be detected, the track shift is 45 ° or less. It has become. Therefore, it can be determined that the safe traveling is performed when the pilot signal for the entire period is detected, and the unstable traveling is determined when the pilot signal for the period of any one of the adjacent tracks is not detected.

Further, during unstable running, the pilot signal of one adjacent track cannot be detected, so that the pilot signal of the adjacent track precedes and the pilot signal of the on-track follows, and ATF-2 of A head and ATF- of B head. In the case of 1, the rising position of the pilot signal cannot be accurately detected.

 Next, the operation of the above configuration will be described.

At the start of operation, the track is not always on-track, so it is only on-track that the pilot signal can be detected correctly. The position of the on-track pilot can be detected by the ATF position and the playback head. Further, when the track is not on-track, the level of the pilot signal is low, and thus the lower the threshold value for discrimination, the easier the detection. However, considering erroneous detection due to noise or the like, it is better to set a certain dead zone to detect the on-track pilot signal.

Now system controller and ATF window generator D
When the reset signal RESET is output from 5, the reset signal RESET is applied to the up / down counter D10 and RSF / FD11 via the 3-input OR gate D12 and 2-input OR gate D16, respectively, and is initialized. As a result, the Q output of the RSF / FD11 becomes L and the output becomes H, and the switches SW1 and SW1 'are switched to the a contact side. When the switches SW1 and SW1 'are on the a-contact side, a small range + V _ref , -V _ref is supplied as the reference level of the comparator A14 and the detection sensitivity is set high.

The switch SW2 is at the switching side a when it is at H, L when the switching signal ON / is in the period H of the pilot signal for on-track.
Since it is switched to the b contact side at the time of, the comparator A14 having a dead zone is used when converting the on-track pilot signal to a digital signal, and its output is input to the 130 KHz detector D7 via the a contact side of the switch SW2. To be done. On the other hand, when detecting the pilot signals of both adjacent tracks, the digital signal obtained by converting the pilot signals by the zero-cross comparator A16 is applied to the input of the 130 KHz detector D7 via the b contact side of the switch SW2.

When the 130 KHz detector D7 detects the pilot signal of one and a half waves, it applies the sample pulse BP to the control input of the S / H circuit A3 and also applies the detection pulse DET to the controller and the timing generator D8.

Controller and timing generator D8 is RSF / FD11 Q
It operates according to the output state, and when the Q output is H, tracking is stable and ATF is at any position of ATF.
It operates to detect the error signal. If the on-track pilot signal cannot be detected correctly,
The sample pulse GP1 is not output, but the sample pulse GP1 is output when it is detected correctly.

When the pilot signals of the on-track and both adjacent tracks are correctly detected, the up signal UP is supplied to the up-down counter D10 and the counter value is incremented by +1.
However, when all the pilot signals in the three periods are not correctly detected, the down signal DOWN is supplied to the up / down counter D10 to decrement the count value by -1.

When the Q output of the RSF / FD 11 is L, or when it is determined that tracking is not yet performed, the ATF error signal detection operation is performed only when the on-track pilot signal is in front. That is, AT of A head
Only in the case of the ATF-2 of the F-1 and B-heads, the pilot signal detection operation is performed to detect the track deviation amount and send it to the capstan servo. In other cases, the detection operation is not performed. The operation of digitally detecting the pilot signal is performed in the same manner as in the stable state.

When each initial pilot signal is correctly detected at each ATF position, the up / down counter D10 outputs a carry signal. This carry signal sets RSF / FD11 and its Q
Set the output to H. It can be judged that the tracking is stabilized by the H of the Q output of the RSF / FD11.

When the Q output of RSF / FD11 becomes H, switches SW1 and SW1 'are switched to the b contact side, which causes comparator A1
+ V _2ref and −V _2ref are applied as 4 reference levels, respectively. This reference level increases the dead zone width of the comparator A14 so that only a pilot signal having a large amplitude can be detected, which enables strong detection against noise.

2-input AND gate D1 when Q output of RSF / FD11 is L
4 is turned on, and 2-input AND gate D13 is turned off. The controller and timing generator D8 outputs a sample pulse GP1 when a predetermined time has elapsed after the on-track pilot signal was correctly detected, and outputs the sample pulse GP1 through the 2-input AND gate D14 and the 2-input OR gate D15. Applied to the control input of the S / H circuit A11, and at this time the amount of track deviation output from the differential amplifier A9 is calculated.
Temporarily hold. The level held in the S / H circuit A11 is AT
It is supplied to the capstan servo as an F error signal.

3-input AND gate when Q output of RSF / FD11 is H
Since D13 is turned on and the 2-input AND gate D14 is turned off, the sample pulse GP1 is applied to the control input of the S / H circuit A11 via the 3-input AND gate D13 and the 2-input OR gate D15. At this time, the output of the comparator A10 is also applied to the other input of the 3-input AND gate D13.
The output of the comparator A10 becomes H when the output of the differential amplifier A9 is smaller than 1/2 of the level of the pilot signal of the on-rack. Therefore, when the output of the comparator A10 is H and the track shift amount is 1/2 (or 1/3) or more of the level of the on-track pilot signal, even if the on-track pilot signal is correctly detected, comparator
When the output of A10 becomes L, 3-input AND gate D
13 is off. Therefore, the sample pulse GP1 is sent to the S / H via the 3-input AND gate D13 and the 2-input OR gate D15.
It is not applied to the circuit A11, and the track shift amount at this time is not output as an ATF error signal. That is, when the pilot signal remains unerased and interferes with the pilot signal of the previous recording, and the level of the pilot signal increases, it is not supplied to the capstan servo as an ATF error signal.

FIG. 8 shows the waveform of each part in FIG. In the figure, (a) is the output of 130 KHz BPF, (b) is
Waveform obtained by converting 130 KHz of (a) into a digital signal, (c)
Is an on-track pilot window that becomes H only when the pilot signal is on-track, (d) is a sample pulse BP output at the first half of each pilot signal period, that is, when one and a half waves are detected, (e) is on The sample pulses OP, (f), and (g) generated in the latter half of the track, that is, at the time when three or more waves among the six waves are detected, are sample pulses SP1, which are generated in other pilot signal periods like the sample pulse OP. SP2 and (h) are reset signals RT generated at the end of each pilot signal period.

Fig. 9 shows comparator output, sample pulse BP, OP, SP1, SP2, detection pulse DET, reset signal RT in each period.
FIG. 6 is a timing chart showing the detailed relationship of FIG.

As the 130 KHz detection circuit D7, for example, the one shown in FIG. 10 can be applied.

The 130 KHz component digital signal from the comparator A14 or the zero-cross comparator A16 (FIG. 1) is applied to the phase inversion detection circuit D7-1. Basic clock f _M is D type FF
D7-2, 32 / 8-ary counter D7-3, cycle counter ID7-
9, D type FFD7-10, period counter IID7-11, and D type FFD7-17 with reset.

In addition to the digital signal, the phase inversion detection circuit D7-1 receives the gate signal from the system controller and the ATF window generator D5, and its output is D
It is applied to the D input of the type FFD7-2 and one input of the AND gate D7-14. The D-type FFD7-2 delays the signal by one clock, and its Q output is applied to the R input of the 32 / 8-ary counter D7-3 and the R input of RSFFD7-4 via the OR gate D7-12, respectively.

When the 32 / 8-ary counter D7-3 counts 32 clocks, the CY output becomes H for one clock period, which is RSFFD7-4.
To the S input of. Also, Q ₄ output is AND gate D7-1
Applied to one of the three inputs. RSFFD7-4 has its Q output applied to the other inputs of AND gates D7-13 and D7-14,
The output of the AND gate D7-13 is applied to the OR gate D7-12, and the output of the AND gate D7-14 is RSFFD7-5 and D7-6.
Is applied to the S input and the CK input of the detection counter D7-7.

The Q output of RSFFD7-5 is the E input of the detection counter D7-7,
It is applied to the R input of the cycle counter ID7-9 respectively and RSF
The Q output of FD7-6 is applied to the R input of period counter IID7-11. CY output of detection counter D7-7 is RSFFD7
It is applied to the S input of -8 and the Q output of RSFFD7-8 is applied to one input of AND gate D7-15. RSFFD7−
In the case of 8, the Q output becomes H when the S input has a rising edge, and the Q output becomes L when the input has a falling edge.

CY output of cycle counter ID7-9 is D of D-type FFD7-10
Applied to the input. The Q output of D-type FFD7-10 is applied to one input of NOR gate D7-16.

CY output of cycle counter IID7-11 is NOR gate D7-16
To the other input and the R input of RSFFD7-6.

The output of NOR gate D7-16 is applied to the input of RSFFD7-5, the R input of detection counter D7-7 and the input of RSFFD7-8, respectively.

The output of AND gate D7-15 is supplied to the D input of D-type FFD7-17 with reset, and AND gates D7-18 and D7-
It is supplied to one of the 19 inputs. D type FFD7 with reset
Controller and timing generator D8 for R input of -17
Reset signal RT is applied, and its Q and output are supplied to the other inputs of AND gates D7-18 and D7-19.

The detection pulse DET is output to the output of the AND gate D7-18, and the sample pulse BP is output to the output of the AND gate D7-19.

In the above configuration, the D-type FFD 7-17 with reset is reset by the reset signal RT at the beginning of each period, and its Q and output are L and H. When the phase of the digital signal is inverted, the output of the phase inversion detection circuit D7-1 becomes H for one clock period. The output of the phase inversion detection circuit D7-1 is D
Type FFD7-2 delayed by 1 clock, OR gate D7-1
R input of 32/8 base counter D7-3 and RSFFD7− via 2
It is applied to the R input of 4 and this allows a 32 / 8-ary counter
D7-3 is reset to 0, and the Q output of RSFFD7-4 is set to L.

When the 32 / 8-ary counter D7-3 counts 32 basic clocks f _M input to the CK input, the CY output becomes H,
Since this is applied to the S input of RSFFD7-4, the Q output of RSFFD7-4 becomes H. The output of the AND gate D7-13 in which the Q output of the RSFFD7-4 is applied to one input becomes H when the other input becomes H. Since the Q ₄ output of the 32 / 8-ary counter D7-3 is applied to the other input of the AND gate D7-13, when the Q ₄ output becomes H, that is, the CY of the 32 / 8-ary counter D7-3 is CY. Count 8 clocks of CK input after output goes high (40 counts from phase inversion)
Then, the output of the AND gate D7-13 becomes H, which is the 32 / 8-ary count D7-3 and RSF via the OR gate D7-12.
It is set to the initial state by being applied to the R input of F7-4.

When the phase is inverted within 32 clocks after the phase inversion, the CY output of the 32 / 8-ary counter D7-3 does not become H but is reset to the initial state, and the Q output of RSFFD7-4 remains L. In addition, if the phase inversion occurs after the CY output of the 32 / 8-ary counter D7-3 becomes H and before 8 clocks are counted, that is, during the H period of the Q output of RSFFD7-4, the AND gate D7 -14 through RSFF D7-5 and D7-6
Is set, its Q output becomes H, and at this time, 32/8
The advance counters D7-3 and RSFFD7-4 are reset to the initial state.

The phase inversion detection circuit D7-1, D-type FFD7-2, 32 / 8-ary counter D7-3, RSFFD7-4, OR gate D7-12, AND gates D7-13 and D7-14 provide a constant pulse width, that is, continuous. It constitutes a circuit that detects 1/2 period of the frequency.

Since the pilot signal f ₁ is f _M / 72, it is originally 36, but when the specified pulse width of 32 to 40 is detected, the Q outputs of RSFFD7-5 and D7-6 become H, and the counters D7-7 and D7. -9
And make D7-11 countable.

The detection counter D7-7 has an AND gate D7-1 at its CK input.
4 outputs, ie 1 clock period H for every 1/2 period detected
Pulse is applied and the counting operation is performed. When the detection counter D7-7 counts the specified value, the CY output becomes H, and this is applied to the S input of RSFFD7-8 to make its Q output H. The Q output of RSFFD7-8 is applied to one input of the AND gate D7-15. That is, the detection counter
When D7-7 obtains the detection pulse of the specified number of 1/2 periods, one input of the AND gate D7-15 is set to H and the state is waited.

On the other hand, the cycle counter ID7-9 is a counter that manages a fixed time interval, 126 counts after the Q output of RSFFD7-5 becomes H, that is, after counting 1/2 period x 3 + 1/4 period, the detection counter When the CY output of D7-7 becomes H, one input of the AND gate D7-15 becomes H via RSFFD7-8.
When the CY output of D7-9 becomes H, its output becomes H for one clock period.

When the output of the AND gate D7-15 becomes H, the output of the AND gate D7-19 also becomes H, and this is output as the sample pulse BP. On the other hand, D type FFD7-1 with reset
This is taken in by the D input of 7 becoming H,
Its Q and output are H and L, respectively. Therefore, thereafter, when the output of the AND gate D7-15 becomes H, this appears in the AND gate D7-18 and is output as the detection pulse DET. The Q and output of the D-type FFD 7-17 with reset does not change its state until the reset signal RT is applied again at the beginning of the next period.

When the CK input of the detection counter D7-7 does not have the specified number of count pulses, the RSFFD7-8 has its Q output at L level.
As it is, the output of the AND gate D7-15 never becomes H.

The CY output of the cycle counter ID7-9 is delayed by one clock by the D-type FFD7-10 and then the RSFFD7-5 and D7-8 and the detection counter D7-7 are initialized via the NOR gate D7-16. .

The cycle counter IID7-11 is a counter that manages the time width in which the specified frequency is recorded after detecting the first 1/2 period. In this example, when 2 blocks (76 μs) are counted, the CY output becomes H and RSFFD7-5, D7-8 and D7-6
Further, the detection counter D7-7 is initialized, and the period counter ID7-9 and the period counter IID7-11 are also reset to the initial state.

FIGS. 11 (a) to 11 (g) are timing charts showing waveforms of respective parts in the circuit of FIG. 10, and corresponding symbols are attached to the circuits.

Type FFD7-10 delayed by 1 clock, then NOR gate D
RSFFD7-5 and D7-8 and detection counter D7-7 are initialized via 7-16.

The cycle counter IID7-11 is a counter that manages the time width in which the specified frequency is recorded after detecting the first 1/2 period. In this example, when counting 2 blocks (76 μs), the CY output is at H and RSFFD7-5, D7-8 and D7-6
Further, the detection counter D7-7 is initialized, and the period counter ID7-9 and the period counter IID7-11 are also reset to the initial state.

FIGS. 11 (a) to 11 (g) are timing charts showing waveforms of respective parts in the circuit of FIG. 10, and corresponding symbols are attached to the circuits.

〔effect〕

As described above, according to the present invention, since the pilot signal component after a fixed period of time is sampled and held after the detection of the pilot signal, erroneous sampling due to the false sync signal is prevented, and the wrong track is erroneously recorded. The tracking amount is not disturbed by supplying the shift amount to the capstan servo, and stable tracking control can be performed.

In addition, since the sensitivity is changed during stable driving and unstable driving, reliable and reliable tracking control can be performed during stable driving, and no response is easily made to noise. When driving stably, you can pull in to the on-track faster.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of a rotary head type digital audio reproducing apparatus according to the present invention, FIG. 2 is a waveform diagram showing a relationship between each track and an ATF position, and FIG. 3 is a track shift. And FIG. 4 is a graph showing the relationship between track deviation and pilot signal output level, FIG. 5 is a graph showing relationship between track deviation and sync detection probability, and FIG. 6 is on-track. The figure which shows the RF signal level of 130 degree gap, FIG. 7 is the waveform figure which shows the relationship of the waveform with respect to track gap, FIG. 8 is the waveform figure which shows the waveform of each part of FIG. 1, FIG. 9 is the figure of FIG. FIG. 10 is a timing chart showing the details of the timing of each period, FIG. 10 is a block diagram showing an example of the 130 KHz detection circuit in FIG. 1, and FIG. 11 is a timing chart showing the waveform of each part in FIG. Figure 12 shows the R-DAT track Shows the formatting and block format, FIG. 13 is a diagram showing the ATF track format of R-DAT,
And FIG. 14 is a view for explaining the principle of tracking control by the track pattern of FIG. A7, A11 …… Sample hold (S / H) circuit, A9 …… Differential amplifier, A14 …… Comparator, SW ₁ …… Changeover switch,
D7 ... 130KHz detection circuit, D10 ... up / down counter, D11 ... RS flip-flop.

Claims (1)

(57) [Claims] 1. A plurality of signals including a digital pilot signal and a tracking pilot signal composed of a frequency signal having a small azimuth effect on each of the plurality of diagonal tracks are predetermined in the longitudinal direction of each track with independent recording areas. A plurality of signals on a recording medium, which are recorded in a format and are recorded at different positions with respect to the recording patterns of the pilot signals recorded on four continuous tracks, are reproduced by a rotary head, The width of the rotary head is made wider than the width of each track, and crosstalk between the pilot signals of the on-track and the pilot signals of both adjacent tracks is obtained at the output of the rotary head by reproducing each track.
The capstan servo is controlled according to the level difference of the crosstalk between the pilot signals of the two adjacent tracks so that the rotary head scans each track, and the pilot signal in each output signal of the rotary head is Pilot signal detecting means for detecting a rising edge, and sampling and holding of crosstalk of pilot signals of one adjacent track after a predetermined time set according to the recording pattern in accordance with detection of the pilot signal by the pilot signal detecting means. Of the capstan servo by forming a signal indicating the track deviation amount by the holding means for holding the holding means and the level of the crosstalk of the pilot signal of the other adjacent track after a certain time after the sampling. Means for controlling, the pilot signal The detection means has an on-track pilot signal detection means for detecting an on-track pilot signal, and the detection sensitivity of the on-track pilot signal detection means is set high during startup or unstable traveling, and lowered during stable traveling. A rotating head type digital audio playback device.