JP2516974B2 - Reset device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset device that reliably resets a microcomputer when a power supply voltage drops below a certain value.

2. Description of the Related Art Conventionally, this type of reset device has a structure as shown in FIG. That is, 1 is a microcomputer, 2 is a reset circuit, and a resistor 3 and a capacitor 4 are provided between the power supply and ground.
Insert a circuit element connected in series with the resistor 3 and capacitor 4
Is connected to the reset terminal RST of the microcomputer 1.
Connected to Reference numeral 5 is a RAM connected to the microcomputer 1 by an address bus 6 and a data bus 7.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above-described conventional configuration, when the state where the power supply voltage is lower than the predetermined value continues (for example, when the power is turned off), the electric charge of the capacitor 4 passes through the resistor 3 to the power source. The reset terminal of the microcomputer 1 can be set to a low level because it is discharged to the side, but at the moment of a momentary power failure (hereinafter referred to as a momentary power failure) in which the power supply voltage drops momentarily, the charge of the capacitor 4 passes through the resistor 3 and the power supply side. Since the power supply voltage recovers before being fully discharged, the microcomputer 1 cannot be reset by setting the RST terminal of the microcomputer 1 to the low level, and the microcomputer 1 malfunctions.

Further, in the above conventional configuration, the microcomputer 1
Since the reset terminal RST of and the chip select terminal CS of RAM5 were connected, the following malfunction may occur. That is, in FIG. 6, at t = t ₀ , the microcomputer 1 issues a pulse ▲ ▼ for writing the data 2 to the RAM 5, and the power is turned off before the pulse ▲ ▼ is completed, and the microcomputer 1
For example, when a low level voltage is applied to the reset terminal RST of the RAM at the timing of t = t ₁ , the RAM operates as if the pulse ▲ ▼ ′ was issued, and the previous data is replaced by the data that is the previous data. I sometimes wrote 1 to RAM.

Further, as another conventional example, the power supply voltage is compared by a comparator 8
There is the one shown in FIG. 7 that is compared with the reference value and led to the reset terminal of the microcomputer 1 through the one-shot multivibrator 9, but the circuit configuration is complicated and expensive.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above conventional problems and to provide at low cost a reset device having a simple structure and capable of reliably resetting a microcomputer.

Means for Solving the Problems In order to achieve the above object, the present invention connects a power source to a non-maskable interrupt terminal of a microcomputer, and includes at least two resistance elements between the non-maskable interrupt terminal and a port of the microcomputer. The dividing resistor is connected, the reset terminal of the microcomputer and one end of the capacitor are connected to the connection point of the two resistance elements, and the other end of the capacitor is grounded.

Operation The operation of the present invention with the above configuration is as follows. That is, non-maskable interrupt processing is performed during a momentary power failure of the power supply, and the port is set to output mode to low level to discharge the electric charge of the capacitor and force the reset terminal to a voltage below the voltage at which the microcomputer is reset, ensuring the microcomputer. Will be reset.

EXAMPLES Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a reset device according to an embodiment of the present invention, in which 10 is a sense terminal for detecting a power supply voltage, 11 is a microcomputer, and 12 is a falling edge of an input voltage. A non-maskable interrupt pin (hereinafter referred to as NMI pin) that generates a non-maskable interrupt is connected to the sense pin. 13 is a port whose input and output can be switched by a microcomputer program, and is reset (described later).
When this is applied, the input mode becomes high in impedance. 14 is the reset terminal of the microcomputer,
As shown in FIG. 2b, the terminal voltage is set to reset the microcomputer 11 between V ₁ and V ₂ . R ₁ and R ₂ are dividing resistors connected between the NMI terminal 12 and the port 13, and are, for example, 18 KΩ and 3.3 KΩ, respectively.
The division point P is connected to the reset terminal 14 and
Between the dividing point P and the ground, for example, a capacitor C of 0.47 μF
Is connected. Reference numerals 15 and 16 respectively denote an address terminal and a data terminal of the microcomputer, which are connected to the address terminal 18 and the data terminal 19 of the RAM 17 to exchange addresses and data. Reference numerals 20 and 21 respectively denote a write terminal and a read terminal for outputting a write pulse or a read pulse from the microcomputer, and are connected to the write terminal 22 and the read terminal 23 of the RAM 17, respectively. twenty four
Is a chip select terminal for inhibiting reading and writing of data from the RAM 17 when a low level is detected, and is connected to the reset terminal of the microcomputer.

In the above configuration, the reset operation of the microcomputer will be described below.

Fig. 2 a, b and c are sense terminal 10 and reset terminal 1 respectively
4, shows the voltage waveform that appears at port 13, and when the power is turned on at t = t ₀ , the rising edge of the voltage (V ₀ ) is input from the sense terminal 10 to the NMI terminal 12, and the reset terminal 14 and port 13 The capacitor C has a time constant τ ₁ (= R ₁ · C)
The voltage is applied as it is charged at. Reset terminal
When the voltage applied to 14 exceeds V ₁ , the reset operation of the microcomputer 11 is released,
11 ready for operation. Next, assuming that the power supply voltage instantaneously drops at t = t ₁ , the charge charged in the capacitor C starts discharging to the sense terminal through the resistor R ₁ and at the same time, the NMI terminal connected to the sense terminal 10 becomes When the falling edge is detected, the interrupt shown in the flowchart of FIG. 3 is generated. In FIG. 3, in step 1, processing necessary for interruption is performed, for example, data SAVE or the like is performed. In step 2, the port 13 is set to an output mode with low impedance, and in step 3, a low level is output to the port 13. As a result of the low level being output to the port 13, the charge charged in the capacitor C is discharged to the port through the resistor R ₂ , and therefore the discharge of the capacitor C is time constant τ ₂ (= R · C, where R = R ₁ It will be done rapidly at // R ₂ ). When the charge of the capacitor C is discharged down voltage of the reset terminal 14, the drops to the voltage V _2, the process of the non-maskable interrupt reset operation is applied to the microcomputer 11 ends. Microcomputer 11
When the reset is applied to the port, the port becomes the input mode with high impedance, the power supply voltage is applied from the sense terminal 10 to the NMI terminal 12, and the capacitor C is discharged to the reset terminal 14 with the time constant τ _1. The voltage having the same waveform as when the power is turned on is applied at = t ₀ .

Next, if the power is turned off at t = t ₂ , the sense terminal 10
From the NMI pin to the falling edge of the voltage, the non-maskable interrupt process described above is performed, and the capacitor C
Are discharged with a time constant τ ₂ . Since the power supply is off, the sense terminal is at low level and the capacitor C is not charged.

As described above, according to this embodiment, the power supply voltage is connected to the NMI terminal 12 of the microcomputer 11, and when the power supply voltage is momentarily stopped, the port 13 is forcibly set to the low level and the voltage applied to the reset terminal 14 is controlled. Since it is lowered, the microcomputer 11 can be reliably reset.

In addition, in this embodiment, the data like the conventional example is erroneously
It is possible to prevent malfunctions such as writing to RAM. That is, as shown in FIG. 4, at t = t ₀ , the microcomputer 11 issues a pulse ▲ ▼ for writing the data 2 to the RAM 17 from the write terminal 20, and before this pulse ▲ ▼ is completed. When the power is turned off at t = t ₁ , the voltage of the sense terminal 10 and the NMI terminal 12 is t
At the timing of t = t ₁ , the microcomputer 11 starts the non-maskable interrupt processing at the timing of t = t ₂ . This interrupt processing is not performed until t = t ₂ instead of at the timing of t = t _1. Generally, when a microcomputer receives an interrupt in order to protect the calculation result, it may be processed immediately. This is because the current processing is completed and then the interrupt processing is started. The embodiment of the present invention skillfully utilizes this, and the microcomputer 11 completes the data write operation to the RAM 17 before the non-maskable interrupt processing is started, so that the data written to the RAM 17 is written. Is written correctly without mistakes. The non-maskable interrupt process ends after the microcomputer 11 is reset as shown in the flow chart of FIG. 3, and the chip select terminal 24 of the RAM 17 is not until the microcomputer resets.
Becomes low level, and the data in the RAM 17 is protected.

As is apparent from the above embodiments, the present invention connects the power supply to the non-maskable interrupt terminal of the microcomputer and divides the non-maskable interrupt terminal and the port of the microcomputer by at least two resistance elements. Since a resistor is connected, the reset terminal of the microcomputer and one end of the capacitor are connected to the grounding point of the two resistance elements, and the other end of the capacitor is grounded, the power failure is extremely simple. It is possible to inexpensively provide a reset device that can surely reset the microcomputer even at any time.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a reset device according to an embodiment of the present invention, and FIG.
FIG. 4 is the same operation waveform diagram, FIG. 3 is the same flow chart, FIG. 4 is the same operation waveform diagram, FIG. 5 is a circuit diagram of a conventional example, FIG. 6 is the same operation waveform diagram, and FIG. 7 is another conventional example. It is a block diagram of. 11 …… Microcomputer, 12 …… Non-maskable interrupt terminal, 13 …… Port, 14 …… Reset terminal, R ₁ , R ₂ … Resistance, C …… Capacitor.

Claims (1)

(57) [Claims] 1. A reset device for a microcomputer having a non-maskable interrupt terminal, a port whose input and output can be switched by a program, and a reset terminal, wherein a power supply is connected to the non-maskable interrupt terminal. A dividing resistor composed of at least two resistance elements is connected between the rust terminal and the port, the reset terminal and one end of the capacitor are connected to the connection point of the two resistance elements, and the other end of the capacitor is grounded. A reset device characterized by the above.