JP2515755B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2515755B2 JP2515755B2 JP61225905A JP22590586A JP2515755B2 JP 2515755 B2 JP2515755 B2 JP 2515755B2 JP 61225905 A JP61225905 A JP 61225905A JP 22590586 A JP22590586 A JP 22590586A JP 2515755 B2 JP2515755 B2 JP 2515755B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- solder connection
- connection terminals
- signal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置、特に面付用電子部品を、基板に
両面付した場合に、両面に実装した素子の信号ピンを並
列接続する回路構成が可能な装置に係り、特にメモリ素
子等の多数のアドレス信号を持つ素子の実装に好適な実
装及び信号配線方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a semiconductor device, and particularly to a circuit configuration for connecting signal pins of elements mounted on both surfaces in parallel when surface mounting electronic components are mounted on both surfaces. And a signal wiring method suitable for mounting an element having a large number of address signals such as a memory element.
個々の電子部品を支持し電気信号を接続するための実
装方法には、プリント基板が最も一般的である。その信
号配線層数は、部品の実装密度が高くなるに伴い増加
し、基板は高価なものとなる。そのため、配線の本数を
減らし、また配線の長さを短くし、それぞれの配線の交
差を減らすことが基板を安価に製作するための基本とな
っている。A printed circuit board is the most common mounting method for supporting individual electronic components and connecting electrical signals. The number of signal wiring layers increases as the mounting density of components increases, and the board becomes expensive. Therefore, reducing the number of wirings, shortening the length of the wirings, and reducing the intersections of the respective wirings are the basis for manufacturing the substrate at low cost.
近年さらに部品の実装密度を向上させるために、基板
の両面に、面付実装する技術が普及してきたため、基板
の配線本数と交差は益々増加し、複雑となり、配線層数
が増加して、基板はより高価なものとなってきている。In recent years, in order to further improve the mounting density of components, the technique of surface mounting on both sides of the board has become widespread. Is becoming more expensive.
そこで本発明の目的は、鏡面対称のピン配置を有する
素子を使用することにより、上記両面面付実装に使用す
る基板の配線本数を減らし、その配線層数を減らすこと
により安価な基板を製作することにある。Therefore, an object of the present invention is to manufacture an inexpensive board by reducing the number of wirings of the board used for the double-sided mounting by using an element having a mirror-symmetrical pin arrangement and reducing the number of wiring layers. Especially.
上記目的は、特に半導体メモリ素子のように、多数の
アドレス信号ピンやデータ信号ピンを持ち、それを複数
個並列に接続する回路構成の時、その鏡面対称のピン配
置を持つ同一機能のメモリ素子を基板の両面に鏡面対称
になるように実装する。基板をはさんで向かい合う素子
の信号ピンは回路上共通にすることができるので、それ
ぞれ向かい合う信号ピンを信号ピン接続のランド近傍で
スルーホールを介して接続する。これにより向い合う信
号ピンの配線本数は２本から１本へ減らすことができ
る。The above-mentioned object is to provide a memory device having the same function having a mirror-symmetrical pin arrangement in a circuit configuration having a large number of address signal pins and data signal pins and connecting a plurality of them in parallel, such as a semiconductor memory device. Are mounted on both sides of the board so as to be mirror-symmetric. Since the signal pins of the elements facing each other across the substrate can be made common in the circuit, the signal pins facing each other are connected via a through hole near the land of the signal pin connection. As a result, the number of signal pin wirings facing each other can be reduced from two to one.
上記方法で、向い合う信号をスルーホール接続するこ
とで配線が１本減る。この構成が多ければ多い程、基板
全体の配線総本数は減少し、配線層数を減らすことがで
きるわけである。In the above method, one signal line is reduced by connecting facing signals through holes. The more this structure is, the smaller the total number of wirings on the entire substrate is, and the number of wiring layers can be reduced.
以下、本発明の一実施例を第１図により説明する。 Hereinafter, an embodiment of the present invention will be described with reference to FIG.
本実施例は、256Kビットダイナミックランダムアクセ
スメモリ（以下DRAM）の面付用素子を実装したものであ
る。プリント基板２の上面に通常のDRAM素子１を実装
し、下面にその鏡面対称ピン配置を有する同一機能のDR
AM3を実装する。この場合、第２図（ａ），（ｂ）に示
すようにDRAM素子１と３を向かい合わせにすると、各機
能の信号ピンが対応した位置に合せることができる。し
たがって、制御信号▲▼，▲▼及びアドレス
信号端子A0〜A8をスルーホール４を介して接続する。そ
れらのそれぞれの信号端子を各１本の配線で他のDRAM素
子と接続する。なお、NCは回路結線を行わない通称「空
きピン」である。第３図に、その配線パターン例を示
す。第３図（ａ）は、DRAM素子１を実装する第１層（お
もて面）の配線パターンである。（ｂ）は、その鏡面対
称素子３を実装する第２層（裏面）の配線パターンであ
る。図中長方形のハッチングで示した部分は第２図のピ
ン配置に対応したプリント基板の半田接続端子である。
（ａ），（ｂ）のパターン図は、第１層側から透視した
図であり、それぞれDRAM素子１個分の配線を示してい
る。なお、プリント基板の前述したスルーホール接続部
４は○印で示している。この等価回路図が第４図であ
る。この回路構成を説明する。In this embodiment, a surface mounting element of a 256 Kbit dynamic random access memory (hereinafter referred to as DRAM) is mounted. A DR having the same function as the normal DRAM device 1 mounted on the upper surface of the printed circuit board 2 and its mirror-symmetrical pin arrangement on the lower surface.
Implement AM3. In this case, if the DRAM elements 1 and 3 are faced to each other as shown in FIGS. Therefore, the control signals ▲ ▼, ▲ ▼ and the address signal terminals A0 to A8 are connected through the through hole 4. Each of these signal terminals is connected to another DRAM element by one wire. Note that NC is a so-called "empty pin" that does not connect the circuit. FIG. 3 shows an example of the wiring pattern. FIG. 3A is a wiring pattern of the first layer (front surface) on which the DRAM element 1 is mounted. (B) is a wiring pattern of the second layer (back surface) on which the mirror symmetric element 3 is mounted. The rectangular hatched portions in the figure are solder connection terminals of the printed circuit board corresponding to the pin arrangement of FIG.
The pattern diagrams of (a) and (b) are perspective views seen from the first layer side, and each show a wiring for one DRAM element. The through-hole connecting portion 4 of the printed circuit board described above is indicated by a circle. This equivalent circuit diagram is shown in FIG. This circuit configuration will be described.
ロウアドレスを取り込み、DRAM素子を動作可能状態に
する▲▼信号を、第１層側素子１用の▲
▼と、第２層側素子３用の▲▼の２本設け、２
バンク構成としている。カラムアドレスを取り込み▲
▼信号、読み出し及び書き込みを切り換える▲
▼信号、読み出しデータDin書き込みデータDout、アド
レス信号A0〜A8をそれぞれ第１図で示す方法で結線して
いる。本図は、D0及びD1の２ビット入出力しか示してい
ないが、D2〜Dnの上位ビットに対しても同様である。The row address is taken in and the signal for making the DRAM element operable is sent to the first layer side element 1.
▼ and two for the second layer side element 3 are provided, 2
It has a bank structure. Import column address ▲
▼ Switching between signal, read and write ▲
Signals, read data Din, write data Dout, and address signals A0 to A8 are connected by the method shown in FIG. Although this figure shows only 2-bit input / output of D0 and D1, the same applies to the upper bits of D2-Dn.
本発明によれば、従来の４層以上の多層基板を２層に
することができ、安価な基板とすることができる。According to the present invention, a conventional multilayer substrate having four or more layers can be formed into two layers, and an inexpensive substrate can be obtained.
第１図は本発明の一実施例の256KビットDRAM面付素子を
両面に実装した断面図、第２図（ａ），（ｂ）は第１図
に実装した２つの素子のそれぞれ通常のピン配置の素子
とその鏡面対称のピン配置の素子との上面図、第３図
（ａ），（ｂ）は第１図に示した基板の配線を第１層と
第２層に分けて示す配線図、第４図はプリント基板に実
装したD-RAM素子の等価回路である。 １……通常の256KビットDRAM素子、２……プリント基
板、３……鏡面対称の256KビットDRAM素子、４……基板
のスルーホール、５……チップコンデンサ、６……第１
層の配線パターン、７……第２層の配線パターン。FIG. 1 is a cross-sectional view of a 256K-bit DRAM surface-mounted device according to an embodiment of the present invention mounted on both sides, and FIGS. 2A and 2B are normal pins of the two devices mounted in FIG. 3A and 3B are top views of the element arranged and the element having the mirror-symmetrical pin arrangement, and FIGS. 3A and 3B show the wiring of the substrate shown in FIG. 1 divided into the first layer and the second layer. FIG. 4 and FIG. 4 are equivalent circuits of the D-RAM element mounted on the printed board. 1 ... Ordinary 256K bit DRAM device, 2 ... Printed circuit board, 3 ... Mirror-symmetric 256K bit DRAM device, 4 ... Board through hole, 5 ... Chip capacitor, 6 ... First
Wiring pattern of layer, 7 ... Wiring pattern of second layer.
Claims (1)
と、前記第１の半導体素子に対して鏡面対称ピン配置を
有する上記第１の半導体素子と同一機能の第２の半導体
素子と、その表面に上記第１の半導体素子の信号ピンに
接続されるべき複数の半田接続端子を持つとともにその
裏面に前記第２の半導体素子に接続されるべき複数の半
田接続端子を持ち前記表面の複数の半田接続端子と前記
裏面の複数の半田接続端子とが互いに対向する位置に配
置されてなりかつ前記表面の複数の半田接続端子と前記
裏面の複数の半田接続端子とが半田接続端子部を除く部
分においてスルーホール接続によって電気的に接続され
てなる基板とを有し、前記第１の半導体素子と前記第２
の半導体素子とを前記基板に半田接続により実装してな
ることを特徴とする半導体装置。1. A first semiconductor element having a plurality of signal pins, and a second semiconductor element having the same function as the first semiconductor element having a mirror symmetric pin arrangement with respect to the first semiconductor element, A plurality of solder connection terminals to be connected to the signal pins of the first semiconductor element are provided on the front surface, and a plurality of solder connection terminals to be connected to the second semiconductor element are provided on the back surface thereof. The solder connection terminals and the plurality of solder connection terminals on the back surface are arranged at positions facing each other, and the plurality of solder connection terminals on the front surface and the plurality of solder connection terminals on the back surface exclude the solder connection terminal portion. A substrate electrically connected by a through-hole connection at a portion thereof, and the first semiconductor element and the second semiconductor element.
2. A semiconductor device comprising the semiconductor element of claim 1 mounted on the substrate by soldering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61225905A JP2515755B2 (en) | 1986-09-26 | 1986-09-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61225905A JP2515755B2 (en) | 1986-09-26 | 1986-09-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6381973A JPS6381973A (en) | 1988-04-12 |
| JP2515755B2 true JP2515755B2 (en) | 1996-07-10 |
Family
ID=16836724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61225905A Expired - Lifetime JP2515755B2 (en) | 1986-09-26 | 1986-09-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2515755B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB8927164D0 (en) * | 1989-12-01 | 1990-01-31 | Inmos Ltd | Semiconductor chip packages |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5248418B2 (en) * | 1975-11-07 | 1977-12-09 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5814391Y2 (en) * | 1975-10-02 | 1983-03-22 | 三洋電機株式会社 | Regular rhythm pattern |
-
1986
- 1986-09-26 JP JP61225905A patent/JP2515755B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5248418B2 (en) * | 1975-11-07 | 1977-12-09 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6381973A (en) | 1988-04-12 |
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