JP2512828B2 - Chip component mounting method - Google Patents
Chip component mounting methodInfo
- Publication number
- JP2512828B2 JP2512828B2 JP2237082A JP23708290A JP2512828B2 JP 2512828 B2 JP2512828 B2 JP 2512828B2 JP 2237082 A JP2237082 A JP 2237082A JP 23708290 A JP23708290 A JP 23708290A JP 2512828 B2 JP2512828 B2 JP 2512828B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chip component
- conductive film
- mounting method
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
Description
【発明の詳細な説明】 《産業上の利用分野》 この発明は、プリント配線基板に抵抗、コンデンサ、
インダクタなどのチップ部品を実装する方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a printed wiring board having a resistor, a capacitor,
The present invention relates to a method of mounting a chip component such as an inductor.
《従来の技術》 電子回路装置の小型化を達成するために、回路素子自
体の小型化や形態の工夫がなされているとともに、これ
を実装するプリント基板の配線構造や実装方法について
もさまざまな工夫がなされている。小型で高密度な実装
が可能な素子形態として、ほぼ直方体の素子チップの両
端部に端子導電膜が被覆形成されているチップ部品が知
られている。これはリード線やリードフレームがなく、
プリント配線基板の導電パターン上に端子導電膜を接す
るようにして直接設置されてはんだ付けされる。この種
の実装方法は表面実装と呼ばれており、各種の電子回路
装置に適用されている。<< Prior Art >> In order to achieve miniaturization of electronic circuit devices, the circuit elements themselves have been miniaturized and devised, and the wiring structure and mounting method of the printed circuit board on which they are mounted have been devised in various ways. Has been done. As a small-sized element form capable of high-density mounting, a chip component in which terminal conductive films are formed on both ends of a substantially rectangular element chip is known. This has no lead wire or lead frame,
The terminal conductive film is directly placed on the conductive pattern of the printed wiring board so as to be in contact therewith and soldered. This type of mounting method is called surface mounting and is applied to various electronic circuit devices.
《発明が解決しようとする課題》 チップ部品をプリント配線基板上に直接的に密着配置
する表面実装方法によれば、回路素子のリード線やリー
ドフレームを基板の穴に通してはんだ付けする実装構造
に比べて実装後の高さ（基板の厚み方向の寸法）を大巾
に小さくすることができる。しかし基板の表面にチップ
部品を配列する構造であるため、部品数が多ければ基板
の面積を大きくしなければならず、大規模な回路装置に
なると複数の基板に分けて表面実装したものを多段に重
ねるような構造をとらざるを得ない。<Problems to be Solved by the Invention> According to the surface mounting method in which chip components are directly and closely arranged on a printed wiring board, a mounting structure in which lead wires of a circuit element or a lead frame are passed through holes in a board to be soldered The height after mounting (dimension in the thickness direction of the substrate) can be greatly reduced compared to. However, since the chip parts are arranged on the surface of the board, the area of the board must be increased if the number of parts is large, and in the case of a large-scale circuit device, it is possible to divide the surface-mounted one into a plurality of boards. There is no choice but to take a structure that overlaps.
この発明は前述した従来の問題点に鑑みなされたもの
で、その目的は、チップ部品をプリント配線基板に実装
する際にその厚み寸法を従来よりさらに低く押さえるこ
とができ、しかも基板の厚み方向に容易に多重構造を取
ることができるようにしたチップ部品の実装方法を提供
することにある。The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to make it possible to suppress the thickness dimension of the chip component to be lower than that of the conventional one when mounting the chip component on the printed wiring board, and further, in the thickness direction of the board. Another object of the present invention is to provide a chip component mounting method that can easily adopt a multiple structure.
《課題を解決するための手段》 そこでこの発明では、プリント配線基板の所定位置に
該チップ部品の該端子導電膜それぞれに対応した２つの
仮穴を形成し、該仮穴それぞれの内面に配線用導電膜を
形成してから、該両仮穴の間の部分を切除することでチ
ップ設置穴を形成し、次いで該チップ部品を該チップ設
置穴に該基板と平行な姿勢でほぼ埋設状態で嵌合して該
端子導電膜と該配線用導電膜とをはんだ付けするように
した。<< Means for Solving the Problem >> Therefore, in the present invention, two temporary holes corresponding to the terminal conductive films of the chip component are formed at predetermined positions of the printed wiring board, and wiring is provided on the inner surface of each of the temporary holes. After forming the conductive film, a portion between the temporary holes is cut off to form a chip mounting hole, and then the chip component is fitted into the chip mounting hole in a state parallel to the substrate in a substantially embedded state. Then, the terminal conductive film and the wiring conductive film are soldered.
《作用》 プリント配線基板の所定位置に該チップ部品の該端子
導電膜それぞれに対応した２つの仮穴を形成し、該仮穴
それぞれの内面に配線用導電膜を形成してから、該両仮
穴の間の部分を切除することで、内面に配線用導電膜が
形成されたチップ設置穴を簡単に形成することができ
る。<< Operation >> Two temporary holes corresponding to each of the terminal conductive films of the chip component are formed at predetermined positions on the printed wiring board, and a conductive film for wiring is formed on the inner surface of each of the temporary holes. By cutting the portion between the holes, it is possible to easily form the chip installation hole having the conductive film for wiring formed on the inner surface.
そして、このチップ設置穴にチップ部品を嵌合するこ
とでチップ部品が基板の配線パターンに対して位置決め
され、その状態で端子導電膜と配線用導電膜とをはんだ
付けする。このはんだ付けの際、端子導電膜と配線用導
電膜との間には、入り込んだはんだの表面張力によって
互いに引き合う力が働く。これにより、チップ部品は、
チップ設置穴内に位置決めされ、安定した状態でプリン
ト配線基板の厚み内にほぼ収まって実装される。Then, by fitting the chip component into the chip installation hole, the chip component is positioned with respect to the wiring pattern of the substrate, and in that state, the terminal conductive film and the conductive film for wiring are soldered. During this soldering, a force pulling each other acts between the terminal conductive film and the conductive film for wiring due to the surface tension of the solder that has entered. As a result, the chip parts are
It is positioned in the chip installation hole and mounted in a stable state within the thickness of the printed wiring board.
《実施例》 本発明の一実施例による実装方法の要点を第１図〜第
５図にしたがって順次説明する。<< Embodiment >> The essential points of the mounting method according to an embodiment of the present invention will be sequentially described with reference to FIGS.
まず第１図に示すように、プリント配線基板１の所定
部分に、以下に説明する１個のチップ設置穴の両端部に
相当する２個の細い長方形の穴2aと2bを開口する。First, as shown in FIG. 1, two thin rectangular holes 2a and 2b corresponding to both ends of one chip installation hole described below are opened in a predetermined portion of the printed wiring board 1.
次に第２図に示すように、基板１の表面に所定パター
ンで配線用導電膜３や４などを形成するが、その際にス
ルーホールはんだと同様にして前記の穴2aと2bの内周面
にもそれぞれ導電膜３に連続している導電膜と導電膜４
に連続している導電膜を被覆形成する。Next, as shown in FIG. 2, conductive films 3 and 4 for wiring are formed on the surface of the substrate 1 in a predetermined pattern. At that time, the inner periphery of the holes 2a and 2b is formed in the same manner as through-hole solder. Conductive film and conductive film 4 which are respectively continuous with the conductive film 3 on the surface
To form a continuous conductive film.
次に第３図に示すように、基板１の前記の穴2aと2bの
間を部分をも切除してチップ部品５の寸法に合わせた１
個のチップ設置穴２を形成する。これにより、内面に相
絶縁された２つの配線用導電膜3,4が形成されたチップ
設置穴２を簡単に形成することができる。Next, as shown in FIG. 3, the part between the holes 2a and 2b of the substrate 1 is also cut off to fit the size of the chip component 1
The individual chip mounting holes 2 are formed. As a result, it is possible to easily form the chip mounting hole 2 in which the two electrically insulating conductive films 3 and 4 for wiring are formed on the inner surface.
そして第３図〜第４図に示すように、基板１のチップ
配置穴２にチップ部品５を嵌め込む。こうするとチップ
部品５は基板１の厚み内に埋め込まれた配置状態とな
り、チップ部品５の一方の端子導電膜６が基板１の配線
導電膜３に対向し、他方の端子導電膜７が配線用導電膜
４と対向する。Then, as shown in FIGS. 3 to 4, the chip component 5 is fitted into the chip placement hole 2 of the substrate 1. By doing so, the chip component 5 is placed in a state of being embedded in the thickness of the substrate 1, one terminal conductive film 6 of the chip component 5 faces the wiring conductive film 3 of the substrate 1, and the other terminal conductive film 7 is for wiring. It faces the conductive film 4.
次に第５図に示すように、基板１の所定部分にはんだ
をデップして、チップ設置穴２内のチップ部品５の両端
子導電膜６と７を基板１の配線用導電膜３と４にそれぞ
れはんだ付けする。第５図の８と９はデップされたはん
だを示している。このはんだ付けの際、端子導電膜6,7
と配線用導電膜3,4との間には、入り込んだはんだ8,9の
表面張力によって互いに引き合う力が働く。これによ
り、チップ部品５は、チップ設置穴２内に位置決めさ
れ、安定した状態で基板１の厚み内にほぼ収まって実装
されることになる。Next, as shown in FIG. 5, solder is dipped on a predetermined portion of the substrate 1 so that both terminal conductive films 6 and 7 of the chip component 5 in the chip installation hole 2 are connected to the wiring conductive films 3 and 4 of the substrate 1. Solder to each. 8 and 9 in FIG. 5 show the solder which has been dipped. During this soldering, the terminal conductive film 6,7
Between the wiring and the conductive films 3 and 4 for wiring, a force attracting each other is exerted by the surface tension of the solder 8 and 9 that has entered. As a result, the chip component 5 is positioned in the chip installation hole 2 and is mounted in a stable state, substantially within the thickness of the substrate 1.
以上説明した本発明の実装方法のみによっても電子回
路装置を製作することも可能であるが、一般には従来か
らの各種の実装方法と組合せて使用することになる。第
６図はその一例を示している。Although it is possible to manufacture an electronic circuit device only by the mounting method of the present invention described above, it is generally used in combination with various conventional mounting methods. FIG. 6 shows an example thereof.
第６図において、61と62は最終的に２枚重されたプリン
ト配線基板である。一方のプリント配線基板61には本発
明の実装方法によってチップ部品63が厚み内に埋め込ま
れるように実装されているとともに、その上面側にチッ
プ部品65が従来の表面実装方法によって実装されてい
る。同じく他方のプリント配線基板62には本発明の実装
方法によってチップ部品64が基板の厚み内に埋め込まれ
た状態で実装されているとともに、基板62の下面側に表
面実装方法によってチップ部品66が取付けられている。
さらに基板61と62を２枚重ねした後に部品67のリード線
が基板61、62の穴を貫通してはんだ付けされている。こ
のように本発明の実装方法を適宜に用いることで従来よ
りさらに高密度な実装が可能となり、特に基板の厚み方
向の寸法を小さくすることができる。In FIG. 6, reference numerals 61 and 62 are finally the printed wiring boards which are overlaid on each other. On one printed wiring board 61, the chip component 63 is mounted by the mounting method of the present invention so as to be embedded in the thickness, and the chip component 65 is mounted on the upper surface side by the conventional surface mounting method. Similarly, on the other printed wiring board 62, the chip component 64 is mounted by the mounting method of the present invention in a state of being embedded in the thickness of the substrate, and the chip component 66 is mounted on the lower surface side of the substrate 62 by the surface mounting method. Has been.
Furthermore, after the two boards 61 and 62 are superposed, the lead wires of the component 67 penetrate through the holes of the boards 61 and 62 and are soldered. As described above, by appropriately using the mounting method of the present invention, it is possible to achieve higher density mounting than ever, and in particular, it is possible to reduce the dimension of the substrate in the thickness direction.
《発明の効果》 以上詳細に説明したように、この発明によるチップ部
品の実装方法では、プリント配線基板に形成されたチッ
プ設置穴内にチップ部品が嵌め込まれ、はんだ付けの
際、これがはんだの表面張力によって位置決めされて安
定した状態で基板の厚み内にほぼ収まって埋設された状
態で実装されるので、従来の表面実装方法に比べて実装
後の基板厚み方向の寸法が極めて小さくなるとともに、
基板の穴にチップ部品を嵌め込むことで部品が位置決め
されるので、組立工程も簡単になる。この発明の実装方
法と他の実装方法とを適宜に組合せて電子回路装置を構
成すれば、全体としての実装密度を従来より大きくする
ことができるとともに、特に厚み方向の寸法を小さくす
ることができ、電子回路装置の小型化に大いに寄与す
る。<< Effects of the Invention >> As described in detail above, in the chip component mounting method according to the present invention, the chip component is fitted into the chip installation hole formed in the printed wiring board, and when soldering, this is the surface tension of the solder. Since it is mounted in a state that it is positioned and stable and is almost contained within the thickness of the board and embedded, the dimension in the board thickness direction after mounting is extremely smaller than that of the conventional surface mounting method.
Since the parts are positioned by fitting the chip parts into the holes of the board, the assembly process is also simplified. If the electronic circuit device is configured by appropriately combining the mounting method of the present invention with another mounting method, the mounting density as a whole can be made higher than before, and particularly the dimension in the thickness direction can be made smaller. Greatly contributes to miniaturization of electronic circuit devices.
第１図〜第５図は本発明の一実施例による実装方法の工
程図、第６図は本発明の実装方法と従来からの実装方法
とを組合せて電子回路装置を構成したものの概略図であ
る。 １……プリント配線基板 ２……チップ設置穴 ３、４……配線用導電膜 ５……チップ部品 ６、７……端子導電膜 ８、９……はんだ1 to 5 are process diagrams of a mounting method according to an embodiment of the present invention, and FIG. 6 is a schematic view of an electronic circuit device configured by combining the mounting method of the present invention and a conventional mounting method. is there. 1 ... Printed wiring board 2 ... Chip mounting hole 3, 4 ... Wiring conductive film 5 ... Chip component 6, 7 ... Terminal conductive film 8, 9 ... Solder
───────────────────────────────────────────────────── フロントページの続き (72)発明者 浜田 修一 東京都港区新橋５丁目36番11号 富士電 気化学株式会社内 (56)参考文献 特開 昭57−66693（ＪＰ，Ａ) 実開 昭60−176577（ＪＰ，Ｕ) ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shuichi Hamada 5-36-1 Shimbashi, Minato-ku, Tokyo Inside Fuji Electric Kagaku Co., Ltd. (56) Reference JP-A-57-66693 (JP, A) 60-176577 (JP, U)
Claims (1)
電膜が被覆形成されているチップ部品をプリント配線基
板に実装する方法であって、まず、該プリント配線基板
の所定位置に該チップ部品の該端子導電膜それぞれに対
応した２つの仮穴を形成し、該仮穴それぞれの内面に配
線用導電膜を形成してから、該両仮穴の間の部分を切除
することでチップ設置穴を形成し、次いで該チップ部品
を該チップ設置穴に該基板と平行な姿勢でほぼ埋設状態
で嵌合して該端子導電膜と該配線用導電膜とをはんだ付
けすることを特徴とするチップ部品の実装方法。1. A method of mounting a chip component, in which a terminal conductive film is formed on both ends of a substantially rectangular parallelepiped element chip, on a printed wiring board. First, the chip component is placed at a predetermined position on the printed wiring board. Two temporary holes corresponding to each of the terminal conductive films are formed, the conductive film for wiring is formed on the inner surface of each of the temporary holes, and the portion between the temporary holes is cut off to form the chip mounting hole. And then the chip component is fitted in the chip installation hole in a state parallel to the substrate in a substantially embedded state to solder the terminal conductive film and the wiring conductive film to each other. How to mount parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2237082A JP2512828B2 (en) | 1990-09-10 | 1990-09-10 | Chip component mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2237082A JP2512828B2 (en) | 1990-09-10 | 1990-09-10 | Chip component mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04118987A JPH04118987A (en) | 1992-04-20 |
| JP2512828B2 true JP2512828B2 (en) | 1996-07-03 |
Family
ID=17010148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2237082A Expired - Fee Related JP2512828B2 (en) | 1990-09-10 | 1990-09-10 | Chip component mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2512828B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10127334A1 (en) * | 2001-06-06 | 2002-12-12 | Patent Treuhand Ges Fuer Elektrische Gluehlampen Mbh | circuit board |
| JP4598572B2 (en) * | 2005-03-16 | 2010-12-15 | ローム株式会社 | Mounting structure of optical communication module and portable electronic device using the same |
| JP2015088962A (en) * | 2013-10-31 | 2015-05-07 | 京セラクリスタルデバイス株式会社 | Crystal device |
| JP6282843B2 (en) * | 2013-10-31 | 2018-02-21 | 京セラ株式会社 | Crystal device |
| JP6418810B2 (en) * | 2014-06-26 | 2018-11-07 | 京セラ株式会社 | Crystal device |
| CN108617090A (en) * | 2018-05-14 | 2018-10-02 | 维沃移动通信有限公司 | Mobile terminal and its circuit board |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5766693A (en) * | 1980-10-09 | 1982-04-22 | Tdk Electronics Co Ltd | Method of producing electronic circuit device |
| JPS60176577U (en) * | 1984-04-28 | 1985-11-22 | 日本電気ホームエレクトロニクス株式会社 | Printed board |
-
1990
- 1990-09-10 JP JP2237082A patent/JP2512828B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04118987A (en) | 1992-04-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |