JP2512761B2 - Information playback device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an information reproducing apparatus in an R-DAT, an 8 mm video tape recorder or the like.

[Technical background of the invention and its problems]

The above R-DAT uses a helical scan type rotary head to scan diagonal tracks with respect to the tape and to perform PCM.
The recording / playback of audio signals and the like is performed.

Each track is roughly divided into three areas. In the central PCM area, in addition to the PCM audio signal, the sampling frequency and PCM-ID that indicates whether copying is possible, etc. are recorded, and two subcode areas on both sides of it are recorded. A subcode ID and subcode data are recorded in (SUB1, SUB2).

As the subcode ID, a control ID including the start ID indicating the beginning of the program, a PNO-ID (program number) for identifying the program, and the like, as well as a data ID indicating the type of data and subcode data It is possible to record the number of pack data (PACK) consisting of 8 symbols (64 bits) to be recorded, such as the format ID.

FIG. 8 is a diagram showing a block format of the subcode area. A block with an even address (hereinafter referred to as an even block) has four other pack data (PACK1, PACK3, PACK5, PACK
7), the odd address block (hereinafter referred to as the odd block) is used for the other three pack data (PACK2, PACK4, PACK6) such as PNO-1 to PNO-3 and the 8-byte C1 correction parity. It is set. Information (ITEM) indicating the contents of each pack data is recorded in the upper 4 bits of the first 1 byte of each pack data (PACK1 to PACK7).

Then, the program time is
Absolute time, calendar or TOC (Table of contents)
Information and the like can be recorded, and the reproduced pack data is recorded in the memory for each track, accessed by a control system such as a microcomputer, and sequentially processed.

Packed data has many items as described above, and some of them need to be read relatively frequently due to their nature, and some do not.

However, it is difficult to read this efficiently, which makes it difficult to read accurately, especially when the magnetic tape is run at high speed.

[Object of the Invention]

The present invention, particularly in the R-DAT, selectively outputs items of pack data (ITEM), pack data, and the like, so that a control system such as a microcomputer can efficiently read desired pack data and can perform high-speed running. The purpose is to obtain accurate pack data.

[Outline of Invention]

In the information reproducing apparatus of the present invention, the control means outputs the control signal and the information signal designating the data to the data processing means, inputs the data output from the data processing means and outputs the data to the control system or the like. In the first setting mode, the data processing means inputs from the control means an information signal designating predetermined data to be output to the control system or the like only when the control signal input from the control means is in a specific state. In the second setting mode, the data designated based on the information signal input in the first setting mode is read from the data storage means and output to the control means. As a result, particularly in the R-DAT, items of pack data (ITEM), pack data, and the like are selectively output so that the control system such as a microcomputer can efficiently read the pack data of the mesh.

〔Example〕

FIG. 3 is a block diagram of an embodiment of the present invention.
The reproduction system of T is shown.

The reproduction signal read from the magnetic tape by the rotary drum 4 equipped with a reproduction head is input to the data strobe 5 to extract the clock and data, and the extracted 10-bit data is converted into 8-bit data by the demodulation unit 6. It is demodulated and stored in the memory 3.

The data stored in the memory 3 is subjected to error correction processing by the error correction unit 8, and a correction flag indicating the result of the error correction processing is added and stored in the memory 3 again. The A converter 7 converts the analog signal.

Further, of the data stored in the memory 3, the ITEM and the pack data of the subcode data are transferred to the control unit 2 such as a microcomputer via the subcode processing unit 1 as will be described later in detail, and this control unit Various processes are performed according to 2.

FIG. 4 is a diagram showing the storage state of the subcode data which has been subjected to the C1 correction processing in the memory 3, and as shown in FIG. 4A, 56 pack data for one track has block addresses ( "0" to "15") and the symbol addresses ("0" to "31") in each block are stored in the respective positions.

In the odd number block, the 4-bit data ID and the 3-bit data ID as shown in FIG.
A bit format ID and a 1-bit flag P indicating validity / invalidity of these IDs are recorded. Similarly, in the odd number block, the correction flag 2 bits as shown in FIG. Is recorded.

For this correction flag, the bad one of the C1 correction result of the even symbol and the C1 correction result of the odd symbol is selected, and 2 bits of this correction flag are [00] ₂ (“[...] ₂ ” is the number in parentheses. It indicates that it is a binary number expression.) "No correction",
[01] ₂ "with correction of 1 symbol", [10] ₂ "2
"Correct symbol" and "11" ₂ "Uncorrectable"
The respective correction processing results are shown.

The data ID is set to [0000] ₂ when the recorded data has audio specifications. For example, when the R-DAT is used as a data recorder for recording data other than audio signals in the future, other Is set to the value of.

FIG. 2 is a diagram for explaining the data transfer performed by the subcode processing unit 1 and the control unit 2. The control unit 2 outputs the frame synchronization signal (FSYNC) output from the subcode processing unit 1.
Control signal (CT
RL), serial data (CDAT) that specifies mode settings, etc.
AI) and a clock signal (CCK) are output, and serial data (CDATAO) such as ITEM or pack data is received from the subcode processing unit 1.

In this embodiment, the subcode processing section 1 corresponds to the data processing means of the present invention, and the control section 2 corresponds to the control means of the present invention.

For example, as shown in FIG. 5, while CTRL is set to "H" level, the data selection signal (ITEM mode data) D ₁ for setting the subcode processing unit 1 to the ITEM read mode is output, and CTRL is set to "L". "The ITEM which is set to the level and read from the memory 3 by the subcode processing unit 1 is sequentially received.

When desired pack data is found by the received ITEM, CTRL is set to “H” level to output the data selection signal (PCTL mode data) D ₂ for setting the pack specification mode, and CTRL is set to “L” level. Pack control data (PCT
L) is output.

Further, the CTRL is set to the “H” level, the data (PACK mode data) D ₃ for setting the packed data read mode is output, and the CTRL is set to the “L” level to be read from the memory 3 by the subcode processing unit 1. Receives pack data.

That is, the data of CDATAI output from the control unit 2 is a data selection signal for mode setting when CTRL is “H” level, and the data transmitted / received by CDATAI and CDATAO when CTRL is “L” level. Is ITEM, PCTL or packed data.

As shown in FIG. 6, the access address of the memory 3 generated by the subcode processing unit 1 when the CTRL is set to the “H” level and then to the “L” level is set every two blocks as described later. Is updated in the step of, and is sequentially read for every 7 ITEMs (ITEM table) included in 2 blocks.

In this embodiment, the control signal (CTRL) corresponds to the control signal in the present invention, and its "H" level corresponds to the specific state. Also, ITEM mode data D ₁ , PCTL
The mode data D ₂ and the PACK mode data D ₃ correspond to the information signal in the present invention, and the pack control data (PC
TL) corresponds to the control data according to claim 2.

FIG. 1 is a block diagram of the subcode processing unit 1.
Is a decoder for decoding data selection signals such as ITEM mode data, designated mode data or PACK mode data input from the control unit 2, 12 is a data latch pulse, a register reset pulse or a pulse for address generation The timing generation unit 13 is an address generation unit that generates an access address of the memory 3.

14 ₁ is a latch unit for holding the data read from the memory 3, 14 ₂ is a latch unit for holding the data stored in the memory 3, and the subcode data is the latch unit 14 ₂
Is stored in the memory 3 via the.

15 correction flag detecting section for detecting a correction flag from the output data of the latch portion 14 _1, 16 data ID detection unit for detecting the same data ID, 17 is ITEM detector for detecting the ITEM,
18 the latch portion 14 _1, correction flag detecting section 15, data ID detection section 1
6 is a data switching unit for switching and outputting the data output from the ITEM detection unit 17, and the data switching unit 18
Outputs the output data of the correction flag detector 15, the data ID detector 16 or the ITEM detector 17 when the ITEM read mode is set, and the latch unit 14 ₁ when the pack data read mode is set. The pack data latched in is output.

Reference numeral 19 ₁ denotes a shift register which latches the data output from the data switching unit 18 and outputs it as serial data to the control unit 2. 19 ₂ denotes the PCTL output from the control unit 2 for designating pack data to be read. It is a shift register for holding data.

The shift register 19 ₁ is also used to output the subcode data stored in the memory 3 to the latch 14 ₂ as parallel data.

The subcode processing unit 1 operates in each mode as follows.

(ITEM reading mode) The ITEM mode data output from the control unit 2 is a decoder.
When decoded by 11, the address generator 13 sets the symbol address of the memory 3 to “30” and the block address “9” by the pulse output from the timing generator 12 (fourth
Figure), is latched by the latch portion 14 ₁ reads one byte. This 1-byte data is input to the data ID detection unit 16, and the data ID detection unit 16 outputs a 2-bit data ID flag according to the value of the data ID in the 1-byte data and the flag P. The data ID flag is set to [00] ₂ when the data ID is [0000] ₂ and the result of the parity check is valid, and is set to [11] ₂ otherwise.

Next, the read one byte in the "31" symbol address in the same block, for detecting the correct flag by the latch to correct flag detecting section 15 to the latch 14 _1.

The above data ID flag and correction flag are the timing generator
12 is input, and the timing generation unit 12 checks that the data ID flag is [00] ₂ and the correction flag is not [11] ₂ , and when this condition is satisfied, the address generation unit 12 causes the block address “8”. Then, the symbol address “0” is generated, and the first 1 byte of PACK1 is the latch unit 14 ₁
Latched on.

From this 1-byte data, the ITE of PACK1 is detected by the ITEM detector 17.
The M4 bit is detected, and a total of 8 bits of this ITEM and the above data ID flag and correction flag are latched in the shift register 19 ₁ via the data switching unit 18, and this shift register 1
It is read by the control unit 2 from 9 ₁ .

When the ITEM is read from the shift register 19 ₁ , the block address “9”, the symbol address “0”, the block address “8”, and the symbol address “8” are sequentially generated, and the PAC
The first 1 byte of K2 and PACK3 are read out, and the ITEM detection section 17 reads 4 ITEMs for PACK2 and PACK3 in the same manner as above.
A total of 8 bits of data are latched in the shift register 19 ₁ .

In addition, as a result of the determination of the timing generation unit 12, the data ID
If the conditions of flags and correction flags are not satisfied,
The address generator 13 changes the block address from “9” to “11” →
Update in the order of “13” → “15” → “1” → “3” → “5” → “7”,
The same processing as described above is sequentially performed for each two blocks.
In addition, even if the above block address is cycled, the data ID
If the conditions for flags and correction flags are not met,
Each address is updated from the block address “8” and the symbol address “0”, the ITEM is sequentially read from the memory 3, and latched in the shift register 19 ₁ .

(Pack designation mode) The desired pack data is read from the ITEM read by the control unit 2.
When ITEM is detected, the bit corresponding to the PACK designated as shown in FIG. 7 is set to "1" in order to designate a desired one from the two blocks of pack data PACK1 to PACK7 in which the ITEM is recorded. The 7-bit PCTL set to "is output to the shift register 19 ₂ .

(Pack data read mode) When the PACK mode data is input to the decoder 11 from the control unit 2, the pack data read mode is set, and subsequently the 7-bit PCTL input to the shift register 19 ₂ from the control unit 2 is read. Generates a symbol address in which the first 1 byte of the PACK specified corresponding to the PCTL bit is stored, reads the 1st byte of the PACK, and latches 14 ₁
Latch to.

One byte of PACK latched in the latch unit 14 ₁ is latched in the shift register 19 ₁ via the data switching unit 18, and serially output by CCK output from the control unit 2.

When the pack data of the first 1 byte is output, the address generator 13 increments the symbol address by 1 and the next 1 byte is read from the memory 3.

As described above, when one byte is sequentially output and one pack of data (8 bytes) is transferred, the timing generation unit 12 checks the PCTL bit and the same as above if the desired PACK is designated. And output pack data.

As a result of checking the data ID flag and the correction flag performed by the timing generation unit 12 of the subcode processing unit 1,
The ITEM sequentially read from the block with the block address “8” after going through 16 blocks outputs CCK (clock signal) and is sequentially input.

〔The invention's effect〕

As described above, according to the present invention, in the information reproducing apparatus for outputting a plurality of types of data reproduced from the recording medium, the control means outputs the control signal and the information signal designating the data to the data processing means, The data output from the data processing means is input and output to the control system or the like. In the first setting mode, the data processing means inputs the information signal designating the predetermined data to be output to the control system or the like from the control means only when the control signal input from the control means is in a specific state. In the second setting mode, the data designated based on the information signal input in the first setting mode is read from the data storage means and output to the control means. Specified data can be selectively output from the stored plural kinds of data, and in particular, desired pack data can be efficiently read by a control system such as a microcomputer in the R-DAT, and a desired program can be searched for. It is possible to obtain accurate pack data even when traveling at high speed, such as when performing.

[Brief description of drawings]

FIG. 1 is a block diagram of a subcode processing unit in an embodiment of the present invention, FIG. 2 is a diagram showing a connection state between a subcode processing unit and a control unit of the embodiment, and FIG. 3 is a diagram of an embodiment of the present invention. FIG. 4 is a block diagram, FIG. 4 is a diagram showing a storage state of subcode data in a memory of the embodiment, FIG. 5 is a timing chart between a subcode processing unit and a control unit of the embodiment, and FIG. 6 is a CTRL of the embodiment. Due to changes in signal level
FIG. 7 is a timing chart showing the transfer of ITEM, FIG. 7 is a diagram showing a setting example of PCTL, and FIG. 8 is a diagram showing a block format of a subcode area in R-DAT. 1 ... Subcode processing unit, 2 ... Control unit, 3 ... Memory, 11 ... Decoder, 12 ... Timing generation unit, 13 ...
Address generation section, 14 ₁ , 14 ₂ ...... Latch section, 15 ...... Correction flag detection section, 16 ...... Data ID detection section, 17 ...... ITEM detection section, 18 ...... Data switching section, 19 ₁ , 19 ₂ ... … Shift register.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Hatanaka 292 Yoshida-cho, Totsuka-ku, Yokohama City, Kanagawa Prefecture Home Appliances Research Laboratory, Hitachi, Ltd. (56) References JP 62-232768 (JP, A)

Claims (2)

(57) [Claims] 1. A data storage means for storing a plurality of types of data reproduced from a recording medium, a control means for outputting a control signal and an information signal for designating the data and inputting the data, and an output from the control means. And a data processing unit that inputs the control signal and the information signal, reads the data from the data storage unit, and outputs the data to the control unit, the data processing unit including the control unit input from the control unit. A first setting mode in which the information signal is input from the control means only when the signal is in a specific state, and data designated by the information signal input in the first setting mode is read from the data storage means. An information reproducing apparatus having a second setting mode for outputting to the control means. 2. The control means outputs control data for designating unique data in the data when the control signal is not in a specific state, and the data processing means uses the control signal to output the control data. The information reproducing apparatus according to claim 1, having a third setting mode for inputting control data.