JP2511551B2 - Common bus control method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a common bus control system in an electronic switching system.

[Prior Art] Conventionally, an electronic exchange system includes a plurality of devices having device numbers 1, 2, and 3 as shown in FIG. Multiple devices are connected to a common bus 210,21 via transceivers 200,201,202,203,204.
Connected by 1,212,213,214,215. The data transmission / reception interface unit 13, 23, 33 of each device establishes frame synchronization of the time division slot of the common bus by the frame head signal generated by the synchronization frame head signal generation unit 90 of the first device, and The data on the common bus is latched by the signal transmitted from the basic clock source 91 of the first device, and the data is transmitted again on the common bus. In the figure, 80, 81, 84, 85 are drivers and 82, 83, 86, 87 are receivers.

[Problems to be Solved by the Invention] In the above-described conventional electronic exchange system, each device is a synchronous frame head signal generation unit 90 of the device of device number 1.
The data on the common bus is transmitted and received based on the two signals output from the system basic clock source 91 and the system basic clock source 91.
Therefore, as shown in FIG. 7, the above-mentioned timing difference between the two signals may occur between the devices due to the delays of the drivers 80 and 81 transmitting the clock, the receivers 82 and 83, and the cable delay between the devices. As a result, when the data A sent from the data transmission / reception interface unit 33 onto the common bus 211 is received normally by the data transmission / reception interface unit 23 of the device number 2, the data transmission / reception interface unit of the device number 1 is received. When receiving with 13, it may not be able to receive normally.

That is, conventionally, data on the common bus is transmitted and received on the basis of the basic clock transmitted from the system basic clock source 91 and the frame head signal transmitted from the synchronous frame head signal generation unit 90. Therefore, as the number of devices increases, the transmission delay of each device affects the transmission delay from the basic device, which makes it impossible to receive data normally. As a result, in the case of a large device number, there is a small margin between the data on the common bus and the data punching signal that latches this data, and there is a problem that data cannot be normally received unless the number of devices is limited. there were.

[Means for Solving the Problem] In order to solve such a problem, in the common bus control system according to the present invention, the common bus is composed of a transmission bus and a reception bus, and the transmission bus and the reception bus are the first. No. 1 device, and sequentially sends the frame head signal for synchronization of the time division slot of the common bus from the 1st device to the nth device through the delay means, and the respective transmission bus and reception bus of the above device Are connected to phase correction means for performing phase correction between the data on these buses and the data punching signal for latching this data, and the delay means provided in each of the devices are respectively connected based on the synchronization frame head signal. This is a method in which transmission delay information of a unique delay difference is set and the output of each delay means of the above apparatus is used as a data punching signal.

Further, each of the above devices is provided with a timing signal generating means for generating a timing signal for adjusting the timing for transmitting / receiving the data on the common bus from the output of the delay means.

In addition, the first and second basic signals having a fixed delay difference generated by the delay unit of the first device are transmitted to the delay units of the second to nth devices in the order of serial number, Each delay means gives a fixed delay difference to the received basic signals, outputs them to the next device, and sends them to the timing signal generating means of its own device.

[Operation] Transmission delay information of a delay difference unique to each device is set by the delay means provided in each device, and the data on the common bus is latched based on the output of the delay means.

Further, the timing for transmitting / receiving data on the common bus is adjusted based on the output of the delay means.

Further, the received first and second basic signals are given a fixed delay difference and are output to the next device, and are also sent to the timing signal generating means of the own device.

EXAMPLES Next, the present invention will be described with reference to the drawings.

An embodiment will be described with reference to FIGS. 1, 2, 3, and 4. This embodiment shows the case of three devices with device numbers 1, 2, and 3, and outputs the clock and frame head signals generated by the system basic clock source 91 and the synchronization frame head signal generation unit 90 to the driver 80, 81
And a delay setting circuit (a circuit that corrects one clock of the system basic clock) 1, 2, and 3 to each device.

Then, each device has a clock sent from the system basic clock source 91 and a synchronization frame head signal generation unit 90.
It receives the frame head signals sent from the device and operates based on these signals. Common buses 41-46, 48-52
It consists of transmission buses 46-41 and reception buses 48-52, respectively.
Phase correction circuit (circuit that corrects one clock of the system basic clock) on these transmission and reception buses 1
5,25,27,35,37 and 14,24,26,34,36 are provided. The common bus is time-divisionally controlled to 1024 with the received basic clock based on the frame head signal received by each device.

Also, the delay setting circuits 1, 2, 3 are two signals 100, 101, 102, 103, 104 in which the timing signal generating circuits 12, 22, 32 of the respective devices are provided with fixed delays for the frame head signals.
And 105 (the device number 1 has no delay difference between the two signals, and the signal having the delay difference increased by one each time the device number increases by one). The timing signal generation circuits 12, 22, 32 receive the above two signals and generate timing signals 61, 63, 65 and 60, 62, 64 for transmitting / receiving data to / from the transmission bus and the reception bus for each device to transmit / receive data. It is sent to the interface units 13, 23, 33. Based on this timing signal, the data transmission / reception interface units 13, 23, 33 send data to the transmission buses 46, 44, 42, and the reception interface units 23, 33 receive the reception buses 49, 51.
Receive data from.

Data is received from the reception buses 49, 51 based on the frame head signals 100, 102, 104 created by the synchronization frame head signal creation unit 90. When the device number increases, the delay setting circuit causes The phase is corrected so as to sequentially increase by the amount of the clock, and the phase shift of the frame head signal occurs between the devices.

However, since the receiving bus is connected from the device number 1 to the device number 3 through the phase correction circuits 14, 24, 26, 34, 36, it has the same direction as the frame head signal and the same number of phase corrections. Therefore, when the data on the reception bus is received at the timing of the frame head signal, the same data can be received regardless of the device number (see the relationship between the reception timing and the time division slot in FIG. 4).

However, on the transmission side, since the directions of the transmission bus and the frame head signal are opposite, the transmission timing must be transmitted earlier by the data slot fixed before the reception timing for each device (the fourth timing). See the relationship between the transmission timing and the reception timing in the figure). The difference between the transmission timing and the reception timing is
[Phase correction circuits 14, 15, 24 to 27, 34 to 3 on the common bus
7] x [system basic clock]. This transmission timing is created by the timing signal creation circuit 12, 22, 32 for each device. Note that FIG. 4 shows the operation of the circuit when the common bus is multiplexed by 1024 divisions.

Next, taking the device number 3 (FIG. 2) as an example,
This will be described in detail with reference to the time chart in the figure.

The latch circuit 37, which is a phase correction circuit, receives the data sent from the data transmission / reception interface unit 33 from the receiver 83.
System basic clock received from device number 2 in
Latch with CLK3 (phase correction for 1 clock), device number 2
To the device. Latch circuit 36 that is a phase correction circuit
Latches the data input from the device having the device number 2 through the reception bus 50 with the system basic clock CLK3 and sends the data to the reception bus 51.

The signal 105 output from the delay setting circuit 3 is 4
It is input to the bit counter 150 as a load input, thereby loading "0" provided to the data input terminals of 0, 1, 2, 3 of the counter 150. The 4-bit counter 150 counts up from the above load input “0” by a signal obtained by inverting the system basic clock CLK3 by the inverter 151, and outputs the counter output 110 output from the output terminals of 0, 1, 2, 3 The 4th bit from the 3rd bit to the 6th bit from the lower side of the load data terminal of the 10-bit counter 160 is input. In addition, "0" is input to the remaining 1 and 2 bits of the counter 160 and 6 bits in total of 7 bits to 10 bits.

The signal 104 output from the delay setting circuit 3 is delayed by a half clock of the system basic clock CLK3 by a half clock delay circuit (half CLK delay circuit) 170, and the delay signal 130 is loaded into the 10-bit counter 160. Input to the input terminal. That is, the signal output from the delay setting circuit 3
Since the 4-bit counter 150 counts up by the delay difference between 104 and the signal 105, the value (signal 110) loaded in the 10-bit counter 160 changes, and that value is loaded by the 10-bit counter 160 (device number 3). Load value is 8 →
Signal 120).

Although this delay difference varies depending on the device number, 4
The counting procedure of the bit counter 150 and the 10-bit counter 160 is determined, and the transmission / reception timing unique to each device is obtained. Then, the carry signal 140 of the 10-bit counter 160 is delayed by one clock of the system basic clock CLK3 by a delay circuit (1 CLK delay circuit) 190, and the delay signal 65 is transferred to the data transmission / reception interface unit 33.
To enter. Here, in the timing signal generation circuit 32, the carry signal 140 of the 10-bit counter 160 is
Used to obtain the transmit timing signal, counter 16
The count output 120 of 0 is never used. The count value of the counter 160 at this time is 2 ¹⁰ = 1024. The delay signal 65 described above serves as a timing signal for sending data to the transmission bus via the line 33a.

Also, the signal 104 output from the delay setting circuit 3 is delayed by one clock of the system basic clock CLK3 by the one-clock delay circuit (1 CLK delay circuit) 180, and the delay signal 64
Is input to the data transmission / reception interface unit 33. This delay signal 64 becomes a timing signal for receiving data from the reception bus. Incidentally, in the device of the device number 3 whose detailed configuration is shown in FIG. 2, the phase correction circuits 34, 35, 36, 37 of the same device in FIG. 1 are constituted by latch circuits.

FIG. 5 is a diagram showing a specific example of the delay setting circuits 1, 2, and 3 shown in FIG. 1 and its peripheral circuits. The delay setting circuit 1 used in the device of device number 1 receives the synchronizing frame head signal (see FIG. 3) output from the synchronizing frame head signal generating section 90 by one clock delay circuit 109.
And another one-clock delay circuit 110, 112a.

The frame head signal delayed by one clock by the one-clock delay circuit 109 is the signal 100 and the signal 101.
Is sent to the timing signal generation circuit 12. The frame head signal at this time is a pulse signal having a width of one clock cycle as shown in FIG.

Further, the signal 100 and the signal 101 have the same pulse waveform as shown in FIG. 3, in other words, these two signals are signals having the delay difference “0”. Then, the signal 100 is also sent to the data transmission / reception interface unit 13.

Also, the delay setting circuit 2 used for the device of device number 2
Is a delay circuit 11 for one clock which constitutes the delay setting circuit 1.
A 1-clock delay circuit 111 that receives an output of 0, a 1-clock delay circuit 112b that similarly receives the output of a 1-clock delay circuit 112a that constitutes the delay setting circuit 1, and a 1-clock delay that receives the output of this 1-clock delay circuit 112b Clock delay circuit
With 113a.

Then, the output of the delay circuit 110 for one clock and the output of the delay circuit 112b for one clock are sent to the timing signal generating circuit 22 of the device of the device number 2 as signals 103 and 102.
The signal 103 used here is a signal delayed by one clock from the signals 100 and 101, and the signal 102 is delayed by two clocks by the delay circuit 112 composed of delay circuits 112a and 112b. It becomes a signal. Therefore, the signal 102 becomes a signal delayed by one clock from the signal 103. This is best shown in FIG. The signal 102 is also sent to the data transmission / reception interface unit 23.

Also, the delay setting circuit 3 used for the device of device number 3
Has the same configuration as the delay setting circuit 2 described above. That is, the delay setting circuit 3 receives the output of the 1-clock delay circuit 115 that constitutes the delay setting circuit 2 and the 1-clock delay circuit 113 that constitutes the delay setting circuit 2 1 Clock delay circuit 113b
And 1 for receiving the output of the delay circuit 113b for one clock
It has a clock delay circuit 116a.

Then, the output of the 1-clock delay circuit 111 and the output of the 1-clock delay circuit 113b are sent to the timing signal generation circuit 32 as signals 105 and 104. Here, as shown in FIG. 3, the signal 104 is delayed by two clocks with respect to the signal 105. That is, these two signals are in the state of delay difference "2".

The 1-clock delay circuits 113a and 113b are combined to form a 2-clock delay circuit 113 as a whole. The signal 104 is also sent to the data transmission / reception interface unit 33. In this way, the delay circuits used in the devices of the device numbers 2 and 3 have the same configuration even in the devices having the further increased device numbers.

As described above, in each device, the above-mentioned two signals (two signals having a fixed delay difference for each device) are input to the timing signal generating circuits 12, 22, 32 shown in FIG. Two signals can be automatically set to create the timing of sending data to the transmission bus of each device and the timing of receiving data from the reception bus.

In this example, the fixed delay difference between the two signals created by each device is set to one clock, but the fixed delay difference is not limited to one clock.

[Effects of the Invention] As is apparent from the above description, according to the common bus control method of the present invention, data transfer between devices can be achieved by considering only the delay difference of one device even if the number of devices increases. Well, because the number of devices is not limited and the margin between the data on the common bus and the punching signal of the data is large, it is possible to increase the distance between the devices and increase the data transmission speed on the common bus. Also has the effect of being possible.

Further, since the timing signal generating means is provided for each device, there is an effect that accurate data transmission can be performed on the common bus.

Further, since a fixed delay difference is given to the received first and second basic signals and output to the next device and also to the timing signal creating means of the own device, this delay difference is calculated. By using this, it is possible to automatically create the timing of transmission / reception with respect to the common bus, and it is possible to prevent the setting error for this timing creation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a device to which a common bus control system according to the present invention is applied, FIG. 2 is a detailed block diagram of the device shown in FIG. 1, and FIG. 3 is a common bus in the same embodiment. FIG. 4 is a diagram for explaining generation of a timing signal transmitted / received to / from the device, FIG. 4 is a diagram showing a relationship between a time division slot for each device and a transmission / reception timing signal in the embodiment, and FIG. 5 is a delay setting circuit used in FIG. FIG. 6 is a diagram showing a concrete example of the above and its peripheral circuits, and FIGS. 6 and 7 are diagrams for explaining a conventional system configuration. 1,2,3 …… Delay setting circuit. 10 …… Basic signal generation circuit, 12,
22,32 …… Timing signal generation circuit, 13,23,33 …… Data transmission / reception interface section, 14 to 16,24 to 28,34 to 39…
… Phase correction circuit (latch circuit), 20,30 …… Delay circuit, 4
1 to 46 …… Transmission bus, 48 to 52 …… Reception bus, 80,81,88…
... driver, 82, 83 ... receiver, 90 ... synchronization frame head signal generator, 91 ... system basic clock source,
110,111,180,190 …… 1 clock delay circuit, 170 …… Half clock delay circuit, 112,113 …… 2 clock delay circuit, 150 …… 4 bit counter, 160 …… 10 bit counter.

Claims (3)

(57) [Claims] 1. An electronic switching system comprising n devices, numbered 1 to n, wherein the devices are connected in order of device number by a common bus that is time-division controlled, wherein the common bus is a transmission bus. A reception bus, wherein the transmission bus and the reception bus are connected in the first device, and the time division slots of the common bus are sequentially synchronized from the first device to the nth device. Phase correction means for sending the frame head signal through the delay means, and performing phase correction on the transmission bus and the reception bus of each of the devices for phase correction of the data on these buses and the data punching signal that latches this data, respectively. Connected, the delay means provided in each of the respective devices sets transmission delay information of the respective delay difference based on the synchronization frame head signal, A common bus control method, wherein the output of each of the delay means is used as the data punching signal. 2. A common bus control system according to claim 1, wherein said device is provided with a timing signal creating means for creating a timing signal for adjusting a timing for transmitting / receiving data on said common bus from said delay means output. A common bus control method characterized by being provided in each of the. 3. The common bus control system according to claim 2, wherein the first and second basic signals having a fixed delay difference generated by the delay means of the first device are applied to the second device. No. to n-th device are sequentially transmitted to the delay devices, and each delay device gives a fixed delay difference to these received basic signals and outputs them to the next device and the timing of its own device. A common bus control method characterized in that it is sent to a signal creating means.