JP2508255B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a NAND type EPROM designed to prevent erroneous writing.

[Conventional technology]

Before describing the conventional technology, a NAND EPROM will be described first. NAND type EPROM is a highly integrated EPROM.
Figure (a) shows a conventional NAND-type EPROM having a structure in which a plurality of memory transistors are connected in series to one bit line.
FIG. 3 (b) is a pattern diagram corresponding to FIG. 3 (a). In this example, four stages of memory transistors (T1) to (T4) are connected in series, and (W1) to (W4)
Is a word line connected to the control gate of each of the memory transistors (T1) to (T4). FIG. 4 (a) is a circuit diagram of a conventional EPROM which is not a NAND type, and FIG. 4 (b) is a pattern diagram corresponding to FIG. 4 (a). Only one memory transistor (T1) is connected in series to the bit line (B1), and the number of word lines (W1) is also one. Next, the operation will be described.

The NAND type EPROM shown in FIG. 3 has a feature that it is advantageous for high integration because the number of contact holes (C1) for connecting the bit line (B1) is smaller than that of the non-NAND type EPROM shown in FIG. However, on the other hand, a special combination of high voltage is required for writing. FIG. 5 is a graph showing memory transistor write characteristics showing the relationship between the control gate voltage Vc _G and the threshold voltage V _TH after writing when the drain voltage of the memory transistor is 9V. Consider a case where the memory transistor (T2) shown in FIG. 3 is selectively written by utilizing this memory transistor characteristic. Selected bit line (B1)
A high voltage of 9V is applied to the selected word line (W
It is necessary to apply a high voltage of 10 V to 2) and a high voltage of 20 V to the unselected word lines (W1), (W3) and (W4).

Now, select (10V) / unselect (20V) this word line
The high voltage level of (V) is a combination of voltage levels that easily cause erroneous writing. The first reason is that the word line (W2) in which the high voltage level (hereinafter referred to as "non-selection level") 20V of the non-selected word lines (W1), (W3), (W4) is selected. Since it is higher than the high voltage level (hereinafter referred to as “selection level”) of 10V, the selection level of 10V may be momentarily passed during the rising of the non-selection level. During this slight period, erroneous writing may occur in the memory transistors (T1), (T3), (T4) to which the non-selected word lines (W1), (W3), (W4) are connected. Secondly, considering the breakdown voltage characteristics of the memory transistors (T1) to (T4) against high voltage, the non-selection level caused by breakdown voltage failure or leak failure, etc.
It is possible that the voltage level will drop from 20V. Therefore, the non-selection level of 20V is not reached, but when the voltage level of about 10V is settled down, it corresponds to the selection level, and erroneous writing may occur.

[Problems to be Solved by the Invention]

Since the conventional NAND type EPROM is configured as described above, erroneous writing is likely to occur because the unselected word line high voltage is higher than the selected word line high voltage at the selected bit line when writing the EPROM. There was a problem.

The present invention has been made to solve the above problems, and until the high voltage level of a non-selected word line is confirmed, each high voltage level of a plurality of word lines related to writing is stored in the memory. The purpose is to obtain a semiconductor integrated circuit in which erroneous writing is prevented by preventing application to the control gate of a transistor.

[Means for solving the problem]

A NAND type EPROM according to the present invention is provided with a circuit for detecting a non-selection level at the time of a write operation in a word line connected to a control gate of a memory transistor,
Similarly, by generating a signal for controlling the write control circuit provided on the word line, the application time of the high voltage applied to the control gate of the memory transistor is controlled, and each non-selection level during writing reaches a predetermined level. It is so arranged that writing to the memory transistor is not performed during the period in which it is not performed.

[Action]

The NAND type EPROM according to the present invention can prevent erroneous writing to a non-selected memory transistor due to a rising period of the non-selected level or a voltage drop of the non-selected level at the time of writing, thus making it difficult to cause a defect. it can.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Figure 1 is a circuit diagram of a 4-stage stacked NAND EPROM, and Figure 2 is a NAND.
3 is a circuit diagram showing a memory configuration of a type EPROM. FIG. In the figure, (B1) ₁ (C1) (T1) to (T4), (W1) to (W4) are the third
The description is omitted because it is similar to that shown in the conventional example of the figure. First, description will be made with reference to FIG. Word line (W1)
The voltage level applied to ~ (W4) goes through the transistor (D1) ~ (D4) that plays the role of diode, and the wiring (L1)
~ (L4) and input to the high voltage detection circuit (1). As an example of the high-voltage detection circuit (1), the circuit is composed of two stages of CMOS type inverters here. The transistors of this circuit adjust the channel width and channel length, respectively, to obtain the input signal from the word line. Is, for example, 15
It is necessary to set the inverter output of the second stage to become "H" only after it becomes V or more. The value of 15 V or higher means a voltage at which writing is impossible in the memory transistor writing characteristics shown in FIG. Next, the output (H1) to (H4) of the high voltage detection circuit (1)
Is input to the 4-input NOR circuit (2). It is necessary to adjust the following contents for each transistor size of the 4-input NOR circuit (2). That is, the output is set to "L" only when three of the four inputs are at "H" level. In this case, if it is difficult to obtain the "H" or "L" level voltage level with only one stage of the 4-input NOR circuit (2), it is necessary to adjust the output level by further inserting two stages of inverters. is there. Next, the output of the 4-input NOR circuit (2) is the high voltage power inverter (3) for EPROM.
Input to the word line (W1) ~
Set the voltage level of (W4) to memory transistors (T1) to (T
4) Input to each gate of transfer gates (TF1) to (TF4) inserted to control the period of transmission.

The operation will be described below. Now, assume that the bit line (B1) and the word line (W2) are selected during writing. Remaining word lines (W1), (W3), (W
4) becomes the non-selection level 20V and the word line (W2) becomes the selection level 10V. As a result, the output (H1), (H3), (H4) of the high voltage detection circuit (1) becomes "H" level, and only the output (H2) of the high voltage detection circuit (1) becomes "L" level. Therefore, the output of the 4-input NOR circuit (2) becomes "L" level according to the above circuit configuration, and a high voltage is obtained as the output (4) of the high voltage power supply inverter (3), and the transfer gate (TF1) ~ Turn on (TF4).
If only one of the word lines (W1), (W3), (W4) other than the word line (W2) is 15 here.
If the voltage does not exceed V, the output (4) of the high-voltage power supply inverter (3) goes to "L" level and the transfer gates (TF1) to (TF4) remain off, so the memory transistors (T1) to (T4). No high voltage is applied to the control gate of), and erroneous writing does not occur.

Since the actual memory array has the configuration shown in FIG. 2, some memory transistors such as unselected bit lines (B2) to (BN) other than the selected bit line (B1) may be included. In some cases, a high voltage (10V or 20V) level for writing is applied to the control gate. However, since the bit lines (B2) to (BN) are not selected, writing is not performed. On the other hand, non-selected word lines connected to the control gates of other memory transistors connected to the selected bit line (B1), eg (W5) to (W8), are set to "L" level. , This is also connected to wirings (L1) to (L4) via transistors (D5) to (D8) that also play the role of diodes, so it is possible to affect other selected word lines. There is no.

In the embodiment shown in FIG. 1, (W1)-
(W4) Transfer gate transistors (TF1) to (T
Although F4) is provided, it is not limited to the example of the circuit shown in FIG. 1 and may be another circuit.

Further, the high-voltage detection circuit (1) and the 4-input NOR circuit (2) are only shown as an example, and it is not particularly limited to this circuit, and other circuits can realize desired functions. it can.

Furthermore, for NAND EPROMs with 8 or 16 stages,
A circuit showing the effect of the present invention can be realized by expanding the basic structure of FIG.

〔The invention's effect〕

As described above, according to the present invention, in the writing of the NAND type EPROM, among the word lines connected to the control gates of the plurality of memory transistors connected in series to the selected bit line, the high voltage higher than that of the selected word line is used. If the high voltage of the non-selected word line requiring the memory cell does not reach the predetermined level, the high voltage is not applied to the control gate of the memory transistor, and the erroneous writing to the non-selected memory transistor does not occur.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a NAND type EPROM according to an embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a circuit diagram showing a memory configuration of a NAND type EPROM according to an embodiment of the present invention, and FIG. ) And (b) are circuit diagrams and pattern diagrams showing a conventional NAND type EPROM having a plurality of memory transistors per bit line, and FIGS. 4 (a) and 4 (b) are conventional non-NAND type EPROs.
A circuit diagram and a pattern diagram showing M, and FIG. 5 are graphs showing write characteristics of the memory transistor. In the figure, (1) is a high voltage detection circuit, (2) is 4 inputs
NOR circuit, (3) high-voltage power inverter, (4) output, (B1) to (BN) bit lines, (D1) to (D8) transistors functioning as diodes, (H1) to (H4)
Is the output of the high voltage detection circuit, (L1) to (L4) are the wiring, and (T
1) to (T8) are memory transistors, (TF1) to (TF8)
Is a transfer gate, and (W1) to (W8) are word lines. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. In a NAND type EPROM, a high voltage detection circuit is provided in a word line connected to a control gate of a memory transistor, and the high voltage detection circuit is composed of a plurality of serial memory transistors connected to a selected bit line during EPROM writing. The high voltage of the non-selected word line, which is higher than the high voltage required to write the selected word line among the above, is detected, and the write high voltage application time of the word line of the memory transistor selected by this high voltage detection signal is detected. A semiconductor integrated circuit having a control circuit and a circuit for realizing the control, wherein the write high voltage is not applied to the word line of the memory transistor while the non-selection high voltage is not applied. circuit.