JP2504515B2 - Test channel instruction execution control method - Google Patents

Description

[Detailed Description of the Invention] [Overview] Regarding a test channel instruction execution control method, a test
In order to prevent channel instructions from being overtaken and processed, in a computer system consisting of one or more CPUs and input / output processing dedicated processors, the CPU issues to the input / output processing dedicated processors. Test channel
A test channel signal holding unit that holds the request signal, an interrupt end signal holding unit that holds the request signal that notifies the end of the I / O interrupt issued by the CPU, a holding signal and an interrupt end signal of the test channel signal holding unit An interrupt control unit that controls the interrupt signal to the processor unit by using the holding signal of the holding unit as an input is provided, and the interrupt control unit performs a test operation when there is an unprocessed interrupt end signal in the interrupt end signal holding unit. It is configured to prevent the channel request signal from interrupting the processor unit.

[Industrial applications]

The present invention relates to a test channel instruction execution control system in an electronic computer system including a CPU and an input / output processing dedicated processor.

[Conventional technology]

In the field of large-scale electronic computers, in order to improve processing capacity, a system configuration has been generalized in which a processor dedicated to input / output processing is provided to reduce the load on the CPU.

FIG. 4 is a diagram showing a configuration example of an electronic computer system.

In FIG. 4, 401 is a main memory, 402 is a storage controller, 403
Is a CPU-A, 404 is a CPU-B, 405 is a processor dedicated to input / output processing, 406 is a channel, and 407 is an input / output device.

 The computer system shown in FIG. 4 will be described.

CPU-A403, CPU-B404 and I / O processing dedicated processor 4
05 are connected to the storage control device 402 in parallel with each other. The CPU-A403, the CPU-B404, and the input / output processing dedicated processor 405 can individually access the main memory 401 via the storage control device 402.

The CPU-A403 and the CPU-B404 can individually request processing to the processor 405 dedicated to input / output processing. Further, the CPU-A403 and the CPU-B404 can communicate with each other.

A plurality of channels 406 are connected to the input / output processing dedicated processor 405. A plurality of input / output devices 407 are connected to each channel 406. When the input / output processing dedicated processor 405 receives an input / output request from the CPU-A 403 or the CPU-B 404, it accesses the main storage 401 via the storage controller 402 and the input / output requested via the channel 406. After accessing the device 407, the data is transferred.

In the example of the electronic computer system shown in FIG.
Although the case where there is one is shown, there may be only one CPU, or there may be three or more CPUs.

The operation of the computer system shown in FIG. 4 will be described below simply as a CPU.

When the CPU detects an input / output instruction, it rewrites the control table, and then requests the input / output processing dedicated processor 405 to perform processing.

Thereafter, the CPU immediately executes the issued I / O instruction if the issued I / O instruction is an asynchronous instruction, and if the issued I / O instruction is a synchronized instruction, the CPU 40
Wait for the response from 5 and then start executing the next instruction.

When such a configuration is adopted, the processing capacity of the I / O processor 405 itself and the reduction of the response time to the CPU greatly affect the processing capacity of the entire system.

As one of control methods performed to shorten the response time from the input / output processing dedicated processor 405 to the CPU, there is a test channel instruction issued from the CPU to the input / output processing dedicated processor 405.

The test channel instruction is an instruction for checking the state of the channel 406. Upon receiving the test channel instruction, the input / output processing dedicated processor 405 notifies the CPU of, for example, the following condition code (CC) according to the state of the channel 406 at that time.

CC = 0: Available CC = 1: Interrupt pending CC = 2: Running CC = 3: Not available When executing a test channel instruction, this instruction is executed frequently and the last channel instruction is synchronous. Since it is an instruction and the CPU waits for a response from the input / output processing dedicated processor 405, the requirements for processing speed and response time become severe. Therefore, the test channel instruction from the CPU to the I / O processing dedicated processor 405 is controlled by the I / O processing dedicated processor 405 to be an interrupt. As a result, the I / O processing dedicated processor 405 can perform a test even if another processing is being performed at that time.
It becomes possible to accept channel instructions and return responses to the CPU, which reduces the CPU wait time.

However, this method has drawbacks. That is, CPU
If a test channel instruction is issued immediately after the I / O interrupt completion notification is issued from the I / O processing dedicated processor 405, the I / O processing dedicated processor 405 issues an interrupt before the processing related to the I / O interrupt completion notification. Performs processing related to a certain test channel instruction.
As a result, the input / output processing dedicated processor 405 determines that the channel 4
Even though 06 can be used, the condition code CC = 1 (interrupt pending) will be returned. This is a logical contradiction.

The conventional method described above will be described in more detail with reference to FIGS. 4 to 7.

 FIG. 5 is an operation flow diagram (No. 1) of each unit.

Figure 5 shows channel 40 in I / O interrupt processing.
FIG. 6 is a diagram showing a flow of operations of an input / output processing dedicated processor 405 and a CPU. In the case of this figure, the above logical inconsistency does not occur.

In the following, referring to FIG. 5, in the input / output interrupt processing, the channel 406, the input / output processing dedicated processor 405 and the CPU
The flow of the operation will be described.

The channel 406 notifies the I / O processing dedicated processor 405 of the end of the data transfer. This is performed as an interrupt to the input / output processing dedicated processor 405.
For example, an interrupt is used to notify that the data transfer between the input / output device 407 and the main memory 401 has been completed.

When the input / output processing dedicated processor 405 receives the interrupt signal from the channel 406, the input / output processing dedicated processor 405 updates the control table in the local memory existing inside itself, and the channel 40
Remember that 6 holds an interrupt. That is,
Turn on the interrupt hold bit.

The input / output processing dedicated processor 405 links the information of the accepted interrupt to the interrupt queue existing in the main memory 401.

 FIG. 6 shows an example of the interrupt queue.

In FIG. 6, 601 is a channel control table, 602 is an interrupt information link pointer, and 603 is interrupt information.

As shown in FIG. 6, the interrupt information 603 is stored in the main memory 401.
It is linked to the interrupt information link pointer 602 provided in the channel control table 601 therein.

The input / output processing dedicated processor 405 turns on the C by turning on the interrupt pending latch existing in the storage controller 402.
Notify the PU of the presence of an I / O interrupt.

The CPU detects that the interrupt pending latch existing in the storage controller 402 is ON.

When the CPU can accept an interrupt, the CPU fetches the information at the head of the interrupt queue existing in the main memory 401 and turns off the interrupt pending latch existing in the storage controller 402.

The CPU sends an interrupt end notification to the I / O processing dedicated processor 405. After that, the processing routine corresponding to the information at the head of the interrupt queue existing in the main memory 401 extracted in the processing of is executed.

The input / output processing dedicated processor 405 detects an interrupt end notification from the CPU.

The input / output processing dedicated processor 405 accesses the interrupt queue on the main memory 401.

If there is unprocessed interrupt information, the I / O processing dedicated processor 405 reconnects the link of the interrupt queue, and then turns on the interrupt pending latch existing in the storage controller 402.

The input / output processing-dedicated processor 405 turns off the interrupt holding bit in the control table in the local storage existing inside itself.

 With the above, the interrupt of the channel 406 is terminated.

In the case shown in FIG. 5, no problem occurs, but in the following cases, a problem occurs.

That is, if the same or another CPU issues a test channel instruction to the I / O processing dedicated processor 405 immediately after the CPU sends an interrupt end notification to the I / O processing dedicated processor 405, The processing routine for the test channel instruction may be activated by the interrupt before the processing-dedicated processor 405 finishes the processing related to the interrupt end notification.

If the channel that generated the interrupt and the channel that is the target of the test channel instruction are the same,
The processor 405 dedicated to input / output processing sees that the interrupt holding bit in the control table in the local memory existing inside itself is ON, understands that the channel concerned holds the interrupt, and informs the CPU. CC = 1, that is,
The channel reports a condition code indicating that the interrupt is pending.

When this is seen from the CPU side, CC = 1 for the test channel instruction, that is, the interrupt is pending for the test channel instruction, although the interrupt processing from the channel has already ended and the interrupt end notification has been issued. The contradictory result is that a condition code that says

Even when the CPU that sent the interrupt end notification and the CPU that sent the test channel instruction are different, if the communication from the CPU is informed that the interrupt from the channel has ended, the same as above Contradiction arises.

When the above-mentioned contradiction occurs, using Fig. 7,
This will be specifically described.

FIG. 7 is an operation flow diagram (No. 2) of each unit. This figure shows channel 406, I / O processor 405, CP
It is a figure which shows the flow of operation | movement of U-A403 and CPU-B404.

Hereinafter, with reference to FIG. 7, in the input / output interrupt processing, the channel 406, the input / output processing dedicated processor 405, and the CPU-A
The operation flow of 403 and CPU-B 404 will be described.

The channel 406 notifies the I / O processing dedicated processor 405 of the end of the data transfer. This is performed as an interrupt to the input / output processing dedicated processor 405.
For example, an interrupt is used to notify that the data transfer between the input / output device 407 and the main memory 401 has been completed.

When the input / output processing dedicated processor 405 receives the interrupt signal from the channel 406, the input / output processing dedicated processor 405 updates the control table in the local memory existing inside itself, and the channel 40
Remember that 6 holds an interrupt. That is,
Turn on the interrupt hold bit.

The input / output processing dedicated processor 405 links the information of the accepted interrupt to the interrupt queue existing in the main memory 401.

The input / output processing dedicated processor 405 turns on the C by turning on the interrupt pending latch existing in the storage controller 402.
Notifies the PU-A403 and CPU-B404 of the existence of an I / O interrupt.

The CPU-A 403 detects that the interrupt pending latch existing in the storage controller 402 is ON.

When the CPU-A 403 is ready to accept an interrupt, the CPU-A 403 takes out the information at the head of the interrupt queue existing in the main memory 401, and turns off the interrupt pending latch existing in the storage controller 402.

CPU-A403 is a dedicated input / output processor 405 and CPU
-Send an interrupt end notification to B404. afterwards,
The processing routine corresponding to the information at the head of the interrupt queue existing in the main memory 401, which is extracted in the processing of (1), is executed.

The CPU-B404 issues a test channel instruction to the processor 405 dedicated to input / output processing.

By the test channel instruction issued by CPU-B404,
An interrupt occurs in the input / output processing dedicated processor 405.

The input / output processing-dedicated processor 405 reads the control table in the local storage that exists inside itself.

The input / output processing dedicated processor 405 sees that the interrupt holding bit in the read control table is ON,
Understands that the relevant channel holds an interrupt, and notifies CC = 1, that is, the condition code indicating that the relevant channel has an interrupt pending.

 This is a logical contradiction when viewed from the CPU-B404.

The input / output processing dedicated processor 405 detects the interrupt end notification from the CPU-A 403 sent before the test channel instruction from the CPU-B 404.

The input / output processing dedicated processor 405 accesses the interrupt queue on the main memory 401.

If there is unprocessed interrupt information, the I / O processing dedicated processor 405 reconnects the link of the interrupt queue, and then turns on the interrupt pending latch existing in the storage controller 402.

The input / output processing-dedicated processor 405 turns off the interrupt holding bit in the control table in the local storage existing inside itself.

 With the above, the interrupt of the channel 406 is terminated.

In the case shown in FIG. 7, a processor dedicated to input / output processing
At 405, a test channel instruction received later after the interrupt end notification received earlier is postponed and processed, resulting in a logical contradiction.

In order to solve this logical contradiction, when the I / O processing dedicated processor 405 receives a test channel instruction, it is confirmed by a micro program whether or not an interrupt end notification exists, and if an interrupt end notification exists. For example, it is conceivable to perform control such that processing related to interrupt end notification is executed first.

However, in this way, the number of steps of the micro program is increased and the speed of response time to the CPU is limited, so this method is not practical.

[Problems to be Solved by the Invention]

In the conventional method, there is a problem that, in the processor dedicated to input / output processing, a test channel instruction that has received the interrupt end notification that has been received first is overtaken and processed, resulting in a logical contradiction.

The present invention shortens the response time by processing the test channel instruction issued from the CPU to the I / O processing dedicated processor as an interrupt, and at the same time, the test channel instruction that receives the interrupt end notification received earlier can be By preventing overtaking and processing,
It is an object of the present invention to provide a test channel instruction execution control method that prevents a decrease in processing capacity and prevents a logical contradiction.

[Means for solving the problem]

In order to achieve the above object, the test channel instruction execution control system of the present invention uses an input / output processing dedicated processor in an electronic computer system comprising one or a plurality of CPUs and an input / output processing dedicated processor. , A test channel signal holding unit that holds the test channel request signal issued by the CPU, an interrupt end signal holding unit that holds the request signal that notifies the end of the I / O interrupt issued by the CPU, and the test channel signal An interrupt control unit that controls the interrupt signal to the processor unit by inputting the hold signal of the holding unit and the interrupt end signal of the holding unit is provided, and the interrupt control unit stores the unprocessed interrupt end signal in the interrupt end signal holding unit. If present, inhibits the test channel request signal from interrupting the processor. To configure.

 FIG. 1 is an explanatory view of the principle of the present invention.

In FIG. 1, 101 is a CPU-A, 102 is a CPU-B, 103 is an input / output processing dedicated processor, 104 is a channel, 105 is an input / output device, 106 and 107 are test channel signal holding units, 108 and 1
09 is an interrupt end signal holding unit, 110 is an interrupt control unit, 111
Is a processor unit.

[Action]

The electronic computer system to which the present invention is applied includes a plurality of computer systems.
It comprises a CPU (CPU-A101, CPU-B102) and a processor 103 dedicated to input / output processing.

A plurality of channels 104 are connected to the input / output processing dedicated processor 103. A plurality of input / output devices 105 are connected to each channel 104.

The input / output processing dedicated processor 103 includes a plurality of test channel signal holding units 106 and 107 for holding a test channel instruction signal, and a plurality of built-in interrupt end signal holding units 108 for holding an interrupt end notification signal. And 109
From the processor unit 111, the interrupt control unit 110 that controls the interrupt signal to the processor unit 111 by using the held signals of the test channel signal holding units 106 and 107 and the held signals of the interrupt end signal holding units 108 and 109 as input. Become.

The CPU-A 101 and the CPU-B 102 issue a test channel request signal for inquiring the state of the channel 104 and a request signal for notifying the end of the input / output interrupt to the dedicated input / output processing processor 103.

The input / output processing dedicated processor 103 handles the test channel request signal as an interrupt signal, and handles the request signal for notifying the end of the input / output interrupt as a normal request signal instead of an interrupt.

The test channel request signal issued by the CPU-A101 is held by the test channel signal holding unit 106, and the CPU
The test channel request signal issued by -B102 is held by the test channel signal holding unit 107.

A request signal notifying the end of the interrupt issued by the CPU-A 101 is held by the interrupt end signal holding unit 108, and a request signal notifying the end of the interrupt issued by the CPU-B 102 is the interrupt end signal holding unit 109. Hold.

The signals held by the test channel signal holding units 106 and 107 and the signals held by the interrupt end signal holding units 108 and 109 are input to the interrupt control unit 110.

If there is an unprocessed interrupt end signal in the interrupt end signal holding unit 108 or 109, the interrupt control unit 110 sends the test channel request signal to the processor unit.
Suppress interrupting 111.

By the operation of the interrupt control unit 110, it is possible to prevent the test channel instruction, which has received the interrupt end notification received first, from being overtaken and processed.

〔Example〕

 FIG. 2 is a block diagram of an embodiment of the present invention.

In FIG. 2, 201 is a CPU-A, 202 is a CPU-B, 203 is an input / output processing dedicated processor, 204 is a set / reset latch for holding a test channel request signal issued by the CPU-A201, 205 is a set for holding the test channel request signal issued by the CPU-B202.
Reset latch, 206 is a set / reset latch for holding the interrupt end notification request signal issued by the CPU-A201, and 207 is a set / reset latch for holding the interrupt end notification request signal issued by the CPU-B202. Latch, 208 selects the test channel request signal or interrupt end notification request signal held by the set / reset latches 204 to 207 to select the data bus 20.
Selector for sending to processor unit 210 via 9, 2
Reference numeral 09 is a data bus, 210 is a processor unit, 211 is a decoder for decoding signals for resetting the set / reset latches 204 to 207 that the processor unit 210 sends out via the data bus 209, and 212 is a set・ Reset Latch 20
4 and an OR circuit for ORing the signals held by the set / reset latch 205, and 213 is a set / reset
An OR circuit for ORing signals held by the latch 206 and the set / reset latch 207, and 214 is a decoder 21.
OR circuit for taking the logical sum of the output signals of 1 and 215 is the OR circuit 2
An AND circuit for ANDing the output of 12 and the inverted output of the output of the OR circuit 213 and the inverted output of the output of the OR circuit 214, and 216 is an AND
A latch for holding the output of 215, an AND for outputting an interrupt signal to the processor unit 210 by taking the logical product of the output of the AND circuit 215 and the inverted output of the output of the latch 216.
Circuit.

 The operation of FIG. 2 will be described below.

Input / output processing dedicated processor 203 consists of two CPUs, CPU-A201
And CPU-B202.

The input / output processing dedicated processor 203 is a CPU-A201 or CPU-A
It receives the test channel request signal and interrupt end notification request signal issued from the B202, and performs the processing according to each.

In Fig. 2, the test channel issued by CPU-A201
The request signal is represented by TCH_A, and the test channel request signal issued by the CPU-B202 is represented by TCH_B. Further, the interrupt end notification request signal issued by the CPU-A 201 is represented by RACK_A, and the interrupt end notification request signal issued by the CPU-B 202 is represented by RACK_B.

CPU-A20 received by I / O processor 203
The test channel request signals from 1 and the CPU-B 202 are held in the set / reset latches 204 and 205 as TCH_HLD_A and TCH_HLD_B, respectively.

In addition, the interrupt end notification request signal received by the I / O processing dedicated processor 203 is RACK_HLD_A and RACK_
HLD_B is held in the set / reset latches 206 and 207, respectively.

TCH_HLD_A held by the set / reset latch 204,
TCH_HLD_B held by the set / reset latch 205, RACK_HLD_A held by the set / reset latch 206, and RACK_HLD_B held by the set / reset latch 207
Is displayed on the processor unit 210 via the data bus 209 after being selected by the selector 208.

The test channel request signal TCH_A or TCH_B issued by the CPU-A201 or CPU-B202 is the TCH_HLD_A and TCH_HLD_A and TCH_B in the set / reset latches 204 and 205, respectively.
It is held as CH_HLD_B. After that, through the OR circuit 212, A
The ND circuit 215 logically ANDs the inverted output of RACK_VLD which is the output of the OR circuit 213 and the inverted output of Release which is the output of the OR circuit 214, and becomes the test channel request valid signal TCH_VLD. The rising edge of the test channel request valid signal TCH_VLD is captured by the latch 216 and the AND circuit 217, and the interrupt signal RUPT for the processor unit 210 is generated.

As an example, the I / O processing dedicated processor 203 is the CPU-A2.
A case will be described in which requests are received in the order of TCH_A, RACK_A, and TCH_B while the request signal from 01 or the CPU-B202 is not held. FIG. 3 is a timing chart of each signal in this case. The figure also shows the processing in the processor 203 dedicated to input / output processing.

When the first TCH_A signal is accepted, the RACK_VLD signal and
Since both Release signals are "0", TCH_VLD signal is "1"
Then, the interrupt signal RUPT is generated at the rising edge of this signal, and the processor unit 210 is interrupted.

Upon receipt of the interrupt, the processor unit 210 interrupts the processing that has been executed up to that point and starts processing for the test channel request.

When the processing for the test channel request is completed, the processor unit 210 issues a Release signal to TCH_A and sets / resets the request signal that was held.
Reset the latch 204.

Since the cause of interruption has disappeared, the processor unit 210
Restarts normal processing.

At this time, even if the TCH_B request is issued, the RACK is already
Since _A is accepted and the RACK_VLD signal is "1", the RUPT signal remains "0". As a result, the interrupt to the processor unit 210 is not performed.

The processor unit 210 detects the RACK_request during the normal processing, and when the processing is completed, outputs the Release signal of RACK_A. This signal resets the set / reset latch 206 that held RACK_HLD_A, and
The signal becomes "0" and the TCH_VLD signal becomes "1". An interrupt signal RUPT is generated at the rising edge of this signal, and the processor unit 210 is interrupted.

 This interrupt processes the TCH_B request.

As described above, according to the present embodiment, it is possible to prevent the interrupt end notification request received earlier from being overtaken by the test channel request received later and processed earlier. .

〔The invention's effect〕

According to the execution control method of the test channel instruction according to the present invention, the response time is shortened by processing the test channel instruction issued from the CPU to the processor dedicated to the input / output processing as an interrupt, and at the same time in advance. It is possible to prevent the processing capability from deteriorating and prevent a logical contradiction from occurring by preventing the test channel instruction request received later from being processed after the received interrupt end notification request.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is a timing diagram of each signal, FIG. 4 is a diagram showing a configuration example of an electronic computer system, and FIG. FIG. 7 is an operation flow diagram of each unit (No. 1), FIG. 6 is a diagram showing an example of an interrupt queue, and FIG. 7 is an operation flow diagram of each unit (No. 2). In FIG. 1, 101: CPU-A 102: CPU-B 103: Input / output processing dedicated processor 104: Channel 105: Input / output device 106: Test channel signal holding unit 107: Test channel signal holding unit 108: Interrupt end signal Holding unit 109: Interrupt end signal holding unit 110: Interrupt control unit 111: Processor unit

Claims (1)

(57) [Claims] 1. A CPU (101, 102) comprising one or a plurality of CPUs (101, 102) and an input / output processing dedicated processor (103), wherein the CPU (101, 102) is an input / output processing dedicated processor (103).
Issue a test channel request signal to inquire about the channel status and a request signal to notify the end of the I / O interrupt, and the I / O processor (103) uses the test channel request signal as an interrupt signal. In a computer system that handles a request signal notifying an end of an I / O interrupt as a normal request signal instead of an interrupt, a test channel issued by the CPU (101, 102) in the I / O processor (103). Test channel signal holding unit that holds request signals (106,10
7), an interrupt end signal holding unit (108,109) that holds a request signal that notifies the end of the I / O interrupt issued by the CPU (101,102), and a holding signal and an interrupt end signal of the test channel signal holding unit (106,107) An interrupt control unit (110) that controls the interrupt signal to the processor unit (111) by using the hold signal of the holding unit (108, 109) as an input is provided, and the interrupt control unit (110) includes the interrupt end signal holding unit (1).
(08,109) has an unprocessed interrupt end signal, it suppresses the test channel request signal from interrupting the processor (111). .