JP2501485B2 - Time axis correction device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for reproducing a signal from a record carrier (including a recording medium), and more particularly to a time axis correction of a reproduced signal.

[0002]

2. Description of the Related Art As a suitable device to which the present invention is applied, there is an optical still image recording / reproducing device. The optical still image recording device uses a disc-shaped recording medium (hereinafter referred to as a recording disc) at a predetermined rotation speed (for example, 1800 rp in the case of the NTSC system).
m) a motor for rotating, a signal converting means for recording a signal on the recording disk or reproducing a signal recorded on the recording disk, and a whole or a part of this signal converting means on the recording disk. Time axis changing means for changing the time axis of the reproduction signal by moving in the recording signal locus (hereinafter referred to as track) direction, and reproduction synchronization signal detecting means for extracting the image synchronization signal (for example, horizontal synchronization signal) from the reproduction signal. And a tracking control means for controlling so that the scanning position of the signal converting means is always located on the track. The signal conversion means includes an optical system for converging and irradiating a light beam generated from a light source such as a semiconductor laser onto the recording disc, an optical system for detecting reflected light from the recording disc, and a photodetector. Contains.

When recording a signal, the rotation of the motor is controlled by a reference synchronizing signal synchronized with the signal to be recorded to rotate the recording disk, and the light quantity of the light beam is modulated strongly and one image is concentric. Record above. When reproducing the recorded signal, the tracking control means is operated with the light amount of the light beam kept constant, and the reproduced signal is obtained from the reflected light from the recording disk.

In the above apparatus, one of the important functions is to retrieve a desired image from many images recorded on the recording disk, and this retrieval is fast and accurate. Required.

The time required for retrieval (retrieval time) is the time from the start of retrieval to the reproduction of the desired image. In the above-mentioned device, the reproduction signal includes time axis fluctuation. This is the time until the time axis fluctuation is corrected and an accurate image signal is reproduced.

The time-axis fluctuation occurs because the relative speed of the recording disk and the converting means when recording the signal is different from that when reproducing the signal, and is mainly caused by eccentricity caused by mounting the recording disk or uneven rotation of the motor. .
Conventionally, the correction of the time base fluctuation has been performed by comparing the phases of the reference synchronization signal and the reproduction synchronization signal by the phase comparison means and adding the signal of the phase comparison means to the time base change means.

[0007]

However, in the conventional structure, when the time axis changing means is simply driven, the output signal of the phase comparing means, that is, the time axis error signal is added to the time axis changing means at the maximum point. Therefore, not only the movable range of the time axis changing means needs to be more than twice the range necessary for simply correcting the time axis error, but also a large signal is applied to the time axis changing means, so that the control system is controlled. There was a case where the pulling-in was unstable and the pulling-in time was very long.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above drawbacks and to provide a time axis correcting device which has a simple structure and which can reduce the movable range of the time axis changing means and which can perform stable control pull-in. is there.

[0009]

In order to solve the above problems, a time axis correction apparatus of the present invention is an apparatus for correcting a time axis fluctuation of a reproduced signal, and a time for detecting a time axis error of the reproduced signal. Axis error detecting means, time axis changing means for changing the reproduction signal reading position from the recording medium in the time axis direction, and time for controlling the time axis changing means based on the time axis error signal of the time axis error detecting means. An axis correction control loop, a command signal generating means for generating a command signal for operating the control loop when the time axis error of the reproduction signal is close to zero, and the time axis correction in response to the signal from the command signal generating means. And a closing means for closing the control loop.

[0010]

With the above construction, since the control loop is operated when the time-axis error of the reproduction signal becomes close to zero, the movable range of the control means can be narrowed and the control pull-in becomes stable and pull-in is possible. It takes less time.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a time axis correction device showing an embodiment of the present invention. To explain the outline of the device, a light beam 2 generated from a light source 1 such as a semiconductor laser is collimated by a coupling lens 3, passes through a beam splitter 4, is reflected by a reflecting mirror 5, and is converged by a converging lens 6 to form a recording disk. Converged on 7. The reflected light 8 reflected by the recording disk 7 passes through the converging lens 6 again, is reflected by the reflecting mirror 5 and the beam splitter 4, and is irradiated onto the photodetector 9. The converging lens 6 is attached to the element 10, and the element 10 is configured to scan the light beam 2 in the track direction by moving the converging lens 6 in the track direction on the recording disk 7.

The above-mentioned optical system and element 10 are attached to a transfer table 11 so that they can move in the radial direction of the recording disk 7 together with the transfer table 11. The recording disk 7 is attached to the rotary shaft 13 of the motor 12, and the motor 12 is rotated by a signal synchronized with the reference synchronization signal.

The light beam focused on the recording disk 7 is focusing-controlled so that the beam diameter is always constant, and tracking-controlled so that the light beam is always positioned on the track. Since it is not directly related to the present invention, it will not be described in detail.

The control of the motor 12 will be described. Vertical sync signal separation circuit from the signal of composite signal generation circuit 14
The vertical synchronizing signal is extracted via 15, and the phase of the signal obtained by dividing the vertical synchronizing signal by half and the rotation signal of the recording disk 7 are compared by the phase comparator 16, and the signal of the phase comparator 16 is compared. It is added to the motor 12 via a drive circuit 17. A mark is provided on the recording disk 7, and this is detected by a rotation detector 18 (for example, a photocoupler), and one signal is obtained for each rotation. Therefore, the signal obtained by dividing the vertical synchronizing signal by half and the signal from the rotation detector 18 are compared in phase by the phase comparator 16 to rotate the motor 12, so that the motor 12 and the recording disk 7 generate a composite signal. It is controlled to rotate in synchronization with the signal of the circuit 14.

The time axis correction will be described. The signal of the composite signal generating circuit 14 is input to the horizontal synchronizing signal separating circuit 19 for extracting the horizontal synchronizing signal, and the signal of the horizontal synchronizing signal separating circuit 19 is 1 / N (N is 1 or more) in the frequency dividing circuit 20. Integer). The delay circuit 21 is for delaying the signal of the frequency dividing circuit 20, and is configured to change the delay amount according to an external signal. The delay circuit 21 may be composed of, for example, a monostable multivibrator, and the threshold level may be changed by an external signal.

22 is a phase comparator, 23 is a low pass filter,
Reference numeral 24 is a voltage controlled oscillator, and 25 is a frequency dividing circuit. Phase comparator
The signals of the delay circuit 21 and the frequency dividing circuit 25 are input to the 22. The phase comparator 22 compares the phases of both signals and transmits the signal to the voltage controlled oscillator 24 via the low pass filter 23. . The voltage controlled oscillator 24 oscillates at a frequency according to the input signal and transmits this signal to the frequency dividing circuit 25 and the phase comparator 26. The frequency divider circuit 25 divides the signal of the voltage controlled oscillator 24 into 1 / N and transmits this signal to the phase comparator 22. Therefore, the signal of the voltage controlled oscillator 24 is controlled so as to be synchronized with the signal of the delay circuit 21 and to oscillate at a frequency N times the frequency of the signal of the delay circuit 21 (this is called phase lock control).

The output of the photodetector 9 is input to the reproduction signal processing circuit 27, and demodulated into an image signal by the reproduction signal processing circuit 27. The horizontal synchronizing signal circuit 28 extracts the horizontal synchronizing signal from the signal of the reproduction signal processing circuit 27 and uses this signal as a phase comparator.
Enter in 26. The signals of the horizontal synchronizing signal separation circuit 28 and the voltage controlled oscillator 24 are input to the phase comparator 26, the phase comparator 26 compares the phases of both signals, and this signal is switched to the switch 29, the pull-in detection circuit 30 and It is transmitted to the control circuit 31. A time axis correction command signal is input to the input end A when a desired track is searched, and the input end A is connected to the pull-in detection circuit 30 and the control circuit 31.

The pull-in detection circuit 30 and the control circuit 31 will be described in detail later, but the pull-in detection circuit 30 has an input terminal A.
Is a circuit for determining whether or not the signal of the phase comparator 26 is within a certain value after the time axis correction command signal is input to the control circuit 31, and the control circuit 31 inputs the time axis correction command signal to the input terminal A. Signal from the phase comparator 26
The delay amount of the delay circuit 21 is transmitted to the delay circuit 21, and then only the low frequency component of the signal of the phase comparator 26 is transmitted to the delay circuit 21. Therefore the phase comparator
When the signal of 26 is transmitted to the delay circuit 21 via the control circuit 31, the delay amount of the delay circuit 21 is controlled at high speed so that the signal of the phase comparator 26 falls within a certain value, and then the phase comparator When only the low frequency component of the signal of 26 is transmitted to the delay circuit 21 via the control circuit 31, the delay amount of the delay circuit 21 is controlled only for the signal of the low frequency component of the signals of the phase comparator 26 ( This control is called the first control means).

When the control circuit 31 transfers only the low frequency component of the signal of the phase comparator 26 to the delay circuit 21, the phase comparator 26 receives a time base fluctuation signal of mainly high frequency component which is not compensated by the first control means. Is output. The signal of the phase comparator 26 is applied to the element 10 via the switch 29, the compensating circuit 32 and the driving circuit 33. The element 10 outputs the light beam 2 to the track of the recording disk 7 according to the signal of the phase comparator 26. It is controlled so as to scan in the direction (this control is referred to as second control means). The switch 29 is for opening and closing the control system of the second control means, and performs the opening and closing operation according to the signal of the pull-in detection circuit 30, and the compensation circuit 32 compensates the phase of the control system of the second control means. It is for doing.

Of the time and axis fluctuations contained in the reproduced signal, only the high frequency component mainly by the second control means is actually compensated. Therefore, in the case of a color video signal, the influence of time axis fluctuation may appear in the color signal, but a processing method such as a low-pass conversion method or a buried chroma method which is generally known as a signal processing method of the color video signal. If the processing is performed with, the time base fluctuation of the color signal is corrected, so there is no problem. Here, the low frequency conversion method is a method of converting a 3.58 MHz color signal to a frequency such as 630 KHz, mixing with an FM modulated luminance signal, and recording / reproducing, and the buried chroma method is a 3.58 MHz color signal, for example. This is a method in which a signal is converted to a frequency such as 1.5 MHz, and is FM-modulated together with a luminance signal for recording and reproduction.

The pull-in detection circuit 30 will be described with reference to FIG. The pull-in detection circuit 30 includes comparators 41 and 42,
It is composed of an inverting circuit 43 and AND circuits 44 and 45. The input terminal B is connected to the input terminals of the comparators 41 and 42, and the output signal of the phase comparator 26 is input to the input terminal B. The comparators 41 and 42 are comparators having different threshold levels, respectively, and when a signal larger than the threshold level is input, the outputs of the comparators 41 and 42 become HIGH. The threshold level of the comparator 41 is lower than that of the comparator 42. The output signal of the comparator 42 is input to the inverting circuit 43 for inverting the signal, and the output signal of the comparator 41 and the output signal of the inverting circuit 43 are input to the AND circuit 44, respectively. AND
As for the output signal of the circuit 44, the signal at the input terminal B is the comparator 41.
Greater than the threshold level of, comparator 42
HIGH when the threshold level is lower than
Becomes The time axis correction command signal is input to the input terminal A, and the signal of the AND circuit 44 and the input terminal A are input.
Signal is input to the AND circuit 45. AN
The output terminal C of the D circuit 45 is connected to the switch 29, and when the input terminal A is HIGH and the signal of the input terminal B is within a certain range, the output terminal C of the AND circuit 45 becomes HIGH and the switch 29 Short circuit. When the switch 29 is short-circuited, the second control means operates.

As described above, the pull-in detection circuit 30 detects that the signal of the phase comparator 26 falls within a certain range, and thereafter operates the second control means.
10 does not swing greatly, and the second control means operates stably. Further, if the element 10 largely shakes, focusing control or tracking control may be lost, but since the element 10 does not greatly shake, focusing control and tracking control are not affected by the shake of the element 10, and the device is stable. Operate.

Next, the control circuit 31 will be described with reference to FIG. To explain the relationship between FIG. 1 and FIG. 3, the signal of the phase comparator 26 is input to the input end D, the time axis correction command signal is input to the input end A, and the output end E is the input end of the delay circuit 21. It is connected to the. R1 to R4 are fixed resistors, C1 is a capacitor, VR1 is a variable resistor, 51 and 52 are differential amplifiers having large amplification factors and input impedances, 53 and 54 are switches, and 55 is a monostable multivibrator (hereinafter referred to as monomulti). 56) is a limiting circuit, and 57 is an inverting circuit that inverts the polarity of the input signal. The input end D is connected to one end of the fixed resistor R1, and the other end of the fixed resistor R1 is connected to the inverting input end of the differential amplifier 51. The inverting input terminal and the output terminal of the differential amplifier 51 are connected via a fixed resistor R2, and the non-inverting input terminal of the differential amplifier 51 is connected to the central end of the variable resistor VR1. Variable resistor V
Voltages of opposite polarities are input to both ends of R1, for example, + 12V is applied to one end and -12V is applied to the other end. The output end of the differential amplifier 51 and the inverting input end of the differential amplifier 52 are connected via a fixed resistor R3, the output of the differential amplifier 51 is input to the switch 53, and the output end of the switch 53 is fixed. It is connected to one end of the resistor R4, and the other end of the fixed resistor R4 is connected to the inverting input end of the differential amplifier 52. The inverting input terminal and the output terminal of the differential amplifier 52 are connected via the capacitor C1, the inverting input terminal of the differential amplifier 52 is connected to the output terminal of the switch 54, and the input terminal of the switch 54 is differential. It is connected to the output terminal of the amplifier 52. The non-inverting input terminal of the differential amplifier 52 is set to zero potential, the output of the differential amplifier 52 is input to the limiting circuit 56, and the output terminal of the limiting circuit 56 is connected to the output terminal E. The input terminal A is the input terminal of the monomulti 55 and the inverting circuit 57.
, The output end of the inverting circuit 57 is connected to the input end for operating the opening / closing of the switch 54, and the output end of the monomulti 55 is the input end for operating the opening / closing of the switch 53. It is connected to the.

When the time axis correction is not performed, the input terminal A is LOW, the switch 53 is open, and the switch 54 is short-circuited. When the input terminal A becomes HIGH to perform the time axis correction, the switch 54 is opened and the input terminal A is
Mono Multi 55 operates at the rising edge of the signal of
Output becomes HIGH for a predetermined period. While the output of Mono-multi 55 is HIGH, switch 53 is short-circuited,
When the output of becomes LOW, it becomes open.

Differential amplifier 52 when switch 54 is short circuited
Is zero, and when the switch 54 is open, the differential amplifier 52 operates as an integrating circuit and outputs a signal obtained by integrating the signal of the differential amplifier 51. When the switch 54 is open and the switch 53 is short-circuited, the differential amplifier 52 operates with the fixed resistor R3.
And the parallel resistance value of R4 (the resistance value of R3 × R4 / (R3 + R4)) and the capacitance value of the capacitor C1 operate as a quick responsive integrating circuit, and when the switches 53 and 54 are open, the differential amplifier 52 It operates as an integrating circuit having a slow response due to the resistance value of the fixed resistor R3 and the capacitance value of the capacitor C1. The limiting circuit 56 is for limiting the delay amount of the delay circuit 21, and is configured so that the delay circuit 21 transmits the signal of the frequency dividing circuit 20 to the phase comparator 22 without changing the frequency. For example, when the delay circuit 21 is composed of a non-triggerable mono-multi, the frequency of the signal of the frequency dividing circuit 20 is 127 μsec and the delay amount of the delay circuit 21 is 130 μ
If it becomes sec, the signal of the delay circuit 21 is
The signal of is divided into 1/2 and the second control means malfunctions. Therefore, if the limiting circuit 56 is configured such that the maximum delay amount of the delay circuit 21 is less than 127 μsec, the second limiting means does not malfunction, and highly reliable time axis correction can be performed.

Further, as described above, the first control means controls the time base fluctuation of the low frequency component. However, the time base fluctuation of the low frequency component is almost a cycle centered on a certain constant value when viewed over a long period. Change. Therefore switch 54
The limiting circuit 56 is configured so that the delay amount of the delay circuit 21 becomes a substantially constant value (N × H) / 2 (H is the period of the signal of the horizontal synchronizing signal separation circuit 19) when is short-circuited. Ok
When the first control means operates, the delay amount of the delay circuit 21 fluctuates around about (N × H) / 2, so the control range of the first control means is ± (N × H) / 2. (+ Indicates the advance amount, − indicates the feed amount), and the control range is widest and stable. Instead of the switch 54, a switch is provided between the output of the differential amplifier 52 and the input of the limiting circuit 56, and when the time axis correction is performed, this switch is short-circuited and the signal of the differential amplifier 52 is transmitted to the limiting circuit 56. With such a configuration, the differential amplifier 52 is always operating as an integrating circuit, and an extremely large signal may be transmitted to the delay circuit 21 via the limiting circuit 56. May become unstable. If the response of the limiting circuit 56 and the delay circuit 21 is slower than that of the differential amplifier 52 operating as an integrating circuit, the pull-in is stable, but in this case also, as shown in FIG. If the output of the differential amplifier 52 is set to zero by the switch 54, the control system of the first control means can be pulled in more quickly and more stably.

As described above, when the time axis correction command signal is input to the input terminal A, the switch 53 is short-circuited by the monomulti 55 for a certain period of time, and the differential amplifier 52 becomes an integrating circuit having a fast response. Since the response of the control system of the control means of No. 1 becomes high-speed, the signal of the phase comparator 26 instantaneously falls within a certain fixed value, and the switch 53 is opened, the differential amplifier 52 becomes an integrating circuit having a slow response. The first control means is a phase comparator
The delay amount of the delay circuit 21 is controlled according to the 26 low frequency components.

In FIG. 1, the switch 29 is opened and closed by detecting that the output of the phase comparator 26 falls within a certain range, but from the time when the time axis correction command signal is input to the input terminal A. The switch 29 may be configured to be closed after a certain time. Further, the control circuit 31 is configured to transfer only the low frequency component of the signal of the phase comparator 26 to the delay circuit 21 after a fixed time, but it is detected that the signal of the phase comparator 26 falls within a certain range. Then, only the low frequency component of the signal of the phase comparator 26 may be transmitted to the delay circuit 21.

A specific example of the phase comparator 26 shown in FIG. 1 will be described with reference to FIG. Explaining the relationship between FIG. 1 and FIG. 4, the input terminal F
The signal of the horizontal synchronizing signal separation circuit 28 is input to the input terminal, the signal of the voltage controlled oscillator 24 is input to the input terminal G, and the output terminal I is input to the switch 29, the pull-in detection circuit 30, and the control circuit 31, respectively. It is connected. 61 is a constant voltage circuit that generates a constant voltage signal, 62 is a monomulti that operates at the rising edge of the signal at the input terminal G, 63, 64, 65 and 69 are switches, 66, 67,
68 is a differential amplifier with a large amplification factor and large input impedance, R5 is a fixed resistor C2, C3, C4 is a capacitor,
Reference numeral 70 is a mono-multi that operates at the rising edge of the signal at the input terminal F. The output of the constant voltage circuit 61 is input to the switch 63, the output end of the switch 63 and the inverting input end of the differential amplifier 66 are connected via the fixed resistor R5, and the inverting input end of the differential amplifier 66 is the switch. The output terminal of the differential amplifier 66 is connected to the output terminal of 64, and the output terminal of the differential amplifier 66 is connected to the input terminal of the switch 64. The output terminal and the inverting input terminal of the differential amplifier 66 are connected via the capacitor C2, and the non-inverting input terminal of the differential amplifier 66 is set to zero potential. The output terminal of the differential amplifier 66 is the input terminal of the switch 65, the output terminal of the switch 65 is the non-inverting input terminal of the differential amplifier 67, and the non-inverting input terminal of the differential amplifier 67 is the capacitor C.
3 and the other end of the capacitor C3 is set to zero potential. The inverting input terminal and the output terminal of the differential amplifier 67 are connected, the output terminal of the differential amplifier 67 is the input terminal of the switch 69, and the output terminal of the switch 69 is the differential amplifier.
The non-inverting input terminal of 68 and the non-inverting input terminal of the differential amplifier 68 are connected to one end of the capacitor C4, respectively. The other end of the capacitor C4 is set to zero potential, the inverting input end and the output end of the differential amplifier 68 are connected, and the output end is connected to the output end I. Inverted Q output terminal of Monomulti 62 is a switch
The input terminal for operating the opening / closing of 63, the Q output terminal of the monomulti 62 is the input terminal for operating the opening / closing of the switch 64, and the input terminal F is the input terminal for operating the opening / closing of the switch 65. The Q output terminals of the monomulti 70 are respectively connected to the input terminals for operating the opening and closing of the switch 69.

The operation of the phase comparator 26 of FIG. 4 will be described with reference to the timing chart of FIG. FIG. 5 shows a state in which the signal of the phase comparator 26 is kept within a certain value by the first control means. (A) is a signal waveform of the input terminal G, and (b) is a mono-multi signal. The signal waveform of the Q output terminal of 62, (c) the signal waveform of the inverted Q output terminal of the monomulti 62, (d) the output waveform of the differential amplifier 66, (e) the signal waveform of the input terminal F, (f) ) Is the output waveform of the differential amplifier 67, (g) is the signal waveform at the Q output end of the monomulti 70, and (h) is the output waveform of the differential amplifier 68.

The mono-multi 70, switch 69, and the like in FIG.
If the output of the differential amplifier 67 is sampled and held again by the differential amplifier 68 and the capacitor C4, the waveform (h) of FIG. 5 is obtained, the output fluctuation during the short circuit period of the switch 65 of (f) is eliminated, and the extremely accurate phase is obtained. Comparisons can be made.

The pull-in detection circuit 30 described with reference to FIG. 2 and FIG.
4. The control circuit 31 explained in 1. and the phase comparator explained in FIG.
26 is not limited to any embodiment. The frequency dividing circuits 20 and 25, the delay circuit 21, and the phase comparator as described in the embodiment of FIG.
If configured with 22, the low-pass filter 23 and the voltage controlled oscillator 24, the first control means can operate with respect to the time axis fluctuation of (N × H) or less, but the time axis fluctuation is H or less. In such a case, the configuration can be simplified as shown in FIG.

Although FIG. 6 will be described below, the detailed description of FIG. 1 will be omitted. The signal of the horizontal synchronizing signal separation circuit 19 is directly input to the delay circuit 71, and the signal of the delay circuit 71 is input to the phase comparator 26. Input end A
When the time axis correction command signal is input to the control circuit 31, the control circuit 31 transmits the signal of the phase comparator 26 to the delay circuit 71, and the delay circuit 71 delays the signal of the phase comparator 26 to a certain constant value. Change. After that, the control circuit 31 transmits only the low frequency component of the signal of the phase comparator 26 to the delay circuit 71, and the pull-in detection circuit 30 switches the signal for short-circuiting the switch 29.
Send to 29. The signal of the phase comparator 26 is the switch 29, the compensation circuit
It is transmitted to the element 10 via the drive circuit 33 and the drive circuit 32, and the time axis correction is performed.

As described with reference to FIGS. 1 and 4, the first control means corrects the time base fluctuation of the low frequency component including the constant H shift, and the second control means the first control means. Mainly compensates the fluctuation of the high frequency component on the time axis, which is not compensated by. In order to prevent the second control means from largely responding to the time base fluctuation of the low frequency component, in the low frequency region, the control gain of the first control means is higher than the loop gain of the control system of the second control means. It may be configured to increase the loop gain.

The present invention is not limited to the embodiment, and for example, instead of the horizontal period signal included in the image signal, a signal having a constant frequency for time axis correction is recorded and this signal is recorded. May be configured to correct the time axis fluctuation that occurs during playback. The constant frequency in this case is the motor 12
A signal that is an integral multiple of the number of revolutions is preferable.

Needless to say, the present invention can also be applied to a device for reproducing a signal from a recording disk having spiral tracks, but a magnetic recording / reproducing device, a magneto-optical recording / reproducing device, and a capacitive type recording / reproducing device. It can also be applied to a playback device or the like.

[0037]

The present invention has been described in detail above. However, if the present invention is applied to an apparatus, the time axis fluctuation can be corrected by using the time axis changing means having a narrow movable range with a simple structure. It is possible to realize the time axis correction control that can be performed at a low cost, can perform extremely stable pull-in, and can shorten the pull-in time.

[Brief description of drawings]

FIG. 1 is a block diagram of a time axis correction device showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a pull-in detection circuit of the same time axis correction device.

FIG. 3 is a circuit diagram showing a specific example of a control circuit of the time axis correction device.

FIG. 4 is a circuit diagram showing a specific example of a phase comparator of the same time axis correction device.

5 is a timing chart of the phase comparator shown in FIG.

FIG. 6 is a block diagram showing a time axis correction device according to another embodiment of the present invention.

[Explanation of symbols]

 19 Horizontal sync signal separation circuit 20 Frequency division circuit 21 Delay circuit 22 Phase comparison circuit 24 Voltage controlled oscillator 25 Frequency division circuit 26 Phase comparator 28 Horizontal synchronization signal separation circuit 29 Switch 30 Pull-in detection circuit 31 Control circuit 33 Drive circuit

Claims (1)

(57) [Claims] 1. A device for correcting a time-axis fluctuation of a reproduction signal, wherein a time-axis error detecting means for detecting a time-axis error of the reproduction signal and a reproduction signal reading position from a recording medium are changed in the time-axis direction. A time axis changing means, a time axis correction control loop for controlling the time axis changing means based on the time axis error signal of the time axis error detecting means, and a control loop when the time axis error of the reproduction signal becomes near zero And a time axis correction device for closing the time axis correction control loop in response to a signal from the command signal generation means. .