JP2501450B2 - Gateway - Google Patents

Description

TECHNICAL FIELD The present invention has been made in view of the above problems, and an object of the present invention relates to a gateway used in a home bus system.

[Background Art] In the home bus system, with regard to the main bus that mainly communicates data information such as telephones and personal computers, the Ministry of Posts and Telecommunications, the Radio Technical Association and the Japan Electronic Machinery Manufacturers' Association have studied standardization plans and are currently specifying their specifications. It is almost at the stage of solidification.

It is also conceivable that a conventional system of time division multiplex transmission using power line carrier, infrared rays, radio waves, and dedicated two lines is combined as a subsystem of the main bus to be constructed as a hose bus system. Therefore, a gateway that organically connects the main bus and subsystems has become necessary.

However, the problem of the gateway is the stagnation of packet data in the gateway and the overflow of the buffer due to the difference in packet length and the difference in transmission rate between the two systems.

FIG. 9 shows the overall configuration of the home bus system, and FIG. 10 shows the configuration of the gateway X that connects the main bus 1 and the sub bus 3 thereof. From the interface unit 2 of the main bus 1 having the unique address A ₁ to the interface unit 4 of the sub bus 3 having the unique address A ₂ of the subsystem, or from the interface unit 4 of the sub bus 3 to the interface unit 2 of the main bus 1, Perform data handshaking as shown in Fig. 11.

That is, when the transmitter sends the ST signal shown in FIG. 11 (a) to the receiver to transmit the data as shown in FIG. 11 (b) and the receiver receives the data, the ACK signal shown in FIG. 11 (c). Is sent to the sender.

By the way, conventionally, when data is transmitted from the main bus 1 having a long message length and a high transmission speed to the sub bus 3, the data is stagnated in the interface unit 2 of the main bus 1, and the amount of the data is limited by the buffer in the interface unit 2. When the value exceeds the limit, the operation to either issue a command that cannot be received to the main system or to request transmission again is performed, which adversely affects the communication of the entire main system. . In addition, in FIG.
a ₁ ... Is a terminal connected to the main bus 1 and b ₁ ... Is a sub bus 3 terminal.

[Object of the Invention] The present invention has been made in view of the above problems, and an object of the present invention is to adjust a transmission speed of an interface unit of a main bus and an interface unit of a sub-bus, and to efficiently perform a buffer memory. To provide a gateway that can be used.

DISCLOSURE OF THE INVENTION The present invention relates to an interface unit of a main bus having a unique address, an interface unit of a sub bus having a unique address and a transmission method and a transmission speed different from each other, and a main bus and a sub bus. CPU for relay control of handshake for data exchange between
Section, and a buffer memory that saves data under the control of the CPU section when the data is stagnant due to the difference in transmission speed between the main bus and the sub bus. Has a data table associated with the transmission / reception bit that distinguishes between transmission data and reception data, and the CPU unit checks the presence / absence bit of the data in the buffer memory, and if it is "present", it transmits / receives. It is characterized in that the bit is checked to determine whether it is output to the main-bus interface unit or the sub-bus interface unit.

 The present invention will be described below with reference to examples.

Embodiment FIG. 1 shows the configuration of the gateway of this embodiment, in which a CPU unit 5 is provided between the interface units 2 and 4, and the CPU 5 controls the CPU unit 5 to connect between the main bus 1 and the sub bus 3. The data transmission speed is adjusted.

Next, the procedure of signal transmission from the main bus 1 to the sub bus 3 of this embodiment will be described.

First, the interface unit 2 of the main bus 1 always takes in the signal on the main bus 1, and if the signal matches the address A _{1 of} its own, inputs the signal and outputs it as parallel data to the CPU unit 5.

If there is no transmission data in the buffer memory 6 (here, the data from the main bus 1 to the sub bus 3 is the transmission data and the data from the sub bus 3 to the main bus 1 is the reception data), the CPU unit 5 has an interface of the sub bus 3 The data of unit 4 is output. At this time, if the ACK signal is not returned from the interface unit 4 of the sub-bus 3, the transmission / reception bit is set to “transmission” in the buffer memory 6 having the table as shown in FIG. Set to "Yes" to save the data.

The interface unit 4 of the sub-bus 3 outputs the data to the sub-bus 3 if the sub-bus 3 is capable of outputting data, and waits for the next transmission data from the CPU section 5.

The handshaking of the received data from the sub bus 3 to the main bus 1 is performed in the same procedure. The only difference is CP
If the ACK signal is not returned when the U unit 5 inputs the reception data from the interface unit 4 of the sub bus 3 and outputs the reception data to the interface unit 2 of the main bus 1, set the transmission / reception bit to "reception". The received data is saved in the buffer memory 6.

As described above, the buffer memory 6 of the present embodiment is not divided into its own memories for transmitting data and receiving data, respectively, but the transmission / reception bits are used to distinguish between them, and free allocation is possible. ing.

However, when the CPU unit 5 checks the buffer memory 6, first, it checks the presence / absence of data,
If "Yes", the transmission / reception bit is checked to determine whether the output is to the interface unit 2 of the main bus 1 or the interface unit 4 of the sub bus 3.

FIG. 3 shows a certain state of the buffer memory 6. In the illustrated buffer memory 6, data is saved in the memory areas "1" to "5", and the next new data is saved in the memory "6". It When data is output from the buffer memory 6, it is output from the memory "1".

In the gateway of this embodiment, the interface unit 2 of the main bus 1 and the interface unit 4 of the sub-bus 3 always send back an ACK signal when handshaking the input data, so that the data in the interface units 2, 4 are Does not stagnate, and signal transmission within each system system can be performed smoothly.
Moreover, by using the buffer memory 6 for both transmission and reception, an efficient buffer can be realized.

In the above embodiment, all the data in the buffer memory 6 are the interface unit 2 and the sub bus 3 of the main bus 1.
However, if there are multiple transmission data for the same terminal in the buffer memory 6, only the latest data (command) is left and the data up to that point is deleted. Is also good.

FIG. 4 shows the contents of the certain buffer memory 6. In the illustrated state, the command 1 exists in the memories "1", "4", and "6", respectively. , Memory "6"
Delete the data of memory "1", "4", leaving the latest command 1 of. In addition, (ON) and (OFF) in the figure indicate the terminal b ₁ sent by operating the operation switch SW of the terminal a _{1 in} FIG.
The ON and OFF data of the load R are shown respectively.

By the way, the interface unit 2 of the main bus 1
When the number of inputs / outputs from the sub-bus 3 is larger than the number of inputs / outputs of the interface unit 4 of the sub-bus 3 (generally, the main bus 1 performs communication and the like, therefore, the amount of data is larger than that of the subsystem for the load control bus). FIG. 6 shows a gateway X in which data can be exchanged with the sub bus 3 side by handshaking only once so as not to burden the interface unit 2 of 1.

FIG. 7 shows the interface unit 2 of the main bus 1.
8 shows the timing of handshaking of transmission data from the sub-bus 3 to the interface units 4a, 4b, and FIG. 8 shows the timing of handshaking of received data from the sub-bus 3 interface units 4a, 4b to the main bus 1 interface unit 2. .

First, from the 8-bit interface unit 2 to the 4-bit interface units 4a and 4b, see FIG. 7 (b).
When outputting the transmission data shown in FIG. 7, the interface unit 2 sets the transmission data, outputs the ST ₁ signal shown in FIG. 7 (a), and waits for the ACK ₃ signal shown in FIG. 7 (e). When the interface unit 4a receives the ST ₁ signal, it inputs the upper 4 bits of the transmission data and returns the ACK ₁ signal as shown in FIG. 7 (c). When the interface unit 4 also receives the ST ₁ signal, it inputs the lower 4 bits of the transmission data and returns the ACK ₂ signal shown in FIG. 7 (d).

The ACK ₁ signal and the ACK ₂ signal become respective clock signals of the flip-flops 7a and 7b. The flip-flops 7a, 7b
The Q output of ₁ enters the AND gate 8 and the ACK ₃ signal cannot be obtained as the gate output unless both the ACK ₁ signal and the ACK ₂ signal are set. That is, after the interface units 4a and 4b both receive the transmission data, the ACK
₃ signal is returned.

Similarly, both receive data (every 4 bits) from the interface units 4a, 4b to the interface unit 2
Is set and each ST ₂ shown in FIGS. 8 (a) and 8 (b) is set.
Signal and ST ₃ signal are input as the clock signals of the flip-flops 9a and 9b, and when the Q output of the flip-flops 9a and 9b is input to the AND gate 10, the ST ₄ signal is output as shown in FIG. 8 (c). The output is output to the interface unit 2, the reception data shown in FIG. 8 (d) is transmitted to the interface unit 2, and the interface unit 2 that receives this data is shown in FIG. 8 (e).
The ACK ₄ signal shown in (1) is transmitted to the interface units 4a and 4b to perform the handshake.

Thus, in the circuit of FIG. 6, the interface unit 2 of the main bus 1 can exchange data with the plurality of interface units 4a, 4b of the sub bus 3 by one handshake. A ₂ a and A ₂ b indicate addresses of the interface units 4a and 4b.

[Effects of the Invention] The present invention relates to a main bus interface unit having a unique address, a sub bus interface unit having a unique address and a transmission method and a transmission speed different from that of a main bus, and a main bus and a sub bus. CPU for relay control of handshake for data exchange between
And a buffer memory that saves data under the control of the CPU when data is stagnant due to the difference in transmission speed between the main bus and sub-bus, so the CPU 5 always returns an ACK signal when handshaking. By doing so, data will not be stagnated in each interface unit, and as a result, signal transmission in each system system can be smoothly performed.
It has a data table in which a bit indicating nothing is associated with a send / receive bit that distinguishes whether the data is send data or receive data, and the CPU part checks the presence / absence bit of the data in the buffer memory If so, the transmit / receive bit is checked and it is determined whether the output is to the main abus interface unit or the sub bus interface unit. Therefore, the buffer memory is divided into its own memory for transmit data and receive data. It is possible to perform free allocation by distinguishing by checking the transmission / reception bit without being performed, and it is possible to realize an efficient buffer by using both the buffer memory for transmission and reception.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams of a buffer memory of the above, FIG. 4 is an explanatory diagram of a buffer memory of another embodiment, and FIG. 6 is a circuit configuration diagram of another example of the gateway, FIGS. 7 and 8 are time charts for explaining the operation of the same, and FIG.
FIG. 10 is a configuration diagram of a home bus system, FIG. 10 is a circuit configuration diagram of a conventional example, and FIG. 11 is a time chart for explaining the operation of the same. 1 ...... main bus, 2,4 ...... interface unit, 3 ...... sub-bus, 5 ...... CPU unit, 6 ...... buffer memory, is A _1, A ₂ ...... address.

Claims (1)

(57) [Claims] 1. A main bus interface unit having a unique address, a transmission method and a transmission speed different from that of the main bus, and a sub bus interface unit having a unique address, and between the main bus and the sub bus. CPU that controls relay of handshake for data transfer
Section and a buffer memory that saves data under the control of the CPU section when the data is stagnant due to the transmission speed between the main bus and the sub bus. The buffer memory is a bit that indicates the presence or absence of data and a data Has a data table associated with the transmission / reception bit that distinguishes between transmission data and reception data, and the CPU unit checks the presence / absence bit of the data in the buffer memory, and if it is "present", it transmits / receives. A gateway characterized by checking the bit and determining whether it is output to the main abus interface unit or the sub bus interface unit.