JP2024040114A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

The present invention provides a technique for improving the switching time of a semiconductor device such as an insulated gate bar polar transistor by suppressing hole accumulation in a P-type floating region. A semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a first conductivity type floating region formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottoms of the trench gate and the trench emitter, and the floating region has a crystal defect forming region on the surface side of the floating region. [Selection diagram] Figure 2

Description

The present disclosure relates to a semiconductor device, and relates to a technique that is effective when applied to a power semiconductor device such as an insulated gate bipolar transistor (IGBT) having a trench gate and a P-type floating region.

As an insulated gate bipolar transistor (IGBT), an IE type IGBT that can utilize an IE (Injection Enhancement) effect has been developed. The IE effect is an effect that increases the concentration of charges accumulated in the drift region by making it difficult for holes to be discharged when the IGBT is on, thereby lowering the on-state voltage of the IGBT. Such IE type IGBTs include a GG type structure, a GGEE type structure, a GE-S type structure, etc. (see Japanese Patent Application Laid-Open No. 2019-029434).

JP2019-029434A

In an IE type IGBT with a GG type structure, a GGEE type structure, or a GE-S type structure, there is a type structure and between GE in the GE-S type structure) may have a P-type floating region. Not only the drift region but also the ease with which holes accumulated in the P-type floating region between the GG and GE trenches can be discharged affects the switching time of the IGBT. In order to further improve the switching characteristics, it is necessary to control the hole accumulation effect on the P-type floating region. A gate trench is a trench region in which an electrode formed within the trench is connected to a gate electrode and functions as the gate electrode. Further, an emitter trench is a trench region in which an electrode formed in the trench is connected to an emitter electrode and functions as an emitter electrode.

An object of the present disclosure is to provide a technique for suppressing hole accumulation in a P-type floating region and improving the switching time of a semiconductor device such as an insulated gate bar polar transistor.

Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

A brief overview of typical features of the present disclosure is as follows.

A semiconductor device according to one embodiment includes:
a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
a first trench and a second trench formed in the semiconductor substrate;
a first trench emitter embedded in the first trench via a first gate insulating film;
a first trench gate embedded in the second trench via a second gate insulating film;
a floating region formed in the semiconductor substrate between the first trench emitter and the first trench gate;
A crystal defect region including a crystal defect is formed locally in the floating region at a position close to the first main surface.

In a cross-sectional view, the floating region is formed to cover a bottom surface of the first trench and a bottom surface of the second trench,
In plan view and cross-sectional view, the crystal defect region is provided apart from the first trench and the second trench.

According to the semiconductor device according to the embodiment described above, it is possible to suppress hole accumulation in the P-type floating region and improve switching time.

FIG. 1 is an overall plan view of a semiconductor chip according to an embodiment. FIG. 2 is a sectional view of a main part of the cell region RR shown in FIG. 1. FIG. 3 is a plan view of a main part of the cell region RR in FIG. 1. FIG. 4 is a flow diagram illustrating a method for manufacturing a p-type floating region according to an embodiment. FIG. 5 is a cross-sectional view of a main part according to another example of the structure of the cell region RR shown in FIG. 1. FIG. 6 is a diagram illustrating the structure of the crystal defect region in FIGS. 2 and 5. FIG. 7 is a diagram illustrating switching characteristics. FIG. 8 is a diagram illustrating the evaluation results of crystal defects according to the embodiment. FIG. 9 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 10 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 9. FIG. 11 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 10. FIG. 12 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 11. FIG. 13 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 12. FIG. 14 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 13. FIG. 15 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 14. FIG. 16 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 15. FIG. 17 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 16. FIG. 18 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 17. FIG. 19 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 18. FIG. 20 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 19. FIG. 21 is a diagram illustrating a method for manufacturing a semiconductor device following FIG. 20. FIG. 22 is a cross-sectional view of a main part of another example of the structure of the cell region RR shown in FIG. 1.

In the following embodiments, when necessary for convenience, the explanation will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one does not differ from the other. This is related to variations, details, supplementary explanations, etc. of some or all of the above. In addition, in the following embodiments, when referring to the number of elements (including numbers, numerical values, amounts, ranges, etc.), we also refer to cases where it is specifically specified or where it is clearly limited to a specific number in principle. However, it is not limited to the specific number, and may be greater than or less than the specific number. Furthermore, in the embodiments described below, the constituent elements (including elemental steps, etc.) are not essential, unless explicitly stated or when it is considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., the shape, positional relationship, etc. of components, etc. are referred to, unless specifically stated or when it is considered that it is clearly not possible in principle. This shall include things that approximate or are similar to, etc. This also applies to the above numerical values and ranges.

Hereinafter, embodiments will be described in detail based on the drawings. In addition, in all the drawings for explaining the embodiment, members having the same function are given the same reference numerals, and repeated explanation thereof will be omitted. Note that, in order to make the explanation clearer, the drawings may be shown more schematically than the actual aspects, but this is merely an example and does not limit the interpretation of the present invention. Furthermore, in the following embodiments, descriptions of the same or similar parts will not be repeated in principle unless particularly necessary.

Further, in the drawings used in the embodiments, hatching may be omitted in order to make the drawings easier to read.

As used herein, a p-type conductivity type of a semiconductor means that the concentration of holes is higher than the concentration of electrons, and holes are the main charge carriers. Furthermore, a p-type semiconductor refers to a semiconductor region containing impurities such as boron and gallium. In this specification, when the conductivity type of a semiconductor is n-type, it means that the concentration of electrons is higher than the concentration of holes, and electrons are the main charge carriers. Furthermore, an n-type semiconductor refers to a semiconductor region containing impurities such as phosphorus or arsenic.

Further, in this specification, a switching operation in which an IGBT is switched from an off state to an on state is referred to as a "turn-on", and a switching operation in which an IGBT is switched from an on state to an off state is referred to as a "turn-off". Note that these switchings do not occur instantaneously, but may include a plurality of stages having a temporal order relationship, including the external circuit to which the IGBT is connected.

(Embodiment)
Hereinafter, semiconductor devices according to embodiments will be described in detail with reference to the drawings. The semiconductor device 100 of this embodiment includes, for example, a semiconductor chip CHP including an IGBT.

FIG. 1 is a plan view of the entire semiconductor chip CHP according to this embodiment. As shown in FIG. 1, most of the semiconductor chip CHP of the semiconductor device 100 is covered with the emitter potential electrode EE. Further, a gate potential electrode GE is formed on the outer periphery of the emitter potential electrode EE so as to surround the emitter potential electrode EE. A region surrounded by a broken line near the center of the emitter potential electrode EE is an emitter pad EP, and a region surrounded by a broken line of the gate potential electrode GE is a gate pad GP. The upper surface of the semiconductor chip CHP is covered with a protective film PIQ (not shown in FIG. 1), but the protective film PIQ is removed from the upper surfaces of the emitter pad EP and gate pad GP. External connection terminals such as wire bonding or clips are connected to the emitter pad EP and gate pad GP, and the semiconductor chip CHP is electrically connected to other chips or wiring boards through the external connection terminals.

(Configuration example 1 of a semiconductor device including an IE type IGBT: GGEE type structure)
FIG. 2 is a sectional view of a main part of the cell region RR shown in FIG. 1. FIG. 3 is a plan view of a main part of the cell region RR in FIG. 1. FIG. 4 is a flowchart illustrating a method for manufacturing the p-type floating region FL according to the embodiment.

As shown in FIG. 2, a semiconductor device 100 including an IE type IGBT has a GGEE type cell structure. The GGEE type cell structure includes a trench gate TG, a trench emitter TE, a p-type base region BL, an n-type emitter region EL, a p-type floating region FL, and an n-type hole barrier region HBL on the first main surface US of the semiconductor substrate SUB. has. The IE type IGBT 100 further includes an n-type drift region DL disposed under the n-type hole barrier region HBL, an n-type field stop layer FSL disposed under the n-type drift region DL, and an n-type field stop layer. It has a p-type collector layer CL disposed below the FSL and a collector electrode CE disposed below the p-type collector layer CL. An emitter electrode EE is electrically connected to the p-type base region BL and the n-type emitter region EL via a contact member or plug in a connection hole CH1 formed in the interlayer insulating film IL. Note that BC is a highly doped p-type base contact layer formed on the surface of the p-type base region BL. Further, the emitter electrode EE is electrically connected to the p-type base region BL formed between the trench emitter TE and the trench emitter TE via a contact member or plug in the connection hole CH2 formed in the interlayer insulating film IL. It is connected to the. An insulating film FPF is formed above the emitter electrode EE. The insulating film FPF is a final passivation film made of, for example, an organic insulating film containing polyimide as a main component. Note that when p-type is the first conductivity type, n-type can be said to be the second conductivity type opposite to the first conductivity type.

In the p-type floating region FL, a crystal defect region CDR in which crystal defects are locally formed is formed, which is indicated by a square dotted line. When the depth of the p-type floating region FL is, for example, about 6 μm, the crystal defect region CDR is provided in a region from 0 to 1 μm in the depth direction from the surface of the p-type floating region FL. Here, the crystal defect density within a depth range of 0 to 1 μm from the surface is, for example, about 1×10 ³ defects/cm ² . A region where the p-type floating region FL is depleted when a reverse bias is applied between the emitter and the drain during turn-off of the IGBT, that is, a p-type floating region with a depth of 3 μm to 6 μm from the first main surface US. The crystal defect density in the region FL is approximately the same as the crystal defect density in the semiconductor substrate SUB.

The IE type IGBT 100 includes a parasitic P channel type MOSFET that uses the p type floating region FL as a source region, the p type base region BL as a drain region, and the trench emitter TE as a gate electrode. The n-type hole barrier region HBL constitutes a channel formation region of a parasitic P-channel MOSFET. The collector electrode CE acts as a back gate of the parasitic P-channel MOSFET via the p-type collector layer CL, the n-type field stop layer FSL, the n-type drift region DL, and the n-type hole barrier region HBL. This parasitic P-channel MOSFET allows holes accumulated in the p-type floating region FL during IGBT switching to be discharged to the emitter electrode EE via a short path, thereby shortening the switching time. Further, since potential fluctuations in the p-type floating region FL are suppressed, the potential of the trench gate TG is stabilized, and switching loss during switching can be suppressed.

The configuration of the IE type IGBT 100 will be described below.

First, the semiconductor substrate SUB is formed of single crystal silicon into which n-type impurities such as phosphorus (P) are introduced. The impurity concentration of the semiconductor substrate SUB is directly the impurity concentration of the drift region DL.

The n-type hole barrier region HBL is formed by introducing n-type impurities from the surface US side of the semiconductor substrate SUB. The introduction of this n-type impurity can be exemplified by using phosphorus as the ion species, for example. Further, the n-type hole barrier region HBL prevents holes from reaching the p-type base region BL and being discharged during operation of the IE-type IGBT, and functions as a barrier against holes. The impurity concentration of the n-type hole barrier region HBL is set higher than the n-type impurity concentration in the n-type drift region DL and lower than the n-type impurity concentration of the n-type emitter region EL, which will be described later.

The p-type floating region FL is formed by introducing p-type impurities from the surface US side of the semiconductor substrate SUB. As shown in FIG. 4, the p-type floating region FL is manufactured using a multi-stage ion implantation method using a first ion implantation step S1, a second ion implantation step S2, and an annealing step S3. be able to. Ion implantation in the first ion implantation step S1 and the second ion implantation step S2 is performed on the same region (desired region) of the surface US of the semiconductor substrate SUB.

In the first ion implantation step S1, for example, the ion species (first conductivity type ion species) is boron (B), and the dose is 6.0×10 ¹² /cm ² to 1.25×10 ¹³ /cm ^{2 .} The implantation energy is 300 keV to 1.25 MeV.

In the second ion implantation step S2, for example, the ion species is boron (B), the dose is 1.0×10 ¹³ /cm ² to 2.75×10 ¹³ /cm ² , and the implantation energy is 300 keV to 1.0 keV. The voltage is set at 25 MeV.

Then, an annealing step S3 is performed after the first ion implantation step S1 and the second ion implantation step S2. In the annealing step S3, heat treatment is performed at, for example, 900° C. for about 30 seconds. As a result, the ions implanted in the first ion implantation step S1 and the second ion implantation step S2 are activated by heat treatment, and the p-type floating region FL in which the crystal defect region CDR described above is formed is formed. . Further, since the annealing process S3 can be performed only once, it is possible to reduce costs by reducing the annealing process.

Note that if the thickness of the p-type floating region FL is insufficient, the ion-implanted impurity (boron) may be diffused by additional heat treatment. Alternatively, the heat treatment step for diffusing the ion-implanted impurity (boron) may also serve as the annealing step S3.

The trench gate TG and the trench emitter TE are composed of an n-type impurity-doped polycrystalline silicon layer formed to be embedded in a trench formed by etching on the first main surface of the semiconductor substrate SUB. The trench gate TG and the trench emitter TE are electrically isolated from the semiconductor layer formed on the semiconductor substrate SUB by the gate insulating film GI. The thickness of the gate insulating film GI is, for example, 0.10 to 0.12 μm.

A suitable value for the depth of the trench is, for example, 3.0 to 3.5 μm, and a suitable value for the width of the trench is, for example, 0.5 to 1.0 μm. Further, the trench is formed in a stripe shape when viewed from above, and the trench gate TG and the trench emitter TE are arranged to face each other so as to sandwich the hole barrier region HBL. A floating region FL is arranged between the trench gate TG and the trench emitter TE. A suitable value for the thickness (or depth) of the p-type floating region FL is, for example, 5 to 6 μm, and the bottom surface of the p-type floating region FL is formed to cover the bottom surface of the trench. This reduces electric field concentration at the bottom of the trench gate TG.

The p-type base region BL is formed by introducing p-type impurities from the surface US side of the semiconductor substrate SUB. This p-type impurity is, for example, boron. Since the acceleration energy for ion implantation into the p-type base region BL is set low, ion implantation damage is small and crystal defects are unlikely to remain.

The p-type base region BL is formed on the n-type hole barrier region HBL so as to be in contact with one side surface of the trench gate TG via the gate insulating film GI. Further, the p-type base region BL is formed on the n-type hole barrier region HBL so as to be in contact with one side surface of the trench emitter TE via the gate insulating film GI.

Further, the ion implantation for forming the p-type base region BL may be performed not only on the n-type hole barrier region HBL but also on the p-type floating region FL. However, in this case, the concentration on the surface of the p-type floating region FL only increases, and there is no change in the function as the p-type floating region FL. Compared to the case where ions are implanted only onto the n-type hole barrier region HBL, there is an advantage that a fine mask pattern is not required.

The n-type emitter region EL is formed by introducing n-type impurities into the surface of the p-type base region BL. This p-type impurity is, for example, arsenic.

The interlayer insulating film IL is formed on the first main surface of the semiconductor substrate SUB so as to cover the n-type emitter region EL, the p-type base region BL, and the p-type floating region FL. The interlayer insulating film IL is, for example, a silicon oxide film or a PSG (Phosphorus Silicate Glass) film formed by a CVD method or the like. The thickness of the interlayer insulating film IL is, for example, about 0.6 μm. Materials for the interlayer insulating film IL include silicon oxide film, PSG film, BPSG (Boron Phosphorus Silicate Glass) film, NSG (Non-doped Silicate Glass) film, SOG (Spin On Glass) film, or a combination thereof. Suitable examples include membranes and the like.

Connection holes CH1 and CH2 are formed in the interlayer insulating film IL. The contact holes CH1 and CH2 can be formed by anisotropic dry etching. By anisotropic dry etching, a part of the first main surface of the semiconductor substrate SUB exposed from the connection holes CH1 and CH2 is etched, forming connection holes CH1 and CH2 that reach partway through the p-type base region BL and the trench emitter TE. be done.

The p-type base contact layer BC can be formed by introducing p-type impurities into the surface of the semiconductor substrate SUB through the connection holes CH1 and CH2. This p-type impurity is, for example, boron.

The emitter electrode EE is formed on the interlayer insulating film IL including the insides of the connection holes CH1 and CH2. The emitter electrode EE can be formed of an aluminum film by sputtering. Alternatively, the emitter electrode EE may be formed as a laminated film, for example, by the following procedure. First, a titanium-tungsten film is formed as a barrier metal film on the first main surface of the semiconductor substrate SUB by, for example, a sputtering method. The thickness of the titanium tungsten film is, for example, about 0.2 μm.

Next, after silicide annealing is performed, an aluminum-based metal film is formed over the entire surface of the titanium-tungsten film by, for example, a sputtering method so as to fill the insides of the connection holes CH1 and CH2. The aluminum-based metal film is composed of, for example, an aluminum film doped with several percent silicon and/or copper, and has a thickness of about 5 μm. The aluminum-based metal film buried inside the connection holes CH1 and CH2 becomes a contact member or a plug.

Next, by processing into a predetermined pattern by dry etching using the resist pattern as a mask, an emitter electrode EE made of a laminated film of a titanium-tungsten film and an aluminum-based metal film can be formed.

Emitter electrode EE is electrically connected to each of n-type emitter region EL, p-type base contact layer BC, and trench emitter TE.

Next, a final passivation film FPF is formed on the emitter electrode EE and the interlayer insulating film IL. The final passivation film FPF is, for example, an organic film containing polyimide as a main component, and has a thickness of, for example, about 10 μm. For the final passivation film FPF, this organic film is applied over the entire surface of the emitter electrode EE and the interlayer insulating film IL, and the emitter pad EP portion and the gate pad GP portion are opened using normal lithography technology. formed by

After the final passivation film FPF is formed, the semiconductor substrate SUB is thinned by performing a back grinding process on the second main surface (back surface) BS opposite to the first main surface of the semiconductor substrate SUB. In the back grinding process, the semiconductor substrate SUB having a thickness of about 800 μm is reduced to, for example, 30 μm to 200 μm.

Next, an n-type field stop layer FSL is formed by selectively introducing an n-type impurity into the second main surface (back surface) BS of the thinned semiconductor substrate SUB by ion implantation. This n-type impurity is, for example, phosphorus.

Next, a p-type collector layer CL is formed by introducing p-type impurities into the second main surface (back surface) BS of the thinned semiconductor substrate SUB by ion implantation. This p-type impurity is, for example, boron. Note that an N-type impurity and a P-type impurity are sequentially introduced, and laser annealing is performed on the second main surface (back surface) BS of the semiconductor substrate SUB to form an n-type field stop layer FSL and a p-type collector layer. A CL may also be formed.

Next, a collector electrode CE is formed on the surface of the p-type collector layer CL by, for example, a sputtering method. The collector electrode CE is made of, for example, a laminated film of an aluminum (Al) layer, a titanium (Ti) layer, a nickel (Ni) layer, a gold (Au) layer, etc. in order from the second main surface (back surface) BS of the semiconductor substrate SUB. can be formed. The collector potential electrode CE may be a metal film such as a titanium nitride film formed by sputtering or CVD.

By the above manufacturing process, the IE type IGBT shown in FIG. 2 can be manufactured. Here, in order to more specifically illustrate the device structure, an example of the main dimensions of each part of the device will be shown.

The trench pitch interval of the pair of trench gates TG is 1.8 μm to 2.0 μm, the trench pitch interval of the pair of trench emitters TE is 0.9 μm to 1.1 μm, and the width WFL of the p-type floating region FL (see FIG. 6). ) is 5.5 to 7 μm, and the depth of the p-type floating region FL is 4.5 to 6 μm.

FIG. 3 is a diagram illustrating a cell formation region, and is a schematic enlarged plan view of region RR in FIG. FIG. 2 is a schematic cross-sectional view taken along line BB in FIG.

Cell formation region RR includes an active cell region RCa, an inactive region Ria, and a hole collector cell region RCc. The active cell region RCa, the inactive region Ria, and the hole collector cell region RCc are each provided so as to extend in a stripe shape along the first direction Y. Furthermore, the active cell region RCa, the inactive region Ria, the hole collector cell region RCc, and the inactive region Ria are set as one layout unit in this order, and are repeatedly arranged in a second direction X perpendicular to the first direction Y. has been done.

Active cells Ca are formed in the active cell region RCa. In FIG. 3, a pair of trench gates TG formed in a stripe shape in the first direction Y and an n-type emitter region EL provided between the pair of trench gates TG are schematically depicted as active cells Ca. It is. A hole collector cell Cc is formed in the hole collector cell region RCc. As explained in FIG. 2, in the hole collector cell Cc, the p-type floating region FL is used as a source region, the p-type base region BL is used as a drain region, the n-type hole barrier region HBL is used as a channel formation region, and the trench emitter TE is used as a gate electrode. This is a parasitic P-channel MOSFET. In FIG. 3, a pair of trench emitters TE formed in a stripe shape in the first direction Y and a connecting trench emitter TEa connecting between the pair of trench emitters TE are schematically depicted as a hole collector cell Cc. It is. In FIG. 3, a p-type floating region FL is schematically drawn in the inactive region Ria. Note that when the connection hole CH2 is formed so as to be in contact with both of the pair of trench emitters TE as shown in FIG. 2, the connection trench emitter TEa can be made unnecessary. When the connection hole CH2 is formed so as to be in contact with only one of the pair of trench emitters TE, it is preferable to provide a connection trench emitter TEa. Here, the trench gate TG and the trench emitter TE extend in the first direction Y in a plan view, and are adjacent to each other in a second direction X that is orthogonal to (or intersects with) the first direction Y in a plan view. It can be considered that there is.

(Example 2 of configuration of semiconductor device including IE type IGBT: GE type structure)
FIG. 5 is a cross-sectional view of a main part according to another example of the structure of the cell region RR shown in FIG. 1. Although FIG. 2 shows a cell structure of a GGEE type structure, FIG. 5 is a cross-sectional view illustrating a cell structure of a GE type structure (or EG type structure or GE-S type structure).

The cell structure of the GE type structure shown in FIG. 5 is different from the cell structure of the GGEE type structure shown in FIG. This is the point where it is formed. The emitter electrode EE is connected between the pair of trench emitters TE and trench gates TG via a contact member or plug in a contact hole CH3 formed in the interlayer insulating film IL, and the n-type emitter regions EL, p It is electrically connected to each of the mold base contact layer BC and the trench emitter TE. The other configurations of the cell structure of the GE type structure in FIG. 5 are the same as the other configurations of the cell structure of the GGEE type structure in FIG. 2, and redundant explanation will be omitted. The p-type floating region FL and crystal defect region CDR in FIGS. 2 and 5 are formed by the same manufacturing method and have the same structure.

(Configuration example 3 of semiconductor device including IE type IGBT: GG type structure)
FIG. 22 is a cross-sectional view of a main part of another example of the structure of the cell region RR shown in FIG. 1. FIG. 22 is a cross-sectional view illustrating the cell structure of the GG type structure. The cell structure of the GG type structure in FIG. 22 is different from the cell structure of the GGEE type structure in FIG. It has the same structure as the pair of trench gates TG (a p-type base region BL, an n-type emitter region EL, a p-type base contact layer BC, and a contact hole CH1 are provided). The other configurations of the cell structure of the GG type structure in FIG. 22 are the same as the other configurations of the cell structure of the GGEE type structure in FIG. 2, and redundant explanation will be omitted. The p-type floating region FL and crystal defect region CDR in FIGS. 2, 5, and 22 are formed by the same manufacturing method and have the same configuration.

(Example of configuration of crystal defect region CDR)
FIG. 6 is a diagram illustrating the structure of the crystal defect region CDR in FIGS. 2 and 5. FIG. 6 shows a cross-sectional view between the trench gate TG and the trench emitter TE in the cell structure of the GGEE type structure in FIG. 2 or the cell structure of the GE type structure in FIG. A graph of the crystal defect density in the depth direction and the lateral direction of the crystal defect region CDR is shown. Here, a case will be exemplified in which the depth of the p-type floating region FL is, for example, about 6 μm. A crystal defect region CDR in which crystal defects are selectively formed is provided in a region from 0 to 1 μm in the depth direction from the surface of the p-type floating region FL.

In the description of the depth direction (dp) of the crystal defect region CDR in FIG. 6, for example, depth 0 indicates the upper end of the p-type floating region FL or the upper end of the crystal defect region CDR, and depth d1 indicates the crystal defect region The depth d2 indicates the lower end of the CDR, the depth d2 indicates the upper end (or upper part) of the depletion layer DEP in the off state (at rated voltage, or more preferably in the avalanche state), and the depth d3 indicates the upper end of the p-type floating region FL. The lower end shall be indicated. The region below the depth d3 is the drift region DL.

The depletion layer DEP expands as the voltage applied to the collector increases, but even if it does not reach the avalanche state, if the crystal defect region CDR does not enter the depletion layer DEP when the voltage is applied to the rated voltage, it will not be effective in terms of leakage. No problem.

The bottom of the p-type floating region FL is located below the bottoms of the trench gate and trench emitter. The p-type floating region FL has a crystal defect region CDR on the surface side of the p-type floating region FL. The crystal defect region CDR is provided on the surface side of the p-type floating region FL between the surface (0) of the p-type floating region FL and the upper end (d2) of the depletion layer DEP. Further, the crystal defect region CDR is formed between the surface of the p-type floating region FL and the upper part of the depletion layer DEP, and in a region where the depletion layer DEP is not formed. By configuring the crystal defect region CDR to exist in a region not included in the depletion layer DEP even when off, it is possible to suppress deterioration of electrical characteristics such as an increase in leakage current when off.

The crystal defect density CDD1 in the depth direction (dp) of the crystal defect region CDR has the following characteristics.
(1) The crystal defect density is relatively high in the upper part of the p-type floating region FL, for example, within the range of 0 to 1 μm at the depth d1 (for example, 1 μm) from the surface (that is, within the range of 0 to 1 μm), There is a portion where the crystal defect density is maximum), and the crystal defect density is reduced in the region of the p-type floating region FL deeper than the depth d1 (1 μm).
(2) The density of crystal defects within a depth range of 0 to 1 μm from the surface of the p-type floating region FL is, for example, 1×10 ³ pieces/cm ² or less.
(3) In the p-type floating region FL, a region with a depth that becomes a depletion layer DEP when a gate voltage is applied at turn-off of the IGBT (during avalanche), for example, a range of about d2 (for example, 3 μm) to d3 (for example, 6 μm) The region with the depth is said to have a relatively low defect density comparable to the defect density of the original semiconductor crystal substrate.

The crystal defect density CDD2 in the lateral direction (wd) of the crystal defect region CDR has the following characteristics.
(4) Crystal defects are formed only within the formation width WFL of the p-type floating region FL (that is, the width in the lateral direction of the formation region of the crystal defect region CDR).
(5) The crystal defect region CDR is formed so as not to contact the trench (TE, TG) or penetrate the gate insulating film GI. That is, it is preferable that no crystal defects exist on the side surfaces of the trenches (TE, TG) or the gate insulating film GI. With this configuration, deterioration of electrical characteristics such as a decrease in reliability of the gate insulating film GI can be suppressed. As the number of crystal defects increases, the possibility that the crystal defects penetrate through the gate insulating film GI increases, so it is preferable to suppress the crystal defect density to 1×10 ³ (pieces/cm ² ) or less.
(6) The crystal defect region CDR is provided apart from the trench gate TG and trench emitter TE without contacting them. The distance w1 between the trench (TE, TG) and the crystal defect region CDR is, for example, 0.1 μm to 0.3 μm, more preferably about 0.2 μm.

(Explanation of improvement in switching characteristics: Effect of crystal defect region CDR)
FIG. 7 is a diagram illustrating switching characteristics. FIG. 7A shows the state of holes (holes h) at the time when gate bias application to the gate electrode of the IGBT is started from the off state in the case where the crystal defect region CDR is not formed. As the gate bias is applied, the potential in the p-type floating region FL increases and holes h are induced, but since a high voltage is applied to the collector, the p-type floating region FL is transformed into a source region and a p-type base. Since the parasitic P-channel MOSFET with the region BL as the drain region and the trench emitter TE as the gate electrode is in an off state due to the substrate bias effect, the induced holes h cannot escape and accumulate in the p-type floating region FL. do.

(B1) in FIG. 7 shows the state of holes (holes h) at the start of gate bias application to the gate electrode of the IGBT in the case where the crystal defect region CDR is formed. Some of it is captured by crystal defects (recombination centers).

(B2) in FIG. 7 shows the state of holes (holes h) after the turn-off of the IGBT progresses and the collector voltage decreases in the case where the crystal defect region CDR is formed. The parasitic P-channel MOSFET that uses the p-type floating region FL as a source region, the p-type base region BL as a drain region, and the trench emitter TE as a gate electrode begins to operate, and holes h begin to be discharged.

That is, immediately after applying the gate bias (before turn-off progresses and the collector voltage decreases), holes h cannot be discharged from the parasitic P-channel MOSFET, and holes h accumulate in the p-type floating region FL. Crystal defects within the crystal defect region CDR are used as a field for recombining the holes h. Thereafter, the bias applied to the NW (n-type hole barrier region HBL) gradually weakens, and the parasitic P-channel MOSFET begins to operate. Therefore, holes h are discharged from the vicinity of the trench emitter TE to the emitter electrode EE side.

Note that the cell structure of the GG type structure in FIG. 22 does not have a parasitic P-channel MOSFET, so the holes h cannot be actively discharged to the emitter electrode EE side, and the holes h are discharged by diffusion. However, since this structure also utilizes the crystal defects in the crystal defect region CDR, it is possible to reduce the influence of the accumulation of holes h. Although the GG type structure shown in FIG. 22 has a lower switching speed than the GGEE structure shown in FIG. Since holes h can be accumulated efficiently, there is an advantage that V _{CE (sat)} can be lowered. Furthermore, since the density of the trench gate TG is high, there is an advantage that the saturation current in the on state can be increased.

The ease with which holes (h) accumulated in the p-type floating region FL between the trench gate TG and the trench emitter TE can be discharged affects the switching time of the IGBT. In order to further improve the switching characteristics, it is necessary to suppress the hole accumulation effect in the p-type floating region FL. The hole accumulation effect is suppressed by utilizing crystal defects within the crystal defect region CDR. Thereby, it is possible to improve the ease of discharging the holes (h) accumulated in the p-type floating region FL. As a result, the turn-on characteristics are improved, and the switching speed of the IGBT can be increased.

On the other hand, in the on state, holes are accumulated in the drift region. At this time, if there are more recombination centers than necessary in the p-type floating region FL, the holes to be accumulated in the drift region are Since the p-type floating region FL is diffused according to the gradient and recombined at the recombination center, the hole accumulation effect in the drift region is reduced, and the electric charge such as an increase in V _{CE (sat)} is lead to a decline in physical characteristics. From this point of view as well, it is preferable to suppress the density of crystal defects in the p-type floating region FL to about 1×10 ³ (pieces/cm ² ) at most.

(Explanation of crystal defect evaluation results)
FIG. 8 is a diagram illustrating the evaluation results of crystal defects according to the embodiment. Specifically, FIG. 8 shows the evaluation results of crystal defects in the depth direction of the p-type floating region FL. The p-type floating region FL is formed by the manufacturing method described in FIG. 4. Here, as a method for evaluating crystal defects, "Japanese Industrial Standards (JIS H 0609)" was used. "JIS H 0609 uses JIS-G solution as an etching solution. JIS-G solution is made up of 126 ml of water, 254 ml of 70% nitric acid, and 20 ml of 50% hydrofluoric acid. The etching rate is about 1 μm/min.

In the crystal defect evaluation result Evr shown in FIG. 8, the p-type floating region FL is etched using JIS-G solution to examine crystal defects. The approximate etching amount (etching depth: depth ds from the semiconductor substrate surface) is calculated from the Si etching rate by the JIS-G solution and the cumulative etching time Tte. In the crystal defect evaluation result Evr, if a crystal defect exists, it is observed as a diagonal black streak. The observed black streaks are the total number of crystal defects existing from the surface to the etching depth, so by repeating etching and observation, the depth at which crystal defects are occurring can be estimated.

In the example of the evaluation result Evr in FIG. 8, the cumulative etching time Tte is 1 min (depth ds from the semiconductor substrate surface: about 1 μm), 2 min (depth ds from the semiconductor substrate surface: about 2 μm), 3 min (semiconductor substrate The following crystal defect evaluation results Evr are shown for three points (depth of ds from the surface: approximately 3 μm). (1) The evaluation result Evr when the cumulative etching time Tte is 1 min indicates that a slight crystal defect is formed within about 1 μm from the surface. (2) The evaluation result Evr when the cumulative etching time Tte is 2 min indicates that no new crystal defects are formed between about 1 μm and 2 μm. (3) The evaluation result Evr when the cumulative etching time Tte is 3 min indicates that no new crystal defects are formed between 2 μm and 3 μm.

After 3 min, no new crystal defects were observed, suggesting that crystal defects were selectively formed only in the shallow region of the p-type floating region FL. By calculation based on the evaluation results when the cumulative etching time was 1 min, it was confirmed that the crystal defect density (CCD1) was 1×10 ² to 1×10 ³ (pieces/cm ² ).
In other words, in the p-type floating region FL formed by the manufacturing method explained in FIG. It was found that it is possible to form Thereby, the effects explained above can be obtained.

(Method for manufacturing a semiconductor device including IE type IGBT)
Next, a method for manufacturing a semiconductor device including an IE type IGBT will be described with reference to FIGS. 9 to 21. Here, as an example, a method for manufacturing an IE type IGBT having the GGEE type cell structure described in FIG. 2 will be described.

As shown in FIG. 9, an n-type drift region DL is formed in the semiconductor substrate SUB. The drift region DL is formed by preparing a semiconductor substrate SUB into which n-type impurities have been introduced in advance and using the n-type semiconductor substrate SUB as the n-type drift region DL, or by using a p-type semiconductor substrate. A SUB is prepared, and an n-type drift region DL is formed on the p-type semiconductor substrate SUB by an epitaxial method. Note that in this embodiment, the drift region DL may be described as a semiconductor substrate SUB.

Next, as shown in FIG. 10, an n-type hole barrier region HBL is formed on the surface of the drift region DL using a photolithography method and an ion implantation method. Hole barrier region HBL has a higher impurity concentration than drift region DL. The impurity for forming the hole barrier region HBL is, for example, phosphorus (P), and this ion implantation may be performed in multiple steps.

Next, as shown in FIG. 11, boron (B) ions are implanted into the surface of the drift region DL using photolithography and ion implantation to form a p-type floating region FL. A mask MK1 is selectively formed in a desired region of the surface US of the semiconductor substrate SUB. The mask MK1 is selectively formed on the surface US of the semiconductor substrate SUB so as to cover the formation region of the hole barrier region HBL and both sides thereof, and so as to perform ion implantation into the formation region of the p-type floating region FL. The ion implantation for forming the p-type floating region FL is performed by introducing boron (B) into the inside of the drift region DL from the surface US side of the semiconductor substrate SUB in two separate steps using the first ion implantation step S1 and the second ion implantation step S2 described in FIG. 4. Here, the first ion implantation step S1 is performed, for example, with boron (B) as the ion species, a dose amount of 6.0×10 ¹² /cm ² to 1.25×10 ¹³ /cm ² , and an implantation energy of 300 keV to 1.25 MeV. The second ion implantation step S2 is performed, for example, with boron (B) as the ion species, a dose amount of 1.0×10 ¹³ /cm ² to 2.75×10 ¹³ /cm ² , and an implantation energy of 300 keV to 1.25 MeV.

Next, as shown in FIG. 12, the annealing process described in FIG. 4 is performed to form a p-type floating region FL. Here, a crystal defect region CDR is formed on the surface US side of the p-type floating region FL.

Note that if the thickness of the p-type floating region FL (depth at which the bottom exists) is insufficient, boron may be diffused by additional heat treatment after (not limited to immediately after). Further, in this step, the above-mentioned annealing may not be performed, and the heat treatment for diffusing boron may also serve as the above-mentioned annealing.

Next, as shown in FIG. 13, an insulating film such as a silicon oxide film is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method, and an insulating film is formed using a photolithography method and dry etching. A mask MK2 is formed by patterning the film. The mask MK2 is used as a mask for forming the first trench T1 (TG trench) and the second trench T2 (TE trench) in the semiconductor substrate SUB. It is selectively formed on the surface of the semiconductor substrate SUB so that the formation region of the two trenches T2 is exposed.

Next, as shown in FIG. 14, a trench forming step is performed. By etching the semiconductor substrate SUB using the patterned mask MK2 as a hard mask, a first trench T1 and a second trench T2 are formed in the semiconductor substrate SUB. Thereafter, the mask MK2 is removed by wet etching or the like.

Here, if necessary, heat treatment may be performed to diffuse boron in order to set the thickness of the p-type floating region FL to a desired value. By performing the diffusion after the trench formation step, the diffusion step can be used even if the distance between the pair of trenches is narrow and it is difficult to form the p-type floating region FL in the region with the distance.

Note that the heat treatment for diffusing boron does not necessarily have to follow this process flow, and the above advantages can be obtained if the heat treatment is performed after the trench formation process. For example, the heat treatment may be performed after forming the conductive film FG inside the first trench T1 and the second trench T2, or may be performed separately in both steps. By doing this, if there are other heat treatment steps such as sacrificial oxidation to remove damage in the trench formation process or heat treatment to incorporate a gate protection diode, which is not specifically described in this specification, Since it can also serve as both functions, the number of steps can be reduced.

Next, as shown in FIG. 15, by performing thermal oxidation treatment on the semiconductor substrate SUB, for example, the inner wall of the trench T1, the inner wall of the trench T2, the upper surface of the floating region FL, and the upper surface of the hole barrier region HBL is An insulating film made of a silicon oxide film is formed. The insulating film formed on the inner wall of the trench T1 and the inner wall of the trench T2 is a gate insulating film GI. The thickness of the gate insulating film GI is, for example, 100 nm.

Next, as shown in FIG. 16, a conductive film FG made of, for example, a polycrystalline silicon film doped with n-type impurities is formed by, for example, a CVD method so as to fill the inside of the trench T1 and the inside of the trench T2. do. The conductive film FG inside the trench T1 becomes a gate potential electrode (also referred to as a first electrode) of the trench gate TG. The conductive film FG inside the trench T2 becomes an emitter potential electrode (also referred to as a second electrode) of the trench emitter TE.
Next, as shown in FIG. 17, a step of forming a base region (also referred to as channel region) BL and an emitter region (also referred to as source region) EL is performed. First, a step of forming the base region BL is performed. After removing or thinning the gate insulating film GI exposed on the surface of the semiconductor substrate SUB by, for example, dry etching or wet etching as appropriate, the floating region FL and the hole barrier are removed by using photolithography and ion implantation. A p-type base region BL is formed on the surface of each region HBL. Base region BL is an impurity region having a higher impurity concentration than floating region FL. The impurity for forming the base region BL is, for example, boron (B).

Next, a step of forming the emitter region EL is performed. By using a photolithography method and an ion implantation method, an n-type emitter region EL is formed on the surface of the base region BL of the active cell region. Emitter region EL is an impurity region having a higher impurity concentration than hole barrier region HBL. At this time, the emitter region EL is not formed in the base region BL of the hole collector cell region. The impurity for forming the emitter region EL is, for example, arsenic (As).

Next, as shown in FIG. 18, a step of forming an interlayer insulating film IL is performed. First, an interlayer insulating film IL such as a silicon oxide film is formed by, for example, a CVD method over the insulating film on the upper surface of the floating region FL, the insulating film on the upper surface of the hole barrier region HBL, and the trench gate TG and trench emitter TE. Form.

Next, as shown in FIG. 19, a step of forming a contact hole (connection hole) CH1, a contact hole (connection hole) CH2, and a base contact layer BC is performed.

By using a photolithography method and a dry etching process (for example, anisotropic dry etching), a contact hole CH1 is formed in the active cell region, penetrating the interlayer insulating film IL and the emitter region EL, and reaching the base region BL. do. In addition, in the hole collector cell region, it is retreated from the first main surface US of the semiconductor substrate toward the second main surface (back surface) BS so as to penetrate the interlayer insulating film IL and straddle the trench emitter TE and base region BL. A contact hole CH2 including a recess is formed.

Next, a p-type base contact layer BC is formed in the base region BL under each of the contact hole CH1 and the contact hole CH2 by using a photolithography method and an ion implantation method. Base contact layer BC is an impurity region having a higher impurity concentration than base region BL. Furthermore, the base contact layer BC in the active cell region is formed so as not to be in contact with the n-type emitter region EL. The impurity for forming the base contact layer BC is, for example, boron, and then heat treatment is performed to activate each impurity region. Note that, if necessary, after some or all of the previous ion implantation steps (not limited to immediately after), heat treatment will be performed to activate each impurity region and diffuse it to a predetermined depth. Good too.

Next, as shown in FIG. 20, a step of forming an emitter potential electrode EE and a final passivation film FPF is performed.

First, for example, an aluminum film is formed on the insulating film IL by, for example, a sputtering method so as to fill the contact hole CH1 and the contact hole CH2. The aluminum films filled in the respective contact holes CH1 and CH2 serve as contact members. Thereafter, this aluminum film is patterned using a photolithography method and a dry etching process, thereby forming an emitter potential electrode EE. At the same time, the gate potential electrode GE shown in FIG. 1 is also formed by patterning the above aluminum film. Furthermore, before forming the aluminum film, a barrier metal film made of, for example, a titanium nitride film or a titanium tungsten film may be formed, and the aluminum film may be formed on this barrier metal film. That is, the emitter potential electrode EE and the like may be a laminated film of a barrier metal film and an aluminum film.

Next, a step of forming a final passivation film FPF is performed. A final passivation film FPF is formed above the emitter electrode EE and above the interlayer insulating film IL. The final passivation film FPF is, for example, an organic film containing polyimide as a main component, and has a thickness of, for example, about 10 μm. The final passivation film FPF is obtained by coating this organic film over the entire surface of the emitter electrode EE and the interlayer insulating film IL, and opening the emitter pad EP portion and the gate pad GP portion using normal lithography. formed by.

Next, as shown in FIG. 21, a field stop layer FSL, a collector layer CL, and a collector potential electrode CE are formed on the second main surface (back surface) BS side of the semiconductor substrate SUB.

First, if necessary, polishing is performed on the second main surface (back surface) of the semiconductor substrate SUB to reduce the thickness of the semiconductor substrate SUB. Next, ion implantation is performed from the second main surface (back surface) side of the semiconductor substrate SUB. This ion implantation forms an n-type field stop region FSL and a p-type collector region CL. Field stop region FSL is an impurity region having a higher impurity concentration than drift region DL. The impurity for forming the field stop region FSL is, for example, phosphorus (P). The impurity for forming the collector region PC is, for example, boron (B).

Next, an aluminum (Al) layer and a titanium layer are sequentially applied to the surface of the collector region CL exposed on the second main surface (back surface) side of the semiconductor substrate SUB by, for example, a sputtering method or a CVD method from the semiconductor substrate SUB side. A collector potential electrode CE is formed of a laminated film such as a (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer.

Above, the invention made by the present inventor has been specifically explained based on examples, but it goes without saying that the present invention is not limited to the above embodiments and examples, and can be modified in various ways. .

100 Semiconductor device CHP Semiconductor chip FL Floating region TG Trench gate TE Trench emitter CDR Crystal defect region CE Collector potential electrode CH1, CH2 Contact hole EE Emitter potential electrode EP Emitter pad GE Gate potential electrode GI Gate insulating film GP Gate pad IL Insulating film EL Emitter region HBL Hole barrier region FSL Field stop layer DL Drift region BL Base region CL Collector layer BC Base contact layer SUB Semiconductor substrate

Claims (19)

a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
a first trench and a second trench formed in the semiconductor substrate;
a first trench emitter embedded in the first trench via a first gate insulating film;
a first trench gate embedded in the second trench via a second gate insulating film;
a floating region formed in the semiconductor substrate between the first trench emitter and the first trench gate;
a crystal defect region containing crystal defects that is locally formed in the floating region at a position close to the first main surface;
In a cross-sectional view, the floating region is formed to cover a bottom surface of the first trench and a bottom surface of the second trench,
In the semiconductor device, the crystal defect region is provided apart from the first trench and the second trench in plan view and cross-sectional view. 2. The semiconductor device according to claim 1, wherein the crystal defect region is located within the floating region and is not in contact with the first trench and the second trench. In plan view, a third trench formed in the semiconductor substrate in a direction opposite to the direction in which the second trench of the first trench is formed;
a second trench emitter embedded in the third trench via a third gate insulating film;
a first base region formed on the first main surface between the first trench emitter and the second trench emitter;
an interlayer insulating film formed on the first main surface so as to cover the first trench emitter, the second trench emitter, the first trench gate, the first base region, and the crystal defect region;
a first contact member that penetrates the interlayer insulating film and reaches the first main surface;
an emitter electrode formed on the interlayer insulating film;
Furthermore,
The semiconductor device according to claim 1, wherein the first contact member connects with the first trench emitter, the second trench emitter, the first base region, and the emitter electrode. 2. The semiconductor device according to claim 1, wherein a location where the density of crystal defects in the crystal defect region is maximum is located near the first main surface. The semiconductor device according to claim 1, wherein the maximum density of the crystal defects is 10 ³ pieces/cm ² or less. The semiconductor device according to claim 1, wherein the first trench emitter and the first trench gate extend in a first direction and are arranged in a second direction intersecting the first direction in a plan view. . a contact hole penetrating the interlayer insulating film and reaching the first main surface;
In the contact hole, the contact hole is formed from the first main surface toward the second main surface, and is formed so as to straddle the first trench emitter, the first base region, and the second trench emitter in plan view. further equipped with a recess,
4. The semiconductor device according to claim 3, wherein the first contact member is embedded in the contact hole and the recess. a fourth trench formed in the semiconductor substrate in a direction opposite to the direction in which the first trench of the second trench is formed in a plan view;
a second trench gate embedded in the fourth trench via a fourth gate insulating film;
a second base region formed in the semiconductor substrate between the first trench gate and the second trench gate;
an emitter region formed on the first main surface on the second base region;
a second contact member that penetrates the interlayer insulating film and reaches the first main surface;
Furthermore,
4. The semiconductor device according to claim 3, wherein the second contact member connects with the second base region and the emitter region. a gate electrode formed on the first main surface and electrically connected to the first trench gate and the second trench gate;
a collector electrode formed on the second main surface;
Furthermore,
The emitter electrode is electrically connected to the first trench emitter, the second trench emitter, the first base region, the second base region, and the emitter region,
9. The semiconductor device according to claim 8, wherein the emitter electrode, the gate electrode, and the collector electrode constitute an IGBT. 10. The semiconductor device according to claim 9, wherein the crystal defect region is formed in a region where the floating region is not depleted when the IGBT is in an off state. (a) A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, a first hole barrier region of a second conductivity type and a second hole barrier region of the second conductivity type. a process of forming
(b) forming a floating region of a first conductivity type opposite to the second conductivity type in the semiconductor substrate between the first hole barrier region and the second hole barrier region;
(c) forming a crystal defect region containing crystal defects that is locally formed at a position close to the first main surface in the floating region;
(d) forming a first trench and a second trench formed to sandwich the floating region in plan view;
(e) After the step (d), forming a first gate insulating film and a second gate insulating film on the side surfaces of the first trench and the second trench, respectively;
(f) After the step (e), a first trench emitter is formed in the first trench through the first gate insulating film, and a first trench emitter is formed in the second trench through the second gate insulating film. a step of forming a trench gate;
In a cross-sectional view, the floating region is formed to cover the bottom surface of the first trench and the bottom surface of the second trench. In a plan view and a cross-sectional view, the crystal defect region is formed to cover the first trench and the bottom surface of the second trench. A method of manufacturing a semiconductor device, wherein the semiconductor device is provided apart from the second trench. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the crystal defect region is located within the floating region and is not in contact with the first trench and the second trench. (g) after the step (f), forming a first base region of the second conductivity type on the first main surface on the first hole barrier region;
(h) After the step (g), an interlayer insulating film is formed on the first main surface to cover the first trench emitter, the second trench emitter, the first trench gate, and the crystal defect region. a process of forming
(i) After the step (h), forming a first contact hole that penetrates the interlayer insulating film on the first base region and reaches the first main surface;
(j) forming a first contact member in the first contact hole after the step (i);
(k) after the step (j), forming an emitter electrode on the interlayer insulating film;
Furthermore,
In the step (d), a third trench is further formed to sandwich the first hole barrier region between the first trench and the first hole barrier region in a plan view,
In the step (e), a third gate insulating film is further formed on the side surface of the third trench,
In the step (f), a second trench emitter is further formed in the third trench via the third gate insulating film,
12. The method of manufacturing a semiconductor device according to claim 11, wherein the first contact member is connected to the first trench emitter, the first base region, the second trench emitter, and the emitter electrode. In the step (d), a fourth trench is further formed to sandwich the second hole barrier region with the second trench,
In the step (e), a fourth gate insulating film is further formed in the fourth trench,
In the step (f), a second trench gate is further formed in the fourth trench via the fourth gate insulating film,
In the step (g), further forming a second base region of the second conductivity type on the first main surface on the second hole barrier region,
In the step (i), further forming a second opening that penetrates the interlayer insulating film on the second base region and reaches the first main surface,
In the step (j), a second contact member is further formed in the second opening,
In the step (h), the interlayer insulating film is further formed on the first main surface so as to cover the second trench gate,
(l) After the step (g) and before the step (h), forming an emitter region of the first conductivity type on the first main surface on the second base region;
Furthermore,
14. The method of manufacturing a semiconductor device according to claim 13, wherein the second contact member is connected to the second base region, the emitter region, and the emitter electrode. The step (i) is
(i1) Formed in the first contact hole in the semiconductor substrate from the first main surface to the second main surface, in a plan view, the first trench emitter, the first base region, and the further comprising a recess formed to straddle the second trench emitter,
14. The method of manufacturing a semiconductor device according to claim 13, wherein the first contact member is embedded in the opening and the recess. The step (b) is an ion implantation process in which the ion species is boron, the dose is 6.0×10 ¹² /cm ² to 1.25×10 ¹³ /cm ² , and the implantation energy is 300 keV to 1.25 MeV. carried out by
The step (c) is
(c1) An ion implantation step in which the ion species is boron, the dose is 1.0×10 ¹³ /cm ² to 2.75×10 ¹³ /cm ² , and the implantation energy is 300 keV to 1.25 MeV;
12. The method for manufacturing a semiconductor device according to claim 11, further comprising: (c2) an annealing step at a processing temperature of 900°C. 12. The semiconductor according to claim 11, wherein a location where the density of crystal defects in the crystal defect region is maximum is located on the first main surface side in a direction from the first main surface to the second main surface. Method of manufacturing the device. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the density of crystal defects in the crystal defect region is 10 ^<3 >/cm ^<2> or less. In plan view, the first trench emitter, the second trench emitter, the first trench gate, and the second trench gate extend in a first direction and are lined up in a second direction intersecting the first direction. 14. The method for manufacturing a semiconductor device according to claim 13.

Images