JP2024027292A - Successive approximation type AD conversion circuit - Google Patents

Abstract

An object of the present invention is to reduce power consumption of a successive approximation type AD conversion circuit. SOLUTION: In a successive approximation type AD conversion circuit, a capacitor type DAC (10) having a capacitor array and a switch array accumulates charges in a capacitor array according to an analog input signal in a sampling period, and in a successive approximation period. A first comparison voltage (V1) based on the accumulated charge is generated on the first comparison wiring (WR1). In the successive approximation period, the control circuit (30) determines the value of the digital output signal while controlling the state of the switch array based on the comparison result signal (SCMP) between the first comparison voltage and the second comparison voltage (V2). A ground shorting switch (SG) is provided between the first comparison wiring and the ground. A first end of the reference change capacitor (CRC) is connected to the first comparison line. A reference change switch (SRC) selectively applies a power supply voltage or a ground voltage to the second end of the reference change capacitor. [Selection diagram] Figure 1

Description

The present disclosure relates to a successive approximation type AD conversion circuit.

A successive approximation type AD conversion circuit generally includes a DAC (digital-to-analog converter), a comparator, and a logic circuit (control circuit) that performs successive approximation. A capacitor type DAC (capacitive DAC) is often used as the DAC.

JP 2019-80292 Publication

When sampling an analog input signal using a capacitor type DAC, a reference voltage source is normally activated and the analog input signal is sampled with respect to the reference voltage. However, in this method, power consumption of the reference voltage source occurs during sampling, which is disadvantageous in reducing power consumption.

The present disclosure aims to provide a successive approximation type AD conversion circuit that contributes to reducing power consumption.

A successive approximation type AD conversion circuit according to the present disclosure is a successive approximation type AD conversion circuit configured to convert an analog input signal into a digital output signal, and includes a capacitor array and a switch array connected to the capacitor array, By connecting the wiring to which the analog input signal is applied during the sampling period to the capacitor array via the switch array, charges corresponding to the analog input signal are accumulated in each capacitor in the capacitor array, and after the sampling period A first comparison voltage based on the accumulated charge of the capacitor array is generated on the first comparison wiring while a predetermined power supply voltage or ground voltage is supplied to each capacitor in the capacitor array via the switch array during the successive approximation period. A capacitor-type DAC configured as shown in FIG. a comparator configured to generate a result signal; a control circuit configured to determine the value of the digital output signal while controlling the state of the switch array based on the comparison result signal during the successive approximation period; A ground shorting switch provided between a first comparison wiring and the ground, a reference changing capacitor having a first end connected to the first comparison wiring, and a second end of the reference changing capacitor, and a reference change switch configured to selectively apply the power supply voltage or the ground voltage.

According to the present disclosure, it is possible to provide a successive approximation type AD conversion circuit that contributes to reducing power consumption.

FIG. 1 is an overall configuration diagram of an AD converter according to a first embodiment of the present disclosure. FIG. 2 is a diagram showing the internal configuration and peripheral circuits of one switch in a switch array according to the first embodiment of the present disclosure. FIG. 3 is a diagram showing four states of one switch in a switch array according to the first embodiment of the present disclosure. FIG. 4 is an enlarged view of a reference change capacitor and a reference change switch according to the first embodiment of the present disclosure. FIG. 5 is a diagram showing three states of the reference change switch according to the first embodiment of the present disclosure. FIG. 6 is a diagram showing a relationship between capacitance values of a plurality of capacitors in a capacitor array according to the first embodiment of the present disclosure. FIG. 7 is a flowchart of AD conversion operation according to the first embodiment of the present disclosure. FIG. 8 is a diagram showing the state of the AD converter when a sampling operation is performed according to the first embodiment of the present disclosure. FIG. 9 is a flowchart of state transition operation according to the first embodiment of the present disclosure. FIG. 10 is a diagram showing states of an AD converter related to state transition operations according to the first embodiment of the present disclosure. FIG. 11 is a diagram illustrating a configuration example of a voltage generation circuit according to the first embodiment of the present disclosure. FIG. 12 is an explanatory diagram of the operation of the voltage generation circuit of FIG. 11 according to the first embodiment of the present disclosure. FIG. 13 is a diagram illustrating another configuration example of the voltage generation circuit according to the first embodiment of the present disclosure. FIG. 14 is a flowchart of successive approximation operation according to the first embodiment of the present disclosure. FIG. 15 is a configuration diagram of a register in a control circuit according to the first embodiment of the present disclosure. FIG. 16 is a diagram showing the state of the AD converter when a successive approximation operation is performed according to the first embodiment of the present disclosure. FIG. 17 is an explanatory diagram of the sampling operation of the reference AD converter. FIG. 18 is an explanatory diagram of the successive approximation operation of the reference AD converter. FIG. 19 is a configuration diagram of a DAC having one scaling capacitor according to the second embodiment of the present disclosure. FIG. 20 is a diagram showing the relationship between capacitance values of a plurality of capacitors in the capacitor array of FIG. 19. FIG. 21 is a configuration diagram of a DAC having two scaling capacitors according to the second embodiment of the present disclosure. FIG. 22 is a diagram showing the relationship between capacitance values of a plurality of capacitors in the capacitor array of FIG. 21. FIG. 23 is an overall configuration diagram of an AD converter according to a third embodiment of the present disclosure. FIG. 24 is a diagram showing the state of the AD converter when a sampling operation is performed according to the third embodiment of the present disclosure. FIG. 25 is a diagram showing the state of an AD converter related to state transition operation according to the third embodiment of the present disclosure.

Examples of embodiments of the present disclosure will be specifically described below with reference to the drawings. In each referenced figure, the same parts are given the same reference numerals, and overlapping explanations regarding the same parts will be omitted in principle. In this specification, for the purpose of simplifying the description, symbols or codes that refer to information, signals, physical quantities, functional units, circuits, elements, parts, etc. are indicated, and information, signals, or codes corresponding to the symbols or codes are indicated. Names of physical quantities, functional units, circuits, elements, parts, etc. may be omitted or abbreviated. For example, the comparison wiring referred to by "WR1" (see FIG. 1), which will be described later, may be written as comparison wiring WR1 or may be abbreviated as wiring WR1, but they all mean the same thing. Point. In this specification, a connection between a plurality of parts forming a circuit, such as any circuit element, wiring, or node, may be understood to refer to an electrical connection unless otherwise specified.

<<First embodiment>>
A first embodiment of the present disclosure will be described. FIG. 1 shows an overall configuration diagram of an AD converter 1 according to the first embodiment. The AD converter 1 is a successive approximation type A/D conversion circuit. An analog input signal Ain is input to the AD converter 1. The AD converter 1 performs an AD conversion operation on an analog input signal Ain. In the AD conversion operation for the analog input signal Ain, the analog input signal Ain is converted into a digital signal by binary search, and the obtained digital signal is output as the digital output signal Dout.

The digital output signal Dout is an N-bit digital signal. That is, the digital output signal Dout has a total of N bits from the first bit to the Nth bit. N is any integer greater than or equal to 2, for example, 8, 10, 12, 14, or 16. Here, it is assumed that the (i+1)th bit is the upper bit when viewed from the i-th bit. Therefore, among the first to Nth bits, the first bit is the least significant bit, and the Nth bit is the most significant bit. i represents any integer, and can be understood to represent a natural number equal to or less than N.

The AD converter 1 includes a DAC 10, a comparator 20, a control circuit 30, and a voltage generation circuit 40, as well as a switch _SG , a switch _SRC , and a capacitor _CRC . The wiring WR_Ain is an analog input wiring to which the analog input signal Ain is applied. The wiring WR_VDD is a power wiring to which a predetermined power supply voltage VDD is applied. Wiring WR_GND is connected to ground. The ground refers to a reference conductive portion having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductive part may be formed using a conductor such as metal. The wiring WR_GND is a ground wiring to which a ground voltage is applied. It may be understood that the wiring WR_GND itself is the ground. The ground voltage has the potential of ground and is therefore 0V. Power supply voltage VDD has a positive DC voltage value (for example, 5V). The analog input signal Ain has a voltage value greater than or equal to 0V and less than or equal to the power supply voltage VDD.

The DAC 10 is a capacitor type DAC (capacitor type digital-to-analog converter). A capacitor type DAC is also generally referred to as a capacitive DAC. The DAC 10 includes a capacitor array 11 and a switch array 12. The capacitor array 11 includes capacitors C[1] to C[N], and the switch array 12 includes switches S[1] to S[N].

Each of the capacitors C[1] to C[N] has a first end and a second end, and charges are accumulated between the first end and the second end. In the configuration of FIG. 1, the first ends of capacitors C[1] to C[N] are all connected to comparison wiring WR1. Switches S[1] to S[N] are provided corresponding to capacitors C[1] to C[N], respectively. That is, a switch S[i] is provided corresponding to the capacitor C[i]. Further, the capacitor C[i] corresponds to the i-th bit in the digital output signal Dout. The analog input signal Ain, the power supply voltage VDD, or the ground voltage can be applied to the second ends of the capacitors C[1] to C[N] via the switches S[1] to C[N]. The voltage applied to the comparison wiring WR1 is referred to as a comparison voltage V1.

FIG. 2 shows the connection relationship between the capacitor C[i], the switch S[i], and the wirings WR_Ain, WR_VDD, and WR_GND. The switches S[1] to S[N] each include a common terminal T _COM and switching terminals Ta, Tb, and Tc. Common terminals T _COM of switches S[1] to S[N] are connected to second ends of capacitors C[1] to C[N], respectively. That is, for example, the common terminal T _COM of the switch S[1] is connected to the second end of the capacitor C[1], and the common terminal T _COM of the switch S[2] is connected to the second end of the capacitor C[2]. Ru. The same applies to the switch S[3] and the like. Each switching terminal Ta of the switches S[1] to S[N] is connected to the wiring WR_Ain and receives the analog input signal Ain. Each switching terminal Tb of the switches S[1] to S[N] is connected to the wiring WR_VDD and receives the power supply voltage VDD. Each switching terminal Tc of the switches S[1] to S[N] is connected to the wiring WR_GND and receives the ground voltage.

Under the control of the control circuit 30, the common terminal T _COM of each of the switches S[1] to S[N] is selectively connected to one of the switching terminals Ta, Tb, and Tc. However, the common terminal T _COM of the switch S[i] may not be connected to any of the switching terminals Ta, Tb, and Tc.

Referring to FIG. 3, below, in any switch S[i], the states in which the common terminal T _COM is connected to the switching terminals Ta, Tb, and Tc are defined as a signal input state, a power supply connection state, and a ground connection state, respectively. The state in which the common terminal T _COM is not connected to any of the switching terminals Ta, Tb, and Tc is called an open state. In the signal input state, power supply connection state, and ground state of the switch S[i], the analog input signal Ain, the power supply voltage VDD, and the ground voltage are applied to the second end of the capacitor C[i], respectively. Note that FIG. 1 shows, as an example, that the switches S[1] to S[N] are all in the signal input state.

The switch _SG is a ground shorting switch, and is provided in series between the comparison wiring WR1 and the ground. That is, the first end of the switch _SG is connected to the comparison wiring WR1, and the second end of the switch _SG is connected to the ground (in other words, connected to the wiring WR_GND). The control circuit 30 controls the switch _SG to be on or off. Hereinafter, the on state and the off state may be simply expressed as on and off, respectively. When the switch S _G is on, the first end and the second end of the switch S _G are electrically connected, and the voltage of the comparison wiring WR1 (ie, the comparison voltage V1) is fixed to 0V. When the switch _SG is off, the first and second ends of the switch _SG are cut off (non-conductive), and the switch _SG does not affect the comparison voltage V1. Incidentally, FIG. 1 shows, as an example, how the switch _SG is turned off.

The capacitor _CRC is a capacitor for changing the reference, and the switch _SRC is a switch for changing the reference. A reference change circuit is configured by a capacitor C _RC and a switch S _RC . Although the details will become clear from the description below, after sampling the analog input signal Ain, the reference change circuit changes (shifts) the voltage that serves as the reference of the comparison voltage V1 to a high level side.

As shown in FIG. 4, the switch _SRC includes switching terminals _T1 and _T2 and a common terminal _T3 . A first end of the capacitor _CRC is connected to the comparison line WR1. The second end of the capacitor _CRC is connected to the common terminal _T3 of the switch _SRC . The switching terminal _T1 of the switch _SRC is connected to the wiring WR_VDD and receives the power supply voltage VDD. The switching terminal _T2 of the switch _SRC is connected to the wiring WR_GND and receives the ground voltage.

Under the control of the control circuit 30, the common terminal _T3 in the switch _SRC is selectively connected to the switching terminal _T1 or _T2 . However, in the switch _SRC , the common terminal _T3 may not be connected to either the switching terminals _T1 or _T2 .

Referring to FIG. 5, in the following, the states in which the common terminal T ₃ is connected to the switching terminals T ₁ and T ₂ in the switch S _RC will be referred to as the power supply connection state and the ground connection state, _respectively . A state in which the switching terminals T ₁ and T ₂ are not connected is called an open state. When the switch _SRC is in the power supply connection state and the ground state, the power supply voltage VDD and the ground voltage are applied to the second end of the capacitor _CRC , respectively. Note that FIG. 1 shows, as an example, how the switch _SRC is connected to the ground.

Each of the switches S[1] to [N], S _G and S _RC can be configured with any switching element such as a MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Switches S[1]-[N] and _SRC may be multiplexers. Regarding an arbitrary switch, when the control circuit 30 controls the switch to a certain focused state, it is synonymous with the control circuit 30 setting the state of the switch to the focused state.

Comparator 20 is connected to comparison wirings WR1 and WR2. As described above, the comparison voltage V1 is applied to the comparison wiring WR1. On the other hand, a comparison voltage V2 is applied to the comparison wiring WR2. The comparator 20 compares the comparison voltages V1 and V2, and generates and outputs a comparison result signal _SCMP indicating the comparison result (level relationship) of the comparison voltages V1 and V2. The comparison result signal _SCMP is a binary signal having a value of "0" or "1". The comparator 20 has a non-inverting input terminal, an inverting input terminal, and an output terminal, and here it is assumed that the inverting input terminal is connected to the comparison wiring WR1 and the non-inverting input terminal is connected to the comparison wiring WR2.

The comparator 20 outputs a comparison result signal S _CMP having a value of "1" when "V1<V2" is established, and has a value of "0" when "V1>V2" is established. It outputs the comparison result signal _SCMP from its own output terminal. When "V1=V2" is satisfied, the comparison result signal _SCMP has a value of "0" or "1". "V1>V2" represents that the comparison voltage V1 is higher than the comparison voltage V2, and "V1<V2" represents that the comparison voltage V1 is lower than the comparison voltage V2. The same applies to other expressions including physical quantities such as voltage.

Control circuit 30 receives comparison result signal _SCMP . The control circuit 30 controls the entire AD conversion operation and outputs a digital output signal Dout obtained by the AD conversion operation. The control circuit 30 is provided with a register 31, and the value of the digital output signal Dout can be stored in the register 31. The control circuit 30 individually controls the states of the switches S[1] to S[N] by supplying a control signal CNT _DAC (DAC input signal) to the DAC 10. The control circuit 30 individually controls the states of the switches S _G and S _RC by supplying a control signal CNT _G to the switch S _G and a control signal CNT _RC to the switch S _RC .

The voltage generation circuit 40 generates a comparison voltage V2 to be compared with the comparison voltage V1, and supplies the generated comparison voltage V2 to the comparison wiring WR2. The comparison voltage V2 can also be referred to as a reference voltage, and in this case, the voltage generation circuit 40 can also be referred to as a reference voltage generation circuit.

In the DAC 10 of FIG. 1, for any integer i, the capacitance value of the capacitor C[i+1] is larger than the capacitance value of the capacitor C[i]. Here, as shown in FIG. 6, it is assumed that the capacitor C[i] in the DAC 10 has a capacitance value of "2 ^i-1 ·C _UNT ". Therefore, in the DAC 10 of FIG. 1, for any integer i, the capacitance value of capacitor C[i+1] is twice the capacitance value of capacitor C[i]. _CUNT represents a predetermined unit capacity value.

FIG. 7 shows a flowchart of AD conversion operation. In the AD conversion operation, first a sampling operation is performed in step S1, then a state transition operation is performed in step S2, a successive approximation operation is performed in step S3, and finally a result output operation is performed in step S4. Hereinafter, a period in which a sampling operation is performed will be referred to as a sampling period, and a period in which a successive approximation operation is performed will be referred to as a successive approximation period.

FIG. 8 shows the state of the AD converter 1 during the sampling period. The sampling period has a predetermined length of time. During the sampling period, the control circuit 30 controls all switches S[1] to S[N] in the DAC 10 to the signal input state, turns on the switch _SG , and connects the switch _SRC to ground. control to the state.

During the sampling period, the wiring WR_Ain is connected to the capacitor array 11 via the switch array 12, so that charges corresponding to the analog input signal Ain are transferred to each capacitor (C[1] to C[N]) in the capacitor array 11. is accumulated in During the sampling period, the comparison wiring WR1 is connected to the ground via the switch _SG , so each capacitor (C[1] to C[N]) in the capacitor array 11 receives the analog input signal Ain with reference to the ground voltage. is charged by On the other hand, since the switch _SRC is connected to the ground during the sampling period, the voltage across the capacitor _CRC is 0V. Note that the operations of the comparator 20 and the voltage generation circuit 40 may be stopped during the sampling period.

FIG. 9 shows an example of the flow of the state transition operation in step S2. In the example of FIG. 9, in the state transition operation, steps S21, S22, S23, and S24 are executed in this order. The operations in steps S21, S22, S23, and S24 are respectively referred to as a connection cancellation operation, a first transition switching operation, a second transition switching operation, and a successive approximation preparation operation.

In the connection cancellation operation of step S21, the states of the switches S[1] to S[N] of the DAC 10 are all switched from the signal input state to the open state. In the first transition switching operation in step S22, the state of the switch _SG is switched from on to off. After step S22, switch _SG is maintained in the off state until the successive approximation operation in step S3 is completed. In the second transition switching operation in step S23, the state of the switch _SRC is switched from the ground connection state to the power supply connection state. After step S23, the switch _SRC is maintained in the power connected state until the successive approximation operation in step S3 is completed. In the successive approximation preparation operation of step S24, the states of the switches S[1] to S[N] of the DAC 10 are switched to a power supply connection state or a ground connection state.

FIG. 10 shows the state of the AD converter 1 after the operations of steps S21 to S24. In the example of FIG. 10, it is assumed that the states of the switches S[1] to S[N] of the DAC 10 are all switched to the ground connection state in step S24.

In the state transition operation, the transition timing of each state of the switches S[1] to S[N], S _G and S _RC can be changed in various ways.
That is, for example, in the state transition operation, steps S21, S22, and S23 may be performed simultaneously, and then step S24 may be performed.
Alternatively, in the state transition operation, steps S21 and S22 may be performed simultaneously, then step S23 may be performed, and then step S24 may be performed. Alternatively, the operations in steps S21 and S22 may be performed simultaneously, and then the operations in step S23 and step S24 may be performed simultaneously.
Alternatively, in the state transition operation, step S21 may be performed, steps S22 and S23 may be performed simultaneously, and then step S24 may be performed. Alternatively, after performing the operation in step S21, the operation in step S22 may be performed, and then the operations in steps S23 and S24 may be performed simultaneously. Alternatively, in the state transition operation, step S21 may be performed, and then steps S22, S23, and S24 may be performed simultaneously.

In step S24, the switches S[1] to S[N] may all be connected to the ground or all connected to the power supply. Alternatively, in step S24, the states of switches S[1] to S[N] are the initial states of switches S[1] to S[N] in the successive approximation operation in step S3 (at "j=N", which will be described later). The state of step S32 (see FIG. 14) may be set. The operation in step S24 may be omitted.

When the switches S[1] to S[N] are connected to the ground, when the switch _SG is turned off and the state of the switch _SRC is switched from the ground connection state to the power supply connection state, the comparison voltage at the comparison wiring WR1 V1 increases by a predetermined voltage amount V1 _SFT .

The voltage amount V1 _SFT is the value of the combined capacitance of the capacitors C[1] to C[N] in the DAC 10 (that is, the capacitance value of the parallel connection circuit of the capacitors C[1] to C[N]) and the capacitor C It is determined depending on the capacitance value of _RC and the value of power supply voltage VDD. If the capacitance values of capacitors C[1] to C[N] and the value of power supply voltage VDD are fixed, the voltage amount V1 _SFT can be arbitrarily adjusted by adjusting the capacitance value of capacitors _CRC . can. In the successive approximation operation described later, the comparison voltage V1 varies according to each state of the switches S[1] to S[N], and the comparison voltage V1 changes when the switches S[1] to S[N] are all grounded. V1 is the lowest. Furthermore, the comparison voltage V1 in the successive approximation operation also depends on the analog input signal Ain during the sampling period. While considering the variation range of the analog input signal Ain, the above-mentioned voltage is set so that the comparison voltage V1 is always 0V or higher even when the switches S[1] to S[N] are all grounded in the successive approximation operation. The quantity V1 _SFT is determined (in other words the capacitance value of the capacitor _CRC is determined). Therefore, the comparator 20 does not require a negative power supply. That is, the comparator 20 drives the ground voltage based on the power supply voltage VDD (or other positive DC voltage).

The comparison voltage V2 generated by the voltage generation circuit 40 has the above voltage amount V1 _SHT as a voltage value (that is, "V2=V1 _SHT "). However, the comparison voltage V2 during the sampling period may be arbitrary. It is sufficient that the comparison voltage V2 having a voltage value equal to the voltage amount V1 _SHT is generated in the voltage comparison circuit 40 and applied to the comparison wiring WR2 at least in the successive approximation period.

A voltage generation circuit 40a in FIG. 11 is an example of the voltage generation circuit 40. The voltage generation circuit 40a includes capacitors C _REF and C _RC ′ and switches S _G ′ and S _RC ′. The switch _SG ' has the same structure as the switch _SG , and the switch _SRC ' has the same structure as the switch _SRC . A first end of the switch _SG ', a first end of the capacitor C _REF , and a first end of the capacitor C _RC ' are connected to the wiring WR2. A second end of the switch _SG ' and a second end of the capacitor C _REF are connected to ground. The second end of the capacitor C _{RC ′} is connected to the common terminal T ₃ of the switch S _{RC ′} . The switching terminal _T1 of the switch _SRC ' is connected to the wiring WR_VDD and receives the power supply voltage VDD. The switching terminal _T2 of the switch _SRC ' is connected to the wiring WR_GND and receives the ground voltage. The control circuit 30 controls on/off of the switch _SG ' similarly to the switch _SG . Under the control of the control circuit 30, the common terminal _T3 is selectively connected to the switching terminal _T1 or _T2 by the switch _SRC '. However, the common terminal T ₃ of the switch S _RC ′ may not be connected to either the switching terminals T ₁ or T ₂ .

When the voltage generation circuit 40a is used as the voltage generation circuit 40, as shown in FIG. 12, during the sampling period, the switch _SG ' is turned on and the common terminal _T3 of the switch _SRC ' is connected to the switching terminal _T2. As a result, a ground voltage is applied to the second end of the capacitor _CRC '. Thereafter, in the successive approximation period, the switch _SG ' is turned off and the common terminal _T3 of the switch _SRC ' is connected to the switching terminal _T1 , so that the power supply voltage VDD is applied to the second terminal of the capacitor _CRC '. applied.

Here, the formula "C _TOTAL : _CRC = C _REF : _CRC '" is established. In this equation, C _TOTAL represents the value of the combined capacitance of capacitors C[1] to C[N] in the DAC 10 (that is, the capacitance value of the parallel connection circuit of capacitors C[1] to C[N]). , _CRC , C _REF , , _CRC ′ represent the capacitance values of the capacitors _CRC , C _REF , , _{CRC ′} , respectively. By configuring each capacitor so that the above formula holds true, the value of the comparison voltage V2 during the successive approximation period matches the voltage amount V1 _SHT described above.

Alternatively, the voltage generation circuit 40b in FIG. 13 may be used as the voltage generation circuit 40. The voltage generation circuit 40b has voltage dividing resistors R1 and R2. In the voltage generation circuit 40b, the power supply voltage VDD is applied to the first end of the voltage dividing resistor R1, and the second end of the voltage dividing resistor R1 and the first end of the voltage dividing resistor R2 are connected to the comparison wiring WR2. A second end of the voltage dividing resistor R2 is connected to ground. When the voltage generation circuit 40b is used as the voltage generation circuit 40, the power supply voltage VDD is divided by the voltage dividing resistors R1 and R2, and a comparison voltage V2 is generated on the comparison wiring WR2. At this time, the resistance value ratio of the voltage dividing resistors R1 and R2 is set so that "V2=V1 _SHT " holds.

FIG. 14 shows a flowchart of the successive approximation operation in step S3. As can be understood from the above description, during the successive approximation period in which the successive approximation operation is performed, the switch _SG is kept off and the switch _SRC is kept connected to the power supply. FIG. 15 shows the structure of the register 31 (see FIG. 1). The register 31 has a storage capacity of N bits and stores values Rg[1] to Rg[N]. The values Rg[1] to Rg[N] are respectively "0" or "1". For any integer i, the value Rg[i+1] is the value of the upper bit of the value Rg[i]. In the successive approximation operation, values Rg[1] to Rg[N] are determined bit by bit from the upper bit side, and the determined value Rg[i] becomes the value of the i-th bit in the digital output signal Dout.

During the successive approximation period, switches S[1] to S[N] are individually set to a power supply connection state or a ground connection state. Charges accumulated in the capacitor array 11 during the sampling period are distributed to the capacitors C[1] to C[N] and _CRC during the successive approximation period. The state of distribution depends on the state of switches S[1] to S[N] during the successive approximation period, and therefore the comparison voltage V1 depends on the state of switches S[1] to S[N] during the successive approximation period. changes. In the successive approximation operation (in other words, during the successive approximation period), the control circuit 30 sequentially switches the state of the switch array 12 by binary search based on the comparison result signal S _CMP while changing the states of the switch array 12 to values Rg[1] to Rg[N] (i.e., The value of the digital output signal Dout) is determined bit by bit.

In the successive approximation operation of FIG. 14, first, in step S31, the value of N is assigned to the variable j managed by the control circuit 30. After that, the process advances to step S32. In step S32, the control circuit 30 controls switch S[j] to be connected to the power supply, and controls all switches S[1] to S[j-1] to be connected to ground. However, when the process of step S32 is executed in the state of "j=1", the switches S[1] to S[j-1] do not exist, so in step S32, the switch S[1] is simply ] is controlled to be connected to the power supply. As an example, FIG. 16 shows the state of each switch in step S32 when "j=N".

In step S33 following step S32, the control circuit 30 acquires the value of the comparison result signal S _CMP at the current time (that is, acquires the value of the comparison result signal S _CMP output from the comparator 20 in the state of the most recent step S32). do). If the obtained value is "1" (Y in step S33), the process proceeds to step S34, and the control circuit 30 performs the processing in steps S34 and S35, while if the obtained value is "0" (N in step S33) ) Proceeding to step S36, the control circuit 30 performs steps S36 and S37.

In step S34, the control circuit 30 determines the value Rg[j] to be "1". In the following step S35, the control circuit 30 maintains the switch S[j] in the power supply connected state. Thereafter, the switch S[j] is maintained in the power connected state until the successive approximation operation in FIG. 14 is completed. After step S35, the process advances to step S38. Since virtually nothing is executed in step S35, step S35 may be omitted.

In step S36, the control circuit 30 determines the value Rg[j] to be "0". In the following step S37, the control circuit 30 switches the state of the switch S[j] from the power supply connection state to the ground connection state. Thereafter, the switch S[j] is maintained in the grounded state until the successive approximation operation in FIG. 14 is completed. After step S37, the process advances to step S38.

In step S38, the control circuit 30 checks whether the variable j is 1. If the variable j is not 1 (N in step S38), the process advances to step S39, where 1 is subtracted from the variable j, and then the process returns to step S32 to repeat the processes at step S32 and thereafter. For example, in the second process of step S32, the switch S[N-1] is set to the power supply connection state, and the switches S[1] to S[N-1] are set to the ground connection state. At this time, if "S _CMP = 1" in the first step S33, the switch S[N] is connected to the power supply in the second step S32, and "S _{CMP =} 1" in the first step S33. =0'', the switch S[N] is connected to the ground in the second step S32.

The process consisting of steps S32 to S37 is referred to as a unit comparison operation. Then, the successive approximation operation includes the first to Nth unit comparison operations. The unit comparison operation executed when "j=N" is the Nth unit comparison operation, and the unit comparison operation executed when "j=N-1" is the (N-1)th unit comparison operation. Yes, the unit comparison operation executed when "j=1" is the first unit comparison operation. In the j-th unit comparison operation, the value Rg[j] is determined, that is, the value of the j-th bit of the digital output signal Dout is determined.

If "j=1" in step S38 (Y in step S38), the successive approximation operation of FIG. 14 is ended. At this stage, all values Rg[1] to Rg[N] have been determined.

In the result output operation in step S4 (see FIG. 7), the control circuit 30 outputs the digital signal having the values Rg[1] to Rg[N] determined in the successive approximation operation in step S3 as the digital output signal Dout. do. The digital output signal Dout is output to an arbitrary circuit (not shown) that utilizes the digital output signal Dout.

Here, FIG. 17 shows the configuration of a reference AD converter 901. Reference AD converter 901 includes a DAC 910 having a capacitor array 911 and a switch array 912, a comparator 920, a control circuit 930, a voltage generation circuit 940, a reference voltage source 950, and a switch 960. Each first end of the capacitors in the capacitor array 911 is commonly connected to the wiring WR1'. A comparison voltage V1' is applied to the wiring WR1'. A wiring WR1' is connected to the inverting input terminal of the comparator 920. Voltage generation circuit 940 supplies comparison voltage V2' to the non-inverting input terminal of comparator 920. The reference voltage source 950 is connected to the wiring WR1' via a switch 960, and supplies a positive reference voltage V _REF to the wiring WR1' when the switch 960 is on.

In the reference AD converter 901, in the sampling operation, the wiring to which the analog input signal Ain is applied is connected to the second end of each capacitor of the capacitor array 911 via the switch array 912, as shown in FIG. The accumulated charges are accumulated in each capacitor of the capacitor array 911. At this time, since the switch 960 is turned on, each capacitor in the capacitor array 911 is charged by the analog input signal Ain based on the reference voltage V _REF . Thereafter, in the successive approximation operation, the switch array 912 is used to supply the power supply voltage VDD' or the ground voltage to the second end of each capacitor in the capacitor array 911 while keeping the switch 960 off (see FIG. 18). ). In the successive approximation operation, the control circuit 930 converts the analog input signal Ain' into a digital signal by binary search while sequentially switching the states of the switch array 912 based on the comparison result of the voltages V1' and V2' by the comparator 920.

In the reference AD converter 901, it is necessary to keep the reference voltage source 950 operating when the sampling operation is performed, and power consumption increases accordingly. There is also a method of removing the reference voltage source 950 from the reference AD converter 901 and using 0V as the reference voltage V _REF , but in this method, the polarity of the comparison voltage V1' becomes negative in the successive approximation operation, so the comparator 920 A negative power supply (negative power supply voltage) is required. When a negative power source is essential, the circuit configuration becomes complicated, such as the need for a circuit to generate the negative power source. For this reason, it is desirable that a negative power supply be unnecessary.

On the other hand, in the AD converter 1 of FIG. 1, the comparison voltage V1 can be increased by an amount corresponding to the reference voltage V _REF after sampling the analog input signal Ain with respect to the ground. Specifically, in the AD converter 1, charges corresponding to the analog input signal Ain are accumulated in each capacitor of the capacitor array 11 using the ground voltage as a reference during the sampling period. Thereafter, a successive approximation operation is performed using the reference change circuit (capacitor C _RC and switch S _RC ) while increasing the comparison voltage V1 by a necessary amount. As a result, AD converter 1 in FIG. 1 does not require a circuit corresponding to reference voltage source 950, and power consumption during the sampling period can be reduced compared to reference AD converter 901.

<<Second embodiment>>
A second embodiment of the present disclosure will be described. The second embodiment and the third and fourth embodiments described later are embodiments based on the first embodiment, and unless there is a contradiction, matters not specifically stated in the second to fourth embodiments are based on the first embodiment. The description of the embodiments also applies to the second to fourth embodiments. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence regarding matters that are inconsistent between the first and second embodiments (the description of the third and fourth embodiments described below may also be given priority). similar). Any plurality of embodiments among the first to fourth embodiments may be combined as long as there is no contradiction.

The DAC 10 in the first embodiment may be provided with one or more scaling capacitors. By using a scaling capacitor, in a capacitor array, the capacitance ratio between the capacitor having the maximum capacitance value and the capacitor having the minimum capacitance value can be kept low, increasing practicality.

The DAC 10_1 shown in FIG. 19 is a DAC 10 modified by adding a scaling capacitor Cs. That is, the DAC 10_1 is obtained by adding the scaling capacitor Cs to the DAC 10 according to the first embodiment. The DAC 10_1 has a scaling capacitor Cs, and also has a capacitor array 11_1 and a switch array 12_1. In the DAC 10_1, N and M are integers that satisfy "N>M≧1", and typically, for example, "M≧2" and "N≧M+2" are satisfied.

The capacitor array 11_1 includes capacitors C[1] to C[N] similarly to the capacitor array 11 of the first embodiment. The switch array 12_1 includes switches S[1] to S[N] similarly to the switch array 12 of the first embodiment. The capacitor array 11_1 is the same as the capacitor array 11 of the first embodiment except for the following differences DP _2A and DP _2B .

The difference DP _2A is that in the DAC 10_1, the first ends of each of the capacitors C[1] to C[M] among the capacitors C[1] to C[N] are connected to the wiring WR_s instead of the wiring WR1. This embodiment is similar to the first embodiment in that each first end of the capacitors C[M+1] to C[N] is connected to the wiring WR1. Further, the second ends of the capacitors C[1] to C[M] are connected to the common terminal _TCOM of the switches S[1] to S[M], respectively, and the second terminals of the capacitors C[M+1] to C[N] are connected to the common terminal TCOM of the switches S[1] to S[M], respectively. It is also similar to the first embodiment that the ends are connected to the common terminal T _COM of the switches S[M+1] to S[N], respectively (see FIG. 2).

In the DAC 10_1, a scaling capacitor Cs is inserted in series between the wirings WR1 and WR_s. That is, in the DAC 10_1, the first end of the scaling capacitor Cs is connected to the wiring WR1, and the second end of the scaling capacitor Cs is connected to the wiring WR_s.

As a difference DP _2B , the capacitance values of the capacitors C[1] to C[N] are different between the DAC 10_1 and the DAC 10 of the first embodiment. See FIG. 20. In the DAC 10_1, for an integer i that satisfies "1≦i≦M", the capacitor C[i] has a capacitance value of "2 ^i-1 ·C _UNT ". In the DAC 10_1, for an integer i that satisfies "M+1≦i≦N", the capacitor C[i] has a capacitance value of "2 ^{i - M-1} ·C _UNT ".

In the DAC 10_1, the value of the combined capacitance of the capacitors C[1] to C[M] and the scaling capacitor Cs (that is, the value of the combined capacitance of the capacitors C[1] to C[M] and the scaling capacitor Cs are connected in series) The capacitance value of the circuit formed) is equal to the unit capacitance value C _UNT .

Except for the differences DP _2A and DP _2B regarding the capacitor array 11_1, the configuration and operation when the DAC 10_1 is used in the AD converter 1 instead of the DAC 10 are the same as in the first embodiment.

The number of scaling capacitors Cs added to the DAC 10 (number of series stages) is arbitrary as long as it is one or more. As an example, FIG. 21 shows a DAC 10_2 as a DAC 10 to which two scaling capacitors Cs are added. The two scaling capacitors Cs in the DAC 10_2 are referred to as scaling capacitors Cs1 and Cs2. A DAC 10_2 is obtained by adding scaling capacitors Cs1 and Cs2 to the DAC 10 according to the first embodiment. The DAC 10_2 has scaling capacitors Cs1 and Cs2, and also has a capacitor array 11_2 and a switch array 12_2. In the DAC 10_2, N, M, and L are integers that satisfy "N>L+M", "L≧1", and "M≧1", and typically, for example, "L≧2", "M≧2", and " N≧L+M+2” is satisfied.

The capacitor array 11_2 includes capacitors C[1] to C[N] similarly to the capacitor array 11 of the first embodiment. The switch array 12_2 includes switches S[1] to S[N] similarly to the switch array 12 of the first embodiment. The capacitor array 11_2 is the same as the capacitor array 11 of the first embodiment except for the following differences DP _2C and DP _2D .

The difference DP _2C is that in the DAC 10_2, each first end of the capacitors C[1] to C[L] among the capacitors C[1] to C[N] is connected to the wiring WR_s2 instead of the wiring WR1, and Each first end of the capacitors C[L+1] to C[L+M] is connected to the wiring WR_s1 instead of the wiring WR1. This embodiment is similar to the first embodiment in that each first end of the capacitors C[L+M+1] to C[N] is connected to the wiring WR1. Further, the second terminals of the capacitors C[1] to C[L] are connected to the common terminal _TCOM of the switches S[1] to S[L], respectively, and the second terminals of the capacitors C[L+1] to C[L+M] The terminals are connected to the common terminal T _COM of the switches S[L+1] to S[L+M], respectively, and the second terminals of the capacitors C[L+M+1] to C[N] are connected to the switches S[L+M+1] to S[N], respectively. It is also the same as the first embodiment in that it is connected to the common terminal T _COM of (see FIG. 2).

In the DAC 10_2, the scaling capacitor Cs1 is inserted in series between the wirings WR1 and WR_s1. That is, in the DAC 10_2, the first end of the scaling capacitor Cs1 is connected to the wiring WR1, and the second end of the scaling capacitor Cs1 is connected to the wiring WR_s1. In the DAC 10_2, the scaling capacitor Cs2 is inserted in series between the wirings WR1 and WR_s2. That is, in the DAC 10_2, the first end of the scaling capacitor Cs2 is connected to the wiring WR1, and the second end of the scaling capacitor Cs2 is connected to the wiring WR_s2.

As a difference DP _2D , the capacitance values of the capacitors C[1] to C[N] are different between the DAC 10_2 and the DAC 10 of the first embodiment. See FIG. 22. In the DAC 10_2, for an integer i satisfying "1≦i≦L", the capacitor C[i] has a capacitance value of "2 ^i-1 ·C _UNT ". In the DAC 10_2, for an integer i that satisfies "L+1≦i≦L+M", the capacitor C[i] has a capacitance value of "2 ^i-L-1 ·C _UNT ". In the DAC 10_2, for an integer i that satisfies "L+M+1≦i≦N", the capacitor C[i] has a capacitance value of "2 ^i-L-M-1 ·C _UNT ".

In the DAC 10_2, the value of the combined capacitance of the capacitors C[1] to C[L+M] and the scaling capacitors Cs1 and Cs2 is equal to the unit capacitance value C _UNT . Furthermore, scaling capacitor Cs2 has a larger capacitance value than scaling capacitor Cs1.

Except for the differences DP _2C and DP _2D regarding the capacitor array 11_2, the configuration and operation when the DAC 10_2 is used in the AD converter 1 instead of the DAC 10 are the same as in the first embodiment.

<<Third Embodiment>>
A third embodiment of the present disclosure will be described. The configuration and operation of the AD converter 1 shown in the first embodiment may be applied to an AD converter having a differential input configuration. FIG. 23 shows the overall configuration of the AD converter 2 to which this application is applied. Like the AD converter 1 described above, the AD converter 2 is a successive approximation type A/D conversion circuit. Analog input signals AinP and AinN are input to the AD converter 2. The AD converter 2 performs an AD conversion operation on the difference signal ADif between the analog input signals AinP and AinN. It is assumed that the difference signal ADif is an analog signal having the potential of the analog input signal AinP as viewed from the potential of the analog input signal AinN.

In the AD conversion operation for the difference signal Adif, the difference signal Adif is converted into a digital signal by binary search, and the obtained digital signal is output as the digital output signal Dout. The digital output signal Dout is an N-bit digital signal as in the first embodiment. When “AinP=AinN”, the digital output signal Dout has a predetermined intermediate value, and when “AinP>AinN”, the value of the digital output signal Dout increases from the intermediate value as the magnitude of the difference signal Adif increases. However, when "AinP<AinN", the value of the digital output signal Dout may decrease from the intermediate value as the magnitude of the difference signal Adif increases.

The AD converter 2 includes two comparison voltage generation blocks. Each comparison voltage generation block includes the DAC 10, switch S _G , switch S _RC , and capacitor C _RC described in the first embodiment. The configurations of the DAC 10, switch S _G , switch S _RC , and capacitor C _RC in each comparison voltage generation block are the same as the configurations of the DAC 10, switch S _G , switch S _RC , and capacitor C _RC described in the first embodiment. . Therefore, in each comparison voltage generation block, the DAC 10 includes a capacitor array 11 consisting of capacitors C[1] to C[N] and a switch array 12 consisting of switches S[1] to S[N]. The connection relationship between the capacitors C[1] to C[N] and the switches S[1] to S[N] in each comparison voltage generation block is the same as that of the capacitors C[1] to C[N] and the switches in the first embodiment. This is the same as the connection relationship between S[1] and S[N]. The connection relationship between the capacitor C _RC and the switch S _RC in each comparison voltage generation block is the same as the connection relationship between the capacitor C _RC and the switch S _RC in the first embodiment.

In the following, the DAC 10, the switch S _G , the switch S _RC , and the capacitor C _RC provided in one of the two comparison voltage generation blocks provided in the AD converter 2 will be described, in particular, the DAC 10P, the switch S _The DAC 10, the switch S _G , the switch S _RC and the capacitor C _RC provided in the other comparison voltage _generation block are respectively referred to as a DAC 10N, a switch S _GN , a switch S _RCN and a capacitor C _RCP . It is called capacitor _CRCN .

The wiring WR_AinP is an analog input wiring to which an analog input signal AinP is applied, and the wiring WR_AinN is an analog input wiring to which an analog input signal AinN is applied. Similar to the first embodiment, the wiring WR_VDD is a power wiring to which a predetermined power supply voltage VDD is applied, and the wiring WR_GND is a ground wiring to which a ground voltage is applied. Analog input signals AinP and AinN correspond to analog input signals Ain for DACs 10P and 10N, respectively.

In the configuration of FIG. 23, the first ends of the capacitors C[1] to C[N] of the DAC10P are all connected to the comparison wiring WR1, and the first ends of the capacitors C[1] to C[N] of the DAC10N are all connected to the comparison wiring WR1. Connected to wiring WR2. This embodiment is similar to the first embodiment in that the voltage applied to the comparison wiring WR1 is the comparison voltage V1, and the voltage applied to the comparison wiring WR2 is the comparison voltage V2. In each of the DACs 10P and 10N, a switch S[i] is provided corresponding to the capacitor C[i]. In each of DACs 10P and 10N, capacitor C[i] corresponds to the i-th bit in digital output signal Dout.

The switches S[1] to S[N] each include a common terminal T _COM and switching terminals Ta, Tb, and Tc (see FIG. 2). In each of the DACs 10P and 10N, the common terminal T _COM of the switch S[i] is connected to the second end of the capacitor C[i]. Each switching terminal Ta of the switches S[1] to S[N] in the DAC 10P is connected to the wiring WR_AinP and receives the analog input signal AinP. Therefore, in the DAC 10P, when the switch S[i] is in the signal input state, the analog input signal AinP is applied to the second end of the capacitor C[i]. Each switching terminal Ta of the switches S[1] to S[N] in the DAC 10N is connected to the wiring WR_AinN and receives the analog input signal AinN. Therefore, in the DAC 10N, when the switch S[i] is in the signal input state, the analog input signal AinN is applied to the second end of the capacitor C[i]. In each of the DACs 10P and 10N, each switching terminal Tb of the switches S[1] to S[N] is connected to the wiring WR_VDD and receives the power supply voltage VDD. In each of the DACs 10P and 10N, each switching terminal Tc of the switches S[1] to S[N] is connected to the wiring WR_GND and receives the ground voltage.

In the DAC 10P, when the switch S[i] is in the signal input state, power supply connection state, and ground state, the analog input signal AinP, power supply voltage VDD, and ground voltage are applied to the second terminal of the capacitor C[i], respectively (see FIG. 3). ). In the DAC 10N, when the switch S[i] is in the signal input state, power supply connection state, and ground state, the analog input signal AinN, power supply voltage VDD, and ground voltage are applied to the second terminal of the capacitor C[i], respectively (see FIG. 3). ). Note that FIG. 23 shows, as an example, that the switches S[1] to S[N] in the DACs 10P and 10N are all in the signal input state.

Switches _SGP and _SGN are ground shorting switches. The switch _SGP is provided in series between the comparison wiring WR1 and the ground. That is, the first end of the switch S _GP is connected to the comparison wiring WR1, and the second end of the switch S _GP is connected to the ground (in other words, connected to the wiring WR_GND). The switch _SGN is provided in series between the comparison wiring WR2 and the ground. That is, the first end of the switch S _GN is connected to the comparison wiring WR2, and the second end of the switch S _GN is connected to the ground (in other words, connected to the wiring WR_GND).

The control circuit 30 controls the switches _SGP and _SGN to be on or off. When the switch S _GP is on, the first end and the second end of the switch S _GP are electrically connected, and the voltage of the comparison line WR1 (ie, the comparison voltage V1) is fixed to 0V. When the switch _SGP is off, the first and second ends of the switch _SGP are cut off (non-conductive), and the switch _SGP does not affect the comparison voltage V1. When the switch _SGN is on, the first and second ends of the switch _SGN are electrically connected, and the voltage of the comparison line WR2 (ie, the comparison voltage V2) is fixed at 0V. When the switch S _GN is off, the first end and the second end of the switch S _GN are cut off (non-conductive), and the switch S _GN does not affect the comparison voltage V2. Note that FIG. 23 shows, as an example, the switches S _GP and S _GN being turned off.

Capacitors C _RCP and C _RCN are reference change capacitors, and switches S _RCP and S _RCN are reference change switches. The capacitor C _RCP and the switch S _RCP constitute a first reference change circuit, and the capacitor C _RCN and the switch S _RCN constitute a second reference change circuit. After sampling the analog input signals AinP and AinN, the first and second reference change circuits change (shift) the reference voltages of the comparison voltages V1 and V2 to the high level side.

Similar to the switch S _RC of FIG. 4, the switches S _RCP and S _RCN each include switching terminals T ₁ and T ₂ and a common terminal T ₃ . A first end of the capacitor _CRCP is connected to the comparison line WR1. The second end of the capacitor _CRCP is connected to the common terminal _T3 of the switch _SRCP . A first end of the capacitor _CRCN is connected to the comparison line WR2. The second end of the capacitor _CRCN is connected to the common terminal _T3 of the switch _SRCN . Each switching terminal _T1 of the switches _SRCP and _SRCN is connected to the wiring WR_VDD and receives the power supply voltage VDD. Each switching terminal _T2 of the switches _SRCP and _SRCN is connected to the wiring WR_GND and receives the ground voltage.

Under the control of the control circuit 30, in each of the switches _SRCP and _SRCN , the common terminal _T3 is selectively connected to the switching terminal _T1 or _T2 (however, the common terminal _T3 is connected to the switching terminal _T1 or T2). ₂ ). When the switch _SRCP is in the power connection state and the ground state, the power supply voltage VDD and the ground voltage are applied to the second end of the capacitor _CRCP , respectively (see FIG. 5). When the switch _{S_RCN} is in the power supply connection state and the ground state, the power supply voltage VDD and the ground voltage are applied to the second end of the capacitor _CRCN , respectively. Note that FIG. 23 shows, as an example, how the switches S _RCP and S _RCN are connected to the ground.

Comparator 20 is connected to comparison wirings WR1 and WR2. Similar to the first embodiment, the comparator 20 of the DAC 2 compares the comparison voltages V1 and V2, and generates and outputs a comparison result signal _SCMP indicating the comparison result (high/low relationship) of the comparison voltages V1 and V2. However, in the AD converter 2, the comparison voltage V2 is output from the DAC 10N. The comparison result signal _SCMP is a binary signal having a value of "0" or "1". The comparator 20 has a non-inverting input terminal, an inverting input terminal, and an output terminal, and here it is assumed that the inverting input terminal is connected to the comparison wiring WR1 and the non-inverting input terminal is connected to the comparison wiring WR2. The comparator 20 outputs a comparison result signal S _CMP having a value of "1" when "V1<V2" is established, and has a value of "0" when "V1>V2" is established. It outputs the comparison result signal _SCMP from its own output terminal. When "V1=V2" is satisfied, the comparison result signal _SCMP has a value of "0" or "1".

Control circuit 30 receives comparison result signal _SCMP . The control circuit 30 controls the entire AD conversion operation and outputs a digital output signal Dout obtained by the AD conversion operation. Similar to the first embodiment, the control circuit 30 is provided with a register 31, and the value of the digital output signal Dout can be stored in the register 31. The control circuit 30 individually controls the states of the switches S[1] to S[N] in the DACs 10P and 10N by supplying a control signal CNT _DAC (DAC input signal) to the DACs 10P and 10N. The control circuit 30 controls the states of the switches S _GP and S _GN by supplying a control signal CNT _G to the switches S _GP and S _GN , and supplies a control signal CNT _RC to the switches S _RCP and S _RCN . This controls the states of switches _SRCP and _SRCN .

In each of the DACs 10P and 10N, the capacitance values of the capacitors C[1] to C[n] are set similarly to the first embodiment (see FIG. 6).

In the AD converting operation in the AD converter 2, the operations of steps S1 to S4 are sequentially executed as in the first embodiment (see FIG. 7).

FIG. 24 shows the state of the AD converter 2 during the sampling period. The sampling period has a predetermined length of time. During the sampling period, the control circuit 30 controls all switches S[1] to S[N] in the DACs 10P and 10N to the signal input state, turns on the switches _SGP and _SGN , and turns on the switches SGP and SGN. Control S _RCP and S _RCN to ground connection state.

During the sampling period, the wiring WR_AinP is connected to the capacitor array 11 via the switch array 12 in the DAC 10P, and as a result, the charge corresponding to the analog input signal AinP is transferred to each capacitor (C[1] to C [N]). Similarly, during the sampling period, the wiring WR_AinN is connected to the capacitor array 11 via the switch array 12 in the DAC 10N, and as a result, charges corresponding to the analog input signal AinN are transferred to each capacitor (C[1 ] to C[N]).

During the sampling period, comparison lines WR1 and WR2 are connected to ground via switches _SGP and _SGN . Therefore, each capacitor (C[1] to C[N]) in the capacitor array 11 in the DAC 10P is charged by the analog input signal AinP with reference to the ground voltage, and each capacitor (C[1] to C[N]) in the capacitor array 11 in the DAC 10N is charged by the analog input signal AinP. 1] to C[N]) are charged by the analog input signal AinN with reference to the ground voltage. Furthermore, since the switches S _RCP and S _RCN are connected to ground during the sampling period, the voltage across each of the capacitors C _RCP and C _RCN is 0V. Note that the operation of the comparator 20 may be stopped during the sampling period.

In the state transition operation in step S2, an operation similar to the state transition operation shown in the first embodiment is performed for each of the two comparison voltage generation blocks. In the state transition operation, the operations of steps S21, S22, S23, and S24 may be executed in this order (see FIG. 9).

In the connection cancellation operation in step S21, the states of the switches S[1] to S[N] in each of the DACs 10P and 10N are all switched from the signal input state to the open state. In the first transition switching operation in step S22, the states of the switches S _GP and S _GN are switched from on to off. After step S22, the switches _SGP and _SGN are maintained in the off state until the successive approximation operation in step S3 is completed. In the second transition switching operation in step S23, the states of the switches S _RCP and S _RCN are switched from the ground connection state to the power supply connection state. After step S23, the switches S _RCP and S _RCN are kept connected to the power supply until the successive approximation operation of step S3 is completed. In the successive approximation preparation operation in step S24, the states of the switches S[1] to S[N] of the DACs 10P and 10N are switched to a power supply connection state or a ground connection state.

FIG. 25 shows the state of the AD converter 2 after the operations in steps S21 to S24. In the example of FIG. 25, it is assumed that the states of the switches S[1] to S[N] of the DACs 10P and 10N are all switched to the ground connection state in step S24.

As stated in the first embodiment, in the state transition operation, the state transition timing of each switch can be changed in various ways, and the description of the first embodiment applies to this embodiment as well. . Therefore, for example, in the state transition operation according to the third embodiment, the operations in steps S21 to S23 may be performed simultaneously, the operations in steps S21 and S22 may be performed simultaneously, and then the operation in step S23 may be performed, After performing the operation in step S21, the operations in steps S22 and S23 may be performed simultaneously. At this time, the operation of step S24 is executed simultaneously with the operation of step S23 or after the operation of step S23. Alternatively, the operation in step S24 may be omitted.

When the switches S[1] to S[N] in the DAC10P are connected to the ground, when the switch _SGP is turned off and the state of the switch _SRCP is switched from the ground connection state to the power supply connection state, the comparison wiring WR1 The comparison voltage V1 increases by a predetermined voltage amount V1 _SFT . Similarly, when the switches S[1] to S[N] in the DAC10N are connected to the ground, if the switch _SGN is turned off and the state of the switch _SRCN is switched from the ground connection state to the power supply connection state, the comparison The comparison voltage V2 on the wiring WR2 increases by a predetermined voltage amount V2 _SFT .

As described in the first embodiment, the voltage amount V1 _SFT can be arbitrarily adjusted by adjusting the capacitance value of the capacitor _CRCP , and the voltage amount V2 _SFT can be arbitrarily adjusted by adjusting the capacitance value of the capacitor _CRCN . can. Here, the DAC 10P and the DAC 10N have the same configuration, and the capacitors C _RCP and C _RCN also have the same configuration (therefore, they have capacitance values). Therefore, “V1 _SFT =V2 _SFT ”. Considering the variation range of analog input signals AinP and AinN, comparison voltages V1 and V2 are The voltage amounts V1 _SFT and V2 _SFT described above are determined so that they are always 0V or higher (in other words, the capacitance values of the capacitors C _RCP and C _RCN are determined). Therefore, the comparator 20 does not require a negative power supply. That is, the comparator 20 drives the ground voltage based on the power supply voltage VDD (or other positive DC voltage).

During the successive approximation period in which the successive approximation operation of step S3 (see FIG. 7) is performed, the switches S _GP and S _GN are kept off, and the switches S _RCP and S _RCN are kept connected to the power supply. In the successive approximation operation, the values Rg[1] to Rg[N] of the register 31 are determined bit by bit from the upper bit side, and the determined value Rg[i] is the value of the i-th bit in the digital output signal Dout. Become. In the successive approximation operation (in other words, during the successive approximation period), the control circuit 30 sequentially switches the states of the switch arrays 12 of the DACs 10P and 10N by binary search based on the comparison result signal S _CMP , while changing the values Rg[1] to Rg[ N] (ie, the value of the digital output signal Dout) is determined bit by bit.

In the AD converter 2, the flowchart of the successive approximation operation in step S3 is the same as that in FIG. 14, and the successive approximation operation in the first embodiment is also applied to this embodiment. However, in the first embodiment, if the state of the switch S[j] is controlled, set, maintained, or switched to the power supply connected state, in the third embodiment, the state of the switch S[j] in each of the DAC10P and DAC10N is changed to the power supply connected state. It is understood that the connected state can be controlled, set, maintained, and switched. Similarly, in the first embodiment, when the state of the switch S[j] is controlled, set, maintained, and switched to the ground connection state, in the third embodiment, the state of the switch S[j] in each of the DAC 10P and DAC 10N is It is understood that it is controlled, set, maintained, and switched to a grounded state.

In the result output operation in step S4 (see FIG. 7), the control circuit 30 outputs the digital signal having the values Rg[1] to Rg[N] determined in the successive approximation operation in step S3 as the digital output signal Dout. do.

Even in the AD converter 2 having a differential input configuration, a circuit corresponding to the reference voltage source 950 (see FIG. 17) is not required, so power consumption during the sampling period can be reduced.

<<Fourth embodiment>>
A fourth embodiment of the present disclosure will be described. Just as the second embodiment can be applied to the first embodiment, the second embodiment may be applied to the third embodiment. The fourth embodiment corresponds to an application of the second embodiment to the third embodiment. In this application, "first embodiment" in the description of the second embodiment may be read as "third embodiment".

That is, for example, in the AD converter 2 according to the third embodiment, the DAC 10_1 (see FIG. 19) described in the second embodiment may be used as each of the DACs 10P and 10N. However, at this time, the switching terminals Ta of the switches S[1] to S[N] in the DAC10_1 as the DAC10P are connected to the wiring WR_AinP, and the switches S[1] to S[N] in the DAC10_1 as the DAC10N are connected to the wiring WR_AinP. It is assumed that the switching terminal Ta of is connected to the wiring WR_AinN (see also FIGS. 3 and 23).

The number of scaling capacitors Cs added to the DACs 10P and 10N (number of series stages) is arbitrary as long as it is 1 or more. That is, for example, in the AD converter 2 according to the third embodiment, the DAC 10_2 (see FIG. 21) described in the second embodiment may be used as each of the DACs 10P and 10N. However, at this time, the switching terminals Ta of the switches S[1] to S[N] in the DAC10_2 as the DAC10P are connected to the wiring WR_AinP, and the switches S[1] to S[N] in the DAC10_2 as the DAC10N are connected to the wiring WR_AinP. It is assumed that the switching terminal Ta of is connected to the wiring WR_AinN (see also FIGS. 3 and 23).

The embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values shown in the above-mentioned explanatory text are merely examples, and it goes without saying that they can be changed to various numerical values.

<<Additional notes>>
Additional notes will be provided regarding the present disclosure, in which specific configuration examples are shown in the above-described embodiments.

A successive approximation type AD conversion circuit according to one aspect of the present disclosure includes a capacitor in a successive approximation type AD conversion circuit (e.g., AD converter 1) configured to convert an analog input signal (Ain) into a digital output signal (Dout). It has a switch array (12) connected to the array (11) and the capacitor array, and connects the wiring to which the analog input signal is applied during the sampling period to the capacitor array via the switch array. A state in which a charge corresponding to a signal is accumulated in each capacitor in the capacitor array, and a predetermined power supply voltage or ground voltage is supplied to each capacitor in the capacitor array via the switch array in a successive approximation period after the sampling period. a capacitor-type DAC (10) configured to generate a first comparison voltage (V1) based on the accumulated charge of the capacitor array on a first comparison wiring (WR1); a comparator connected to a second comparison line (WR2) to which V2) is applied, and configured to compare the first comparison voltage and the second comparison voltage in the successive approximation period to generate a comparison result signal ( _SCMP ); (20); a control circuit (30) configured to determine the value of the digital output signal while controlling the state of the switch array based on the comparison result signal during the successive approximation period; and the first comparison wiring a ground short-circuiting switch (S _G ) provided between and the ground, a reference change capacitor (C RC ) having a first end connected to the first comparison wiring, and a second reference change capacitor (C _RC ) of the reference change capacitor, which has a first end connected to the first comparison wiring. This is a configuration (first configuration) including a reference change switch (S _RC ) configured to selectively apply the power supply voltage or the ground voltage to the end.

This configuration eliminates the need to operate a circuit corresponding to a reference voltage source during the sampling period, thereby reducing power consumption.

In the successive approximation type AD conversion circuit according to the first configuration, the control circuit applies the ground voltage to the first comparison wiring by turning on the ground shorting switch during the sampling period, and The ground shorting switch is turned off during the comparison period, and the control circuit applies the ground voltage to the second end of the reference changing capacitor during the sampling period through control of the reference changing switch. A configuration (second configuration) may be used in which the power supply voltage is applied during the successive approximation period.

Thereby, after sampling the analog input signal, the reference voltage of the first comparison voltage can be changed (shifted) to a higher level side using the reference change switch and the reference change capacitor. Therefore, the comparator can be driven by a single power supply (a power supply without a negative power supply) without operating a circuit corresponding to a reference voltage source during the sampling period.

In the successive approximation type AD conversion circuit according to the second configuration, the voltage applied to the second end of the reference changing capacitor is switched from the ground voltage to the power supply voltage, so that the voltage of the first comparison wiring is set to a predetermined value. The voltage may be increased by a voltage amount (V1 _SHT ), and the second comparison voltage may have the predetermined voltage amount as a voltage value in the successive approximation period (third configuration).

In the successive approximation type AD conversion circuit according to the second or third configuration, the reference change switch includes a first switching terminal (T ₁ ) to which the power supply voltage is applied, a second switching terminal (T 1 ) to which the ground voltage is applied. ₂ ) and a common terminal (T ₃ ) connected to the second end of the reference changing capacitor, and the control circuit is configured to turn on the ground shorting switch when transitioning from the sampling period to the successive approximation period. a first transition switching operation (S22) for switching from on to off; and a second transition switching operation (S23) for switching the connection destination of the common terminal in the reference change switch from the second switching terminal to the first switching terminal. may be performed simultaneously, or the second transition switching operation may be performed after the first transition switching operation (fourth configuration).

In the successive approximation type AD conversion circuit according to any of the first to fourth configurations, the control circuit may sequentially switch states of the switch array by binary search based on the comparison result signal during the successive approximation period. A configuration (fifth configuration) may be used in which the value of the digital output signal is determined bit by bit.

In the successive approximation type AD conversion circuit according to the fifth configuration, the digital output signal is an N-bit digital signal having the first to Nth bits, and the capacitor array has the first to Nth bits. The switch array has first to Nth capacitors (C[1] to C[N]) corresponding to the bits and each having a first end and a second end, and the switch array corresponds to the first to Nth capacitors. the first to Nth switches (S[1] to S[N]), the first comparison wiring is provided on the first end side of each of the first to Nth capacitors, and the i-th switch is It has a first switching terminal (Ta), a second switching terminal (Tb or Tc), a third switching terminal (Tb or Tc), and a common terminal (T _COM ) connected to the second end of the i-th capacitor, and In each of the first to Nth switches, the analog input signal is applied to the first switching terminal, the power supply voltage is applied to one of the second switching terminal and the third switching terminal, and the ground voltage is applied to the other one. and the control circuit connects the first switching terminal to the common terminal of each of the first to Nth switches in the sampling period, and connects the first switching terminal to the common terminal of each of the first to Nth switches in the subsequent successive approximation period. The value of each bit of the digital output signal is determined by binary search based on the comparison result signal in a state where the second or third switching terminal is selectively connected to the common terminal of each of It may be a configuration (sixth configuration) that represents an integer of 2 or more, and i represents a natural number of N or less.

In the successive approximation type AD conversion circuit according to the sixth configuration, the first ends of the first to Nth capacitors are all connected to the first comparison wiring, or among the first to Nth capacitors, The first ends of some of the capacitors are connected to the first comparison wiring, while scaling capacitors (for example, Cs; see FIG. 19) are connected in series between the first ends of the remaining capacitors and the first comparison wiring. A configuration (seventh configuration) may also be used.

Another successive approximation type AD conversion circuit according to one aspect of the present disclosure converts a difference signal (Sdif) between a first analog input signal (AinP) and a second analog input signal (AinN) into a digital output signal (Dout). A successive approximation type AD conversion circuit (2) configured to do this, comprising a first capacitor array and a first switch array connected to the first capacitor array, to which the first analog input signal is applied during a sampling period. By connecting wiring to the first capacitor array via the first switch array, charges corresponding to the first analog input signal are accumulated in each capacitor in the first capacitor array, and A first comparison voltage (V1) based on the accumulated charge of the first capacitor array while a predetermined power supply voltage or ground voltage is supplied to each capacitor in the first capacitor array through the first switch array during the comparison period. a first capacitor type DAC (10P) configured to generate electricity on a first comparison wiring (WR1); a second capacitor array; and a second switch array connected to the second capacitor array; By connecting a wiring to which the second analog input signal is applied to the second capacitor array via the second switch array, a charge corresponding to the second analog input signal is applied to each capacitor in the second capacitor array. a second comparison based on the accumulated charge of the second capacitor array in a state where the power supply voltage or the ground voltage is supplied to each capacitor in the second capacitor array via the second switch array in the successive approximation period; A second capacitor type DAC (10N) configured to generate a voltage (V2) in a second comparison wiring (WR2), connected to the first comparison wiring and the second comparison wiring, and connected to the second comparison wiring in the successive approximation period. a comparator (20) configured to compare a first comparison voltage and the second comparison voltage to generate a comparison result signal (S _CMP ); and a control circuit (30) configured to determine the value of the digital output signal while controlling each state of the second switch array, and a first ground short circuit provided between the first comparison wiring and ground. a first _{reference changing capacitor (C RCP )} having a first end connected to the first comparison wiring; and a second end of the first reference changing capacitor having a predetermined a first reference change switch (S _RCP ) configured to selectively apply a power supply voltage or a ground voltage; a second ground shorting switch (S _GN ) provided between the second comparison wiring and the ground; , the power supply voltage or the ground voltage is selected for a second reference changing capacitor ( _CRCN ) having a first end connected to the second comparison wiring, and a second end of the second reference changing capacitor. This is a configuration (eighth configuration) including a second reference change switch (S _RCN ) configured to provide a second reference change switch (S RCN ).

This configuration eliminates the need to operate a circuit corresponding to a reference voltage source during the sampling period, thereby reducing power consumption.

In the successive approximation type AD conversion circuit according to the eighth configuration, the control circuit controls the first comparison wiring by turning on the first ground shorting switch and the second ground shorting switch during the sampling period. and applying the ground voltage to the second comparison wiring, turning off the first ground shorting switch and the second ground shorting switch in the successive approximation period, and the control circuit Through the control of the second reference change switch, the ground voltage is applied to each second end of the first reference change capacitor and the second reference change capacitor during the sampling period, and during the successive approximation period. It may be a configuration (ninth configuration) that provides the power supply voltage.

Thereby, after sampling the analog input signal, each reference change switch and each reference change capacitor can change (shift) the reference voltage of each comparison voltage to a higher level side. Therefore, the comparator can be driven by a single power supply (a power supply without a negative power supply) without operating a circuit corresponding to a reference voltage source during the sampling period.

In the successive approximation type AD conversion circuit according to the ninth configuration, the voltage applied to the second end of the first reference changing capacitor is switched from the ground voltage to the power supply voltage, so that the voltage of the first comparison wiring increases by a predetermined voltage amount, and the voltage applied to the second end of the second reference changing capacitor is switched from the ground voltage to the power supply voltage, so that the voltage of the second comparison wiring increases by the predetermined voltage amount. A configuration (tenth configuration) may also be used.

In the successive approximation type AD conversion circuit according to the ninth or tenth configuration, the first reference change switch includes a first switching terminal (T ₁ ) to which the power supply voltage is applied, and a second switching terminal to which the ground voltage is applied. (T ₂ ) and a common terminal (T ₃ ) connected to the second end of the first reference change capacitor, and the second reference change switch has a first switching terminal (T ₁ ), the control circuit has a second switching terminal (T ₂ ) to which the ground voltage is applied and a common terminal (T ₃ ) connected to the second end of the second reference changing capacitor; to the successive approximation period, in the first transition switching operation (S22) of switching the first and second ground short switches from on to off, and in each of the first and second reference change switches. A second transition switching operation (S23) for switching the connection destination of the common terminal from the second switching terminal to the first switching terminal is performed simultaneously, or the first transition switching operation is performed and then the second transition switching operation is performed. A configuration (eleventh configuration) may also be used.

In the successive approximation type AD conversion circuit according to any of the eighth to eleventh configurations, the control circuit performs binary search on the first and second switch arrays based on the comparison result signal in the successive approximation period. A configuration (twelfth configuration) may be used in which the value of the digital output signal is determined bit by bit while sequentially switching states.

In the successive approximation type AD conversion circuit according to the twelfth configuration, the digital output signal is an N-bit digital signal having the first to Nth bits, and each capacitor array has the first to Nth bits. It has first to Nth capacitors (C[1] to C[N]) corresponding to the bits and each having a first end and a second end, and each switch array corresponds to the first to Nth capacitors. the first to Nth switches (S[1] to S[N]), and the first comparison wiring is provided at each first end side of the first to Nth capacitors in the first capacitor array. , the second comparison wiring is provided on the first end side of each of the first to Nth capacitors in the second capacitor array, and in each switch array, the i-th switch is connected to the first switching terminal (Ta), the second It has a switching terminal (Tb or Tc), a third switching terminal (Tb or Tc), and a common terminal (T _COM ) connected to the second end of the i-th capacitor, and In each of the N switches, the first analog input signal is applied to the first switching terminal, the power supply voltage is applied to one of the second switching terminal and the third switching terminal, and the ground voltage is applied to the other. , in each of the first to Nth switches in the second switch array, the second analog input signal is applied to the first switching terminal, and the second analog input signal is applied to either the second switching terminal or the third switching terminal. The power supply voltage is applied and the ground voltage is applied to the other side, and the control circuit connects the first switching terminal to the common terminal of each of the first to Nth switches of each switch array during the sampling period, and then In the successive approximation period, based on the comparison result signal in a state where the second or third switching terminal is selectively connected to the common terminal of each of the first to Nth switches of each switch array, The configuration may be such that the value of each bit of the digital output signal is determined by binary search, where N represents an integer greater than or equal to 2, and i represents a natural number less than or equal to N (a thirteenth configuration).

In the successive approximation AD conversion circuit according to the thirteenth configuration, first ends of the first to Nth capacitors in the first capacitor array are all connected to the first comparison wiring, and All the first ends of the first to Nth capacitors in the first capacitor array are connected to the second comparison wiring, or the first ends of some of the first to Nth capacitors in the first capacitor array are connected to the second comparison wiring. is connected to the first comparison wiring, while a scaling capacitor is provided in series between the first ends of the remaining capacitors and the first comparison wiring, and Among the N capacitors, first ends of some of the capacitors are connected to the second comparison wiring, while other scaling capacitors are connected in series between the first ends of the remaining capacitors and the second comparison wiring. The configuration (fourteenth configuration) may also be used.

1, 2 AD converter 10, 10_1, 10_2, 10P, 10N DAC
11, 11_1, 11_2 Capacitor array 12, 12_1, 12_2 Switch array 20 Comparator 30 Control circuit 31 Register 40, 40a, 40b Voltage generation circuit C[1] to C[N] Capacitor S[1] to S[N] Switch S _G , S _GP , S _GN switch (ground short circuit switch)
C _RC , C _RCP , C _RCN capacitor (reference change capacitor)
S _RC , S _RCP , S _RCN switch (standard change switch)
WR1, WR2 Comparison wiring V1, V2 Comparison voltage Ain, AinP, AinN Analog input signal Dout Digital output signal Adif Difference signal WR_Ain, WR_AinP, WR_AinN, WR_VDD, WR_GND Wiring WR_s, WR_s1, WR_s2 Wiring Cs, Cs1, Cs2 Scaling capacitor Ta, Tb, Tc, T ₁ , T ₂ switching terminal T _COM , T ₃ common terminal C _REF , _CRC ' Capacitor _SG ', S _RC ' Switch

Claims (14)

In a successive approximation type AD conversion circuit configured to convert an analog input signal to a digital output signal,
It has a capacitor array and a switch array connected to the capacitor array, and a wiring to which the analog input signal is applied during a sampling period is connected to the capacitor array via the switch array, thereby generating a charge according to the analog input signal. is stored in each capacitor in the capacitor array, and in a successive approximation period after the sampling period, a predetermined power supply voltage or ground voltage is supplied to each capacitor in the capacitor array via the switch array. a capacitor-type DAC configured to generate a first comparison voltage based on accumulated charge on a first comparison wiring;
The first comparison line is connected to a second comparison line to which a second comparison voltage is applied, and is configured to compare the first comparison voltage and the second comparison voltage in the successive approximation period to generate a comparison result signal. A comparator and
a control circuit configured to determine the value of the digital output signal while controlling the state of the switch array based on the comparison result signal during the successive approximation period;
a ground shorting switch provided between the first comparison wiring and ground;
a reference change capacitor having a first end connected to the first comparison wiring;
A successive approximation type AD conversion circuit, comprising: a reference change switch configured to selectively apply the power supply voltage or the ground voltage to a second end of the reference change capacitor. The control circuit applies the ground voltage to the first comparison wiring by turning on the ground shorting switch during the sampling period, and turning off the ground shorting switch during the successive approximation period,
The control circuit provides the ground voltage during the sampling period and the power supply voltage during the successive approximation period to the second end of the reference change capacitor through control of the reference change switch. The successive approximation type AD conversion circuit according to item 1. The voltage applied to the second end of the reference changing capacitor is switched from the ground voltage to the power supply voltage, so that the voltage of the first comparison wiring increases by a predetermined voltage amount,
3. The successive approximation type AD conversion circuit according to claim 2, wherein the second comparison voltage has the predetermined voltage amount as a voltage value in the successive approximation period. The reference change switch has a first switching terminal to which the power supply voltage is applied, a second switching terminal to which the ground voltage is applied, and a common terminal connected to a second end of the reference change capacitor,
When transitioning from the sampling period to the successive approximation period, the control circuit performs a first transition switching operation of switching the ground shorting switch from on to off, and changing the connection destination of the common terminal in the reference change switch. The sequential operation according to claim 2, wherein the second transition switching operation of switching from the second switching terminal to the first switching terminal is performed simultaneously, or the second transition switching operation is performed after the first transition switching operation is performed. Comparison type AD conversion circuit. 5. The control circuit determines the value of the digital output signal bit by bit while sequentially switching the state of the switch array by binary search based on the comparison result signal in the successive approximation period. The successive approximation type AD conversion circuit described in . The digital output signal is an N-bit digital signal having first to Nth bits,
The capacitor array has first to Nth capacitors corresponding to first to Nth bits, each having a first end and a second end,
The switch array has first to Nth switches corresponding to first to Nth capacitors,
The first comparison wiring is provided at each first end side of the first to Nth capacitors,
The i-th switch has a first switching terminal, a second switching terminal, a third switching terminal, and a common terminal connected to the second end of the i-th capacitor,
In each of the first to Nth switches, the analog input signal is applied to the first switching terminal, the power supply voltage is applied to one of the second switching terminal and the third switching terminal, and the ground is applied to the other one. voltage is applied,
The control circuit connects the first switching terminal to the common terminal of each of the first to Nth switches in the sampling period, and connects the first switching terminal to the common terminal of each of the first to Nth switches in the subsequent successive approximation period. determining the value of each bit of the digital output signal by binary search based on the comparison result signal with the second or third switching terminal selectively connected to the common terminal;
6. The successive approximation type AD conversion circuit according to claim 5, wherein N represents an integer greater than or equal to 2, and i represents a natural number less than or equal to N. The first ends of the first to Nth capacitors are all connected to the first comparison wiring, or the first ends of some of the first to Nth capacitors are connected to the first comparison wiring. 7. The successive approximation type AD conversion circuit according to claim 6, wherein a scaling capacitor is provided in series between the first ends of the remaining capacitors and the first comparison wiring. In a successive approximation type AD conversion circuit configured to convert a difference signal between a first analog input signal and a second analog input signal into a digital output signal,
It has a first capacitor array and a first switch array connected to the first capacitor array, and a wiring to which the first analog input signal is applied during a sampling period is connected to the first capacitor array via the first switch array. By connecting, charges corresponding to the first analog input signal are accumulated in each capacitor in the first capacitor array, and a predetermined power supply voltage or ground voltage is applied to the first switch array in the successive approximation period after the sampling period. a first capacitor-type DAC configured to generate a first comparison voltage on a first comparison wiring based on the accumulated charge of the first capacitor array while being supplied to each capacitor in the first capacitor array through the first capacitor array;
a second capacitor array and a second switch array connected to the second capacitor array, and a wiring to which the second analog input signal is applied during the sampling period is connected to the second capacitor array through the second switch array. By connecting to the second analog input signal, charges corresponding to the second analog input signal are accumulated in each capacitor in the second capacitor array, and in the successive approximation period, the power supply voltage or the ground voltage is connected to the second switch array. a second capacitor type DAC configured to generate a second comparison voltage on a second comparison wiring based on the accumulated charge of the second capacitor array while being supplied to each capacitor in the second capacitor array;
a comparator connected to the first comparison wiring and the second comparison wiring and configured to compare the first comparison voltage and the second comparison voltage in the successive approximation period to generate a comparison result signal;
a control circuit configured to determine the value of the digital output signal while controlling each state of the first switch array and the second switch array based on the comparison result signal during the successive approximation period;
a first ground shorting switch provided between the first comparison wiring and ground;
a first reference changing capacitor having a first end connected to the first comparison wiring;
a first reference change switch configured to selectively apply a predetermined power supply voltage or ground voltage to a second end of the first reference change capacitor;
a second ground shorting switch provided between the second comparison wiring and ground;
a second reference changing capacitor having a first end connected to the second comparison wiring;
A successive approximation type AD conversion circuit, comprising: a second reference change switch configured to selectively apply the power supply voltage or the ground voltage to a second end of the second reference change capacitor. The control circuit applies the ground voltage to the first comparison wiring and the second comparison wiring by turning on the first ground shorting switch and the second ground shorting switch during the sampling period, and applies the ground voltage to the first comparison wiring and the second comparison wiring, and During the comparison period, the first ground shorting switch and the second ground shorting switch were turned off,
The control circuit controls each second end of the first reference change capacitor and the second reference change capacitor during the sampling period by controlling the first reference change switch and the second reference change switch. 9. The successive approximation type AD conversion circuit according to claim 8, wherein the ground voltage is applied during the successive approximation period, and the power supply voltage is applied during the successive approximation period. The voltage applied to the second end of the first reference changing capacitor is switched from the ground voltage to the power supply voltage, so that the voltage of the first comparison wiring increases by a predetermined voltage amount,
10. The voltage of the second comparison wiring increases by the predetermined voltage amount by switching the voltage applied to the second end of the second reference changing capacitor from the ground voltage to the power supply voltage. Successive approximation type AD conversion circuit. The first reference changing switch has a first switching terminal to which the power supply voltage is applied, a second switching terminal to which the ground voltage is applied, and a common terminal connected to a second end of the first reference changing capacitor,
The second reference changing switch has a first switching terminal to which the power supply voltage is applied, a second switching terminal to which the ground voltage is applied, and a common terminal connected to a second end of the second reference changing capacitor,
The control circuit performs a first transition switching operation of switching the first and second ground shorting switches from on to off when transitioning from the sampling period to the successive approximation period, and the first and second reference changing switches. A second transition switching operation for switching the connection destination of the common terminal from the second switching terminal to the first switching terminal is performed simultaneously in each of the switches, or the first transition switching operation is performed and then the second transition is performed. The successive approximation type AD conversion circuit according to claim 9, which performs a switching operation. 9. The control circuit determines the value of the digital output signal bit by bit while sequentially switching the states of the first and second switch arrays by binary search based on the comparison result signal in the successive approximation period. The successive approximation type AD conversion circuit according to any one of items 1 to 11. The digital output signal is an N-bit digital signal having first to Nth bits,
Each capacitor array has first to Nth capacitors corresponding to first to Nth bits, each having a first end and a second end,
Each switch array has first to Nth switches corresponding to first to Nth capacitors,
The first comparison wiring is provided at each first end side of the first to Nth capacitors in the first capacitor array,
The second comparison wiring is provided at each first end side of the first to Nth capacitors in the second capacitor array,
In each switch array, the i-th switch has a first switching terminal, a second switching terminal, a third switching terminal, and a common terminal connected to the second end of the i-th capacitor;
In each of the first to Nth switches in the first switch array, the first analog input signal is applied to the first switching terminal, and the power source is applied to one of the second switching terminal and the third switching terminal. voltage is applied and the ground voltage is applied to the other side,
In each of the first to Nth switches in the second switch array, the second analog input signal is applied to the first switching terminal, and the power source is applied to either the second switching terminal or the third switching terminal. voltage is applied and the ground voltage is applied to the other side,
The control circuit connects the first switching terminal to the common terminal of each of the first to Nth switches of each switch array in the sampling period, and connects the first switching terminal to the common terminal of each of the first to Nth switches of each switch array in the subsequent successive approximation period. Based on the comparison result signal in a state where the second or third switching terminal is selectively connected to the common terminal of each of the first to Nth switches, the value of each bit of the digital output signal is determined by binary search. decided,
13. The successive approximation type AD conversion circuit according to claim 12, wherein N represents an integer greater than or equal to 2, and i represents a natural number less than or equal to N. The first ends of the first to Nth capacitors in the first capacitor array are all connected to the first comparison wiring, and the first ends of the first to Nth capacitors in the second capacitor array are all connected to the first comparison wiring. connected to the second comparison wiring, or
Among the first to Nth capacitors in the first capacitor array, first ends of some of the capacitors are connected to the first comparison wiring, while first ends of the remaining capacitors are connected to the first comparison wiring. scaling capacitors are provided in series between them, and among the first to Nth capacitors in the second capacitor array, first ends of some of the capacitors are connected to the second comparison wiring, while the remaining 14. The successive approximation type AD conversion circuit according to claim 13, wherein another scaling capacitor is provided in series between the first end of the capacitor and the second comparison wiring.

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