JP2023090486A - Semiconductor device - Google Patents

Abstract

To provide a vertical semiconductor device capable of improving a breakdown voltage.SOLUTION: A vertical semiconductor device comprises a semiconductor layer, a gate electrode, and a source electrode. The semiconductor layer comprises a drift and a JFET region of a first conductivity type, a body region of a second conductivity type adjacent to the JFET region, and a source region of the first conductivity type. The semiconductor layer comprises a trench reaching the drift region through the source region and the body region from an upper surface of the semiconductor layer. The gate electrode is arranged on an upper surface of the JFET region and an upper surface of a body region of a portion partitioning the JFET region and the source region via a gate insulation film. The source electrode is electrically connected to the source region. The whole of the drift region exposed in the trench is covered by a trench insulation film. A conductor is arranged inside the trench via the trench insulation film. The conductor is electrically connected to the source electrode.SELECTED DRAWING: Figure 1

Description

The technology disclosed in this specification relates to a vertical semiconductor device.

Patent Document 1 discloses an example of a vertical semiconductor device having a planar gate.

Japanese Unexamined Patent Application Publication No. 2012-33731

In the planar gate structure, a channel region is formed on the surface of the semiconductor layer. If the electric field increases on the surface of the semiconductor layer when a reverse bias voltage is applied when the element is turned off, the electric field concentrates in the channel region, resulting in a decrease in breakdown voltage.

One embodiment of the semiconductor device disclosed in this specification is a vertical semiconductor device that includes a semiconductor layer, and a gate electrode and a source electrode that are arranged on an upper surface of the semiconductor layer. The semiconductor layer comprises a drift region of first conductivity type. The semiconductor layer is disposed on the drift region and includes a first conductivity type JFET region disposed at a position exposed to the top surface of the semiconductor layer. A semiconductor layer is disposed on the drift region, adjacent to the JFET region, and includes a body region of a second conductivity type disposed at a position exposed to the top surface. The semiconductor layer is separated from the drift region and the JFET region by a body region and includes a source region of a first conductivity type located at an exposed top surface. The semiconductor layer includes a trench extending from the top surface of the semiconductor layer through the source and body regions to the drift region. The gate electrode is arranged on the upper surface of the JFET region and on the upper surface of the body region separating the JFET region and the source region via a gate insulating film. A source electrode is electrically connected to the source region. The entire drift region exposed in the trench is covered with a trench insulating film. A conductor is arranged inside the trench via a trench insulating film. A conductor is electrically connected to the source electrode.

A conductor is arranged inside the trench via a trench insulating film. A conductor is electrically connected to the source electrode. Thereby, a field plate structure can be formed on the bottom surface of the trench. Due to this field plate structure, the depletion layer can be spread inside the surface of the semiconductor layer, so that the electric field can be shared at positions away from the surface. Since electric field concentration in the channel region arranged on the surface of the semiconductor layer can be alleviated, a high breakdown voltage can be achieved.

The drift region may be exposed below the bottom and sides of the trench. A body region may be exposed on the sides of the trench above the exposed drift region. A trench insulating film may cover a portion of the exposed body region. Details of the effect will be described in Examples.

On the sides of the trench, the trench insulating film may cover an area from the bottom of the trench to a midpoint between the bottom and top surfaces of the exposed body region. Details of the effect will be described in Examples.

The distance from the top surface of the semiconductor layer to the bottom surface of the trench may be in the range of 1 to 3 times the distance from the top surface of the semiconductor layer to the boundary between the drift region and the body region. Details of the effect will be described in Examples.

The thickness of the trench insulating film arranged at the corners of the bottom surface of the trench may be thicker than the thickness of the trench insulating film arranged on the side surfaces and the bottom surface of the trench. Details of the effect will be described in Examples.

The material of the conductor may be the same as the material of the source electrode.

1 is a fragmentary cross-sectional view of a semiconductor device 1 according to Example 1; FIG. It is a simulation result showing the relationship between the depth of the trench T and the breakdown voltage. FIG. 11 is a cross-sectional view of a main part of a semiconductor device 1a of a modified example;

(Structure of semiconductor device 1)
FIG. 1 shows a cross-sectional view of essential parts of a semiconductor device 1 according to a first embodiment. A semiconductor device 1 is a vertical MOSFET having a planar gate structure. The semiconductor device 1 includes a drain electrode 22 , a semiconductor layer 10 , a trench T, a trench insulating film 23 , an embedded electrode 24 , a source electrode 25 , a gate insulating film 26 and a gate electrode 27 .

The semiconductor layer 10 is made of Ga ₂ O ₃ (gallium oxide). The semiconductor layer 10 includes an n ⁺ -type drain region 11, an n ⁻ -type drift region 12, an n-type JFET (Junction Field Effect Transistor) region 13, a p-type body region 14, and an n ⁺ -type source. a region 15; The drain region 11 is provided at a position exposed on the back surface of the semiconductor layer 10 and is in ohmic contact with the drain electrode 22 . The drift region 12 is provided on the drain region 11 and arranged between the drain region 11 and the JFET region 13 and between the drain region 11 and the body region 14 . The drift region 12 is formed by crystal growth from the surface of the drain region 11 using an epitaxial growth technique.

The JFET region 13 is provided on the drift region 12 and extends along the thickness direction (+z direction) of the semiconductor layer 10 from the surface of the drift region 12 to the surface 10a of the semiconductor layer 10. It has a shape protruding from In other words, JFET region 13 extends from surface 10 a of semiconductor layer 10 through body region 14 to drift region 12 . In this embodiment, the impurity concentration of the drift region 12 is 5×10 ¹⁶ (cm ⁻³ ), and the impurity concentration of the JFET region 13 is 5×10 ¹⁷ (cm ⁻³ ).

Body region 14 is provided on drift region 12 , is arranged with JFET region 13 therebetween, and is adjacent to the side surface of JFET region 13 . Source region 15 is provided on body region 14 and is separated from drift region 12 and JFET region 13 by body region 14 .

Trench T extends from surface 10 a of semiconductor layer 10 through source region 15 and body region 14 to reach drift region 12 . The drift region 12 is exposed at the bottom surface Tb of the trench T. As shown in FIG. The entire bottom surface Tb is covered with a trench insulating film 23 . Moreover, the drift region 12, the body region 14, and the source region 15 are exposed from the side surface Ts of the trench T in this order from the lower side. Here, the midpoint HP is defined as the space between the lower surface and the upper surface of the body region 14 exposed on the side surface Ts. On the side surface Ts, a region from the bottom surface Tb to the intermediate point HP is covered with the trench insulating film 23 .

A buried electrode 24 is arranged inside the trench T with a trench insulating film 23 interposed therebetween. Thereby, a field plate structure can be formed on the bottom surface of the trench T. As shown in FIG. In this embodiment, the material of the embedded electrode 24 is the same as the material of the source electrode 25 . Further, in this embodiment, the material of the source electrode 25 is aluminum. The embedded electrode 24 may be formed integrally with the source electrode 25 .

The entire drift region 12 exposed in the trench T is covered with the trench insulating film 23 . The drift region 12 is thereby insulated from the embedded electrode 24 . The lower portion of the body region 14 exposed in the trench T is covered with the trench insulating film 23 . Thereby, a structure is formed in which the upper portion of the body region 14 and the embedded electrode 24 are in contact with each other. This contact portion functions as a hole extraction region HE. The operation of the hole extraction region HE will be described later.

The thickness of the trench insulating film 23 arranged at the corner portion Tc of the trench T is thicker than the thickness of the trench insulating film 23 arranged at the side surface Ts and the bottom surface Tb. Explain the effect. When the trench T functions as a field plate, the electric field concentrates on the corner portion Tc. By selectively thickening the film thickness of the trench insulating film 23 at the corner portion Tc, it is possible to increase the withstand voltage of the corner portion Tc.

A material having a dielectric constant of 23 or less is suitable for the material of the trench insulating film 23 . In this embodiment, the material of the trench insulating film 23 is SiO ₂ (silicon oxide). Note that the thickness of the trench insulating film 23 when silicon oxide is used is preferably 0.2 μm or more from the viewpoint of withstand voltage.

The source electrode 25 is arranged above the surface 10 a of the semiconductor layer 10 . The source electrode 25 is in contact with the embedded electrode 24 and electrically connected to the embedded electrode 24 . Source electrode 25 is in ohmic contact with source region 15 via embedded electrode 24 .

The gate electrode 27 is arranged on the surface 10a of the semiconductor layer 10 with the gate insulating film 26 interposed therebetween. The gate electrode 27 is a planar electrode. The gate electrode 27 faces the entire JFET region 13 via the gate insulating film 26 . The gate electrode 27 further faces the body region 14 in the portion separating the JFET region 13 and the source region 15 via the gate insulating film 26 . The gate electrode 27 extends in the depth direction (+y direction) of the drawing and is in contact with a gate electrode wiring (not shown). In this embodiment, the gate insulating film 26 is made of silicon oxide, and the gate electrode 27 is made of polysilicon.

(Operation of semiconductor device 1)
A channel region CR is formed in the vicinity of the surface of the body region 14 that separates the JFET region 13 and the source region 15 . When the semiconductor device 1 is used, a positive voltage is applied to the drain electrode 22 and the source electrode 25 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 27, an inversion layer is formed in the channel region CR and the semiconductor device 1 is turned on. At this time, electrons flow from the source region 15 to the JFET region 13 via the inversion layer. Electrons flowing into the JFET region 13 flow vertically through the JFET region 13 and the drift region 12 toward the drain electrode 22 . Thereby, the drain electrode 22 and the source electrode 25 are electrically connected. When the gate electrode 27 is grounded, the inversion layer of the channel region CR disappears and the semiconductor device 1 is turned off. Thus, the semiconductor device 1 can perform switching operations based on the voltage applied to the gate electrode 27 .

(effect)
In the planar gate structure, a channel region CR is formed near the surface 10a of the semiconductor layer 10. As shown in FIG. When a reverse bias voltage is applied when the semiconductor device 1 is turned off, if the electric field increases at the surface 10a of the semiconductor layer 10, the electric field concentrates on the channel region CR, resulting in a decrease in breakdown voltage. Therefore, the semiconductor device 1 of this specification has a field plate structure on the bottom surface of the trench T. As shown in FIG. With this field plate structure, the depletion layer can be widened on the inner side (that is, the -z direction side) of the surface 10a of the semiconductor layer 10. FIG. Before the electric field on the surface 10a becomes high, the electric field can be shared in the vicinity of the bottom surface Tb of the trench T, which is located away from the surface 10a. Since electric field concentration in the channel region CR arranged on the surface 10a of the semiconductor layer 10 can be alleviated, a high breakdown voltage can be achieved.

Wide-gap semiconductors such as gallium oxide and silicon carbide have a larger bandgap than Si, and therefore have a lower dielectric constant and a depletion layer that is less likely to spread. Therefore, even if a field plate structure is provided on the surface 10a of the semiconductor layer 10, it is difficult to obtain the field plate effect unlike Si. According to the technique of the present specification, by forming a buried field plate on the bottom surface Tb of the trench T, it is possible to sufficiently obtain the effect of the field plate even in a wide-gap semiconductor in which the depletion layer is difficult to spread.

When a high voltage such as a surge is applied when the semiconductor device 1 is turned off, an avalanche breakdown may occur in the vicinity of the trench T adjacent to the pn junction between the drift region 12 and the body region 14 . According to the technique of the present specification, holes generated by this avalanche breakdown can be rapidly discharged to the source electrode 25 via the hole extraction region HE and the embedded electrode 24 . This makes it possible to have a high avalanche resistance.

(Relationship between depth of trench T and breakdown voltage)
A distance from the surface 10a of the semiconductor layer 10 to the bottom surface Tb of the trench T is defined as a trench depth Dt. Also, the distance from surface 10a to the boundary between drift region 12 and body region 14 is defined as body region depth Dp. A breakdown voltage of the semiconductor device 1 was calculated by simulation when the ratio of the trench depth Dt to the body region depth Dp (Dt/Dp ratio) was changed. FIG. 2 shows the calculation results. The vertical axis is the breakdown voltage BV (V) at which breakdown occurs. The horizontal axis is the Dt/Dp ratio. In the simulation, the body region depth Dp was fixed at 1.0 μm and the trench depth Dt was varied within the range of 1 to 10 μm.

In a conventional semiconductor device having no trench T, the trench depth Dt is zero, so the Dt/Dp ratio is zero. The breakdown voltage at this time is defined as the conventional breakdown voltage BV0. The conventional breakdown voltage BV0 was 920 (V), as indicated by the plotted white circles in FIG.

On the other hand, the Dt/Dp ratio is in the range of 1-10 in the semiconductor device 1 of the present specification having the trench T. FIG. . The breakdown voltage at this time is indicated by plotting black circles in FIG. It can be seen that the breakdown voltage BV takes the maximum value when the Dt/Dp ratio is 1.5. Further, when the Dt/Dp ratio is in the range of 1 to 3 (that is, when the trench depth Dt is in the range of 1 to 3 times the body region depth Dp), the breakdown voltage BV is reduced to the conventional breakdown voltage. It can be seen that the BV0 can be improved by 30% or more (see region A1). More preferably, when the Dt/Dp ratio is in the range of 1 to 2, the breakdown voltage BV can be improved by 40 to 50% compared to the conventional breakdown voltage BV0.

(Manufacturing method of semiconductor device 1)
A semiconductor layer 10 having a drain region 11, a drift region 12, a JFET region 13, a body region 14, and a source region 15 is prepared. A gate insulating film 26 and a gate electrode 27 are formed on the surface 10 a of the semiconductor layer 10 . A mask having openings corresponding to the trenches T is formed by a known photolithographic technique. A trench T is processed by a known dry etching technique. A trench insulating film 23 is formed on the bottom surface Tb and side surfaces Ts of the trench T. As shown in FIG.

The trench T is filled with a sacrificial layer. The upper portion of the sacrificial layer is removed by dry etching until the position of the upper surface of the sacrificial layer coincides with the intermediate point HP. The trench insulating film 23 not covered with the sacrificial layer is selectively removed by wet etching. As a result, as shown in FIG. 1, a structure is formed in which the region from the bottom surface Tb to the intermediate point HP is covered with the trench insulating film 23 .

A buried electrode 24 and a source electrode 25 are formed. The embedded electrode 24 and the source electrode 25 can be integrally formed by collectively forming them. A drain electrode 22 is formed to cover the back surface of the semiconductor layer 10 . Thereby, the semiconductor device 1 shown in FIG. 1 is completed.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims as of the filing. In addition, the techniques exemplified in this specification or drawings can simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

(Modification)
The semiconductor device 1 of FIG. 1 is an example, and is not limited to this form. As shown in the modified semiconductor device 1a shown in FIG. 3, the following various modifications are possible. A portion of the surface of source region 15 may be in direct ohmic contact with source electrode 25 . A p ⁺ -type body contact 16 may be provided in contact with the source electrode 25 . An interlayer insulating film 40 may be provided to cover the gate electrode 27 . The source electrode 25 is arranged on the surface 10 a of the semiconductor layer 10 and may cover the interlayer insulating film 40 . The interlayer insulating film 40 can insulate the gate electrode 27 and the source electrode 25 .

The material _of the semiconductor layer 10 is not limited to _Ga2O3 . For example, Si (silicon), SiC (silicon carbide), GaN (gallium nitride), AlGaN (aluminum gallium nitride), AlN (aluminum nitride), InN (indium nitride), InGaN (indium gallium nitride), mixed crystals thereof, etc. may be

The material of the embedded electrode 24 is not limited to aluminum. Various metals, polysilicon, and the like may be used.

N-type is an example of a first conductivity type. P-type is an example of a second conductivity type. The embedded electrode 24 is an example of a conductor.

1: Semiconductor device 10 Semiconductor layer 10a: Surface 11: Drain region 12: Drift region 13: JFET region 14: Body region 15: Source region 22: Drain electrode 23: Trench insulating film 24: Buried electrode 25: Source electrode 26: Gate insulating film 27: Gate electrode T: Trench Tb: Bottom surface Ts: Side surface

Claims (6)

A vertical semiconductor device comprising a semiconductor layer, and a gate electrode and a source electrode disposed on an upper surface of the semiconductor layer,
The semiconductor layer is
a first conductivity type drift region;
a first conductivity type JFET region disposed on the drift region and disposed at a position exposed to the upper surface of the semiconductor layer;
a body region of a second conductivity type disposed on the drift region, adjacent to the JFET region, and disposed at a position exposed to the top surface;
a source region of a first conductivity type separated from the drift region and the JFET region by the body region and located at a position exposed on the top surface;
a trench extending from the upper surface of the semiconductor layer through the source region and the body region to reach the drift region;
with
the gate electrode is arranged on the upper surface of the JFET region and on the upper surface of the body region in a portion separating the JFET region and the source region via a gate insulating film;
the source electrode is electrically connected to the source region;
the entire drift region exposed in the trench is covered with a trench insulating film;
A conductor is arranged inside the trench via the trench insulating film,
The semiconductor device, wherein the conductor is electrically connected to the source electrode. the drift region is exposed below the bottom and side surfaces of the trench;
the body region is exposed above the exposed drift region on the side surface of the trench;
2. The semiconductor device according to claim 1, wherein said trench insulating film covers the exposed part of said body region. 3. The semiconductor according to claim 2, wherein, on the sides of said trench, said trench insulating film covers an area from the bottom surface of said trench to a midpoint between the exposed lower and upper surfaces of said body region. Device. The distance from the top surface of the semiconductor layer to the bottom surface of the trench is
4. The semiconductor device according to claim 2, wherein the distance is within a range of 1 to 3 times the distance from the upper surface of said semiconductor layer to the boundary between said drift region and said body region. 5. A thickness of said trench insulating film arranged on a corner portion of a bottom surface of said trench is thicker than a thickness of said trench insulating film arranged on a side surface and a bottom surface of said trench. 2. The semiconductor device according to item 1. 6. The semiconductor device according to claim 1, wherein the material of said conductor is the same as the material of said source electrode.

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