JP2022539644A - Staircase structure in three-dimensional memory device and method for forming same - Google Patents

Abstract

Embodiments of a 3D memory device having a staircase structure and method for forming the same are disclosed. In one example, a 3D memory device includes a memory array structure and a staircase structure. A staircase structure is located in the middle of the memory array structure and divides the memory array structure along the lateral direction into a first memory array structure and a second memory array structure. The staircase structure includes a plurality of laterally extending steps and a bridge structure in contact with the memory array structure. A step includes a step over one or more dielectric pairs. The tier includes conductor portions electrically connected to the bridge structure and electrically connected to the memory array structure through the bridge structure. Along a second lateral direction perpendicular to the lateral direction, the width of the conductor portion decreases away from the bridge structure.

Description

Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods thereof.

Planar memory cells are shrunk to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become difficult and expensive. As a result, the memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

Embodiments of 3D memory devices with staircase structures and methods for forming the same are disclosed herein.

In one example, a 3D memory device includes a memory array structure and a staircase structure. A staircase structure is located in the middle of the memory array structure and divides the memory array structure along the lateral direction into a first memory array structure and a second memory array structure. The staircase structure includes a plurality of laterally extending steps and a bridge structure in contact with the first memory array structure and the second memory array structure. The multiple stages include a stage over one or more dielectric pairs. The step includes a conductor portion overlying the upper surface of the step and in contact with and electrically connected to the bridge structure, and a dielectric portion at the same level and in contact with the conductor portion. The tier is electrically connected to at least one of the first memory array structure and the second memory array structure via the bridge structure. Along a second lateral direction perpendicular to the lateral direction, the width of the conductor portion decreases away from the bridge structure.

In another example, a 3D memory device includes a memory array structure and a landing structure in contact with the memory array structure. The landing structure includes a plurality of landing regions at respective depths, each extending along a lateral direction, and a bridge structure in contact with the memory array structure. The plurality of landing areas each include a conductor portion on the respective top surface and a dielectric portion at the same level and in contact with the conductor portion. The conductor portion is electrically connected to the memory array structure through the bridge structure. The width of the conductor portion decreases away from the bridge structure along a second lateral direction perpendicular to the lateral direction. Each of the plurality of landing regions overlies one or more dielectric pairs.

In yet another example, a 3D memory device includes a memory array structure and a staircase structure. The stair structure includes a plurality of steps extending along the lateral direction. The plurality of steps includes a step having a conductor portion on top of the step and a dielectric portion at the same level and in contact with the conductor portion. The conductor portion is electrically connected to the memory array structure. Along a second lateral direction perpendicular to the lateral direction, the width of the conductor portion varies.

In yet another example, a method for forming a staircase structure for a 3D memory device includes the following acts. First, a plurality of steps is formed having a plurality of first sacrificial layers and a plurality of first dielectric layers interleaved within the plurality of steps. A bridge structure is formed in contact with the plurality of steps, the bridge structure having a plurality of alternating second sacrificial layers and a plurality of second dielectric layers. Each first sacrificial layer is in contact with a respective second sacrificial layer at the same level and each first dielectric layer is in contact with a respective second dielectric layer at the same level. A sacrificial portion is formed in the first sacrificial layer corresponding to at least one of the steps. A sacrificial portion is on the top surface of each step and is cut at the edge of the upper step. The second sacrificial layer and sacrificial portion are removed by the same etching process to form a plurality of lateral recesses and a lateral recess, respectively. A plurality of conductor layers are formed within the lateral recess, and conductor portions are formed within the lateral recess and in contact with respective ones of the conductor layers.

The accompanying drawings, which are incorporated in and form a part of the specification, illustrate embodiments of the disclosure and, together with the description, explain the principles of the disclosure and enable those skilled in the art to make and make the disclosure. functions to allow it to be used

FIG. 4A is a schematic diagram of an exemplary 3D memory device having a staircase structure, according to some embodiments of the present disclosure; 1B is a top perspective view of an exemplary staircase structure of the 3D memory device shown in FIG. 1A, according to some embodiments of the present disclosure; FIG. 1B is a plan view of the exemplary 3D memory device shown in FIG. 1A, according to some embodiments of the present disclosure; FIG. 1B is another plan view of the exemplary 3D memory device shown in FIG. 1A, according to some embodiments of the present disclosure; FIG. 1B is a detailed top perspective view of an exemplary staircase structure of the 3D memory device shown in FIG. 1A, according to some embodiments of the present disclosure; FIG. FIG. 4B is a schematic diagram of another exemplary 3D memory device having a staircase structure, according to some embodiments of the present disclosure; 2B is a top perspective view of an exemplary staircase structure of the 3D memory device shown in FIG. 2A, according to some embodiments of the present disclosure; FIG. 2B is a plan view of the exemplary 3D memory device shown in FIG. 2A, according to some embodiments of the present disclosure; FIG. FIG. 4A is a cross-sectional view of an exemplary 3D memory device having a staircase structure, according to some embodiments of the present disclosure; 3B is another cross-sectional view of the 3D memory device shown in FIG. 3A, according to some embodiments of the present disclosure; FIG. 3B is another cross-sectional view of the 3D memory device shown in FIG. 3A, according to some embodiments of the present disclosure; FIG. 3D is a detailed cross-sectional view of the conductor portion shown in FIG. 3C, according to some embodiments of the present disclosure; FIG. 4A-4D illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device, according to some embodiments of the present disclosure; 4A-4D illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device, according to some embodiments of the present disclosure; 4A-4D illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device, according to some embodiments of the present disclosure; 4A-4D illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device, according to some embodiments of the present disclosure; 4A-4D illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device, according to some embodiments of the present disclosure; FIG. 4 illustrates exemplary steps prior to an ion implantation process, according to some embodiments; [0014] Figure 4 illustrates exemplary steps after an ion implantation process, according to some embodiments; 4 is a flowchart of a method for forming an exemplary staircase structure of a 3D memory device, according to some embodiments;

Embodiments of the present disclosure will be described with reference to the accompanying drawings.

Although specific configurations and arrangements are described, it should be understood that this is done for illustration only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that the present disclosure can be employed in various other applications.

References herein to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like refer to the particular embodiment being described. It should be noted that while not all embodiments may include the features, structures, or properties of a particular feature, structure, or property. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when certain features, structures, or characteristics are described in the context of one embodiment, such features, structures, or characteristics are described in the context of other embodiments, whether explicitly described or not. or affecting properties are within the knowledge of those skilled in the art.

In general, the terminology can be understood, at least in part, from its usage in context. For example, as used herein, the term "one or more" may be used to describe a feature, structure, or property in the singular, at least in part depending on the context; It may be used to describe a combination of features, structures, or properties in multiple senses. Similarly, terms such as "a," "an," or "the," again, depending at least in part on the context, shall convey singular usage. It may be understood or understood to convey multiple usages. In addition, the term "based on" is not necessarily intended to convey an exclusive set of factors, and instead is again at least partially contextually delineated. It can be understood that the presence of additional factors, including but not limited to, may be permissible.

"On" not only means "directly on" something, but also includes "on" something with intermediate features or intervening layers, and "on" something. "Above" or "over" means not only "above" or "over" something, but also whether it is an intermediate form or As can also be meant to be "above" or "over" something (i.e., directly on something) without intervening layers, the present disclosure It will be readily understood that the meanings of "on", "above", and "over" in should be interpreted broadly.

In addition, spatially related terms such as "beneath", "below", "lower", "above", "upper", etc. Terminology may be used herein to facilitate description to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatially related descriptors used herein may likewise be interpreted accordingly. good.

As used herein, the term "substrate" refers to the material upon which subsequent layers of material are added. The substrate itself can be patterned. Materials added on top of the substrate may be patterned or left unpatterned. Further, substrates can include a wide variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a section of material that includes regions having a thickness. A layer can extend over the entire structure of the underlying or overlying layer or have an extent that is less than the extent of the underlying or overlying structure. Additionally, a layer can be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can lie between any pair of horizontal surfaces, or between the top and bottom surfaces of a continuous structure. The layers can extend laterally, perpendicularly and/or along the tapered surface. The substrate can be a layer and can include one or more layers therein and/or have one or more layers thereon, on its top side, and/or on its bottom side. can be done. A layer can include multiple layers. For example, interconnect layers include one or more conductor and contact layers in which interconnect lines and/or vertical interconnect access (VIA) contacts are formed and one or more dielectric layers. be able to.

As used herein, the term "nominal" refers to the desired or intended value of a property or parameter for a component or process operation that is set during the design stage of a product or process. with a range of values above and/or below the value of . The range of values may be due to slight variations or tolerances in the manufacturing process. As used herein, the term "about" indicates the value of a given quantity that can vary based on the particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may be used for a given amount that varies between, for example, 10-30% of the value (eg, ±10%, ±20% or ±30% of the value). value can be indicated.

As used herein, the term "3D memory device" refers to a vertically oriented string of memory cell transistors on a laterally oriented substrate such that the memory string extends vertically with respect to the substrate. Refers to a semiconductor device having a memory string, such as a NAND memory string, referred to herein as a "memory string". The term "perpendicular/perpendicularly" as used herein nominally means perpendicular to the outer surface of the substrate.

In some 3D memory devices, memory cells for storing data are vertically stacked via stacked storage structures (eg, memory stacks). 3D memory devices typically include staircase structures formed near stacked storage structures for purposes such as wordline fanout. As the demand for higher storage capacity continues to increase, the number of vertical levels of stacked storage structures also increases, allowing word line VIA contacts to be placed on top of the tiers without piercing the contacts and causing short circuits. becoming more difficult to form. For example, wordline VIA contacts are often formed by forming an opening in the insulating structure in which the stepped structure is located that contacts the step (e.g., the landing area of the step) and filling the opening with a conductive material. be done. Conventionally, these openings formed to contact the steps at different depths/heights are formed in the same etching process. Due to variations in opening depth, openings are often not etched evenly or as desired. For example, openings in contact with lower steps (e.g., deeper openings) and openings in contact with higher steps (e.g., shallower openings) are exposed to the same etch time, resulting in higher steps. The opening in contact with is overetched. Overetching can cause conductive layers (eg, word lines) on top of higher steps to be unnecessarily damaged or even etched. The wordline VIA contacts may unnecessarily contact other conductor layers beneath their respective conductor layers, causing punch-through leading to shorts or unwanted leakage. In order to solve this problem, efforts have been made to increase the thickness of the conductor layer for landing. However, a thicker landing area still cannot adequately reduce the likelihood of punch-through and makes the fabrication process more difficult.

Various embodiments according to the present disclosure provide stair structures and methods of making the same. A staircase structure having multiple steps can include a conductor portion on the top surface of at least one step and a dielectric structure including one or more dielectric pairs below the conductor portion. The conductor portion covers at least the landing area of each step (eg, part of the step) so that the wordline VIA contacts can be in contact with and electrically connected to the respective step. The thickness of the dielectric structure may be equal to the distance from the bottom surface of the conductor portion to the top surface of the substrate, and is the desired thickness to prevent interference between conductor portions at different levels due to punch-through. Along a lateral direction perpendicular to the direction in which the step extends, the width of each conductor portion may gradually decrease from the ends.

In embodiments of the present disclosure, the conductor portion includes overlapping portions and non-overlapping portions. Overlap refers to the portion of a conductor portion that overlaps with the step directly above and/or below (or the conductor portion of the step directly above/below). Non-overlapping portion refers to the portion of the conductor portion that does not overlap with an upper or lower step. A word line VIA contact may be formed on the non-overlapping portion of the conductor portion. The non-overlapping portion of the conductor portion can have a large landing area, which is desirable for the respective wordline VIA contacts to be formed thereon. In some embodiments, along the direction in which the step extends, the dimensions of the non-overlapping portions of the conductor portions are nominally the same as the dimensions of the step.

In some embodiments, the dielectric structure below the conductor portion includes a respective dielectric layer and one or more underlying dielectric pairs, each dielectric pair in an underlying step. It includes a body portion and a dielectric layer. In some embodiments, the number of dielectric pairs under the conductor portion of each level is equal to the number of levels/levels under the level. Even if punch-through occurs on any conductor portion, the wordline VIA contact has no contact on the lower tier conductor portion (or wordline) and leakage or shorting can be reduced/eliminated. As a result, forming the opening becomes easier.

In various embodiments, the steps are formed in the middle of the memory array structure or in stepped structures located on the sides of the memory array structure. The staircase structure can include a bridge structure having a plurality of alternating conductor and dielectric layers. The conductor layer is conductively connected to memory cells in the memory array structure. The conductor portion of each step may contact the conductor layer at the same level along a direction perpendicular to the direction in which the step extends so that a voltage can be applied to the memory cell through the conductor portion and the conductor layer at the same level.

An ion implantation process is performed before the gate exchange to form the conductor portion. An ion implantation process is employed to form the sacrificial portion, which is the ion implantation treatment of the respective sacrificial layer on the top surface of the step. The ion implantation process can change the physical properties of the treated portion such that the sacrificial portion can be etched at a faster rate than other portions of the sacrificial layer not treated by the ion implantation. As a result, one etching process is required to simultaneously remove the sacrificial layer (e.g., for forming the word lines in the bridge structure) and the sacrificial portion so that the lateral recess and lateral recess can be formed. can be applied. The dielectric structure under the sacrificial portion can be reserved. In some embodiments, the lateral recess includes an overetch of the sacrificial layer beneath the step directly above due to the higher etch rate on the sacrificial portion. Conductive material is deposited to fill the lateral recesses in each step and the lateral recesses in the bridge structure. Multiple conductor layers may be formed within the bridge structure. A plurality of conductor portions, each in a respective step and overlying a respective dielectric structure, may be formed within the steps. In some embodiments, the overetch forms an overlap between adjacent conductor portions after being filled with conductor portions.

1A-1C and 2A-2C show schematic diagrams of 3D memory devices 100 and 200, respectively, having staircase structures, according to some embodiments. Specifically, FIGS. 1A-1C show layouts in which the staircase structure is located in the middle of the memory plane, and FIGS. 2A-2C show layouts in which the staircase is located on both sides of the memory plane. The staircase structure of the present disclosure can be formed in both 3D memory devices 100 and 200. FIG. As an example for explaining the present disclosure, embodiments focus on the structure and fabrication process of the staircase structure within the 3D memory device 100 . In some embodiments, staircase structures within 3D memory device 200 may be formed in a similar fabrication process. Note that the x-axis and y-axis are included in FIGS. 1A and 2A to indicate two orthogonal (orthogonal) directions in the plane of the wafer. The x direction is the word line direction of each 3D memory device and the y direction is the bit line direction of each 3D memory device. Note that the structures in this disclosure are for illustrative purposes only and therefore do not represent dimensions, ratios or shapes in the actual product.

FIG. 1A shows a schematic diagram of an exemplary 3D memory device 100 having a staircase structure 102, according to some embodiments of the present disclosure. In some embodiments, 3D memory device 100 includes multiple memory planes. The memory plane comprises a first memory array structure 104-1, a second memory array structure 104-2, and a staircase structure 102 intermediate the first and second memory array structures 104-1 and 104-2. can contain. The first and second memory array structures 104-1 and 104-2, together considered memory array structures, may or may not have the same area. In some embodiments, the staircase structure 102 is in the middle of the first and second memory array structures 104-1 and 104-2. For example, first and second memory array structures 104-1 and 104-2 may be symmetrical in the x-direction with respect to staircase structure 102. FIG. In some examples, the staircase structure 102 is arranged between the first and second memory array structures 104-1 and 104-2 such that the first and second memory array structures 104-1 and 104-2 can have different sizes and/or numbers of memory cells. It is understood that it may be in the middle of the memory array structure 104-1/104-2 rather than in the middle. In some embodiments, the 3D memory device 100 has memory cells in the form of arrays of NAND memory strings (not shown in FIG. 1A) within first and second memory array structures 104-1 and 104-2. NAND flash memory device provided. The first and second memory array structures 104-1 and 104-2 may be any other memory array structures including, but not limited to, gate line slits (GLS), through array contacts (TAC), array common source (ACS), etc. It can contain suitable components.

Each word line in the memory plane that extends laterally in the x-direction (not shown in FIG. 1A) is split into two portions by the staircase structure 102: a first word line portion and a second word line portion across the first memory array structure 104-1. and a second wordline portion across the two memory array structures 104-2. The two portions of each word line may be electrically connected by a bridge structure (shown as bridge structure 108 in staircase structure 102 in FIGS. 1B and 1C) at respective steps in staircase structure 102 . A row decoder (not shown) may be formed directly above, below, or in close proximity to each staircase structure 102 . Each row decoder can bi-directionally drive word lines in opposite directions from the middle of the memory plane.

A detailed structure of the stair structure 102 is shown in FIGS. 1B and 1C. FIG. 1B shows a top plan view of staircase structure 102 in 3D memory device 100 . FIG. 1C shows a top view of staircase structure 102 and its spatial relationship with adjacent first and second memory array structures 104-1 and 104-2. For ease of illustration, FIG. 1C depicts only one staircase structure 102 . In various embodiments, the 3D memory device 100 includes a plurality of staircase structures, for example, between first and second memory array structures 104-1 and 104-2 aligned with the staircase structure 102 along the y-direction. including. For example, another staircase structure can be the same as staircase structure 102 and can be a mirror staircase structure 102 along the y-direction. Also, other possible structures, such as dummy staircases, have been omitted in staircase structure 102 for ease of illustration.

FIG. 1B shows a staircase structure 102 having a staircase 106 and a bridge structure 108 in contact with each other. FIG. 1E shows a detailed 3D perspective view of the stair structure 102. FIG. The stepped structure 102 may comprise silicon (eg, monocrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. can be on a substrate 10 (shown in FIG. 1D) on which the

The staircase 106 may include multiple steps 114 extending along the wordline direction, eg, the x-direction. Each step 114 may have different depths and landing areas along the z-direction, for example, to form contact with corresponding wordline VIA contacts. Each step 114 (denoted as a “level”) of staircase 106 may include one or more material layer pairs. In some embodiments, the top material layer of each step 114 includes conductor portions for interconnection with wordline VIA contacts in the vertical direction. In some embodiments, all two adjacent steps 114 of stairs 106 are offset by nominally the same distance in the z-direction and by nominally the same distance in the x-direction. In this way, each offset can form a "landing area" for interconnection with the wordline contacts of the 3D memory device in the z-direction. In some embodiments, each step 114 includes at least one dielectric layer below the conductor portion.

The bridge structure 108 may include vertically alternating conductor and dielectric layers (not shown), where the conductor layers (e.g., metal or polysilicon layers) are part of the word lines. can function. A staircase 106 in which the wordlines in the staircase 106 are disconnected from the memory array structure (eg, 104-1 and/or 104-2) in the x-direction (eg, in the positive x-direction, the negative x-direction, or both directions) Unlike the wordlines in bridge structure 108, wordline VIA contacts overlying tier 114 and memory array structures (eg, 104-1 and/or 104-2). In some embodiments, at least one step 114 in one of the steps 106 connects the first memory array structure 104-1 and the second memory array structure 104-2 through the bridge structure 108. is electrically connected to at least one of At least one stage 114 is electrically connected to at least one of the first and second memory array structures (eg, 104-1 and/or 104-2) through bridge structure 108 by at least one word line. At least one word line can extend laterally within the memory array structure (eg, 104-1 and/or 104-2) and the bridge structure 108 so that it can be connected to . In one example, steps 114 in staircase 106 are electrically coupled (in the negative x-direction) to first memory array structure 104-1 by respective word line portions extending through bridge structure 108 in the negative x-direction. can be connected. In some embodiments, at least one tier 114 in staircase 106 is separated from first memory array structure 104 through bridge structure 108 by, for example, respective word line portions extending in the negative and positive x-directions, respectively. electrically connected to each of the first and second memory array structures 104-2.

The conductor portions within the staircase 106 and the conductor layers within the bridge structure 108 are each made of, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), Conductive materials may include doped silicon, silicide, or any combination thereof. The dielectric layers in staircase 106 and bridge structure 108 may comprise dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor portion and conductor layer comprise the same material, eg metal such as tungsten, and the dielectric layer comprises the same material such as silicon oxide.

Figures 1C and 1D show the staircase structure 102 between the first and second memory array structures 104-1 and 104-2. As shown in FIGS. 1C and 1D, the staircase 106 may include multiple steps 114 extending along the x-direction, with a wordline VIA contact 116 formed on at least one (eg, each) step 114 . be done. Each of the first and second memory array structures 104-1 and 104-2 may include one or more memory blocks, each memory block including one or more memory fingers 120. FIG. In some embodiments, staircase structures 102 may be between pairs of memory fingers 120 along the y-direction. Each memory finger 120 may include multiple memory strings 112 extending along the z-direction. The memory string 112 comprises a blocking layer, a memory layer, a tunnel layer, a semiconductor layer, and optionally a dielectric within the channel hole and radially from the sidewall toward the center of the channel hole. and a channel structure having a core. Memory string 112 may intersect multiple word lines (eg, conductor layers within memory fingers 120) to form multiple memory cells. The memory cells may form memory cell arrays within respective memory array structures. In some embodiments, the GLS 110 extending along the x and z directions connects memory cells in the first and second memory array structures 104-1 and 104-2 to a plurality of memory fingers 120 along the y direction. split into

According to some embodiments, the bridge structure 108 connects the first memory array structure 104-1 and/or the second memory array structure 104-2 (physically) to achieve a bi-directional word line driving scheme. (both physically and electrically). That is, according to some embodiments, the staircase structure 102 does not necessarily completely cut the memory array structure in the middle, but instead connects the first and second memory array structures 108 connected by the staircase bridge structure 108 . Leave memory array structures 104-1 and 104-2. In this way, each word line can be driven bi-directionally (in both the positive and negative x-directions) from a respective word line VIA contact 116 in the middle of the 3D memory device 100 via the bridge structure 108 . 1C and 1D show exemplary current paths for a bi-directional word line drive scheme with staircase structure 102. FIG. The arrowed current paths represent the current through different word lines at different levels.

2A-2C show schematic diagrams of a 3D memory device 200 having staircase structures 202-1 and 202-2, each on a respective side of a memory array structure 204. FIG. The staircase structures 202 - 1 and 202 - 2 and the memory array structure 204 can be on a substrate 101 similar to that of the 3D memory device 100 . The 3D memory device 200 may include memory planes having memory cell arrays within a memory array structure 204 . Unlike 3D memory device 100, 3D memory device 200 includes two staircase structures 202-1 and 202-2 on either side of memory array structure 204 in the x-direction. Each word line in a memory plane extends laterally in the x-direction across the entire memory plane to a respective step (level) within staircase structure 202-1 or 202-2. A row decoder (not shown) is formed directly above, below, or in close proximity to each staircase structure. That is, each row decoder drives half of the memory cells in one direction (either in the positive or negative x-direction rather than in both directions) via half of the word lines, with each word line traversing the entire memory plane. .

Stair structures 202-1 and 202-2 may have similar/same structures. FIG. 2B shows a front top view of a stair structure that may represent each of stair structures 202-1 and 202-2. The staircase structure may include a staircase 206 having a plurality of steps 214 extending along the x-direction, similar to staircase 106 . The staircase structure also includes a bridge structure 208 electrically and physically connected to the staircase 206 . Bridge structure 208 may include alternating conductor and dielectric layers similar to those of bridge structure 108 . In some embodiments, bridge structure 208 includes multiple steps extending along the x-direction, each step corresponding to a respective step of stairs 206 . Stairs 206 may be similar to stairs 106, for example, at least one step 214 includes a conductor portion on the top surface and is electrically connected to a conductor layer at the same level within bridge structure 208. FIG. A conductor layer within bridge structure 208 may be a word line portion that is electrically connected to a word line (eg, a conductor layer) within memory array structure 204 .

FIG. 2C shows staircase structures 202-1 and 202-2, each on a respective side of memory array structure 204. FIG. As shown in FIG. 2C, the staircase 206 may include multiple steps 214 extending along the x-direction, with a wordline VIA contact 216 formed on at least one (eg, each) step 214 . Memory array structure 204 may include one or more memory blocks, each memory block including one or more memory fingers 220 . Each memory finger 220 may include multiple memory strings 212 similar to memory strings 112 in 3D memory device 200 . Memory strings 212 may intersect multiple word lines (eg, conductor layers within memory fingers 220) to form multiple memory cells that form memory cell arrays within respective memory array structures. In some embodiments, GLS 210 extending along the x-direction and z-direction divide memory cells in memory array structure 204 into multiple memory fingers 220 along the y-direction.

According to some embodiments, bridge structures 208 each connect (both physically and electrically) memory array structures 204 to achieve a unidirectional word line driving scheme. In this way, each wordline can be driven unidirectionally (in the positive or negative x-direction) from the respective wordline VIA contact 216 on one side of the 3D memory device 200 through the bridge structure 208 . As shown in FIG. 2C, the arrowed current paths represent the current passing through two separate word lines at different levels.

3A-3D show three cross-sectional views of a staircase structure (eg, 102), each perpendicular to each other. Specifically, FIGS. 3A and 3B show cross-sectional views of the staircase structure 102 along directions A-A' and B-B', respectively, as shown in FIG. 1B. FIG. 3A shows a cross-sectional view of staircase 106 showing non-overlapping portions of the conductor portions. As shown in FIG. 1B, the AA' direction represents the xz plane and the B-B' direction represents the zy plane. FIG. 3C shows an xy cross-sectional view of steps/levels of stair structure 102 . FIG. 3D shows a detailed cross-sectional view of an exemplary conductor portion. Figures 3A-3D also show a staircase structure 202 along the same direction (shown in Figure 2B), except that the bridge structure can have a different number of conductor/dielectric layer pairs along the z-direction. -1/202-2 cross-sectional views can be represented.

As previously explained, in a 3D memory device, a staircase structure may include a staircase and a bridge structure in contact with the staircase. As shown in FIGS. 3A and 3B, the staircase structure may include a staircase 306 and a bridge structure 308 (only a portion of which is shown in FIG. 3B) in contact with the staircase 306 . The staircase structure can be formed on a substrate 302 similar to the substrate in 3D memory device 100 . The insulating structure 350 can be at least above the steps 306 such that at least the steps 306 are located within the insulating structure 350 . A wordline VIA contact 316 may be formed in the isolation structure 350 and overlies the landing area of each step. Only one wordline VIA contact 316 is shown for ease of illustration. Isolation structure 350 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, and/or silicon oxynitride. Wordline VIA contacts 316 may comprise tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof. Bridge structure 308 may include a plurality of alternating conductor layers 330 and dielectric layers 336 similar to those in 3D memory device 100 .

As shown in FIGS. 3A and 3B, staircase 306 includes a plurality of steps 314 extending along the x-direction, eg, the wordline direction. Each step 314 can have a different depth along the z-direction. In some embodiments, except for the top step, the stairs 306 include conductor portions 320 on the top surface of at least one step 314 and are electrically and physically connected to conductor layers 330 at the same level within the bridge structure 308. be done. In some embodiments, each step 314 within staircase 306 may include a respective conductor portion 320 . Conductor portion 320 may contact dielectric portion 324 (eg, extending along the x-direction) at the same level. Optionally, in each step 314 , conductor portion 320 may overlie and contact another dielectric portion that overlies and contacts underlying dielectric layer 326 . In some embodiments, in each step 314, conductor portion 320 may overlie and contact dielectric layer 326 without any other intervening dielectric portion. In some embodiments, each dielectric layer 326 within staircase 306 contacts a dielectric layer 326 at the same level within bridge structure 308 . In some embodiments, conductor portion 320 may overlie more than one dielectric layer 336 within each step 314 .

Along the x-direction, conductor portions 320 extend into the landing area of each step 314, as shown in FIG. 3A. The non-overlapping portion of conductor portion 320 (shown in FIG. 3D) may be cut off (eg, not extending into the step) at the end of upper step 314 (eg, directly above step 314). That is, little or no overlap is formed between the non-overlapping portions of adjacent conductor portions 320 along the x-direction. In some embodiments, no overlap is formed between non-overlapping portions of any conductor portion 320 along the x-direction. In some embodiments, along the x-direction, the width d of the non-overlapping portion of conductor portion 320 may be less than or equal to the dimension of step 314 . Each wordline VIA contact may be formed over a non-overlapping portion of conductor portion 320 .

In some embodiments, in step 314 , dielectric portion 324 and other dielectric portions (if formed) can have the same material, different from the material of dielectric layer 326 . In some embodiments, dielectric layer 326 comprises silicon oxide. In some embodiments, dielectric portion 324 comprises silicon nitride. In some embodiments, the other dielectric portion (if formed) has the same dimensions as conductor portion 320 along the x-direction. In step 314, the bottom surfaces of dielectric portion 324 and other dielectric portions may be coplanar along the z-direction. Along the z-direction, the thickness of conductor portion 320 may be less than or equal to the thickness of dielectric portion 324, and the thickness of other dielectric portions (if formed) may be greater than the thickness of dielectric portion 324. Small is fine.

As shown in FIG. 3B, along the y-direction, the length D of conductor portion 320 may be less than or equal to the dimension of each step 314 . In some embodiments, length D is equal to the dimension of each step 314 along the y-direction. In some embodiments, length D is less than the dimension of each step 314 and second dielectric portion 323 is formed at the end of step 314 remote from bridge structure 308 . The second dielectric portion 323 may have the same thickness along the z-direction as the dielectric portion 324 and may have the same material as the dielectric portion 324 . Along the x-direction, the width of the second dielectric portion 323 may be smaller than, equal to, or larger than the width d of the conductor portion 320 . The length D and width d of conductor portion 320 are each large enough to cover the landing area of each step 314 and to allow each wordline VIA contact 316 to be formed at the desired location. could be.

As shown in FIGS. 3A and 3B, conductor portions 320 may overlie at least one respective dielectric layer 326 within the same step 314 . In some embodiments, in each step 314 the conductor portion 320 is in contact with and overlies a respective dielectric layer 326 . On the one hand, the dielectric portions 324 are stepped along the x-direction (eg, along the negative x-direction), for example, from the boundary with each conductor portion 320 to the boundary between the step 306 and the memory array structure. 306. In some embodiments, along the z-direction, at least one conductor portion 320 overlies a plurality of alternating dielectric layers 326 and dielectric portions 324 . For example, dielectric layers 326 may include each dielectric layer 326 in the same step and one or more dielectric layers 326 in lower step 314 . Dielectric portion 324 may include one or more dielectric portions 324 in lower step 314 . In some embodiments, along the z-direction, at least one conductor portion 320 also overlies other dielectric portions within the same step 314 . As shown in FIG. 3B, all dielectric portions 324 and dielectric layers 326 underlying conductor portion 320 may be referred to as dielectric structure 340, and the thickness of dielectric structure 340 along the z-direction is , equal to the distance between the bottom surface of each conductor portion 320 and the top surface of the substrate 302 . In some embodiments, the length of dielectric structure 340 along the y-direction is equal to the length of conductor portion 320 (eg, length D). In some embodiments, the width of dielectric structure 340 along the x-direction is equal to the width of conductor portion 320 (eg, width d). In some embodiments, except for the bottom step 314 (eg, the step 314 at the bottom of the staircase 306), the dielectric structure 340 has a lower step 314 (eg, a lower elevation/ It includes at least one pair of dielectric portion 324 and dielectric layer 326 corresponding to step 314) at a greater depth. In some embodiments, except for the bottom step 314 , each dielectric structure 340 includes at least one pair of dielectric portion 324 and dielectric layer 326 corresponding to the lower step 314 and each step 314 and a dielectric layer 326 in the .

FIG. 3C shows a side cross-sectional view of a staircase structure showing the spatial relationship of GLS 310, conductor layer 330, conductor portion 320, and dielectric portion 324. FIG. As shown in FIGS. 3B and 3C, in some embodiments, staircase 306 includes connecting structure 321 in contact with bridge structure 308 . A connection structure 321 that is part of the staircase 306 and extends along the x-direction may include at least one conductor strip and at least one dielectric strip interleaved on the substrate 302 . In some embodiments, the length L of connecting structures 321 along the y-direction is greater than or equal to zero. For each step 314, the dimension of connecting structure 321 along the x-direction can be the length of each dielectric layer 326 (eg, the sum of the width of dielectric portion 324 and conductor portion 320). That is, along the x-direction, the dimension of connecting structure 321 may be the same as the length of the contact area between step 314 and bridge structure 308 . The thickness of connecting structure 321 along the z-direction can be the same as the height of each step 314 . That is, the thickness of the connection structure 321 may be equal to the distance from the top surface of the step 314 /conductor portion 320 to the top surface of the substrate 302 . Each conductor strip may contact conductor layer 330 and dielectric portion 324 on the same level, and each dielectric strip may contact dielectric layer 336 and dielectric layer 326 on the same level. The material of the conductor strips can be the same as the material of the conductor layer 330 and the material of the dielectric strips can be the same as the material of the dielectric layer 336 .

For each step 314 , the top conductor strip may also contact a respective conductor portion 320 , thus electrically connecting conductor portions 320 and conductor layers 330 at the same level. Along the z-direction, the thickness of each conductor strip can be the same as the thickness of the respective conductor layer 330 . In some embodiments, the conductor and dielectric strips that are part of staircase 306 may be considered extensions of conductor layer 330 and dielectric layer 336 entering staircase 306 along the y-direction. In some embodiments of each step 314 , dielectric structure 340 is in contact with respective connecting structure 321 .

As shown in FIG. 3C, GLS 310 may extend along the x-direction and contact bridge structure 308 (eg, or conductor layer 330 within bridge structure 308). In some embodiments, bridge structure 308 may be between GLS 310 and stairs 306 . In some embodiments, along the negative y-direction, the width d of conductor portion 320 may decrease. In various embodiments, along the negative y-direction, width d may continue to decrease by a first distance d1 (eg, from the boundary of bridge structure 308 or connecting structure 321 (if present)); A distance d2 of 2 remains unchanged. As shown in FIG. 3C, the sum of d1 and d2 may be equal to D if connection structure 321 is not formed and may be equal to (DL) if connection structure 321 is formed. In some embodiments, it is desirable that d1 is small so that d1 is negligible compared to d2. For example, d1 can be about 2% to about 20% (eg, 2%, 3%, 5%, 8%, 10%, 15%, 18%, 20%) of d2.

FIG. 3D shows the detailed structure of the conductor portion 320 . For ease of illustration, different patterns/shading are used in FIG. 3D to indicate various portions of conductor portion 320. FIG. In some embodiments, conductor portion 320 may be divided into a non-overlapping portion 320-1 and overlapping portions 320-2 and 320-3. Overlap 320-2 may represent the portion of conductor portion 320 (or the conductor portion 320 of the immediately above step) that overlaps the immediately above step along the z-direction. Overlap 320-3 may represent the portion of conductor portion 320 (or the conductor portion 320 of the step below) that overlaps the step below along the z-direction. Non-overlapping portion 320-1 may represent a portion of conductor portion 320 that does not overlap with an upper or lower step. Together, the non-overlapping portion 320-1 and the overlapping portion 320-3 may form the portion of the conductor portion 320 that is exposed on the top surface of the step 314. FIG. The boundary between overlapping portion 320-2 and non-overlapping portion 320-1 is not physically formed, but may be the edge of step 314 directly above. As shown in FIGS. 3C and 3D, non-overlapping portion 320-1 contacts each of overlapping portions 320-2 and 320-3. As a result, the total area of conductor portion 320 can be the sum of non-overlapping portion 320-1 and overlapping portions 320-2 and 320-3 along the xy plane.

In some embodiments, overlaps 320-2 and 320-3 may have nominally the same shape and/or nominally the same dimensions. In some embodiments, as shown in FIG. 3C, overlap 320-2 has the shape of a right triangle, with the right angle being the edge of step 314 directly above and dielectric portion 324 along the x-direction. formed by the boundaries of The lateral dimension of overlap 320-2 may gradually decrease along the negative y-direction. In some embodiments, the boundary of dielectric portion 324 is along the hypotenuse of a right triangle (eg, overlapping portion 320-2) as well as along the y-direction (eg, aligned with the edge of step 314 directly above). It may include boundaries and boundaries along the x-direction (eg, with connection structure 321 or bridge structure 308). In some embodiments, the non-overlapping portion 320-1 can have the shape of a right-angled trapezoid. The lateral dimension of non-overlapping portion 320-1 may increase along the negative y-direction. That is, the width d of the conductor portion may decrease along the negative y-direction or remain unchanged.

Figures 4A-4D illustrate a fabrication process for forming an exemplary staircase structure of a 3D memory device, according to various embodiments of the present disclosure. 5A and 5B show steps before and after an ion implantation process, according to some embodiments. FIG. 6 is a flowchart of a method 600 for forming an exemplary staircase structure of a 3D memory device, according to some embodiments. It is understood that the acts illustrated in method 600 are not all-inclusive and that other acts may similarly be performed before, after, or during any of the illustrated acts. Additionally, some of the operations may be performed concurrently or in an order different than the order shown in FIG.

Referring to FIG. 6, method 600 begins at operation 602 where a staircase structure having stairs and bridge structures is formed. FIG. 4A shows the corresponding structure.

As shown in FIG. 4A, a stepped structure having steps 406 and bridge structures 408 is formed over substrate 402 . Stairs 406 may contact bridge structure 408 . Step 406 may include a plurality of alternating sacrificial layers 429 and a plurality of dielectric layers 426 to form a plurality of steps 414 extending along the x-direction (see, eg, step 314 in FIG. 3A). Each step 414 may include at least one sacrificial layer 429 /dielectric layer 426 pair. Bridge structure 408 may include a plurality of alternating sacrificial layers 439 and a plurality of dielectric layers 436 . In some embodiments, each sacrificial layer 439 contacts a respective sacrificial layer 429 on the same level and each dielectric layer 436 contacts a respective dielectric layer 426 on the same level. In some embodiments, sacrificial layers 439 and 429 comprise the same material, such as silicon nitride. In some embodiments, dielectric layers 436 and 426 comprise the same material, such as silicon oxide.

To form a stack structure, a material stack may first be formed. The material stack may include vertically alternating first and second dielectric material layers. In some embodiments, the material stack is a dielectric stack and the first material layer and the second material layer comprise different dielectric materials. The alternating first and second dielectric material layers may be alternately deposited on the substrate 402 . In some embodiments, the first dielectric material layer comprises a layer of silicon nitride and the second dielectric material layer comprises a layer of silicon oxide. The material stack is deposited by one or more thin film deposition processes including, but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. can be formed.

A portion of the material stack may be patterned to form a stack structure. In some embodiments, separate masks, eg, separate etching processes, may be used to form staircase 406 and bridge structure 408 . In some embodiments, forming staircase 406 includes repeatedly etching the material stack using an etch mask (eg, a patterned photoresist or PR layer) over the material stack. The etch mask may be repeatedly trimmed, often incrementally inward from all directions, to expose portions of the material stack to be etched. The amount of trimmed PR can be directly related (eg, can be a determining factor) to the step dimensions. For example, the amount of PR cropped along the x-direction may determine the width of step 414 along the x-direction. Trimming of the PR layer can be obtained using a suitable etch, for example an isotropic etch such as a wet etch. One or more PR layers may be formed and trimmed in series to form the steps. In some embodiments, trimming of the PR layer is followed by etching of the material stack using a suitable etching process such as, for example, dry etching and/or wet etching. In some embodiments, the material stack is etched by a step depth along the z-direction following trimming of each PR layer. The step depth may be equal to the number of dielectric material layer pairs (eg, the number of first dielectric material layers/second dielectric material layers) included in the steps. In some embodiments, the number of dielectric material layer pairs is one. A photoresist mask trimming process followed by a material stack etching process is referred to herein as a trim etch cycle. The number of trim etch cycles can determine the number of steps formed in the material along the y-axis. In some embodiments, after forming the steps, a first layer of dielectric material may form sacrificial layer 429 and a second layer of dielectric material may form dielectric layer 426 . A staircase 406 may be formed. In some embodiments, each step 414 includes a pair of sacrificial layer 429 and an underlying dielectric layer 426 (eg, one sacrificial/dielectric pair).

In various embodiments, bridge structure 408 may be formed by patterning another portion of the material stack. An etch mask may or may not be used depending on the design of bridge structure 408 . In various embodiments, the bridge structure 408 can have a "wall-shaped" structure as shown in FIG. 1B or a staircase shape as shown in FIG. 2B. Bridge structure 408 may be formed with steps 406 by the same etching process or by a different etching process. In some embodiments, formation of bridge structure 408 includes a photolithographic process followed by a suitable etching process such as dry etching and/or wet etching. A stepped structure having steps 406 and bridge structures 408 may be formed.

In some embodiments, sacrificial layer 429 is exposed at the top surface of each step 414 after step 406 is formed. At each step 414 , a dielectric layer 426 may underlie a sacrificial layer 429 . In some embodiments, buffering and protection during subsequent ion implantation processes above step 414 so that underlying sacrificial layer 429 can have optimized physical properties, as shown in FIG. 4A. A protective layer 425 may be formed over the top surface of step 414 to provide a . Protective layer 425 may cover at least a portion of step 414 (ie, sacrificial layer 429) that is to undergo the ion implantation process. For example, protective layer 425 may cover at least the landing area (or possible landing area) of step 414 (eg, sacrificial layer 429). Protective layer 425 may comprise any suitable material having a suitable thickness along the z-direction and may be formed using any suitable method. In some embodiments, protective layer 425 comprises a layer of dielectric material. In some embodiments, protective layer 425 includes portions of the second dielectric material layer (eg, silicon oxide) that are not completely etched away during step 414 formation. That is, at least a portion of the second dielectric material layer immediately above the first dielectric material layer in staircase 406 may be reserved during etching of the material stack. In some embodiments, the etching time to form step 414 is controlled to ensure that protective layer 425 has the desired thickness. In some embodiments, protective layer 425 is also deposited using a suitable deposition process, such as CVD, ALD, to deposit a layer of dielectric material such as silicon oxide over step 414 (ie, sacrificial layer 429). and/or may be formed by PVD alone or in addition to controlled etching.

FIG. 5A shows an enlarged view 500 of step 414 prior to the ion implantation process. As shown in FIG. 5A, in some embodiments, the sacrificial layer 429 in each step 414 may be covered by a protective layer 425 that includes the entire layer of second dielectric material immediately above the sacrificial layer 429. . In some embodiments, the step 414 includes a protective layer 425 and an underlying sacrificial layer 429 prior to the ion implantation process. A dielectric layer 426 may underlie each sacrificial layer 429 and may be in contact with the protective layer 425 of the step 414 directly below.

Referring to FIG. 6, method 600 advances to operation 604 where an ion implantation process is performed to form a sacrificial layer over the top surface of each step. FIG. 4B shows the corresponding structure.

An ion implantation process may be performed to form a sacrificial portion 419 on the top surface of at least one step 414, as shown in FIG. 4B. In some embodiments, a plurality of sacrificial portions 419 are respectively formed over respective steps 414 . Sacrificial portion 419 may cover at least the landing area of each step 414 . In some embodiments, the sacrificial portion 419 covers the entire width d of each step 414 (eg, along the x-direction, referring back to FIG. 3A). The sacrificial portion 419 may be cut at the edge of the step 414 directly above such that the sacrificial portion 419 does not extend below the upper step 414 along the x-direction. In various embodiments, sacrificial portion 419 having length D may or may not cover the entire length of each step 414 (eg, along the y-direction, referring back to FIG. 3B). Sacrificial portion 419 may or may not be cut at the boundary between bridge structure 408 and staircase 406, depending on the ion implantation process. Along the z-direction, the thickness of sacrificial portion 419 may be less than or equal to the thickness of sacrificial layer 429 . In some embodiments, the thickness of sacrificial portion 419 is equal to the thickness of sacrificial layer 429 .

Ion implantation may change the physical properties of the treated portion of sacrificial layer 429 (ie, sacrificial portion 419). In some embodiments, the sacrificial portion 419 is removed from the sacrificial portion 419 such that in subsequent gate exchange processes, an etchant for removing the sacrificial layer 429 may have a higher etch rate on the sacrificial portion 419 over the sacrificial layer 429 . can be bombarded with ions to have higher porosity. That is, the etchant for removing sacrificial layer 429 may selectively etch sacrificial portion 419 over sacrificial layer 429 . In some embodiments, sacrificial portion 419 has a lower density than sacrificial layer 429, making it easier to etch. In some embodiments, the ratio between the etch rate over sacrificial portion 419 and the etch rate over sacrificial layer 429 can be about 3:1. In various embodiments, the ion implantation process employs a tilted ion implantation process using suitable ions at any suitable energy. In some embodiments, the angled ion implantation process may also implant ions into bridge structure 408 . In some embodiments, the ions include boron (B) ions. Optionally, a heat treatment such as an annealing process can be performed after ion implantation.

In some embodiments, the portion of sacrificial layer 429 that underlies upper step 414 (see back to FIG. 4A) without undergoing an ion implantation process forms the dielectric portion within each step 414. can. The dielectric portion may contact sacrificial portion 419 at the edge of step 414 directly above. In some embodiments, if the thickness of sacrificial portion 419 is less than the thickness of sacrificial layer 429 , an initial other dielectric portion (not shown) is formed below sacrificial portion 419 . The initial other dielectric portion may be formed by portions of sacrificial layer 429 that underlie sacrificial portion 419 and do not undergo the ion implantation process. In some embodiments, the width of the initial further dielectric portion along the x-direction is the same as the respective sacrificial portion 419 and the width of the initial further dielectric portion along the z-direction is the same as the respective sacrificial portion 419. of the dielectric portion (or sacrificial layer 429). In some embodiments, the length of the initial other dielectric portion along the y-direction may be equal to the length of conductor portion 420 (eg, length D). In some embodiments, along the z-direction, each step 414 includes a sacrificial portion 419 and at least an underlying dielectric layer 426 (and other initial dielectric portions, if formed). . Further, except for the bottom step 414 , each step 414 may overlie one or more pairs of dielectric portion and dielectric layer 426 of the lower step 414 .

Optionally, the sacrificial portion 419 may not completely cover the step 414 along the y-direction, and the second dielectric portion 423 may extend from the portion of the sacrificial layer 429 outside the portion undergoing the ion implantation process. can be formed. In some embodiments, the width of the second dielectric portion 423 along the x-direction may be less than, equal to, or greater than the width (eg, width d) of each step 414. good. In some embodiments, the thickness of the second dielectric portion 423 along the z-direction may be less than or equal to the thickness of the respective sacrificial layer 429 .

FIG. 5B shows an enlarged view 502 of stage 414 after the ion implantation process. As shown in FIG. 5B, a sacrificial portion 419 may be formed in each step 414 under each protective layer 425 . Sacrificial portions 419 of adjacent steps 414 do not overlap along any direction. Optionally, protective layer 425 may be removed after the ion implantation process to expose underlying sacrificial portion 419 . In some embodiments, a suitable etching process, such as dry etching and/or wet etching, is performed to remove protective layer 425 . In this way, the dielectric layer 426 of each step 414 can be cut at the edge of each step 414 . In some embodiments, protective layer 425 is reserved.

Referring to FIG. 6, method 600 proceeds to operation 606 where a plurality of lateral recesses are formed in the bridge structure and lateral recesses are formed from each sacrificial portion. FIG. 4C shows the corresponding structure.

As shown in FIG. 4C, a plurality of lateral recesses 428 may be formed in bridge structure 408 and lateral recesses 418 may be formed from respective sacrificial portions 419 . In some embodiments, a GLS (eg, a slit structure, see back to GLS 310 in FIG. 3C) may be formed in contact with bridge structure 408 prior to forming lateral recess 428 and lateral recess 418 . The GLS may extend into the step structure in the xz plane, exposing the substrate 402 and the sacrificial/dielectric pair (439/436) in the bridge structure 408. FIG. An etching process employing a suitable etchant such as phosphoric acid may be used to remove sacrificial layer 439 and sacrificial portion 419 through the GLS. In some embodiments, the etching process comprises an isotropic etching process such as wet etching. The etchant removes all the sacrificial layer 439 exposed on the sidewalls of the GLS as well as the sacrificial portion 419 in the same etching process, eg simultaneously. Dielectric layer 436 may be reserved. Lateral recess 428 may be formed from the removal of sacrificial layer 439 and lateral recess 418 may be formed from the removal of sacrificial portion 419 .

In some embodiments, the respective lateral recesses 418 are exposed above the top surface of the respective steps 414 when the protective layer 425 is removed prior to the etching process. In some embodiments, when protective layers 425 are reserved, lateral recesses 418 are formed under respective protective layers 425 . In some embodiments, lateral recess 418 contacts second dielectric portion 423 laterally (along the negative y-direction). In some embodiments, lateral recess 418 contacts underlying dielectric layer 426 .

In some embodiments, the etchant has a higher etch rate on sacrificial portion 419 than on sacrificial layer 439 . The ratio of etch rates on sacrificial portion 419 to sacrificial layer 439 may be in the range of about 5:1 to about 2:1. In some embodiments the ratio is about 3:1. As the etchant approaches step 406 from the GLS, portions of the dielectric portion may be overetched as a result of the higher etch rate on sacrificial portion 419 . The over-etched portion of the dielectric portion may overlap the directly above step 414 and correspond to the later-formed overlap portion of the conductor portion (eg, see back to overlap 320-2 in FIG. 3D). The overetch may be part of lateral recess 418 . In some embodiments, the etch time is controlled such that at least one desired portion (eg, desired length along the y-direction) of dielectric material under each lateral recess 418 is retained. be. The reserved dielectric material under the lateral recesses 418 is the respective dielectric structure (see back to FIG. 3A) under the landing areas on which the respective wordline VIA contacts are to be formed. ) can form.

In some embodiments, a portion of step 406 below sacrificial portion 419 may be removed during the etching process. As shown in FIG. 4C, the removed portion of step 406 may include a portion of the dielectric portion and a portion of dielectric layer 426 below sacrificial portion 419 (eg, lower step 414). In some embodiments, the removed portion of staircase 406 may nominally have length L along the y-direction and the same length as sacrificial layer 429 along the x-direction. . In some embodiments, along the z-direction, if the thickness of sacrificial portion 419 is less than the thickness of sacrificial layer 429, the etchant also removes a portion of each of the other initial dielectric portions, leaving lateral recesses. Each other dielectric portion is formed in contact with and under portion 418 .

In some embodiments, an insulating structure 450 is formed over the staircase structure prior to the etching process such that at least the staircase 406 is within the insulating structure 450 . Insulating structure 450 may comprise a suitable dielectric material and is deposited by any suitable deposition method such as CVD, ALD and/or PVD. In some embodiments, insulating structure 450 comprises silicon oxide and is deposited by CVD. In some embodiments, if protective layer 425 is removed before insulating structure 450 is formed, a dielectric material may be deposited in contact with sacrificial portion 419 to form insulating structure 450 . In some embodiments, deposited dielectric material may accumulate on protective layer 425 if protective layer 425 is reserved. As a result, insulating structure 450 may include protective layer 425 and a dielectric material deposited over protective layer 425 . Note that isolation structure 450 may be formed at any suitable time after staircase 406 is formed and before wordline VIA contacts are formed. The specific timing for forming isolation structure 450 should not be limited by embodiments of the present disclosure.

Referring to FIG. 6, method 600 proceeds to operation 608 where a plurality of conductor layers are formed within the lateral recesses and conductor portions are formed within respective lateral recesses. FIG. 4D shows the corresponding structure.

A plurality of conductor layers 430 may be formed within the bridge structure 408 and a conductor portion 420 may be formed within each step 414 within the staircase 406, as shown in FIG. 4C. In some embodiments, a suitable deposition process such as ALD, CVD and/or PVD is performed to deposit a suitable conductive material to fill lateral recess 428 and lateral recess 418 in the same process. be. Conductive material may fill lateral recesses 428 and lateral recesses 418 from the GLS. The over-etched portion of each lateral recess 418 may be filled with a conductive material to form an overlap of the conductor portion 420 below the step 414 directly above. For other portions of lateral recess 418 to form non-overlapping portions and other overlapping portions (eg, see back to non-overlapping portion 320-1 and overlapping portion 320-3, respectively, in FIG. 3D). Both may be filled with a conductive material, both over the top surface of each step 414 . In some embodiments, the conductive material may also fill the removed portion of staircase 406 under sacrificial portion 419 (or conductive portion 420), forming connection structure 421 (see back to FIG. 3C). do. Conductive materials may include tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.

Referring to FIG. 6, method 600 proceeds to operation 610 where wordline VIA contacts are formed in contact with respective conductor portions. FIG. 4E shows the corresponding structure.

As shown in FIG. 4E, wordline VIA contacts 416 are formed in insulating structures 450 and contact respective conductor portions 420 . In some embodiments, wordline VIA contacts 416 are formed on non-overlapping portions of respective conductor portions 420 . Wordline VIA contact 416 may be formed by patterning insulating structure 450 to form an opening that exposes conductor portion 420 and depositing a suitable conductive material to fill in the opening. In some embodiments, patterning of insulating structure 450 includes a photolithographic process followed by a suitable etching process, such as dry etching and/or wet etching. Conductive materials include tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the ACS is formed within the GLS after the conductor layer 430 and conductor portion 420 are formed.

Embodiments of the present disclosure provide 3D memory devices. A 3D memory device includes a memory array structure and a staircase structure. A staircase structure is located in the middle of the memory array structure and divides the memory array structure along the lateral direction into a first memory array structure and a second memory array structure. The staircase structure includes a plurality of laterally extending steps and a bridge structure in contact with the first memory array structure and the second memory array structure. The multiple stages include a stage over one or more dielectric pairs. The step includes a conductor portion overlying the upper surface of the step and in contact with and electrically connected to the bridge structure, and a dielectric portion at the same level and in contact with the conductor portion. The tier is electrically connected to at least one of the first memory array structure and the second memory array structure via the bridge structure. Along a second lateral direction perpendicular to the lateral direction, the width of the conductor portion decreases away from the bridge structure.

In some embodiments, a portion of the conductor portion overlaps the upper step.

In some embodiments, the lateral dimension of the portion of the conductor portion decreases along the second lateral direction.

In some embodiments, a portion of the conductor portion has a right triangle side shape.

In some embodiments, the step further includes a dielectric layer under the conductor portion and the dielectric portion.

In some embodiments, the conductor portions and dielectric layers each overlie one or more dielectric pairs.

In some embodiments, along the lateral direction, the width of another portion of the conductor portion is equal to the dimension of the step.

In some embodiments, along the second lateral direction the length of the conductor portion is less than or equal to the second dimension of the step.

In some embodiments, the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction.

In some embodiments, the conductor portion includes at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon. In some embodiments, the dielectric portion comprises silicon nitride. In some embodiments, the dielectric layer comprises silicon oxide.

In some embodiments, the bridge structure includes a plurality of interleaved conductor layers each in contact with the first and second memory array structures. In some embodiments, the conductor portions are in contact and electrically connected to respective conductor layers at the same level.

In some embodiments, each of the one or more dielectric pairs includes a dielectric portion and a dielectric layer corresponding to the lower step.

Embodiments of the present disclosure provide 3D memory devices. A 3D memory device includes a memory array structure and a landing structure in contact with the memory array structure. The landing structure includes a plurality of landing regions at respective depths, each extending along a lateral direction, and a bridge structure in contact with the memory array structure. The plurality of landing areas each include a conductor portion on the respective top surface and a dielectric portion at the same level and in contact with the conductor portion. The conductor portion is electrically connected to the memory array structure through the bridge structure. The width of the conductor portion decreases away from the bridge structure along a second lateral direction perpendicular to the lateral direction. Each of the plurality of landing regions overlies one or more dielectric pairs.

In some embodiments, a portion of the conductor portion overlaps the upper landing area.

In some embodiments, the lateral dimension of the portion of the conductor portion decreases along the second lateral direction.

In some embodiments, a portion of the conductor portion has a right triangle side shape.

In some embodiments, the plurality of landing areas further includes a dielectric layer under the conductor portion and the dielectric portion.

In some embodiments, the conductor portions and dielectric layers each overlie one or more dielectric pairs.

In some embodiments, the width of the different portions of the conductor portion along the lateral direction is equal to the dimension of the respective landing area.

In some embodiments, along the second lateral direction the length of the conductor portion is less than or equal to the second dimension of the respective landing area.

In some embodiments, the landing structure includes multiple steps extending along the lateral direction. In some embodiments, each of the plurality of landing areas overlies the top surface of a respective step.

In some embodiments, the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction.

In some embodiments, the conductor portion includes at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon. In some embodiments, the dielectric portion comprises silicon nitride. In some embodiments, the dielectric layer comprises silicon oxide.

In some embodiments, the bridge structure includes a plurality of interleaved conductor layers, each in contact with the memory array structure. In some embodiments, the conductor portions are in contact and electrically connected to a respective one of the second conductors at the same level.

In some embodiments, each of the one or more dielectric pairs includes a dielectric portion and a dielectric layer corresponding to the underlying landing area.

Embodiments of the present disclosure provide 3D memory devices. A 3D memory device includes a memory array structure and a staircase structure. The stair structure includes a plurality of steps extending along the lateral direction. The plurality of steps includes a step having a conductor portion on top of the step and a dielectric portion at the same level and in contact with the conductor portion. The conductor portion is electrically connected to the memory array structure. Along a second lateral direction perpendicular to the lateral direction, the width of the conductor portion varies.

In some embodiments, a portion of the conductor portion overlaps the upper step.

In some embodiments, the lateral dimension of the portion of the conductor portion decreases along the second lateral direction.

In some embodiments, a portion of the conductor portion has a right triangle side shape.

In some embodiments, the staircase structure further includes a dielectric layer below the conductor portion and the dielectric portion.

In some embodiments, the conductor portions and dielectric layers each overlie one or more dielectric pairs.

In some embodiments, along the lateral direction, the width of another portion of the conductor portion is equal to the dimension of the step.

In some embodiments, along the second lateral direction the length of the conductor portion is less than or equal to the second dimension of the step.

In some embodiments, the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction.

In some embodiments, the conductor portion includes at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon. In some embodiments, the dielectric portion comprises silicon nitride. In some embodiments, the dielectric layer comprises silicon oxide.

In some embodiments, the 3D memory device further includes a bridge structure in contact with the staircase structure and the memory array structure. The bridge structure includes a plurality of interleaved conductor layers, each in contact with the memory array structure. The conductor portion is in contact and electrically connected to one of the conductor layers on the same level. The staircase structure is electrically connected to the memory array structure through the bridge structure.

In some embodiments, each of the one or more dielectric pairs includes a dielectric portion and a dielectric layer corresponding to the lower step.

Embodiments of the present disclosure provide a method for forming a staircase structure for a 3D memory device. The method includes the following operations. First, a plurality of steps is formed having a plurality of first sacrificial layers and a plurality of first dielectric layers interleaved within the plurality of steps. A bridge structure is formed in contact with the plurality of steps, the bridge structure having a plurality of alternating second sacrificial layers and a plurality of second dielectric layers. Each first sacrificial layer is in contact with a respective second sacrificial layer at the same level and each first dielectric layer is in contact with a respective second dielectric layer at the same level. A sacrificial portion is formed in the first sacrificial layer corresponding to at least one of the steps. A sacrificial portion is on the top surface of each step and is cut at the edge of the upper step. The second sacrificial layer and sacrificial portion are removed by the same etching process to form a plurality of lateral recesses and a lateral recess, respectively. A plurality of conductor layers are formed within the lateral recess, and conductor portions are formed within the lateral recess and in contact with respective ones of the conductor layers.

In some embodiments, the method further includes forming a dielectric portion within each first sacrificial layer. The sacrificial portion is in contact with and at the same level as the sacrificial layer.

In some embodiments, the etching process has a higher etch rate over the sacrificial portion than the etch rate over the second sacrificial layer.

In some embodiments, the ratio of the etch rate over the sacrificial portion to the etch rate over the second sacrificial layer is about 3:1.

In some embodiments, forming the lateral recess further includes removing a portion of the dielectric below the upper step by an etching process.

In some embodiments, forming a sacrificial portion includes exposing the first sacrificial layer in at least one of the steps to alter the etch rate of the exposed portion of the first sacrificial layer in an etching process. performing an ion implantation process over the treated portion.

In some embodiments, the ion implantation process includes an angled ion implantation process using boron (B).

In some embodiments, the method further includes forming a protective layer over the first sacrificial layer prior to the ion implantation process.

In some embodiments, the method further includes removing the protective layer after the ion implantation process.

In some embodiments, the method further includes retaining portions of the first sacrificial layer and the first dielectric layer corresponding to a lower step below the sacrificial portion.

In some embodiments, the method further includes removing another portion of the first sacrificial layer and the first dielectric layer under the sacrificial portion by an etching process.

In some embodiments, the method further includes forming a slit structure within the staircase structure and removing the plurality of second sacrificial layers and sacrificial portions through the slit structure.

In some embodiments, forming the plurality of conductors and conductor portions includes depositing a conductor material to fill the lateral recesses and lateral recess portions.

In some embodiments, the method further includes forming a contact over the conductor portion.

The above descriptions of specific embodiments may be adapted to various applications by others by applying the knowledge of those of ordinary skill in the art without undue experimentation and without departing from the general concepts of this disclosure. It exposes the general nature of this disclosure to which such specific embodiments may be readily modified and/or adapted. Therefore, such adaptations and modifications are intended to come within the meaning and range of equivalents of the embodiments of the disclosure, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, so that the terminology or terminology herein can be interpreted by those skilled in the art from the standpoint of teaching and guidance. Yo.

Embodiments of the present disclosure have been described above with functional building blocks that illustrate implementations of specific functions and their relationships. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.

The Summary and Abstract sections may describe one or more, but not all of the exemplary embodiments of the present disclosure contemplated by the inventors, and thus limit the scope of the present disclosure and the appended claims. that is not intended at all.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only according to the following claims and their equivalents.

100 three-dimensional (3D) memory device 101 substrate 102 step structure 104-1 first memory array structure 104-2 second memory array structure 106 step 108 bridge structure 110 gate line slit (GLS)
112 memory string 114 tier 116 wordline vertical interconnect access (VIA) contact 120 memory finger 200 3D memory device 202-1 staircase structure 202-2 staircase structure 204 memory array structure 206 staircase 208 bridge structure 210 GLS
212 memory string 214 step 216 word line VIA contact 220 memory finger 302 substrate 306 step 308 bridge structure 310 GLS
314 step 316 word line VIA contact 320 conductor portion 320-1 non-overlapping portion 320-2 overlapping portion 320-3 overlapping portion 321 connection structure 323 second dielectric portion 324 dielectric portion 326 dielectric layer 330 conductor layer 336 dielectric layer 340 dielectric structure 350 insulating structure 402 substrate 406 step 408 bridge structure 414 step 418 lateral recess 419 sacrificial portion 420 conductor portion 421 connecting structure 423 second dielectric portion 425 protective layer 426 dielectric layer 428 lateral recess 429 sacrificial layer 430 conductor layer 436 dielectric layer 439 sacrificial layer 450 insulating structure 500 enlarged view of step 414 502 enlarged view of step 414

Claims (51)

a memory array structure;
a staircase structure intermediate the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure, wherein the staircase structure (i) the and (ii) a bridge structure in contact with said first memory array structure and said second memory array structure, wherein said plurality of steps comprises one or more. comprising a step above the dielectric pair of
the step includes a conductor portion overlying the top surface of the step and in contact with and electrically connected to the bridge structure, and a dielectric portion at the same level and in contact with the conductor portion; said tier electrically connected to at least one of said first memory array structure and said second memory array structure through said bridge structure;
A three-dimensional (3D) memory device, wherein the width of the conductor portion decreases away from the bridge structure along a second lateral direction perpendicular to the lateral direction. 3. The 3D memory device of claim 1, wherein a portion of said conductor portion overlaps an upper step. 3. The 3D memory device of claim 2, wherein a lateral dimension of said portion of said conductor portion decreases along said second lateral direction. 4. The 3D memory device of claim 3, wherein said portion of said conductor portion has a right triangle side shape. The step is
5. The 3D memory device of any one of claims 1-4, further comprising a dielectric layer under the conductor portion and the dielectric portion. 6. The 3D memory device of claim 5, wherein the conductor portion and the dielectric layer each overlie the one or more dielectric pairs. 7. A 3D memory device according to claim 5 or 6, wherein along the lateral direction the width of another portion of the conductor portion is equal to the dimension of the step. 8. The 3D memory device of any one of claims 1-7, wherein along the second lateral direction, the length of the conductor portion is less than or equal to the second dimension of the step. 9. The 3D memory device of any one of claims 1 to 8, wherein the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction. the conductor portion includes at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon;
the dielectric portion comprises silicon nitride;
10. The 3D memory device of any one of claims 1-9, wherein the dielectric layer comprises silicon oxide. said bridge structure comprising a plurality of interleaved conductor layers each in contact with said first and second memory array structures;
11. The 3D memory device of any one of claims 1 to 10, wherein the conductor portions are in contact and electrically connected to respective conductor layers at the same level. 12. The 3D memory device of any one of claims 1 to 11, wherein each of said one or more dielectric pairs comprises a dielectric portion and a dielectric layer corresponding to an underlying step. a memory array structure;
a landing structure in contact with the memory array structure, the landing structure comprising: (i) a plurality of landing regions at respective depths, each extending along a lateral direction; and (ii) the memory array structure. a contacting bridge structure;
each of the plurality of landing areas includes a conductor portion on a respective upper surface and a dielectric portion on the same level and in contact with the conductor portion, the conductor portion extending through the bridge structure to the electrically connected to a memory array structure, the width of the conductor portion decreasing away from the bridge structure along a second lateral direction perpendicular to the lateral direction;
A three-dimensional (3D) memory device, wherein each of the plurality of landing areas overlies one or more dielectric pairs. 14. The 3D memory device of claim 13, wherein a portion of said conductor portion overlaps an upper landing area. 15. The 3D memory device of claim 14, wherein a lateral dimension of said portion of said conductor portion decreases along said second lateral direction. 16. The 3D memory device of claim 15, wherein said portion of said conductor portion has a right triangle side shape. The plurality of landing areas are
17. The 3D memory device of any one of claims 13-16, further comprising a dielectric layer under the conductor portion and the dielectric portion. 18. The 3D memory device of claim 17, wherein the conductor portion and the dielectric layer each overlie the one or more dielectric pairs. 19. The 3D memory device of any one of claims 14-18, wherein along the lateral direction the width of another portion of the conductor portion is equal to the dimension of the respective landing area. 20. The 3D memory device of any one of claims 13-19, wherein along the second lateral direction the length of the conductor portion is less than or equal to the second dimension of the respective landing area. wherein the landing structure includes a plurality of steps extending along the lateral direction;
21. The 3D memory device of any one of claims 13-20, wherein each of said plurality of landing areas overlies said top surface of said respective step. 22. The 3D memory device of claim 21, wherein the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction. the conductor portion includes at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon;
the dielectric portion comprises silicon nitride;
23. The 3D memory device of any one of claims 13-22, wherein the dielectric layer comprises silicon oxide. said bridge structure comprising a plurality of interleaved conductor layers each in contact with said memory array structure;
24. The 3D memory device of any one of claims 13 to 23, wherein said conductor portion is in contact and electrically connected to a respective one of said second conductors at said same level. 25. The 3D memory device of any one of claims 13-24, wherein each of the one or more dielectric pairs comprises a dielectric portion and a dielectric layer corresponding to an underlying landing area. a memory array structure;
a stepped structure including a plurality of steps extending along a lateral direction, said steps being at the same level as and in contact with a conductor portion on top of said step. and wherein the conductor portion is electrically connected to the memory array structure;
A three-dimensional (3D) memory device, wherein the width of the conductor portion varies along a second lateral direction perpendicular to the lateral direction. 27. The 3D memory device of claim 26, wherein a portion of said conductor portion overlaps an upper step. 28. The 3D memory device of claim 27, wherein a lateral dimension of said portion of said conductor portion decreases along said second lateral direction. 29. The 3D memory device of claim 28, wherein said portion of said conductor portion has a right triangle side shape. 30. The 3D memory device of any one of claims 26-29, wherein the stepped structure further comprises a dielectric layer under the conductor portion and the dielectric portion. 31. The 3D memory device of claim 30, wherein the conductor portion and the dielectric layer each overlie the one or more dielectric pairs. 32. The 3D memory device of any one of claims 26 to 31, wherein the width of another portion of the conductor portion along the lateral direction is equal to the dimension of the step. 33. The 3D memory device of any one of claims 26-32, wherein along the second lateral direction the length of the conductor portion is less than or equal to the second dimension of the step. 34. The 3D memory device of any one of claims 26-33, wherein the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction. the conductor portion includes at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon;
the dielectric portion comprises silicon nitride;
35. The 3D memory device of any one of claims 26-34, wherein the dielectric layer comprises silicon oxide. further comprising a bridge structure in contact with the staircase structure and the memory array structure;
said bridge structure comprising a plurality of interleaved conductor layers each in contact with said memory array structure;
said conductor portion being in contact and electrically connected to one of said conductor layers at said same level;
36. The 3D memory device of any one of claims 26-35, wherein the staircase structure is electrically connected to the memory array structure via the bridge structure. 37. The 3D memory device of any one of claims 26-36, wherein each of said one or more dielectric pairs comprises a dielectric portion and a dielectric layer corresponding to an underlying step. A method for forming a staircase structure of a three-dimensional (3D) memory device, comprising:
forming a plurality of steps including a plurality of first sacrificial layers and a plurality of first dielectric layers interleaved within the plurality of steps;
forming a bridge structure in contact with the plurality of steps, the bridge structure comprising a plurality of alternating second sacrificial layers and a plurality of second dielectric layers; one sacrificial layer in contact with a respective second sacrificial layer at the same level, and each first dielectric layer in contact with a respective second dielectric layer at the same level; a step;
forming a sacrificial portion in said first sacrificial layer corresponding to at least one of said steps, said sacrificial portion being on the top surface of said respective step and at the edge of the upper step; a step that is disconnected;
removing the second sacrificial layer and the sacrificial portion by the same etching process to form a plurality of lateral recesses and lateral recesses, respectively;
(i) forming a plurality of conductor layers within said lateral recess; and (ii) a conductor portion within said lateral recess and in contact with a respective one of said conductor layers. . 39. The method of Claim 38, further comprising forming a dielectric portion within each said first sacrificial layer, said sacrificial portion being in contact with and at the same level as said sacrificial layer. 40. A method according to claim 38 or 39, wherein in the etching process the etching rate over the sacrificial portion is higher than the etching rate over the second sacrificial layer. 41. The method of Claim 40, wherein the ratio of the etch rate over the sacrificial portion to the etch rate over the second sacrificial layer is about 3:1. 40. The method of Claim 39, wherein forming the lateral recess further comprises removing a portion of the dielectric portion under the upper step by the etching process. Forming the sacrificial portion comprises:
an ion implantation process onto the exposed portion of the first sacrificial layer of the at least one of the steps to vary the etch rate of the exposed portion of the first sacrificial layer in the etching process; 43. A method according to any one of claims 38 to 42, comprising the step of performing 39. The method of claim 38, wherein the ion implantation process comprises an angled ion implantation process using boron (B). 45. The method of Claim 43 or 44, further comprising forming a protective layer over said first sacrificial layer prior to said ion implantation process. 46. The method of Claim 45, further comprising removing said protective layer after said ion implantation process. 47. The method of any one of claims 38-46, further comprising retaining portions of the first sacrificial layer and the first dielectric layer corresponding to a lower step below the sacrificial portion. . 47. The method of Claim 46, further comprising removing another portion of said first sacrificial layer and said first dielectric layer under said sacrificial portion by said etching process. forming a slit structure within the staircase structure;
49. The method of any one of claims 38-48, further comprising removing the plurality of second sacrificial layers and the sacrificial portion through the slit structure. 50. The method of Claim 49, wherein forming the plurality of conductors and the conductor portion comprises depositing a conductor material to fill the lateral recess and the lateral recess portion. 51. The method of any one of claims 38-50, further comprising forming a contact over the conductor portion.

Images