JP2022166265A - SiC semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SiC semiconductor device capable of reducing an influence on an SiC semiconductor chip due to a modified layer.

SOLUTION: An SiC semiconductor device 1 includes an SiC semiconductor layer 2 (SiC semiconductor chip) having a laminate structure including an SiC semiconductor substrate 6 and an SiC epitaxial layer 7 and including a first principal surface 3 (element formation surface) formed by the SiC epitaxial layer 7 and side surfaces 5A to 5D formed by the SiC semiconductor substrate 6 and the SiC epitaxial layer 7, and modified lines 22A to 22D (modified layers) formed in a portion composed of the SiC semiconductor substrate 6 at intervals from the SiC epitaxial layer 7 in the side surfaces 5A to 5D and modified into properties different from that of the SiC semiconductor substrate 6.

SELECTED DRAWING: Figure 3

COPYRIGHT: (C)2023,JPO&INPIT

Description

The present invention relates to SiC semiconductor devices.

In recent years, a SiC semiconductor wafer processing method called a stealth dicing method has attracted attention. In the stealth dicing method, a SiC semiconductor wafer is selectively irradiated with a laser beam and then cut along the portion irradiated with the laser beam. According to this method, the SiC semiconductor wafer having a relatively high hardness can be cut without using a cutting member such as a dicing blade, so that the manufacturing time can be shortened.

Patent Literature 1 discloses a method for manufacturing a SiC semiconductor device using the stealth dicing method. In the manufacturing method of Patent Literature 1, a plurality of rows of modified regions (modified layers) are formed on the entire side surfaces of SiC semiconductor chips (SiC semiconductor layers) cut out from a SiC semiconductor wafer. The multiple rows of modified regions extend along the tangential direction of the main surface of the SiC semiconductor chip and are formed at intervals in the normal direction of the main surface of the SiC semiconductor chip.

JP 2012-146878 A

The modified layer is formed by modifying the SiC single crystal to have other properties. Therefore, considering the influence of the modified layer on the SiC semiconductor chip (SiC semiconductor layer), it is not desirable to form a plurality of modified layers on the entire side surface of the SiC semiconductor chip. Examples of the influence of the modified layer on the SiC semiconductor chip include fluctuations in the electrical characteristics of the SiC semiconductor chip due to the modified layer and the generation of cracks in the SiC semiconductor chip originating from the modified layer. be.

One embodiment provides a SiC semiconductor device capable of reducing the influence of the modified layer on the SiC semiconductor chip.

One embodiment has a laminated structure including a SiC semiconductor substrate and a SiC epitaxial layer, and has an element forming surface formed by the SiC epitaxial layer and a side surface formed by the SiC semiconductor substrate and the SiC epitaxial layer. a SiC semiconductor chip; and a single modified layer formed on the side surface of the SiC semiconductor substrate at a distance from the SiC epitaxial layer and modified to have a property different from that of the SiC semiconductor substrate. A SiC semiconductor device comprising: According to this structure, it is possible to reduce the influence of the modified layer on the SiC semiconductor chip, especially on the SiC epitaxial layer forming the element forming surface.

In one embodiment, a SiC semiconductor chip having a first main surface as an element forming surface, a second main surface opposite to the first main surface, and side surfaces, and exposed from the first main surface and the side surfaces and a first conductivity type impurity region having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the first impurity region, and the A first conductor exposed from the second main surface and the side surfaces and formed in a region on the second main surface side with respect to the first impurity region so as to be electrically connected to the first impurity region. a second impurity region of the mold, and a single single impurity region formed on the side surface at a portion where the second impurity region is exposed at a distance from the first impurity region and modified to have properties different from those of the SiC semiconductor chip. and a modified layer. According to this structure, it is possible to reduce the influence of the modified layer on the SiC semiconductor chip, particularly on the element formation surface where the first impurity region is exposed.

FIG. 1 is a diagram showing a unit cell of 4H—SiC single crystal applied to an embodiment of the present invention. FIG. 2 is a plan view showing the silicon surface of the unit cell of the 4H—SiC single crystal shown in FIG. FIG. 3 is a perspective view of the SiC semiconductor device according to the first embodiment of the present invention as viewed from one angle, and is a perspective view showing a first example of a modification line. FIG. 4 is a perspective view of the SiC semiconductor device shown in FIG. 3 as seen from another angle. FIG. 5 is an enlarged view of region V shown in FIG. FIG. 6 is an enlarged view of area VI shown in FIG. 7 is a plan view of the SiC semiconductor device shown in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 7. FIG. 9 is a perspective view showing a SiC semiconductor wafer used for manufacturing the SiC semiconductor device shown in FIG. 3. FIG. 10A is a cross-sectional view showing an example of a method for manufacturing the SiC semiconductor device shown in FIG. 3. FIG. FIG. 10B is a diagram showing the process after FIG. 10A. FIG. 10C is a diagram showing the process after FIG. 10B. FIG. 10D is a diagram showing the process after FIG. 10C. FIG. 10E is a diagram showing the process after FIG. 10D. FIG. 10F is a diagram showing the process after FIG. 10E. FIG. 10G is a diagram showing the process after FIG. 10F. FIG. 10H is a diagram showing the process after FIG. 10G. FIG. 10I is a diagram showing the process after FIG. 10H. FIG. 10J is a diagram showing the process after FIG. 10I. FIG. 10K is a diagram showing the process after FIG. 10J. FIG. 10L is a diagram showing the process after FIG. 10K. FIG. 10M is a diagram showing the process after FIG. 10L. FIG. 11 is a perspective view showing a semiconductor package in which the SiC semiconductor device shown in FIG. 3 is incorporated, through a sealing resin. 12A is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a second embodiment of the modification line. FIG. 12B is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a third embodiment of the modification line. FIG. 12C is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a fourth embodiment of the modification line. FIG. 12D is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a fifth embodiment of the modification line. FIG. 12E is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a sixth example of the modification line. FIG. FIG. 13 is a perspective view showing a SiC semiconductor device according to a second embodiment of the present invention, which is a perspective view showing a structure to which the modification line according to the first embodiment is applied. FIG. 14 is a perspective view of the SiC semiconductor device according to the third embodiment of the present invention as seen from one angle, and is a perspective view showing a structure to which the modification line according to the first embodiment is applied. FIG. 15 is a perspective view of the SiC semiconductor device shown in FIG. 14 viewed from another angle. 16 is a plan view showing the SiC semiconductor device shown in FIG. 14. FIG. FIG. 17 is a plan view of FIG. 16 with the resin layer removed. FIG. 18 is an enlarged view of region XVIII shown in FIG. 17 and is a view for explaining the structure of the first main surface of the SiC semiconductor layer. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 18. FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 18. FIG. FIG. 21 is an enlarged view of area XXI shown in FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 17. FIG. FIG. 23 is an enlarged view of region XXIII shown in FIG. FIG. 24 is a graph for explaining sheet resistance. FIG. 25 is an enlarged view of a region corresponding to FIG. 18, showing a SiC semiconductor device according to the fourth embodiment of the present invention. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 25. FIG. FIG. 27 is an enlarged view of a region corresponding to FIG. 21, showing the SiC semiconductor device according to the fifth embodiment of the present invention. FIG. 28 is an enlarged view of a region corresponding to FIG. 18, showing the SiC semiconductor device according to the sixth embodiment of the present invention.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

In the embodiment of the present invention, a hexagonal SiC (silicon carbide) single crystal is applied. Hexagonal SiC single crystals have a plurality of polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals and 6H-SiC single crystals, depending on the period of the atomic arrangement. In the embodiments of the present invention, examples in which 4H—SiC single crystals are applied will be described, but other polytypes are not excluded from the present invention.

The crystal structure of the 4H—SiC single crystal will be described below. FIG. 1 is a diagram showing a 4H—SiC single crystal unit cell (hereinafter simply referred to as “unit cell”) applied to an embodiment of the present invention. FIG. 2 is a plan view showing the silicon surface of the unit cell shown in FIG.

1 and 2, the unit cell includes a tetrahedral structure in which four C atoms are bonded to one Si atom in a tetrahedral arrangement (regular tetrahedral arrangement). The unit cell has an atomic arrangement in which four tetrahedral structures are stacked. The unit cell has a hexagonal prism structure having a regular hexagonal silicon face, a regular hexagonal carbon face, and six sides connecting the silicon face and the carbon face.

A silicon plane is a termination plane terminated by Si atoms. On the silicon surface, one Si atom is positioned at each of six vertexes of a regular hexagon, and one Si atom is positioned at the center of the regular hexagon.

A carbon face is a terminated face terminated by C atoms. In the carbon plane, one C atom is positioned at each of six vertexes of a regular hexagon, and one C atom is positioned at the center of the regular hexagon.

The crystal planes of the unit cell are defined by four coordinate axes (a1, a2, a3, c) including the a1, a2, a3 and c axes. The value of a3 among the four coordinate axes takes the value of -(a1+a2). Crystal planes of a 4H—SiC single crystal will be described below with reference to a silicon plane as an example of a hexagonal termination plane.

The a1 axis, the a2 axis, and the a3 axis are the arrangement directions of the Si atoms closest to the central Si atom (hereinafter simply referred to as the "nearest atom direction") in a plan view of the silicon surface viewed from the c axis. ) are set accordingly. The a1-axis, the a2-axis and the a3-axis are each set with an angle shifted by 120° following the arrangement of Si atoms.

The c-axis is set in the normal direction of the silicon surface with reference to the Si atoms positioned at the center. The silicon plane is the (0001) plane. The carbon plane is the (000-1) plane.

The side surfaces of the hexagonal prism include six crystal planes along the direction of the closest atoms in a plan view of the silicon plane viewed from the c-axis. More specifically, the side surfaces of the hexagonal prism include six crystal planes each containing two nearest Si atoms in a plan view of the silicon plane viewed from the c-axis.

The side faces of the hexagonal column are (1-100) plane, (0-110) plane, (-1010) plane, and (-1100) plane clockwise from the tip of the a1 axis in a plan view of the silicon plane viewed from the c-axis. planes, including the (01-10) and (10-10) planes.

The diagonal planes along the diagonal lines of the hexagonal prism include six crystal planes along the intersecting directions intersecting the direction of the closest atom in a plan view of the silicon surface viewed from the c-axis. More specifically, the diagonal planes of the hexagonal prism include six crystal planes each containing two Si atoms that are not closest to each other in a plan view of the silicon plane viewed from the c-axis. When viewed on the basis of the Si atom positioned at the center, the intersecting direction of the nearest-neighbor atom direction is the orthogonal direction perpendicular to the nearest-neighbor atom direction.

The diagonal planes of the hexagonal prism are (11-20) plane, (1-210) plane, (-2110) plane, (-1-120) plane, (- Including the 12-10) plane and the (2-1-10) plane.

The crystal orientation of the unit cell is defined by the normal direction of the crystal plane. The normal direction of the (1-100) plane is the [1-100] direction. The normal direction of the (0-110) plane is the [0-110] direction. The normal direction of the (−1010) plane is the [−1010] direction. The normal direction of the (−1100) plane is the [−1100] direction. The normal direction of the (01-10) plane is the [01-10] direction. The normal direction of the (10-10) plane is the [10-10] direction.

The normal direction of the (11-20) plane is the [11-20] direction. The normal direction of the (1-210) plane is the [1-210] direction. The normal direction of the (−2110) plane is the [−2110] direction. The normal direction of the (-1-120) plane is the [-1-120] direction. The normal direction of the (-12-10) plane is the [-12-10] direction. The normal direction of the (2-1-10) plane is the [2-1-10] direction.

A hexagonal crystal has 6-fold symmetry, with equivalent crystal planes and equivalent crystal directions every 60°. For example, the (1-100), (0-110), (-1010), (-1100), (01-10) and (10-10) planes form equivalent crystal planes. ing.

In addition, the [1-100] direction, [0-110] direction, [-1010] direction, [-1100] direction, [01-10] direction and [10-10] direction form equivalent crystal directions. ing. In addition, [11-20] direction, [1-210] direction, [-2110] direction, [-1-120] direction, [-12-10] direction and [2-1-10] direction are equivalent forming a crystal orientation.

The c-axis is the [0001] direction ([000-1] direction). The a1 axis is the [2-1-10] direction ([-2110] direction). The a2 axis is the [-12-10] direction ([1-210] direction). The a3 axis is the [-1-120] direction ([11-20] direction).

The (0001) plane and the (000-1) plane are collectively referred to as the c-plane. The [0001] direction and the [000-1] direction are collectively referred to as the c-axis direction. The (11-20) plane and the (-1-120) plane are collectively referred to as the a-plane. The [11-20] direction and the [-1-120] direction are collectively referred to as the a-axis direction. The (1-100) plane and the (-1100) plane are collectively referred to as the m-plane. The [1-100] direction and the [-1100] direction are collectively referred to as the m-axis direction.

FIG. 3 is a perspective view of the SiC semiconductor device 1 according to the first embodiment of the present invention viewed from one angle, and is a perspective view showing a first example of modification lines 22A to 22D. FIG. 4 is a perspective view of the SiC semiconductor device 1 shown in FIG. 3 as seen from another angle.

FIG. 5 is an enlarged view of region V shown in FIG. FIG. 6 is an enlarged view of area VI shown in FIG. FIG. 7 is a plan view of SiC semiconductor device 1 shown in FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 7. FIG.

3 to 8, SiC semiconductor device 1 includes a SiC semiconductor layer 2. As shown in FIG. The SiC semiconductor layer 2 includes a 4H—SiC single crystal as an example of a hexagonal SiC single crystal. The SiC semiconductor layer 2 (SiC semiconductor chip) is formed in the shape of a rectangular parallelepiped chip.

SiC semiconductor layer 2 has first main surface 3 on one side, second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting first main surface 3 and second main surface 4. is doing. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (square shape in this embodiment) in plan view (hereinafter simply referred to as "plan view") when viewed from the normal direction Z. .

The first main surface 3 is an element formation surface on which a semiconductor element is formed. The second main surface 4 of the SiC semiconductor layer 2 is a ground surface having grinding marks. The side surfaces 5A to 5D each consist of a smooth cleavage plane facing the crystal plane of the SiC single crystal. The side surfaces 5A-5D do not have grinding marks.

The thickness TL of the SiC semiconductor layer 2 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm to 60 μm, 60 μm to 80 μm, 80 μm to 100 μm, 100 μm to 120 μm, 120 μm to 140 μm, 140 μm to 160 μm, 160 μm to 180 μm, or 180 μm to 200 μm. The thickness TL is preferably 60 μm or more and 150 μm or less.

The first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal in this embodiment. The first main surface 3 faces the (0001) plane (silicon plane). The second main surface 4 faces the (000-1) plane (carbon plane) of the SiC single crystal.

The first main surface 3 and the second main surface 4 have an off angle θ of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by an off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

The off angle θ may be 0° or more and 5.0° or less. The off angle θ is 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, or 2.5°. ° to 3.0°, 3.0° to 3.5°, 3.5° to 4.0°, 4.0° to 4.5° or 4.5° to 5.0° It may be set within the following angle range. The off angle θ is preferably greater than 0°. The off angle θ may be less than 4.0°.

The off angle θ may be set within an angle range of 3.0° or more and 4.5° or less. In this case, the off angle θ is preferably set in the range of 3.0° or more and 3.5° or less or 3.5° or more and 4.0° or less.

The off angle θ may be set within an angle range of 1.5° or more and 3.0° or less. In this case, the off angle θ is preferably set within an angle range of 1.5° or more and 2.0° or less or 2.0° or more and 2.5° or less.

Each of the side surfaces 5A to 5D may have a length of 0.5 mm or more and 10 mm or less. The surface areas of the sides 5A-5D are equal to each other in this configuration. When the first main surface 3 and the second main surface 4 are formed in a rectangular shape in plan view, the surface areas of the side surfaces 5A and 5C may be less than the surface areas of the side surfaces 5B and 5D. may exceed the surface area of

5 A of side surfaces and 5 C of side surfaces are extended along the 1st direction X, and are mutually opposed to the 2nd direction Y which cross|intersects the 1st direction X in this form. The side surface 5B and the side surface 5D extend along the second direction Y and face each other in the first direction X in this embodiment. The second direction Y is a direction perpendicular to the first direction X, more specifically.

The first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal in this embodiment. The second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

Side 5A and side 5C are formed by the a-plane of SiC single crystal and face each other in the a-axis direction. The side surface 5A is formed by the (-1-120) plane of the SiC single crystal. The side surface 5C is formed by the (11-20) plane of the SiC single crystal.

Side 5B and side 5D are formed by the m-plane of SiC single crystal and face each other in the m-axis direction. The side surface 5B is formed by the (-1100) plane of the SiC single crystal. The side surface 5D is formed by the (1-100) plane of SiC single crystal.

The side surface 5A and the side surface 5C are inclined toward the c-axis direction ([0001] direction) of the SiC single crystal with respect to the normal line of the first main surface 3 of the SiC semiconductor layer 2. It may form a surface.

In this case, when the normal to the first main surface 3 of the SiC semiconductor layer 2 is 0°, the side surface 5A and the side surface 5C are at an off angle θ with respect to the normal to the first main surface 3 of the SiC semiconductor layer 2. You may incline at the corresponding angle. The angle corresponding to the off angle θ may be equal to the off angle θ, or may be an angle exceeding 0° and less than the off angle θ.

On the other hand, side surface 5B and side surface 5D extend planarly along the normal to first main surface 3 of SiC semiconductor layer 2 . More specifically, side surface 5B and side surface 5D are formed substantially perpendicular to first main surface 3 and second main surface 4 .

In this embodiment, the SiC semiconductor layer 2 has a laminated structure including an n ⁺ -type SiC semiconductor substrate 6 (second impurity region) and an n-type SiC epitaxial layer 7 (first impurity region). The SiC semiconductor substrate 6 forms the second main surface 4 of the SiC semiconductor layer 2 .

SiC epitaxial layer 7 forms first main surface 3 of SiC semiconductor layer 2 . SiC semiconductor substrate 6 and SiC epitaxial layer 7 form side surfaces 5A to 5D of SiC semiconductor layer 2 .

The n-type impurity concentration of SiC epitaxial layer 7 is equal to or lower than the n-type impurity concentration of SiC semiconductor substrate 6 . The n-type impurity concentration of SiC epitaxial layer 7 is more specifically less than the n-type impurity concentration of SiC semiconductor substrate 6 . SiC semiconductor substrate 6 may have an n-type impurity concentration of 1.0×10 ¹⁸ cm ⁻³ or more and 1.0×10 ²¹ cm ⁻³ or less. The n-type impurity concentration of SiC epitaxial layer 7 may be 1.0×10 ¹⁵ cm ⁻³ or more and 1.0×10 ¹⁸ cm ⁻³ or less.

The thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. The thickness TS is 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, It may be 130 μm or more and 140 μm or less or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 6, it is possible to reduce the resistance value by shortening the current path.

The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness TE is 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or It may be 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

An active region 8 and an outer region 9 are set in the SiC semiconductor layer 2 . The active region 8 is a region in which a Schottky barrier diode D as an example of a semiconductor element is formed. The outer area 9 is the area outside the active area 8 .

The active region 8 is set in the central portion of the SiC semiconductor layer 2 with a gap in the inner region from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view. The active region 8 is set in a rectangular shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

Outer region 9 is set in a region between side surfaces 5A to 5D of SiC semiconductor layer 2 and the periphery of active region 8 . The outer region 9 is set in an endless shape (in this form, a square ring shape) surrounding the active region 8 in plan view.

A main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2 . A main surface insulating layer 10 selectively covers the active area 8 and the outer area 9 . The main surface insulating layer 10 may have a single layer structure consisting of a silicon oxide (SiO ₂ ) layer or a silicon nitride (SiN) layer.

Main surface insulating layer 10 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed over the silicon nitride layer. The silicon nitride layer may be formed over the silicon oxide layer. The main surface insulating layer 10 has a single-layer structure made of a silicon oxide layer in this embodiment.

Main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C, and 11D exposed from side surfaces 5A to 5D of SiC semiconductor layer 2 . The insulating side surfaces 11A to 11D are continuous with the side surfaces 5A to 5D of the SiC semiconductor layer 2, respectively. The insulating side surfaces 11A to 11D are formed flush with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are composed of cleaved surfaces.

The thickness of the principal surface insulating layer 10 may be 1 μm or more and 50 μm or less. The thickness of the principal surface insulating layer 10 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

A first principal-surface electrode layer 12 is formed on the principal-surface insulating layer 10 . The first principal-surface electrode layer 12 is formed in the central portion of the SiC semiconductor layer 2 with a gap in the inner region from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

A passivation layer 13 (insulating layer) is formed on the main surface insulating layer 10 . Passivation layer 13 may have a single layer structure consisting of a silicon oxide layer or a silicon nitride layer.

Passivation layer 13 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed over the silicon nitride layer. The silicon nitride layer may be formed over the silicon oxide layer. The passivation layer 13 has a single layer structure made of a silicon nitride layer in this embodiment.

Side surfaces 14A, 14B, 14C, and 14D of passivation layer 13 are spaced inward from side surfaces 5A to 5D of SiC semiconductor layer 2 in plan view. Passivation layer 13 exposes the periphery of first main surface 3 of SiC semiconductor layer 2 in plan view. Passivation layer 13 exposes main surface insulating layer 10 .

A sub-pad opening 15 is formed in the passivation layer 13 to expose a portion of the first main surface electrode layer 12 as a pad region. Sub-pad opening 15 is formed in a rectangular shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in plan view.

The thickness of the passivation layer 13 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 13 may be 1 μm to 10 μm, 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm.

A resin layer 16 (insulating layer) is formed on the passivation layer 13 . The passivation layer 13 and the resin layer 16 form one insulating laminated structure (insulating layer). In FIG. 7, the resin layer 16 is indicated by hatching.

The resin layer 16 may contain a negative type or positive type photosensitive resin. In this embodiment, the resin layer 16 contains polybenzoxazole as an example of a positive photosensitive resin. The resin layer 16 may contain polyimide as an example of a negative type photosensitive resin.

The resin side surfaces 17A, 17B, 17C, and 17D of the resin layer 16 are spaced inward from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view. The resin layer 16 exposes the periphery of the first main surface 3 of the SiC semiconductor layer 2 in plan view. The resin layer 16 exposes the main surface insulating layer 10 together with the passivation layer 13 . The resin side surfaces 17A to 17D of the resin layer 16 are formed flush with the side surfaces 14A to 14D of the passivation layer 13 in this embodiment.

The resin side surfaces 17A to 17D of the resin layer 16 are portions that define dicing streets when the SiC semiconductor device 1 is cut out from one SiC semiconductor wafer. In this form, the side surfaces 14A to 14D of the passivation layer 13 are also portions that define the dicing streets.

By exposing the peripheral portion of first main surface 3 of SiC semiconductor layer 2 from resin layer 16 and passivation layer 13 , it is not necessary to physically cut resin layer 16 and passivation layer 13 . Thereby, the SiC semiconductor device 1 can be smoothly cut out from one SiC semiconductor wafer. Moreover, the insulating distance from the side surfaces 5A to 5D of the SiC semiconductor layer 2 can be increased.

The distance between the side surfaces 5A-5D and the resin side surfaces 17A-17D (side surfaces 14A-14D) may be 1 μm or more and 25 μm or less. Even if the distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) is 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. good. Of course, side surfaces 14A to 14D of passivation layer 13 may be formed flush with side surfaces 5A to 5D of SiC semiconductor layer 2 .

A pad opening 18 is formed in the resin layer 16 to expose a portion of the first main surface electrode layer 12 as a pad region. Pad opening 18 is formed in a rectangular shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in plan view.

Pad opening 18 communicates with sub-pad opening 15 . The inner wall of the pad opening 18 is flush with the inner wall of the sub-pad opening 15 . The inner wall of pad opening 18 may be located on the side of side surfaces 5A to 5D of SiC semiconductor layer 2 with respect to the inner wall of sub-pad opening 15 . The inner wall of pad opening 18 may be located in the inner region of SiC semiconductor layer 2 with respect to the inner wall of sub-pad opening 15 . The resin layer 16 may cover the inner wall of the sub-pad opening 15 .

The thickness of the resin layer 16 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 16 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

A second main surface electrode layer 19 is formed on the second main surface 4 of the SiC semiconductor layer 2 . The second main surface electrode layer 19 forms an ohmic contact with the second main surface 4 (SiC semiconductor substrate 6) of the SiC semiconductor layer 2. As shown in FIG.

A plurality of modified lines 22A to 22D (modified layers) are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2, respectively. More specifically, the reforming lines 22A to 22D are formed layer by layer on the side surfaces 5A to 5D in a one-to-one correspondence relationship.

The modified lines 22A to 22D include a single-layer modified line 22A formed on the side surface 5A, a single-layer modified line 22B formed on the side surface 5B, a single-layer modified line 22C formed on the side surface 5C, and a single-layer modified line 22D formed on the side surface 5D. Modification lines 22A-22D consist of a single layer in this configuration.

A mode in which a plurality of reforming lines 22A are formed so as to overlap each other in the reforming line 22A of one layer, so that one layer of reforming line 22A can be regarded as being formed by the reforming line 22A composed of a plurality of layers. may be included.

A plurality of reforming lines 22B are formed overlapping each other in one layer of reforming line 22B, so that one layer of reforming line 22B can be regarded as being formed by reforming line 22B composed of a plurality of layers. may be included.

A plurality of reforming lines 22C are formed to overlap each other in the reforming line 22C of one layer, so that the reforming line 22C composed of a plurality of layers can be regarded as forming one reforming line 22C. may be included.

A plurality of reforming lines 22D are formed overlapping each other in one layer of reforming line 22D, so that one layer of reforming line 22D can be considered to be formed by reforming line 22D composed of multiple layers. may be included.

However, in these cases, multiple layers of modified lines 22A to 22D must be formed on the corresponding side surfaces 5A to 5D, which is not preferable from the viewpoint of an increase in man-hours and a delay in manufacturing time. Therefore, this embodiment shows an example in which reforming lines 22A to 22D each made of a single layer are formed on each of the side surfaces 5A to 5D.

Modified lines 22A-22D include layered regions in which a portion of the SiC single crystal forming side surfaces 5A-5D is modified to have properties different from those of the SiC single crystal. Modified lines 22A-22D include regions modified to have different physical properties from SiC single crystals such as density, refractive index, mechanical strength (crystal strength), or other physical properties.

Modification lines 22A-22D may include at least one layer of a melt rehardening layer, a defect layer, a dielectric breakdown layer, or a refractive index change layer. The melt rehardened layer is a layer that is hardened again after part of the SiC semiconductor layer 2 has been melted. The defect layer is a layer containing holes, cracks, etc. formed in the SiC semiconductor layer 2 . A dielectric breakdown layer is a layer in which a part of the SiC semiconductor layer 2 is dielectrically broken down. The refractive index change layer is a layer in which part of the SiC semiconductor layer 2 is changed to have a refractive index different from that of the SiC single crystal.

The modification lines 22A to 22D extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2 . The tangential direction of the first main surface 3 is a direction orthogonal to the normal direction Z. As shown in FIG. The tangential direction includes a first direction X (the m-axis direction of the SiC single crystal) and a second direction Y (the a-axis direction of the SiC single crystal).

More specifically, the reforming line 22A is formed in a strip shape extending linearly along the m-axis direction on the side surface 5A. Further, the reforming line 22B is formed in a strip shape extending linearly along the a-axis direction on the side surface 5B. Further, the reforming line 22C is formed in a strip shape extending linearly along the m-axis direction on the side surface 5C. Further, the reforming line 22D is formed in a strip shape extending linearly along the a-axis direction on the side surface 5D.

The modification lines 22A to 22D are formed from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2 at intervals. The modification lines 22A-22D expose the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2 from the side surfaces 5A-5D. In other words, modification lines 22A to 22D are not formed in main surface insulating layer 10, passivation layer 13 and resin layer 16. FIG.

The modification lines 22A to 22D are formed from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2 at intervals. The modification lines 22A-22D expose the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A-5D.

As a result, the modification lines 22A to 22D form the side surfaces 5A to 5D of the SiC semiconductor layer 2 on the side of the first main surface 3 when viewed from the normal direction of the side surfaces 5A to 5D of the SiC semiconductor layer 2. It is divided into a region and a region on the second main surface 4 side.

Modification lines 22A to 22D are formed in SiC semiconductor substrate 6 . Modification lines 22A-22D are formed on second main surface 4 at intervals from the boundary between SiC semiconductor substrate 6 and SiC epitaxial layer 7 .

Thereby, the modification lines 22A to 22D expose the SiC epitaxial layer 7 in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2 . That is, the SiC epitaxial layer 7 is included in a region on the first main surface 3 side of the regions divided into two by the modification lines 22A to 22D on the side surfaces 5A to 5D of the SiC semiconductor layer 2 .

On each of the side surfaces 5A to 5D, modification lines 22A to 22D, a surface layer portion of the first main surface 3 of the SiC semiconductor layer 2, and a surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 form a line tangential to the first main surface 3. A stripe pattern extending in the direction is formed.

Modification line 22A and modification line 22B are connected to each other at a corner connecting side surface 5A and side surface 5B of SiC semiconductor layer 2 . Modification line 22B and modification line 22C are connected to each other at a corner connecting side surface 5B and side surface 5C of SiC semiconductor layer 2 .

Modified line 22</b>C and modified line 22</b>D are connected to each other at a corner connecting side surface 5</b>C and side surface 5</b>D of SiC semiconductor layer 2 . Modification line 22</b>D and modification line 22</b>A are connected to each other at a corner connecting side surface 5</b>D and side surface 5</b>A of SiC semiconductor layer 2 .

Thereby, the modification lines 22A to 22D are integrally formed so as to surround the SiC semiconductor layer 2. As shown in FIG. That is, the modification lines 22A to 22D form one endless (annular) modification line surrounding the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2 .

The thickness TR of the modified lines 22A to 22D with respect to the normal direction Z is preferably equal to or less than the thickness TL of the SiC semiconductor layer 2 (TR≦TL). More preferably, the thickness TR of the modified lines 22A-22D is less than the thickness TS of the SiC semiconductor substrate 6 (TR<TS).

The thickness TR of the modified lines 22A to 22D may be equal to or greater than the thickness TE of the SiC epitaxial layer 7 (TR≧TE). The thickness TR of the modified line 22A, the thickness TR of the modified line 22B, the thickness TR of the modified line 22C, and the thickness TR of the modified line 22D may be equal to or different from each other. may

A ratio TR/TL of the thickness TR of the modified lines 22A to 22D to the thickness TL of the SiC semiconductor layer 2 is preferably 0.1 or more and less than 1.0. The ratio TR/TL is 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0. may be

The ratio TR/TL is 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less. , 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR/TL is preferably 0.2 or more and 0.5 or less.

A ratio TR/TS of thickness TR of modified lines 22A to 22D to thickness TS of SiC semiconductor substrate 6 is more preferably 0.1 or more and less than 1.0. The ratio TR/TS is 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0. may be

The ratio TR/TS is 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less. , 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR/TS is preferably 0.2 or more and 0.5 or less.

Referring to FIG. 5, the reforming line 22A includes a plurality of a-plane reforming sections 28 (reforming sections). In other words, the modified line 22A is formed by an aggregate of a plurality of a-surface modified portions 28. As shown in FIG. A plurality of a-plane modified portions 28 are portions in which the SiC single crystal exposed from the side surface 5A has been modified to have properties different from those of the SiC single crystal. A region around each a-plane modified portion 28 on the side surface 5A may be modified to have properties different from those of the SiC single crystal.

The plurality of a-plane modified portions 28 connect one end portion 28a located on the first main surface 3 side, the other end portion 28b located on the second main surface 4 side, and the one end portion 28a and the other end portion 28b. Each includes a connecting portion 28c.

The plurality of a-plane modified portions 28 are formed linearly extending in the normal direction Z, respectively. As a result, the plurality of a-plane modified portions 28 are formed in stripes as a whole. The plurality of a-plane modified portions 28 may include a plurality of a-plane modified portions 28 formed in a tapered shape in which the width in the m-axis direction narrows from the one end portion 28a side toward the other end portion 28b side.

The plurality of a-plane modified portions 28 are formed at intervals in the m-axis direction so as to face each other in the m-axis direction. A plurality of a-plane modified portions 28 may overlap each other in the m-axis direction. A strip-shaped region extending in the m-axis direction is formed by a line connecting one ends 28a of the plurality of a-plane modified portions 28 and a line connecting the other ends 28b of the plurality of a-plane modified portions 28. FIG. The reforming line 22A is formed by this belt-like region.

The plurality of a-surface modified portions 28 may each form a notch portion obtained by notching the side surface 5A. The plurality of a-plane modified portions 28 may each form a recess that is recessed in the a-axis direction from the side surface 5A. The plurality of a-plane modified portions 28 may be formed in a point shape (dot shape) according to the length in the normal direction Z and the width in the m-axis direction.

In the m-axis direction, the pitch PR between the central portions of the plurality of adjacent a-plane modified portions 28 may be more than 0 μm and 20 μm or less. The pitch PR may be greater than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

With respect to the m-axis direction, the width WR of each a-plane modified portion 28 may exceed 0 μm and be 20 μm or less. The width WR may be greater than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

The reforming line 22C has the same structure as the reforming line 22A except that it is formed on the side surface 5C. The description of the reforming line 22A is applied mutatis mutandis to the description of the reforming line 22C by reading the "side surface 5A" as "the side surface 5C".

Referring to FIG. 6, a modification line 22D includes a plurality of m-plane modification portions 29 (modification portions). In other words, the modified line 22</b>D is formed by an aggregate of multiple m-plane modified portions 29 . A plurality of m-plane modified portions 29 are portions in which the SiC single crystal exposed from the side surface 5D has been modified to have properties different from those of the SiC single crystal. A region around each m-plane modified portion 29 on the side surface 5D may be modified to have properties different from those of the SiC single crystal.

The plurality of m-plane modified portions 29 connect one end portion 29a located on the first main surface 3 side, the other end portion 29b located on the second main surface 4 side, and the one end portion 29a and the other end portion 29b. Each includes a connecting portion 29c.

The plurality of m-plane modified portions 29 are formed linearly extending in the normal direction Z, respectively. As a result, the plurality of m-plane modified portions 29 are formed in stripes as a whole. The plurality of m-plane modified portions 29 may include a plurality of m-plane modified portions 29 formed in a tapered shape in which the width in the a-axis direction narrows from the one end portion 29a side toward the other end portion 29b side.

A plurality of m-plane modified portions 29 are formed at intervals in the a-axis direction so as to face each other in the a-axis direction. A plurality of m-plane modified portions 29 may overlap each other in the a-axis direction. A band-like region extending in the a-axis direction is formed by a line connecting one ends 29a of the plurality of m-plane modified portions 29 and a line connecting the other ends 29b of the plurality of m-plane modified portions 29. FIG. The modified line 22D is formed by this belt-like region.

The plurality of m-plane modified portions 29 may each form a notch portion obtained by notching the side surface 5D. The plurality of m-plane modified portions 29 may each form a recess that is recessed in the m-axis direction from the side surface 5D. The plurality of m-plane modified portions 29 may be formed in a point shape (dot shape) according to the length in the normal direction Z and the width in the a-axis direction.

A pitch PR between central portions of the plurality of m-plane modified portions 29 adjacent to each other in the a-axis direction may be 0 μm or more and 20 μm or less. The pitch PR may be 0 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, or 15 μm to 20 μm.

The width WR of each m-plane modified portion 29 in the a-axis direction may be greater than 0 μm and equal to or less than 20 μm. The width WR may be greater than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

The modified line 22B has the same structure as the modified line 22D except that it is formed on the side surface 5B. The description of the reforming line 22D is applied mutatis mutandis to the description of the reforming line 22B by reading "side surface 5D" as "side surface 5B".

Referring to FIG. 8 , an n-type diode region 35 is formed in the surface layer portion of first main surface 3 of SiC semiconductor layer 2 in active region 8 . Diode region 35 is formed in the central portion of first main surface 3 of SiC semiconductor layer 2 in this embodiment. In this embodiment, the diode region 35 is set in a square shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in plan view.

The n-type impurity concentration of diode region 35 may be equal to or higher than the n-type impurity concentration of SiC epitaxial layer 7 . Diode region 35 is formed using part of SiC epitaxial layer 7 in this embodiment. The n-type impurity concentration of diode region 35 is equal to the n-type impurity concentration of SiC epitaxial layer 7 . Diode region 35 may be formed by introducing an n-type impurity into the surface layer of SiC epitaxial layer 7 .

A p ⁺ -type guard region 36 is formed in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2 in the outer region 9 . The guard region 36 is formed in a strip shape extending along the diode region 35 in plan view.

More specifically, the guard region 36 is formed in an endless shape (for example, a square ring shape, a square ring shape with chamfered corners, or a ring shape) surrounding the diode region 35 in plan view. Thus, the guard region 36 is formed as a guard ring region. Diode region 35 is defined by guard region 36 in this embodiment. Also, the active area 8 is defined by a guard area 36 .

The p-type impurity in guard region 36 may not be activated. In this case, guard region 36 is formed as a non-semiconductor region. The p-type impurity in guard region 36 may be activated. In this case, guard region 36 is formed as a p-type semiconductor region.

The aforementioned main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2 . A diode opening 37 that exposes the diode region 35 is formed in the main surface insulating layer 10 . Diode opening 37 exposes the inner peripheral edge of guard region 36 in addition to diode region 35 . Diode opening 37 is formed in a rectangular shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in plan view.

The above-described first main-surface electrode layer 12 is formed on the main-surface insulating layer 10 . The first main-surface electrode layer 12 enters the diode opening 37 from above the insulating layer. The first main surface electrode layer 12 is electrically connected to the diode region 35 within the diode opening 37 .

More specifically, the first main-surface electrode layer 12 forms a Schottky junction with the diode region 35 . Thereby, a Schottky barrier diode D having the first main surface electrode layer 12 as an anode and the diode region 35 as a cathode is formed. The above-described passivation layer 13 and resin layer 16 are formed on the principal surface insulating layer 10 .

FIG. 9 is a perspective view showing a SiC semiconductor wafer 41 used for manufacturing SiC semiconductor device 1 shown in FIG.

The SiC semiconductor wafer 41 is a base member of the SiC semiconductor substrate 6 . The SiC semiconductor wafer 41 includes a 4H—SiC single crystal as an example of a hexagonal SiC single crystal. SiC semiconductor wafer 41 in this embodiment has an n-type impurity concentration corresponding to the n-type impurity concentration of SiC semiconductor substrate 6 .

SiC semiconductor wafer 41 is formed in a plate-like or board-like shape. SiC semiconductor wafer 41 may be formed in a disc shape. The SiC semiconductor wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43 . ing.

The thickness TW of the SiC semiconductor wafer 41 exceeds the thickness TS of the SiC semiconductor substrate 6 (TS<TW). The thickness TW of the SiC semiconductor wafer 41 is matched with the thickness TS of the SiC semiconductor substrate 6 by grinding.

The thickness TW may be greater than 150 μm and less than or equal to 750 μm. The thickness TW may be greater than 150 μm and 300 μm or less, 300 μm or more and 450 μm or less, 450 μm or more and 600 μm or less or 600 μm or more and 750 μm or less. Considering the grinding time of the SiC semiconductor wafer 41, the thickness TW is preferably over 150 μm and 500 μm or less. The thickness TW is typically 300 μm or more and 450 μm or less.

The first wafer main surface 42 and the second wafer main surface 43 face the c-plane of the SiC single crystal in this embodiment. The first wafer main surface 42 faces the (0001) plane (silicon plane). The second wafer main surface 43 faces the (000-1) plane (carbon plane) of the SiC single crystal.

The first wafer main surface 42 and the second wafer main surface 43 have an off-angle θ of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z of the first wafer main surface 42 is inclined by an off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

The off angle θ may be 0° or more and 5.0° or less. The off angle θ is 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, or 2.5°. ° to 3.0°, 3.0° to 3.5°, 3.5° to 4.0°, 4.0° to 4.5° or 4.5° to 5.0° It may be set within the following angle range. The off angle θ is preferably greater than 0°. The off angle θ may be less than 4.0°.

The off angle θ may be set within an angle range of 3.0° or more and 4.5° or less. In this case, the off angle θ is preferably set in the range of 3.0° or more and 3.5° or less or 3.5° or more and 4.0° or less.

The off angle θ may be set within an angle range of 1.5° or more and 3.0° or less. In this case, the off angle θ is preferably set within an angle range of 1.5° or more and 2.0° or less or 2.0° or more and 2.5° or less.

SiC semiconductor wafer 41 includes a first wafer corner portion 45 connecting first wafer main surface 42 and wafer side surface 44 and a second wafer corner portion 46 connecting second wafer main surface 43 and wafer side surface 44 . The first wafer corner portion 45 has a first chamfered portion 47 inclined downward from the first wafer main surface 42 toward the wafer side surface 44 . The second wafer corner portion 46 has a second chamfered portion 48 inclined downward from the second wafer main surface 43 toward the wafer side surface 44 .

The first chamfered portion 47 may be formed in a convex curved shape. The second chamfered portion 48 may be formed in a convex curved shape. First chamfered portion 47 and second chamfered portion 48 suppress cracks in SiC semiconductor wafer 41 .

One orientation flat 49 is formed on the wafer side surface 44 of the SiC semiconductor wafer 41 as an example of a mark indicating the crystal orientation of the SiC single crystal. The orientation flat 49 is a notch formed in the wafer side surface 44 of the SiC semiconductor wafer 41 . The orientation flat 49 in this embodiment extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal.

A wafer side surface 44 of the SiC semiconductor wafer 41 may be formed with a plurality of (for example, two) orientation flats 49 indicating the crystal orientation. The multiple (eg, two) orientation flats 49 may include a first orientation flat and a second orientation flat.

The first orientation flat may be a notch extending linearly along the a-axis direction ([11-20] direction) of the SiC single crystal. The second orientation flat may be a notch extending linearly along the m-axis direction ([1-100] direction) of the SiC single crystal.

A plurality of device formation regions 51 respectively corresponding to the SiC semiconductor devices 1 are set on the first wafer main surface 42 of the SiC semiconductor wafer 41 . The plurality of device formation regions 51 are set in a matrix arrangement at intervals in the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction).

Each device formation region 51 has four sides 52A, 52B, 52C, 52D along the crystal orientation of the SiC single crystal. The four sides 52A-52D correspond to the four side surfaces 5A-5D of the SiC semiconductor layer 2, respectively. The four sides 52A-52D include two sides 52A, 52C along the m-axis direction ([1-100] direction) and two sides 52B, 52D along the a-axis direction ([11-20] direction).

The plurality of device forming regions 51 are partitioned by grid-like cutting lines 53 extending along the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction). The lines to cut 53 include a plurality of lines to cut first 54 and a plurality of lines to cut 55 .

The multiple first lines to cut 54 each extend along the m-axis direction ([1-100] direction). The plurality of second lines to cut 55 each extend along the a-axis direction ([11-20] direction). After a predetermined structure is formed in the plurality of device forming regions 51 , the SiC semiconductor wafer 41 is cut along the lines 53 to cut, thereby cutting out the plurality of SiC semiconductor devices 1 .

10A to 10M are cross-sectional views showing an example of a method of manufacturing SiC semiconductor device 1 shown in FIG. 10A to 10M, for convenience of explanation, only regions where three SiC semiconductor devices 1 are formed are shown, and illustration of other regions is omitted.

Referring to FIG. 10A, in manufacturing SiC semiconductor device 1, first, SiC semiconductor wafer 41 is prepared (see also FIG. 9). Next, an n-type SiC epitaxial layer 7 is formed on the first wafer main surface 42 of the SiC semiconductor wafer 41 .

In the step of forming SiC epitaxial layer 7 , SiC is epitaxially grown from first wafer main surface 42 of SiC semiconductor wafer 41 . The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less.

Thereby, a SiC semiconductor wafer structure 61 including the SiC semiconductor wafer 41 and the SiC epitaxial layer 7 is formed. SiC semiconductor wafer structure 61 includes a first major surface 62 and a second major surface 63 .

A first main surface 62 and a second main surface 63 of the SiC semiconductor wafer structure 61 correspond to the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2, respectively. The thickness TWS of the SiC semiconductor wafer structure 61 may be greater than 150 μm and less than or equal to 800 μm. Preferably, the thickness TWS is greater than 150 μm and less than or equal to 550 μm.

Next, referring to FIG. 10B, p ⁺ -type guard region 36 is formed on first main surface 62 of SiC semiconductor wafer structure 61 . The step of forming guard region 36 includes a step of selectively introducing p-type impurities into the surface layer portion of first main surface 62 of SiC semiconductor wafer structure 61 through an ion implantation mask (not shown). More specifically, guard region 36 is formed in the surface layer portion of SiC epitaxial layer 7 .

Guard region 36 defines active region 8 and outer region 9 in SiC semiconductor wafer structure 61 . An n-type diode region 35 is defined in the region (active region 8 ) surrounded by the guard region 36 .

The diode region 35 may be formed by selectively introducing an n-type impurity into the surface layer portion of the first main surface 62 of the SiC semiconductor wafer structure 61 through an ion implantation mask (not shown).

Next, referring to FIG. 10C, main surface insulating layer 10 is formed on first main surface 62 of SiC semiconductor wafer structure 61 . Main surface insulating layer 10 contains silicon oxide (SiO ₂ ). Main surface insulating layer 10 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (for example, a thermal oxidation treatment method).

Next, referring to FIG. 10D , a mask 64 having a predetermined pattern is formed on main surface insulating layer 10 . Mask 64 has a plurality of openings 65 . The plurality of openings 65 expose regions in which the diode openings 37 are to be formed in the main insulating layer 10 .

Next, unnecessary portions of the main surface insulating layer 10 are removed by an etching method through the mask 64 . Thereby, a diode opening 37 is formed in the main surface insulating layer 10 . After formation of diode opening 37, mask 64 is removed.

Next, referring to FIG. 10E , a base electrode layer 66 serving as the base of first main-surface electrode layer 12 is formed on first main surface 62 of SiC semiconductor wafer structure 61 . The base electrode layer 66 is formed over the entire first main surface 62 of the SiC semiconductor wafer structure 61 and covers the main surface insulating layer 10 . The first principal-surface electrode layer 12 may be formed by a vapor deposition method, a sputtering method, or a plating method.

Next, referring to FIG. 10F, a mask 67 having a predetermined pattern is formed over base electrode layer 66 . The mask 67 has an opening 68 that exposes a region of the base electrode layer 66 other than the region where the first main surface electrode layer 12 is to be formed.

Unnecessary portions of the base electrode layer 66 are then removed by an etching method through a mask 67 . Thereby, the base electrode layer 66 is divided into a plurality of first main surface electrode layers 12 . After forming the first main surface electrode layer 12, the mask 67 is removed.

Next, referring to FIG. 10G, passivation layer 13 is formed on first main surface 62 of SiC semiconductor wafer structure 61 . Passivation layer 13 includes silicon nitride (SiN). Passivation layer 13 may be formed by a CVD method.

Next, referring to FIG. 10H, resin layer 16 is applied on passivation layer 13 . The resin layer 16 collectively covers the active area 8 and the outer area 9 . The resin layer 16 may contain polybenzoxazole as an example of a positive type photosensitive resin.

Next, referring to FIG. 10I, the resin layer 16 is selectively exposed and then developed. Thereby, pad openings 18 are formed in the resin layer 16 . Further, dicing streets 69 along the planned cutting lines 53 (sides 52A to 52D of each device formation region 51) are defined in the resin layer 16. As shown in FIG.

Unnecessary portions of the passivation layer 13 are then removed. Unnecessary portions of passivation layer 13 may be removed by an etching method through resin layer 16 . A sub-pad opening 15 is thereby formed in the passivation layer 13 . A dicing street 69 along the planned cutting line 53 is defined in the passivation layer 13 .

In this embodiment, the step of removing unnecessary portions of the passivation layer 13 using the resin layer 16 has been described. However, the resin layer 16 and the pad opening 18 may be formed after the sub-pad opening 15 is formed in the passivation layer 13 .

In this case, prior to the step of forming the resin layer 16, an unnecessary portion of the passivation layer 13 is removed by etching through a mask to form the sub-pad opening 15. FIG. According to this process, the passivation layer 13 can be formed in an arbitrary shape.

Next, referring to FIG. 10J, second main surface 63 of SiC semiconductor wafer structure 61 (second wafer main surface 43 of SiC semiconductor wafer 41) is ground. Thereby, the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) is thinned. Also, grinding marks are formed on the second main surface 63 of the SiC semiconductor wafer structure 61 .

The SiC semiconductor wafer structure 61 is ground to a thickness TWS corresponding to the thickness TL of the SiC semiconductor layer 2 . The SiC semiconductor wafer structure 61 may be ground to a thickness TWS of 40 μm to 200 μm.

In other words, the SiC semiconductor wafer 41 is ground to a thickness TW corresponding to the thickness TS of the SiC semiconductor substrate 6 . The SiC semiconductor wafer 41 may be ground to a thickness TW of 40 μm or more and 150 μm or less.

Next, referring to FIG. 10K, a plurality of modified lines 70 (modified layers) are formed as bases for modified lines 22A to 22D. In the step of forming the modified line 70 , pulsed laser light is irradiated from the laser light irradiation device 71 toward the SiC semiconductor wafer structure 61 .

In this embodiment, the SiC semiconductor wafer structure 61 is irradiated with laser light from the first main surface 62 side of the SiC semiconductor wafer structure 61 through the main surface insulating layer 10 . The SiC semiconductor wafer structure 61 may be directly irradiated with the laser light from the second main surface 63 side of the SiC semiconductor wafer structure 61 .

A laser light condensing portion (focus) is set in the middle of the SiC semiconductor wafer structure 61 in the thickness direction. The laser beam irradiation position on the SiC semiconductor wafer structure 61 is moved along the planned cutting line 53 (four sides 52A to 52D of each device forming region 51).

More specifically, the laser beam irradiation position on the SiC semiconductor wafer structure 61 is moved along the first planned cutting line 54 . Further, the irradiation position of the laser beam with respect to the SiC semiconductor wafer structure 61 is moved along the second planned cutting line 55 .

As a result, the SiC semiconductor wafer structure 61 extends along the cutting lines 53 (four sides 52A to 52D of each device forming region 51) in the middle of the thickness direction of the SiC semiconductor wafer structure 61, and the crystal state of the SiC single crystal differs from that of the other regions. A plurality of modified lines 70 modified to have different properties are formed.

Two modified lines 70 along sides 52A and 52C of device forming region 51 each include a-plane modified portion 28 . Two modified lines 70 along the sides 52B and 52D of the device formation region 51 each include the m-plane modified portion 29 .

A plurality of modified lines 70 are formed one by one with respect to the four sides 52A to 52D of each device formation region 51 in a one-to-one correspondence relationship. The plurality of modified lines 70 are also laser processing traces formed in the middle of the SiC semiconductor wafer structure 61 in the thickness direction. More specifically, the a-plane modified portion 28 and the m-plane modified portion 29 included in the modified line 70 are traces of laser processing.

The condensing part (focus) of the laser beam, laser energy, pulse duty ratio, irradiation speed, etc. are arbitrary depending on the position, size, shape, thickness, etc. of the modified lines 70 (modified lines 22A to 22D) to be formed. is set to the value of

Next, referring to FIG. 10L, second main surface electrode layer 19 is formed on second main surface 63 of SiC semiconductor wafer structure 61 . The second principal surface electrode layer 19 may be formed by a vapor deposition method, a sputtering method, or a plating method.

Annealing may be performed on the second main surface 63 (ground surface) of the SiC semiconductor wafer structure 61 prior to the step of forming the second main surface electrode layer 19 . The annealing treatment may be performed by a laser annealing treatment method using laser light.

According to the laser annealing treatment method, the SiC single crystal of the surface layer portion of the second main surface 63 of the SiC semiconductor wafer structure 61 is modified to form an Si amorphous layer. In this case, the SiC semiconductor device 1 having the Si amorphous layer on the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 is manufactured. On the second main surface 4 of the SiC semiconductor layer 2, grinding marks and a Si amorphous layer coexist. According to the laser annealing treatment method, the ohmic property of the second main surface electrode layer 19 with respect to the second main surface 4 of the SiC semiconductor layer 2 can be enhanced.

Next, referring to FIG. 10M, a plurality of SiC semiconductor devices 1 are cut out from SiC semiconductor wafer structure 61 . In this step, a tape-shaped support member 73 is adhered to the second main surface 63 side of the SiC semiconductor wafer structure 61 .

Next, an external force is applied to the line to cut 53 from the second main surface 63 side of the SiC semiconductor wafer structure 61 through the support member 73 . The external force to the line to cut 53 may be applied by a pressing member such as a blade.

In another form, the support member 73 may be adhered to the first main surface 62 side of the SiC semiconductor wafer structure 61 . In this case, an external force may be applied to the line to cut 53 from the first main surface 62 side of the SiC semiconductor wafer structure 61 via the support member 73 . The external force may be applied by a pressing member such as a blade.

In still another form, a stretchable support member 73 may be attached to the first main surface 62 side or the second main surface 63 side of the SiC semiconductor wafer structure 61 . In this case, the SiC semiconductor wafer structure 61 may be cleaved by stretching the elastic support member 73 in the m-axis and a-axis directions.

When the SiC semiconductor wafer structure 61 is cleaved using the support member 73, the support member 73 is preferably attached to the second main surface 63 side of the SiC semiconductor wafer structure 61 where there are few obstacles.

In this way, the SiC semiconductor wafer structure 61 is cleaved along the planned cutting lines 53 starting from the modification lines 70 (the modification lines 22A to 22D), and a plurality of SiC semiconductor devices 1 are formed into one SiC semiconductor wafer structure. 61 (SiC semiconductor wafer 41).

A portion of the modified line 70 along the side 52A of each device forming region 51 becomes the modified line 22A. A portion of the modified line 70 along the side 52B of each device forming region 51 becomes the modified line 22B. A portion of the modified line 70 along the side 52C of each device formation region 51 becomes the modified line 22C. A portion of the modified line 70 along the side 52D of each device formation region 51 becomes a modified line 22D. The SiC semiconductor device 1 is manufactured through the steps including the above.

In this embodiment, the step of grinding SiC semiconductor wafer structure 61 (FIG. 10J) was performed prior to the step of forming modification lines 70 (modification lines 22A-22D) (FIG. 10K). However, the step of grinding the SiC semiconductor wafer structure 61 (FIG. 10J) is performed at an arbitrary timing after the step of preparing the SiC semiconductor wafer 41 (FIG. 10A) and before the step of forming the second main surface electrode layer 19 (FIG. 10L). can be implemented in

For example, the step of grinding SiC semiconductor wafer structure 61 (FIG. 10J) may be performed prior to the step of forming SiC epitaxial layer 7 (FIG. 10A). Also, the step of grinding the SiC semiconductor wafer structure 61 (FIG. 10J) may be performed after the step of forming the modification lines 70 (the modification lines 22A to 22D) (FIG. 10K).

Further, the step of grinding the SiC semiconductor wafer structure 61 (FIG. 10J) follows the step of preparing the SiC semiconductor wafer 41 (FIG. 10A), followed by the step of forming the modification lines 70 (modification lines 22A to 22D) (FIG. 10K). It may be performed in multiple times at any previous timing. Further, the grinding step of the SiC semiconductor wafer structure 61 (FIG. 10J) is performed at an arbitrary timing after the step of preparing the SiC semiconductor wafer 41 (FIG. 10A) and before the step of forming the second main surface electrode layer 19 (FIG. 10L). may be divided into multiple times.

FIG. 11 is a perspective view showing a semiconductor package 74 incorporating the SiC semiconductor device 1 shown in FIG. 3 through a sealing resin 79 .

Referring to FIG. 11, the semiconductor package 74 in this form is of the so-called TO-220 type. Semiconductor package 74 includes SiC semiconductor device 1 , pad portion 75 , heat sink 76 , multiple (two in this embodiment) terminals 77 , multiple (two in this embodiment) conducting wires 78 and sealing resin 79 . The pad portion 75, the heat sink 76, and the plurality of terminals 77 form a lead frame as an example of a connection object.

Pad portion 75 includes a metal plate. The pad portion 75 may contain iron, gold, silver, copper, aluminum, or the like. The pad portion 75 is formed in a square shape in plan view. Pad portion 75 has a planar area equal to or greater than the planar area of SiC semiconductor device 1 . SiC semiconductor device 1 is arranged on pad portion 75 .

The second main surface electrode layer 19 of the SiC semiconductor device 1 is electrically connected to the pad portion 75 via the conductive bonding material 80 . The conductive bonding material 80 is interposed in the region between the second principal surface electrode layer 19 and the pad section 75 .

The conductive bonding material 80 may be metallic paste or solder. The metallic paste may be a conductive paste containing Au (gold), Ag (silver) or Cu (copper). The conductive bonding material 80 is preferably made of solder. The solder may be a lead-free type solder. The solder may include at least one of SnAgCu, SnZnBi, SnCu, SnCuNi or SnSbNi.

The heat sink 76 is connected to one side of the pad portion 75 . In this form, the pad portion 75 and the heat sink 76 are formed from a single metal plate. A through hole 76 a is formed in the heat sink 76 . The through hole 76a is formed in a circular shape.

The plurality of terminals 77 are arranged along the side of the pad portion 75 opposite to the heat sink 76 . Each of the terminals 77 includes a metal plate. Terminals 77 may include iron, gold, silver, copper, aluminum, or the like.

The plurality of terminals 77 includes first terminals 77A and second terminals 77B. The first terminals 77A and the second terminals 77B are arranged at intervals along the side of the pad portion 75 opposite to the heat sink 76 . The first terminals 77A and the second terminals 77B extend in a strip shape along a direction orthogonal to their arrangement direction.

The plurality of conductors 78 may be bonding wires or the like. Plurality of conductors 78 includes conductor 78A and conductor 78B. Lead wire 78A is electrically connected to first terminal 77A and first main surface electrode layer 12 of SiC semiconductor device 1 . Thereby, the first terminal 77A is electrically connected to the first main surface electrode layer 12 of the SiC semiconductor device 1 via the conducting wire 78A.

Conducting wire 78B is electrically connected to second terminal 77B and pad portion 75 . Thereby, the second terminal 77B is electrically connected to the second main surface electrode layer 19 of the SiC semiconductor device 1 through the conducting wire 78B. The second terminal 77B may be formed integrally with the pad portion 75 .

A sealing resin 79 seals the SiC semiconductor device 1 , the pad section 75 and the plurality of conductors 78 so that the heat sink 76 and the plurality of terminals 77 are partly exposed. The sealing resin 79 is formed in a rectangular parallelepiped shape.

The form of semiconductor package 74 is not limited to TO-220. As the semiconductor package 74, SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package) or various forms similar thereto may be applied.

As described above, SiC semiconductor device 1 includes a plurality of modified lines 22A to 22D formed on side surfaces 5A to 5D of SiC semiconductor layer 2 one by one. According to the SiC semiconductor device 1, only one modification line 22A-22D is formed on each side surface 5A-5D of the SiC semiconductor layer 2. As shown in FIG. Thereby, the influence on the SiC semiconductor layer 2 caused by the modification lines 22A to 22D can be reduced.

Effects on the SiC semiconductor layer 2 caused by the modification lines include variations in the electrical characteristics of the SiC semiconductor layer 2 caused by the modification lines, cracks in the SiC semiconductor layer 2 originating from the modification lines, and the like. is exemplified.

Fluctuations in leakage current characteristics are exemplified as fluctuations in electrical characteristics of the SiC semiconductor layer 2 due to modified lines. A SiC semiconductor device may be sealed with a sealing resin 79 as shown in FIG.

In this case, it is conceivable that mobile ions in the sealing resin 79 enter the SiC semiconductor layer 2 through the modification line. A structure in which a plurality of modified lines are formed at intervals along the normal direction Z over the entire side surfaces 5A to 5D increases the risk of current path formation due to such an external structure.

In addition, in a structure in which a plurality of modified lines are formed along the normal direction Z over the entire side surfaces 5A to 5D of the SiC semiconductor layer 2, the risk of cracks occurring in the SiC semiconductor layer 2 increases. Therefore, like the SiC semiconductor device 1, by limiting the regions where the reforming lines 22A to 22D are formed, it is possible to suppress fluctuations in the electrical characteristics of the SiC semiconductor layer 2 and occurrence of cracks.

Further, according to the SiC semiconductor device 1, since the thinning process of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) is performed, the SiC semiconductor is processed by the one-layer modification line 70 (modification lines 22A to 22D). Wafer structure 61 can be properly cleaved.

In other words, according to the thinned SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41), the plurality of modified lines 70 (modified lines 22A to 22D) are not formed at intervals in the normal direction Z. In addition, the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) can be properly cleaved.

In this case, the second main surface 4 of the SiC semiconductor layer 2 is a ground surface. SiC semiconductor device 1 preferably includes SiC semiconductor layer 2 having a thickness TL of 40 μm or more and 200 μm or less. The SiC semiconductor layer 2 having such a thickness TL can be appropriately cut out from the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

In the SiC semiconductor layer 2, the thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. Thickness TE of SiC epitaxial layer 7 in SiC semiconductor layer 2 may be 1 μm or more and 50 μm or less. Thinning the SiC semiconductor layer 2 is also effective in reducing the resistance value.

Further, according to the SiC semiconductor device 1, the modification lines 22A to 22D are formed from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2 at intervals. Stress tends to concentrate at corners connecting first main surface 3 of SiC semiconductor layer 2 and side surfaces 5A to 5D.

Therefore, by forming the modification lines 22A to 22D at intervals from the corners connecting the first main surface 3 and the side surfaces 5A to 5D of the SiC semiconductor layer 2, cracks at the corners of the SiC semiconductor layer 2 are generated. can be appropriately suppressed.

In particular, according to the SiC semiconductor device 1, the modified lines 22A to 22D are formed in the SiC semiconductor substrate 6 while avoiding the SiC epitaxial layer . In other words, the modification lines 22A to 22D expose the SiC epitaxial layer 7 in which the main part of the semiconductor element (the Schottky barrier diode D in this form) is formed. As a result, the influence of the modification lines 22A to 22D on the semiconductor device can be appropriately reduced.

Further, according to the SiC semiconductor device 1, the modification lines 22A to 22D are formed from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2 at intervals. Stress tends to concentrate at the corners connecting the second main surface 4 of the SiC semiconductor layer 2 and the side surfaces 5A to 5D.

Therefore, by forming the modified lines 22A to 22D at intervals from the corners connecting the second main surface 4 and the side surfaces 5A to 5D of the SiC semiconductor layer 2, cracks are generated at the corners of the SiC semiconductor layer 2. can be appropriately suppressed.

Further, according to SiC semiconductor device 1 , main surface insulating layer 10 and first main surface electrode layer 12 formed on first main surface 3 of SiC semiconductor layer 2 are included. Main surface insulating layer 10 has insulating side surfaces 11A to 11D that are continuous with side surfaces 5A to 5D of SiC semiconductor layer 2 .

Principal surface insulating layer 10 enhances insulation between side surfaces 5A to 5D of SiC semiconductor layer 2 and first principal surface electrode layer 12 in a structure in which modification lines 22A to 22D are formed. Thereby, in the structure in which the modification lines 22A to 22D are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2, the stability of the electrical characteristics of the SiC semiconductor layer 2 can be enhanced.

FIG. 12A is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a second example of modification lines 22A to 22D. Hereinafter, structures corresponding to the structures described for the SiC semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The modified lines 22A to 22D according to the first embodiment are connected to each other at corners connecting the side surfaces 5A to 5D of the SiC semiconductor layer 2 . On the other hand, the modified lines 22A to 22D according to the second embodiment are formed at corners connecting the side surfaces 5A to 5D of the SiC semiconductor layer 2 with a space therebetween.

More specifically, modified line 22A and modified line 22B are formed spaced apart from each other in normal direction Z at a corner connecting side surface 5A and side surface 5B of SiC semiconductor layer 2 . Modification line 22B and modification line 22C are formed spaced apart from each other in normal direction Z at a corner connecting side surface 5B and side surface 5C of SiC semiconductor layer 2 .

Modified line 22C and modified line 22D are formed spaced apart from each other in normal direction Z at a corner connecting side 5C and side 5D of SiC semiconductor layer 2 . Modification line 22D and modification line 22A are formed spaced apart from each other in normal direction Z at a corner connecting side surface 5D and side surface 5A of SiC semiconductor layer 2 .

Of course, at least one of the modified lines 22A to 22D is formed at a corner connecting one of the side surfaces 5A to 5D of the SiC semiconductor layer 2 with a gap from the other modified lines 22A to 22D. good too. Two or three of modification lines 22A to 22D may be connected to each other at corners connecting any of side surfaces 5A to 5D of SiC semiconductor layer 2 .

The modified lines 22A to 22D according to the second embodiment are formed by adjusting the condensing part (focus) of the laser beam in the process of forming the modified lines 70 (modified lines 22A to 22D) ( See also FIG. 10K). Even when the modification lines 22A to 22D according to the second embodiment are formed, the same effects as when the modification lines 22A to 22D according to the first embodiment are formed can be obtained.

FIG. 12B is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a third example of modification lines 22A to 22D. Hereinafter, structures corresponding to the structures described for the SiC semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The modified lines 22A to 22D according to the first embodiment are formed in strips extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2 . On the other hand, the modified lines 22A to 22D according to the third embodiment are formed in a strip shape extending downwardly from the first main surface 3 toward the second main surface 4 of the SiC semiconductor layer 2. there is More specifically, the modified lines 22A to 22D according to the third embodiment each include a first end region 81, a second end region 82 and an inclined region 83, respectively.

The first end region 81 is located on the first main surface 3 side of the SiC semiconductor layer 2 in the vicinity of the corner of the SiC semiconductor layer 2 . The second end region 82 is located on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the first end region 81 in the vicinity of the corner of the SiC semiconductor layer 2 . The inclined region 83 slopes downward from the first principal surface 3 toward the second principal surface 4 in the region between the first end region 81 and the second end region 82 .

At a corner connecting side surface 5A and side surface 5B of SiC semiconductor layer 2, first end region 81 of modification line 22A and first end region 81 of modification line 22B may be located. A second end region 82 of the modification line 22A and a second end region 82 of the modification line 22B may be located at corners connecting the side surfaces 5A and 5B of the SiC semiconductor layer 2 .

A first end region 81 of the modification line 22A and a second end region 82 of the modification line 22B may be located at corners connecting the side surfaces 5A and 5B of the SiC semiconductor layer 2 . The second end region 82 of the modification line 22A and the first end region 81 of the modification line 22B may be positioned at corners connecting the side surfaces 5A and 5B of the SiC semiconductor layer 2 .

Modification line 22A and modification line 22B may be connected to each other at a corner connecting side surface 5A and side surface 5B of SiC semiconductor layer 2, or may be spaced apart from each other.

The first end region 81 of the modification line 22B and the first end region 81 of the modification line 22C may be located at corners connecting the side surfaces 5B and 5C of the SiC semiconductor layer 2 . A second end region 82 of the modification line 22B and a second end region 82 of the modification line 22C may be located at corners connecting the side surfaces 5B and 5C of the SiC semiconductor layer 2 .

A first end region 81 of the modification line 22B and a second end region 82 of the modification line 22C may be positioned at corners connecting the side surfaces 5B and 5C of the SiC semiconductor layer 2 . The second end region 82 of the modification line 22B and the first end region 81 of the modification line 22C may be positioned at corners connecting the side surfaces 5B and 5C of the SiC semiconductor layer 2 .

Modification line 22B and modification line 22C may be connected to each other at a corner connecting side surface 5B and side surface 5C of SiC semiconductor layer 2, or may be spaced apart from each other.

At corners connecting side surfaces 5C and 5D of SiC semiconductor layer 2, first end region 81 of modification line 22C and first end region 81 of modification line 22D may be located. A second end region 82 of the modification line 22C and a second end region 82 of the modification line 22D may be positioned at corners connecting the side surfaces 5C and 5D of the SiC semiconductor layer 2 .

A first end region 81 of the modification line 22C and a second end region 82 of the modification line 22D may be located at corners connecting the side surfaces 5C and 5D of the SiC semiconductor layer 2 . The second end region 82 of the modification line 22C and the first end region 81 of the modification line 22D may be positioned at corners connecting the side surfaces 5C and 5D of the SiC semiconductor layer 2 .

Modification line 22C and modification line 22D may be connected to each other at a corner connecting side surface 5C and side surface 5D of SiC semiconductor layer 2, or may be spaced apart from each other.

At corners connecting side surface 5D and side surface 5A of SiC semiconductor layer 2, first end region 81 of modification line 22D and first end region 81 of modification line 22A may be located. A second end region 82 of the modification line 22D and a second end region 82 of the modification line 22A may be located at the corner connecting the side surface 5D and the side surface 5A of the SiC semiconductor layer 2 .

A first end region 81 of the modification line 22D and a second end region 82 of the modification line 22A may be located at corners connecting the side surfaces 5D and 5A of the SiC semiconductor layer 2 . The second end region 82 of the modification line 22D and the first end region 81 of the modification line 22A may be positioned at corners connecting the side surfaces 5D and 5A of the SiC semiconductor layer 2 .

Modification line 22D and modification line 22A may be connected to each other at a corner connecting side surface 5D and side surface 5A of SiC semiconductor layer 2, or may be spaced apart from each other.

The modified lines 22A to 22D according to the third embodiment are formed by adjusting the condensing part (focus) of the laser beam in the process of forming the modified lines 70 (modified lines 22A to 22D) ( See also FIG. 10K). Even when the modification lines 22A to 22D according to the third embodiment are formed, the same effects as when the modification lines 22A to 22D according to the first embodiment are formed can be obtained.

In particular, according to the modified lines 22A to 22D according to the third embodiment, cleavage starting points can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). As a result, the SiC semiconductor wafer structure 61 can be properly cleaved even when the modification lines 22A to 22D are formed from a single layer.

FIG. 12C is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a fourth example of modification lines 22A to 22D. Hereinafter, structures corresponding to the structures described for the SiC semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The modified lines 22A to 22D according to the first embodiment are formed in strips extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2 . On the other hand, the modification lines 22A to 22D according to the fourth embodiment slope downward from the first main surface 3 toward the second main surface 4 of the SiC semiconductor layer 2 and extend in a curved shape (curved shape). It is shaped like a strip. More specifically, the modified lines 22A to 22D according to the fourth embodiment each include a first end region 84, a second end region 85 and a curved region 86, respectively.

The first end region 84 is located on the first main surface 3 side of the SiC semiconductor layer 2 in the vicinity of the corner of the SiC semiconductor layer 2 . The second end region 85 is positioned on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the first end region 84 in the vicinity of the corner of the SiC semiconductor layer 2 .

The curved region 86 slopes downward from the first principal surface 3 toward the second principal surface 4 in a concave curve and connects the first end region 84 and the second end region 85 . The curved region 86 may slope downward in a convex curve from the second major surface 4 toward the first major surface 3 .

A first end region 84 of the modification line 22A and a first end region 84 of the modification line 22B may be located at corners connecting the side surfaces 5A and 5B of the SiC semiconductor layer 2 . A second end region 85 of the modification line 22A and a second end region 85 of the modification line 22B may be located at corners connecting the side surfaces 5A and 5B of the SiC semiconductor layer 2 .

A first end region 84 of the modification line 22A and a second end region 85 of the modification line 22B may be positioned at corners connecting the side surfaces 5A and 5B of the SiC semiconductor layer 2 . The second end region 85 of the modification line 22A and the first end region 84 of the modification line 22B may be positioned at corners connecting the side surfaces 5A and 5B of the SiC semiconductor layer 2 .

Modification line 22A and modification line 22B may be connected to each other at a corner connecting side surface 5A and side surface 5B of SiC semiconductor layer 2, or may be spaced apart from each other.

A first end region 84 of the modification line 22B and a first end region 84 of the modification line 22C may be located at corners connecting the side surfaces 5B and 5C of the SiC semiconductor layer 2 . The second end region 85 of the modification line 22B and the second end region 85 of the modification line 22C may be located at the corner connecting the side surface 5B and the side surface 5C of the SiC semiconductor layer 2 .

A first end region 84 of the modification line 22B and a second end region 85 of the modification line 22C may be positioned at corners connecting the side surfaces 5B and 5C of the SiC semiconductor layer 2 . The second end region 85 of the modification line 22B and the first end region 84 of the modification line 22C may be located at corners connecting the side surfaces 5B and 5C of the SiC semiconductor layer 2 .

Modification line 22B and modification line 22C may be connected to each other at a corner connecting side surface 5B and side surface 5C of SiC semiconductor layer 2, or may be spaced apart from each other.

A first end region 84 of the modification line 22C and a first end region 84 of the modification line 22D may be located at corners connecting the side surfaces 5C and 5D of the SiC semiconductor layer 2 . A second end region 85 of the modification line 22C and a second end region 85 of the modification line 22D may be located at corners connecting the side surfaces 5C and 5D of the SiC semiconductor layer 2 .

A first end region 84 of the modification line 22C and a second end region 85 of the modification line 22D may be positioned at corners connecting the side surfaces 5C and 5D of the SiC semiconductor layer 2 . The second end region 85 of the modification line 22C and the first end region 84 of the modification line 22D may be positioned at corners connecting the side surfaces 5C and 5D of the SiC semiconductor layer 2 .

Modification line 22C and modification line 22D may be connected to each other at a corner connecting side surface 5C and side surface 5D of SiC semiconductor layer 2, or may be spaced apart from each other.

A first end region 84 of the modification line 22D and a first end region 84 of the modification line 22A may be located at corners connecting the side surfaces 5D and 5A of the SiC semiconductor layer 2 . The second end region 85 of the modification line 22D and the second end region 85 of the modification line 22A may be positioned at the corner connecting the side surface 5D and the side surface 5A of the SiC semiconductor layer 2 .

A first end region 84 of the modification line 22D and a second end region 85 of the modification line 22A may be positioned at corners connecting the side surfaces 5D and 5A of the SiC semiconductor layer 2 . The second end region 85 of the modification line 22D and the first end region 84 of the modification line 22A may be located at corners connecting the side surfaces 5D and 5A of the SiC semiconductor layer 2 .

Modification line 22D and modification line 22A may be connected to each other at a corner connecting side surface 5D and side surface 5A of SiC semiconductor layer 2, or may be spaced apart from each other.

The modified lines 22A to 22D according to the fourth embodiment are formed by adjusting the condensing part (focus) of the laser beam in the process of forming the modified lines 70 (modified lines 22A to 22D) ( See also FIG. 10K). Even when the modification lines 22A to 22D according to the fourth embodiment are formed, the same effects as when the modification lines 22A to 22D according to the first embodiment are formed can be obtained.

In particular, according to the modification lines 22A to 22D according to the fourth embodiment, cleavage starting points can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). As a result, the SiC semiconductor wafer structure 61 can be properly cleaved even when the modification lines 22A to 22D are formed from a single layer.

FIG. 12D is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a fifth example of modification lines 22A to 22D. Hereinafter, structures corresponding to the structures described for the SiC semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The modified lines 22A to 22D according to the first embodiment are formed in strips extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2 . On the other hand, the modified lines 22A to 22D according to the fifth embodiment are band-shaped extending in a meandering curved shape (curved shape) toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. formed. More specifically, the modification lines 22A to 22D according to the fifth embodiment each include a plurality of first regions 87, a plurality of second regions 88 and a plurality of connection regions 89, respectively.

The multiple first regions 87 are located in a region of the SiC semiconductor layer 2 on the first main surface 3 side. The plurality of second regions 88 are located in a region on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the plurality of first regions 87 . A plurality of curved regions 86 connect corresponding first regions 87 and second regions 88, respectively.

Modification line 22A and modification line 22B may be connected to each other at a corner connecting side surface 5A and side surface 5B of SiC semiconductor layer 2, or may be spaced apart from each other.

Modification line 22B and modification line 22C may be connected to each other at a corner connecting side surface 5B and side surface 5C of SiC semiconductor layer 2, or may be spaced apart from each other.

Modification line 22C and modification line 22D may be connected to each other at a corner connecting side surface 5C and side surface 5D of SiC semiconductor layer 2, or may be spaced apart from each other.

Modification line 22D and modification line 22A may be connected to each other at a corner connecting side surface 5D and side surface 5A of SiC semiconductor layer 2, or may be spaced apart from each other.

The meandering period of the reforming lines 22A-22D is arbitrary. Each of the reforming lines 22A to 22D may be formed in a belt-like shape extending concavely from the first principal surface 3 toward the second principal surface 4 . In this case, the modification lines 22A-22D may include two first regions 87, one second region 88 and two connection regions 89, respectively.

Further, each of the reforming lines 22A to 22D may be formed in a belt-like shape extending in a convex curve from the second main surface 4 toward the first main surface 3. As shown in FIG. In this case, the modification lines 22A-22D may include one first region 87, two second regions 88 and two connection regions 89, respectively.

The modified lines 22A to 22D according to the fifth embodiment are formed by adjusting the condensing part (focus) of the laser beam in the process of forming the modified lines 70 (modified lines 22A to 22D) ( See also FIG. 10K). Even when the modification lines 22A to 22D according to the fifth embodiment are formed, the same effects as when the modification lines 22A to 22D according to the first embodiment are formed can be obtained.

In particular, according to the modification lines 22A to 22D according to the fifth embodiment, cleavage starting points can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). As a result, the SiC semiconductor wafer structure 61 can be properly cleaved even when the modification lines 22A to 22D are formed from a single layer.

FIG. 12E is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a sixth example of modification lines 22A to 22D. Hereinafter, structures corresponding to the structures described for the SiC semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The modified lines 22A to 22D according to the first embodiment are formed in the same shape as the side surfaces 5A to 5D of the SiC semiconductor layer 2. As shown in FIG. On the other hand, the modified lines 22A to 22D according to the sixth embodiment are formed in the side surfaces 5A to 5D of the SiC semiconductor layer 2 with different occupation ratios RA, RB, RC and RD. The occupation ratios RA to RD are the ratios of the reforming lines 22A to 22D occupying the side surfaces 5A to 5D.

More specifically, the exclusive proportions RA to RD differ depending on the crystal plane of the SiC single crystal. The occupied ratios RB, RD of the modified lines 22B, 22D formed on the m-plane of the SiC single crystal are less than the occupied ratios RA, RC of the modified lines 22A, 22C formed on the a-plane of the SiC single crystal (RB, RD≦RA, RC). More specifically, the occupancy ratios RB, RD are less than the occupancy ratios RA, RC (RB, RD<RA, RC).

The occupation ratios RA and RC of the reforming lines 22A and 22C may be equal to each other or may be different from each other. Moreover, the occupation ratios RB and RD of the reforming lines 22B and 22D may be equal to each other or may be different from each other.

The surface area of reformation lines 22B, 22D for sides 5B, 5D is in this configuration less than the surface area of reformation lines 22A, 22C for sides 5A, 5C, respectively. The thickness TR of modified lines 22B, 22D is less than the thickness TR of modified lines 22A, 22C, respectively, in this embodiment.

The modified lines 22A to 22D according to the sixth embodiment are formed by adjusting the condensing part (focus) of the laser beam in the process of forming the modified line 70 (see also FIG. 10K). Even when the modification lines 22A to 22D according to the sixth embodiment are formed, the same effects as when the modification lines 22A to 22D according to the first embodiment are formed can be obtained.

In particular, the modified lines 22A to 22D according to the sixth embodiment are formed in the side surfaces 5A to 5D of the SiC semiconductor layer 2 with different occupation ratios RA to RD, respectively. More specifically, the reforming lines 22A-22D have different occupation ratios RA-RD depending on the crystal plane of the SiC single crystal.

The occupied ratios RB, RD of the modified lines 22B, 22D formed on the m-plane of the SiC single crystal are less than the occupied ratios RA, RC of the modified lines 22A, 22C formed on the a-plane of the SiC single crystal (RB, RD≦RA, RC).

A SiC single crystal is likely to crack along the direction of the closest atoms (see also FIGS. 1 and 2) in a plan view of the c-plane (silicon plane) along the c-axis, and along the direction intersecting the directions of the nearest atoms. It has a physical property that it is hard to crack. The closest atom direction is the a-axis direction and its equivalent direction. The cross direction of the nearest neighbor direction is the m-axis direction and its equivalent direction.

Therefore, in the step of forming the modified line 70, since the crystal plane along the direction of the closest atom of the SiC single crystal has the property of being relatively fragile, the modified line having a relatively large exclusive ratio The SiC single crystal can be appropriately cut (cleaved) without forming 70 (see also FIG. 10L). The crystal planes along the nearest-neighbor atom direction are the m-planes and their equivalent planes.

That is, in the step of forming the reformed lines 70, the occupancy ratio of the reformed lines 70 along the second planned cutting lines 55 extending in the a-axis direction is set to can be less than the exclusive share of

On the other hand, a reformed line 70 having a relatively large occupied ratio is formed on the crystal plane along the intersecting direction of the nearest-neighbor atom directions of the SiC single crystal. As a result, inappropriate cutting (cleavage) of the SiC semiconductor wafer structure 61 can be suppressed, so cracks caused by the physical properties of the SiC single crystal can be appropriately suppressed. The crystal planes along the direction intersecting the directions of nearest neighbors are the a-planes and their equivalent planes.

As described above, according to the modification lines 22A to 22D according to the sixth embodiment, the physical properties of the SiC single crystal are used to adjust the occupation ratios RA to RD of the modification lines 22A to 22D with respect to the side surfaces 5A to 5D, can be reduced. Thereby, the influence on the SiC semiconductor layer 2 caused by the modification lines 22A to 22D can be further reduced. Moreover, the time required for forming the reforming line 70 can be shortened.

Occupancy ratios RA-RD may be adjusted by the surface area of reforming lines 22A-22D relative to sides 5A-5D. The occupation ratios RA-RD may be adjusted by the thickness TR of the reformed lines 22A-22D. The occupation ratios RA-RD may be adjusted by the number of reforming lines 22A-22D.

Reforming lines according to the first embodiment, second embodiment, third embodiment, fourth embodiment, fifth embodiment and sixth embodiment (hereinafter simply referred to as "first to sixth embodiment") SiC semiconductor device 1 including at least two of 22A to 22D at the same time may be formed.

Also, the features of the reforming lines 22A-22D according to the first to sixth embodiment examples can be combined in any manner and in any form among them. That is, the reforming lines 22A to 22D having a form in which at least two of the features of the reforming lines 22A to 22D according to the first to sixth embodiments are combined may be employed.

For example, the features of the reforming lines 22A-22D according to the third embodiment may be combined with the features of the reforming lines 22A-22D according to the fifth embodiment. In this case, the curved shape ( Belt-shaped reforming lines 22A to 22D extending in a curved shape are formed.

FIG. 13 is a perspective view showing a SiC semiconductor device 91 according to the second embodiment of the present invention, and is a perspective view showing a structure to which modification lines 22A to 22D according to the first embodiment are applied. Hereinafter, structures corresponding to the structures described for the SiC semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

In this embodiment, the reforming lines 22A to 22D according to the first embodiment are applied. However, instead of or in addition to the reforming lines 22A to 22D according to the first embodiment, the reforming according to the second, third, fourth, fifth or sixth example of the embodiment Lines 22A-22D may be employed. Moreover, the reforming lines 22A to 22D having a form in which at least two of the features of the reforming lines 22A to 22D according to the first to sixth embodiments are combined may be employed.

Referring to FIG. 13, in this embodiment, insulating side surfaces 11A to 11D of main surface insulating layer 10 are formed at intervals inward from side surfaces 5A to 5D of SiC semiconductor layer 2 in plan view. Principal surface insulating layer 10 exposes the peripheral portion of first principal surface 3 of SiC semiconductor layer 2 in plan view.

Main surface insulating layer 10 exposes the peripheral portion of first main surface 3 of SiC semiconductor layer 2 together with resin layer 16 and passivation layer 13 . Insulating side surfaces 11A to 11D of main surface insulating layer 10 are formed flush with resin side surfaces 17A to 17D of resin layer 16 and side surfaces 14A to 14D of passivation layer 13 in this embodiment. In this embodiment, the insulating side surfaces 11A to 11D of the main surface insulating layer 10 are also the portions defining the dicing streets.

This main surface insulating layer 10 is formed by carrying out a step of removing the main surface insulating layer 10 by an etching method after the step of removing the passivation layer 13 in the step of FIG. 10I described above.

In this case, in the step of FIG. 10K described above, the inside of the SiC semiconductor wafer structure 61 may be directly irradiated with laser light from the first main surface 62 side of the SiC semiconductor wafer structure 61 without passing through the main surface insulating layer 10 . .

As described above, the SiC semiconductor device 91 can also achieve the same effects as those described for the SiC semiconductor device 1 . However, the structure of the SiC semiconductor device 1 according to the first embodiment is preferable in order to improve the insulation between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12. FIG.

FIG. 14 is a perspective view of the SiC semiconductor device 101 according to the third embodiment of the present invention viewed from one angle, showing a structure to which the modification lines 22A to 22D according to the first embodiment are applied. It is a diagram. FIG. 15 is a perspective view of the SiC semiconductor device 101 shown in FIG. 14 viewed from another angle. FIG. 16 is a plan view showing SiC semiconductor device 101 shown in FIG. FIG. 17 is a plan view of FIG. 16 with the resin layer 129 removed.

In this embodiment, the reforming lines 22A to 22D according to the first embodiment are applied. In other words, in the manufacturing process of the SiC semiconductor device 101, the same processes as those shown in FIGS. 10A to 10M are applied.

In the SiC semiconductor device 101, instead of or in addition to the modification lines 22A to 22D according to the first embodiment, a second embodiment, a third embodiment, a fourth embodiment, a fifth embodiment, or a sixth embodiment may be adopted. Moreover, the reforming lines 22A to 22D having a form in which at least two of the features of the reforming lines 22A to 22D according to the first to sixth embodiments are combined may be employed.

Referring to FIGS. 14 to 17, SiC semiconductor device 101 includes SiC semiconductor layer 102. SiC semiconductor layer 102 includes SiC semiconductor layer 102; The SiC semiconductor layer 102 includes a 4H—SiC single crystal as an example of a hexagonal SiC single crystal. The SiC semiconductor layer 102 (SiC semiconductor chip) is formed in a rectangular parallelepiped chip shape.

SiC semiconductor layer 102 has first main surface 103 on one side, second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting first main surface 103 and second main surface 104. is doing. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular shape in this embodiment) in plan view (hereinafter simply referred to as "plan view") when viewed from the normal direction Z. .

The first main surface 103 is an element formation surface on which semiconductor elements are formed. The second main surface 104 of the SiC semiconductor layer 102 is a ground surface having grinding marks. The side surfaces 105A to 105D each consist of a smooth cleavage plane facing the crystal plane of the SiC single crystal. The side surfaces 105A-105D do not have grinding marks.

The thickness TL of the SiC semiconductor layer 102 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm to 60 μm, 60 μm to 80 μm, 80 μm to 100 μm, 100 μm to 120 μm, 120 μm to 140 μm, 140 μm to 160 μm, 160 μm to 180 μm, or 180 μm to 200 μm. The thickness TL is preferably 60 μm or more and 150 μm or less.

The first main surface 103 and the second main surface 104 face the c-plane of the SiC single crystal in this embodiment. The first major surface 103 faces the (0001) plane (silicon plane). The second main surface 104 faces the (000-1) plane (carbon plane) of the SiC single crystal.

The first main surface 103 and the second main surface 104 have an off angle θ of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by an off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

The off angle θ may be 0° or more and 5.0° or less. The off angle θ is 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, or 2.5°. ° to 3.0°, 3.0° to 3.5°, 3.5° to 4.0°, 4.0° to 4.5° or 4.5° to 5.0° It may be set within the following angle range. The off angle θ is preferably greater than 0°. The off angle θ may be less than 4.0°.

The off angle θ may be set within an angle range of 3.0° or more and 4.5° or less. In this case, the off angle θ is preferably set in the range of 3.0° or more and 3.5° or less or 3.5° or more and 4.0° or less.

The off angle θ may be set within an angle range of 1.5° or more and 3.0° or less. In this case, the off angle θ is preferably set within an angle range of 1.5° or more and 2.0° or less or 2.0° or more and 2.5° or less.

Each of the side surfaces 105A-105D may have a length of 1 mm or more and 10 mm or less (eg, 2 mm or more and 5 mm or less). The surface area of sides 105B, 105D exceeds the surface area of sides 105A, 105C in this configuration. The first main surface 103 and the second main surface 104 may be formed in a square shape in plan view. In this case, the surface areas of side surfaces 105B and 105D are equal to side surfaces 105B and 105D.

105 A of side surfaces and 105 C of side surfaces are extended along the 1st direction X, and are mutually opposed to the 2nd direction Y which cross|intersects the 1st direction X in this form. Side 105B and side 105D extend along the second direction Y and face each other in the first direction X in this embodiment. The second direction Y is a direction perpendicular to the first direction X, more specifically.

The first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal in this embodiment. The second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

Side 105A and side 105C form short sides of SiC semiconductor layer 102 in plan view. Side 105A and side 105C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. The side surface 105A is formed by the (-1-120) plane of the SiC single crystal. The side surface 105C is formed by the (11-20) plane of the SiC single crystal.

Side 105B and side 105D form long sides of SiC semiconductor layer 102 in a plan view. Side 105B and side 105D are formed by the m-plane of SiC single crystal and face each other in the m-axis direction. The side surface 105B is formed by the (-1100) plane of the SiC single crystal. The side surface 105D is formed by the (1-100) plane of SiC single crystal.

The side surface 105A and the side surface 105C are inclined toward the c-axis direction ([0001] direction) of the SiC single crystal with respect to the normal line of the first main surface 103 of the SiC semiconductor layer 102. It may form a surface.

In this case, side surface 105A and side surface 105C are at an off angle θ with respect to the normal to first main surface 103 of SiC semiconductor layer 102 when the normal to first main surface 103 of SiC semiconductor layer 102 is 0°. You may incline at the corresponding angle. The angle corresponding to the off angle θ may be equal to the off angle θ, or may be an angle exceeding 0° and less than the off angle θ.

In this embodiment, SiC semiconductor layer 102 has a laminated structure including n ⁺ -type SiC semiconductor substrate 106 (second impurity region) and n-type SiC epitaxial layer 107 (first impurity region). SiC semiconductor substrate 106 and SiC epitaxial layer 107 correspond to SiC semiconductor substrate 6 and SiC epitaxial layer 7 according to the first embodiment, respectively. The SiC semiconductor substrate 106 forms the second main surface 104 of the SiC semiconductor layer 102 .

SiC epitaxial layer 107 forms first main surface 103 of SiC semiconductor layer 102 . SiC semiconductor substrate 106 and SiC epitaxial layer 107 form side surfaces 105A to 105D of SiC semiconductor layer 102 .

The thickness TS of the SiC semiconductor substrate 106 may be 40 μm or more and 150 μm or less. The thickness TS is 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, It may be 130 μm or more and 140 μm or less or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 106, it is possible to reduce the resistance value by shortening the current path.

The thickness TE of the SiC epitaxial layer 107 may be 1 μm or more and 50 μm or less. The thickness TE is 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or It may be 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

The n-type impurity concentration of SiC epitaxial layer 107 is equal to or lower than the n-type impurity concentration of SiC semiconductor substrate 106 . The n-type impurity concentration of SiC epitaxial layer 107 is more specifically less than the n-type impurity concentration of SiC semiconductor substrate 106 . The SiC semiconductor substrate 106 may have an n-type impurity concentration of 1.0×10 ¹⁸ cm ⁻³ or more and 1.0×10 ²¹ cm ⁻³ or less. SiC epitaxial layer 107 may have an n-type impurity concentration of 1.0×10 ¹⁵ cm ⁻³ or more and 1.0×10 ¹⁸ cm ⁻³ or less.

The SiC epitaxial layer 107 has a plurality of regions with different n-type impurity concentrations along the normal direction Z in this embodiment. More specifically, SiC epitaxial layer 107 includes high-concentration region 108 having a relatively high n-type impurity concentration and low-concentration region 109 having a lower n-type impurity concentration than high-concentration region 108 .

High-concentration region 108 is formed in a region of SiC semiconductor layer 102 on the first main surface 103 side. The low-concentration region 109 is formed in a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the high-concentration region 108 .

The n-type impurity concentration of the high-concentration region 108 may be 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. The n-type impurity concentration of the low concentration region 109 may be 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁶ cm ⁻³ or less.

The thickness of the high-concentration region 108 is less than or equal to the thickness of the low-concentration region 109 . The thickness of the high concentration region 108 is more specifically less than the thickness of the low concentration region 109 . The thickness of heavily doped region 108 is less than half the total thickness of SiC epitaxial layer 107 .

An active region 111 and an outer region 112 are set in the SiC semiconductor layer 102 . The active region 111 is a region in which a vertical MISFET (Metal Insulator Field Effect Transistor) as an example of a semiconductor element is formed. Outer region 112 is the region outside active region 111 .

The active region 111 is set in the central portion of the SiC semiconductor layer 102 with a gap in the inner region from the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view. The active region 111 is set in a square shape (rectangular shape in this form) having four sides parallel to the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view.

Outer region 112 is set in a region between side surfaces 105A to 105D of SiC semiconductor layer 102 and the periphery of active region 111 . The outer region 112 is set in an endless shape (in this form, a square ring shape) surrounding the active region 111 in plan view.

A main surface insulating layer 113 is formed on the first main surface 103 of the SiC semiconductor layer 102 . A main surface insulating layer 113 selectively covers the active area 111 and the outer area 112 . The main surface insulating layer 113 may contain silicon oxide (SiO ₂ ).

Main surface insulating layer 113 has insulating side surfaces 114A, 114B, 114C, and 114D exposed from side surfaces 105A to 105D of SiC semiconductor layer 102 . The insulating side surfaces 114A-114D are continuous with the side surfaces 105A-105D. The insulating side surfaces 114A-114D are formed flush with the side surfaces 105A-105D, respectively. The insulating side surfaces 114A to 114D consist of cleaved surfaces.

The thickness of main surface insulating layer 113 may be 1 μm or more and 50 μm or less. The thickness of the principal surface insulating layer 113 may be 1 μm to 10 μm, 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm.

A main-surface gate electrode layer 115 as one of the first main-surface electrode layers is formed on the main-surface insulating layer 113 . Main-surface gate electrode layer 115 penetrates main-surface insulating layer 113 and is electrically connected to an arbitrary region of SiC semiconductor layer 102 .

Main surface gate electrode layer 115 includes gate pad 116 and gate fingers 117 and 118 . Gate pad 116 and gate fingers 117 and 118 are located in active area 111 .

Gate pad 116 is formed along side surface 105A of SiC semiconductor layer 102 in plan view. Gate pad 116 is formed along the central region of side surface 105A of SiC semiconductor layer 102 in plan view.

Gate pad 116 may be formed along a corner connecting any two of side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view. Gate pad 116 may be formed in a square shape in plan view.

Gate fingers 117 , 118 include outer gate finger 117 and inner gate finger 118 . Outer gate fingers 117 are led out from gate pad 116 and extend in strips along the periphery of active area 111 .

In this embodiment, the outer gate fingers 117 are formed along the three sides 105A, 105B, 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions.

The outer gate finger 117 has a pair of open ends 119,120. A pair of open ends 119 and 120 are formed in a region facing the gate pad 116 with the inner region of the active region 111 interposed therebetween. A pair of open ends 119 and 120 are formed along side surface 105C of SiC semiconductor layer 102 in this embodiment.

Inner gate fingers 118 are brought out from gate pad 116 to an inner region of active area 111 . The inner gate fingers 118 extend in strips in the inner region of the active area 111 . Inner gate fingers 118 extend from gate pad 116 toward side 105C.

A main-surface source electrode layer 121 as one of the first main-surface electrode layers is further formed on the main-surface insulating layer 113 . Main surface source electrode layer 121 penetrates main surface insulating layer 113 and is electrically connected to an arbitrary region of SiC semiconductor layer 102 . Main-surface source electrode layer 121 includes source pad 122 , source lead-out wiring 123 and source connection portion 124 in this embodiment.

Source pad 122 is formed in active area 111 spaced from gate pad 116 and gate fingers 117 and 118 . Source pad 122 is C-shaped in plan view (FIG. 16) so as to cover a C-shaped (inverted C-shaped in FIGS. 16 and 17) region defined by gate pad 116 and gate fingers 117 and 118. and an inverted C shape in FIG. 17).

The source lead-out wiring 123 is formed in the outer region 112 . The source lead-out line 123 extends along the active region 111 in a strip shape. In this form, the source lead-out line 123 is formed in an endless shape (in this form, a square ring shape) surrounding the active region 111 in plan view. Source lead-out wiring 123 is electrically connected to SiC semiconductor layer 102 in outer region 112 .

The source connection portion 124 connects the source pad 122 and the source lead-out line 123 . A source connection 124 is provided in the region between the pair of open ends 119 and 120 of the outer gate finger 117 . The source connection portion 124 crosses the boundary region between the active region 111 and the outer region 112 from the source pad 122 and is connected to the source lead-out wiring 123 .

The MISFET formed in the active region 111 includes an npn-type parasitic bipolar transistor due to its structure. When the avalanche current generated in outer region 112 flows into active region 111, the parasitic bipolar transistor is turned on. In this case, the control of the MISFET may become unstable due to latch-up, for example.

Therefore, in SiC semiconductor device 101 , the structure of main surface source electrode layer 121 is used to form an avalanche current absorption structure that absorbs the avalanche current generated in outer region 112 .

More specifically, the avalanche current generated in the outer region 112 is absorbed by the source lead-out line 123 and reaches the source pad 122 via the source connecting portion 124 . If a conductor for external connection (eg, bonding wire) is connected to source pad 122, the avalanche current is taken out by this conductor.

As a result, it is possible to prevent the parasitic bipolar transistor from turning on due to an unwanted current generated in the outer region 112 . Therefore, since latch-up can be suppressed, the stability of MISFET control can be improved.

A gate voltage is applied to main surface gate electrode layer 115 . The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the main surface source electrode layer 121 . The source voltage may be a reference voltage (eg, GND voltage).

A passivation layer 125 (insulating layer) is formed on the main surface insulating layer 113 . Passivation layer 125 may have a single layer structure consisting of a silicon oxide layer or a silicon nitride layer.

Passivation layer 125 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed over the silicon nitride layer. The silicon nitride layer may be formed over the silicon oxide layer. The passivation layer 125 has a single layer structure consisting of a silicon nitride layer in this form.

Side surfaces 126A, 126B, 126C, and 126D of passivation layer 125 are spaced inward from side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view. The passivation layer 125 exposes the periphery of the SiC semiconductor layer 102 in plan view. Passivation layer 125 exposes main surface insulating layer 113 .

Passivation layer 125 selectively covers main-surface gate electrode layer 115 and main-surface source electrode layer 121 . A gate subpad opening 127 and a source subpad opening 128 are formed in the passivation layer 125 . Gate subpad opening 127 exposes gate pad 116 . Source subpad opening 128 exposes source pad 122 .

The passivation layer 125 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the passivation layer 125 may be 1 μm to 10 μm, 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm.

A resin layer 129 (insulating layer) is formed on the passivation layer 125 . The passivation layer 125 and the resin layer 129 form one insulating laminated structure (insulating layer). In FIG. 16, the resin layer 129 is indicated by hatching.

The resin layer 129 may contain a negative type or positive type photosensitive resin. In this embodiment, the resin layer 129 contains polybenzoxazole as an example of a positive photosensitive resin. The resin layer 129 may contain polyimide as an example of a negative type photosensitive resin.

Resin layer 129 selectively covers main-surface gate electrode layer 115 and main-surface source electrode layer 121 . Resin side surfaces 130A, 130B, 130C, and 130D of resin layer 129 are spaced inwardly from side surfaces 105A to 105D of SiC semiconductor layer 102 . The resin layer 129 exposes the main insulating layer 113 together with the passivation layer 125 . The resin side surfaces 130A to 130D of the resin layer 129 are formed flush with the side surfaces 126A to 126D of the passivation layer 125 in this embodiment.

Resin side surfaces 130A to 130D of resin layer 129 are portions that define dicing streets when SiC semiconductor devices 101 are cut out from one SiC semiconductor wafer. In this form, the side surfaces 126A to 126D of the passivation layer 125 are also part of the dicing streets.

Exposing the peripheral portion of SiC semiconductor layer 102 from resin layer 129 and passivation layer 125 eliminates the need to physically cut resin layer 129 and passivation layer 125 . Thereby, the SiC semiconductor device 101 can be smoothly cut out from one SiC semiconductor wafer. Also, the insulating distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 can be increased.

The distance between side surfaces 105A-105D and resin side surfaces 130A-130D (side surfaces 126A-126D) may be 1 μm or more and 25 μm or less. Even if the distance between the side surfaces 105A to 105D and the resin side surfaces 130A to 130D (side surfaces 126A to 126D) is 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. good. Of course, side surfaces 126A to 126D of passivation layer 125 may be formed flush with side surfaces 105A to 105D of SiC semiconductor layer 102 .

A gate pad opening 131 and a source pad opening 132 are formed in the resin layer 129 . Gate pad opening 131 exposes gate pad 116 . Source pad opening 132 exposes source pad 122 .

Gate pad opening 131 in resin layer 129 communicates with gate sub-pad opening 127 in passivation layer 125 . The inner wall of gate pad opening 131 may be located outside the inner wall of gate sub-pad opening 127 . The inner wall of gate pad opening 131 may be located inside the inner wall of gate sub-pad opening 127 . Resin layer 129 may cover the inner wall of gate sub-pad opening 127 .

Source pad opening 132 in resin layer 129 communicates with source sub-pad opening 128 in passivation layer 125 . The inner walls of gate pad opening 131 may be located outside the inner walls of source sub-pad opening 128 . The inner walls of source pad opening 132 may be located inside the inner walls of source subpad opening 128 . Resin layer 129 may cover the inner wall of source subpad opening 128 .

The thickness of the resin layer 129 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 129 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

A drain electrode layer 133 as a second main surface electrode layer is connected to the second main surface 104 of the SiC semiconductor layer 102 . The maximum voltage that can be applied between the main surface source electrode layer 121 and the drain electrode layer 133 when turned off may be 1000 V or more and 10000 V or less.

The drain electrode layer 133 may include at least one of a Ti layer, Ni layer, Au layer, Ag layer, and Al layer. The drain electrode layer 133 may have a single layer structure including a Ti layer, Ni layer, Au layer, Ag layer, or Al layer.

The drain electrode layer 133 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in an arbitrary manner. Drain electrode layer 133 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer and an Ag layer stacked in this order from second main surface 104 of SiC semiconductor layer 102 .

The SiC semiconductor substrate 106 is formed as a drain region 134 (second impurity region) of the MISFET. The SiC epitaxial layer 107 is formed as a drift region 135 (first impurity region) of the MISFET.

A plurality of modified lines 22A to 22D according to the first embodiment are formed on side surfaces 105A to 105D of the SiC semiconductor layer 102 . The structure of the modified lines 22A to 22D according to the third embodiment is similar to that of the modified lines 22A to 22D according to the first embodiment, except that the modified lines 22A to 22D are formed in the SiC semiconductor layer 102 instead of the SiC semiconductor layer 2. Similar to structure.

The description of the reforming lines 22A to 22D according to the first embodiment is applied mutatis mutandis to the description of the reforming lines 22A to 22D according to the third embodiment. 22D will be omitted.

FIG. 18 is an enlarged view of region XVIII shown in FIG. 17 and is a view for explaining the structure of first main surface 103 of SiC semiconductor layer 102 . 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 18. FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 18. FIG. FIG. 21 is an enlarged view of area XXI shown in FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 17. FIG. FIG. 23 is an enlarged view of region XXIII shown in FIG.

18 to 22, a p-type body region 141 is formed in the surface layer portion of first main surface 103 of SiC semiconductor layer 102 in active region 111. Referring to FIGS. Body region 141 defines active region 111 .

In this embodiment, body region 141 is formed over the entire region forming active region 111 on first main surface 103 of SiC semiconductor layer 102 . The p-type impurity concentration of body region 141 may be 1.0×10 ¹⁷ cm ⁻³ or more and 1.0×10 ¹⁹ cm ⁻³ or less.

A plurality of gate trenches 142 are formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 in the active region 111 . The plurality of gate trenches 142 are each formed in a strip shape extending along the first direction X (the m-axis direction of the SiC single crystal) in plan view, and are spaced apart along the second direction Y (the a-axis direction of the SiC single crystal). is formed with a space between

In this embodiment, each gate trench 142 extends from the peripheral portion on one side (side surface 105B side) of the active region 111 toward the peripheral portion on the other side (side surface 105D side). The plurality of gate trenches 142 are formed in a stripe shape as a whole in plan view.

Each gate trench 142 traverses an intermediate portion between one peripheral edge and the other peripheral edge in the active area 111 . One end of each gate trench 142 is located on one side of the active region 111 . The other end of each gate trench 142 is located on the other peripheral edge of the active region 111 .

Each gate trench 142 may have a length of 0.5 mm or more. The length of each gate trench 142 is the length from the end of each gate trench 142 and the outer gate finger 117 on the side of the connecting portion to the opposite end in the cross section shown in FIG.

The length of each gate trench 142 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less) in this embodiment. A total extension of one or more gate trenches 142 per unit area may be 0.5 μm/μm ² or more and 0.75 μm/μm ² or less.

Each gate trench 142 integrally includes an active trench portion 143 and a contact trench portion 144 . The active trench portion 143 is a portion along the MISFET channel in the active region 111 .

The contact trench portion 144 is a portion mainly intended for contact with the outer gate finger 117 in the gate trench 142 . The contact trench portion 144 extends from the active trench portion 143 to the peripheral portion of the active region 111 . A contact trench portion 144 is formed in the region immediately below the outer gate finger 117 . The extension amount of the contact trench portion 144 is arbitrary.

Each gate trench 142 penetrates body region 141 and reaches SiC epitaxial layer 107 . Each gate trench 142 includes sidewalls and a bottom wall. The sidewalls forming the long sides of each gate trench 142 are formed by the a-plane of SiC single crystal. A side wall forming a short side of each gate trench 142 is formed by an m-plane of SiC single crystal.

A sidewall of each gate trench 142 may extend along the normal direction Z. FIG. A sidewall of each gate trench 142 may be formed substantially perpendicular to first main surface 103 of SiC semiconductor layer 102 .

In SiC semiconductor layer 102, the sidewall of each gate trench 142 forms an angle with respect to first main surface 103 of SiC semiconductor layer 102, which may be 90° or more and 95° or less (for example, 91° or more and 93° or less). . Each gate trench 142 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

The bottom wall of each gate trench 142 is located in SiC epitaxial layer 107 . More specifically, the bottom wall of each gate trench 142 is located in high concentration region 108 of SiC epitaxial layer 107 .

The bottom wall of each gate trench 142 faces the c-plane of the SiC single crystal. The bottom wall of each gate trench 142 has an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

A bottom wall of each gate trench 142 may be formed parallel to first main surface 103 of SiC semiconductor layer 102 . Of course, the bottom wall of each gate trench 142 may be formed in a convex curve toward the second main surface 104 of the SiC semiconductor layer 102 .

With respect to the normal direction Z, each gate trench 142 may have a depth of 0.5 μm or more and 3.0 μm or less. The depth of each gate trench 142 is 0.5 μm to 1.0 μm, 1.0 μm to 1.5 μm, 1.5 μm to 2.0 μm, 2.0 μm to 2.5 μm, or 2.5 μm to 2.5 μm. 0 μm or less.

The width of each gate trench 142 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of each gate trench 142 may be 0.1 μm to 0.5 μm, 0.5 μm to 1.0 μm, 1.0 μm to 1.5 μm, or 1.5 μm to 2 μm.

Referring to FIG. 21 , opening edge portion 146 of each gate trench 142 includes an inclined portion 147 inclined downward from first main surface 103 of SiC semiconductor layer 102 toward the inside of each gate trench 142 . Opening edge portion 146 of each gate trench 142 is a corner connecting first main surface 103 of SiC semiconductor layer 102 and the side wall of each gate trench 142 .

In this embodiment, the sloped portion 147 is formed in a concave curved shape directed inward of the SiC semiconductor layer 102 . The inclined portion 147 may be formed in a convex curved shape directed inward of each gate trench 142 . The sloped portion 147 reduces electric field concentration on the opening edge portion 146 of each gate trench 142 .

A gate insulating layer 148 and a gate electrode layer 149 are formed in each gate trench 142 . In FIG. 18, the gate insulating layer 148 and the gate electrode layer 149 are indicated by hatching.

Gate insulating layer 148 contains at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). include.

Gate insulating layer 148 may have a laminated structure including a SiN layer and a SiO ₂ layer laminated in this order from the first main surface 103 side of SiC semiconductor layer 102 . Gate insulating layer 148 may have a laminated structure including a SiO ₂ layer and a SiN layer laminated in this order from the first main surface 103 side of SiC semiconductor layer 102 . The gate insulating layer 148 may have a single layer structure consisting of a _SiO2 layer or a SiN layer. The gate insulating layer 148 has a single layer structure consisting of a SiO ₂ layer in this embodiment.

The gate insulating layer 148 is formed in a film shape along the inner wall surface of the gate trench 142 so that a recessed space is defined in the gate trench 142 . The gate insulating layer 148 includes a first region 148a, a second region 148b and a third region 148c.

The first region 148 a is formed along sidewalls of the gate trench 142 . A second region 148 b is formed along the bottom wall of the gate trench 142 . Third region 148 c is formed along first main surface 103 of SiC semiconductor layer 102 . A third region 148 c of the gate insulating layer 148 forms part of the main surface insulating layer 113 .

The thickness Ta of the first region 148a is smaller than the thickness Tb of the second region 148b and the thickness Tc of the third region 148c. A ratio Tb/Ta of the thickness Tb of the second region 148b to the thickness Ta of the first region 148a may be 2 or more and 5 or less. A ratio T3/Ta of the thickness Tc of the third region 148c to the thickness Ta of the first region 148a may be 2 or more and 5 or less.

The thickness Ta of the first region 148a may be 0.01 μm or more and 0.2 μm or less. The thickness Tb of the second region 148b may be 0.05 μm or more and 0.5 μm or less. The thickness Tc of the third region 148c may be 0.05 μm or more and 0.5 μm or less.

By thinning the first region 148 a of the gate insulating layer 148 , it is possible to suppress an increase in carriers induced in the region near the side wall of each gate trench 142 in the body region 141 . This can suppress an increase in channel resistance. By thickening the second region 148b of the gate insulating layer 148, electric field concentration on the bottom wall of each gate trench 142 can be alleviated.

By increasing the thickness of the third region 148c of the gate insulating layer 148, the breakdown voltage of the gate insulating layer 148 in the vicinity of the opening edge portion 146 of each gate trench 142 can be improved. Further, by increasing the thickness of the third region 148c, it is possible to prevent the third region 148c from disappearing due to the etching method.

This can suppress removal of the first region 148a by the etching method due to disappearance of the third region 148c. As a result, the gate electrode layer 149 can be appropriately opposed to the SiC semiconductor layer 102 (body region 141) with the gate insulating layer 148 interposed therebetween.

The gate insulating layer 148 further includes a bulging portion 148 d that bulges into each gate trench 142 at the opening edge portion 146 of each gate trench 142 . The bulging portion 148d is formed at a corner connecting the first region 148a and the third region 148c of the gate insulating layer 148. As shown in FIG.

The bulging portion 148d protrudes inward from each gate trench 142 in a curved shape. The bulging portion 148 d narrows the opening of each gate trench 142 at the opening edge portion 146 of each gate trench 142 .

The dielectric strength of the gate insulating layer 148 at the opening edge portion 146 is improved by the bulging portion 148d. Of course, the gate insulating layer 148 without the bulging portion 148d may be formed. Also, a gate insulating layer 148 having a uniform thickness may be formed.

A gate electrode layer 149 is embedded in each gate trench 142 with a gate insulating layer 148 interposed therebetween. More specifically, the gate electrode layer 149 is embedded in a recessed space partitioned by the gate insulating layer 148 in each gate trench 142 . Gate electrode layer 149 is controlled by a gate voltage.

The gate electrode layer 149 has an upper end located on the opening side of each gate trench 142 . The upper end portion of the gate electrode layer 149 is formed in a concave curved shape that is recessed toward the bottom wall of each gate trench 142 . The upper end portion of the gate electrode layer 149 has a constricted portion that is constricted along the protruding portion 148 d of the gate insulating layer 148 .

A cross-sectional area of the gate electrode layer 149 (a cross-sectional area perpendicular to the direction in which each gate trench 142 extends) may be 0.05 μm ² or more and 0.5 μm ² or less. The cross-sectional area of gate electrode layer 149 is defined as the product of the depth of gate electrode layer 149 and the width of gate electrode layer 149 .

The depth of the gate electrode layer 149 is the distance from the top end to the bottom end of the gate electrode layer 149 . The width of gate electrode layer 149 is the width of gate trench 142 at an intermediate position between the top and bottom ends of gate electrode layer 149 . In the case where the upper end portion has a curved surface (concave curved shape in this embodiment), the position of the upper end portion of the gate electrode layer 149 is the middle position of the upper surface of the gate electrode layer 149 in the depth direction.

Gate electrode layer 149 includes p-type polysilicon doped with p-type impurities. The p-type impurity of gate electrode layer 149 may contain at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

The p-type impurity concentration of gate electrode layer 149 is higher than the p-type impurity concentration of body region 141 . More specifically, the p-type impurity concentration of gate electrode layer 149 is higher than the p-type impurity concentration of body region 141 .

The p-type impurity concentration of the gate electrode layer 149 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. The sheet resistance of the gate electrode layer 149 may be 10 Ω/square or more and 500 Ω/square or less (about 200 Ω/square in this embodiment).

Referring to FIGS. 18 and 20, gate interconnection layer 150 is formed in active region 111 . Gate wiring layer 150 is electrically connected to gate pad 116 and gate fingers 117 and 118 . In FIG. 20, the gate wiring layer 150 is indicated by hatching.

Gate wiring layer 150 is formed on first main surface 103 of SiC semiconductor layer 102 . More specifically, the gate wiring layer 150 is formed on the third region 148 c of the gate insulating layer 148 .

Gate wiring layer 150 is formed along outer gate fingers 117 in this configuration. More specifically, gate wiring layer 150 is formed along three side surfaces 105A, 105B and 105D of SiC semiconductor layer 102 so as to partition the inner region of active region 111 from three directions.

The gate wiring layer 150 is connected to the gate electrode layer 149 exposed from the contact trench portion 144 of each gate trench 142 . In this embodiment, the gate wiring layer 150 is formed by a drawn portion of the gate electrode layer 149 drawn from each gate trench 142 onto the first main surface 103 of the SiC semiconductor layer 102 . The top end of the gate wiring layer 150 is connected to the top end of the gate electrode layer 149 .

18, 19 and 21, a plurality of source trenches 155 are formed in first main surface 103 of SiC semiconductor layer 102 in active region 111. Referring to FIG. Each source trench 155 is formed in a region between two gate trenches 142 adjacent to each other.

The plurality of source trenches 155 are each formed in a strip shape extending along the first direction X (the m-axis direction of the SiC single crystal). The plurality of source trenches 155 are formed in a stripe shape as a whole in plan view. With respect to the second direction Y, the pitch between the central portions of the source trenches 155 adjacent to each other may be 1.5 μm or more and 3 μm or less.

Each source trench 155 penetrates body region 141 and reaches SiC epitaxial layer 107 . Each source trench 155 includes sidewalls and a bottom wall. The sidewalls forming the long sides of each source trench 155 are formed by the a-plane of SiC single crystal. A side wall forming a short side of each source trench 155 is formed by an m-plane of SiC single crystal.

A sidewall of each source trench 155 may extend along the normal Z direction. A sidewall of each source trench 155 may be formed substantially perpendicular to first main surface 103 of SiC semiconductor layer 102 .

In SiC semiconductor layer 102, the sidewall of each source trench 155 forms an angle of 90° or more and 95° or less (for example, 91° or more and 93° or less) with respect to first main surface 103 of SiC semiconductor layer 102. . Each source trench 155 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

The bottom wall of each source trench 155 is located in SiC epitaxial layer 107 . More specifically, the bottom wall of each source trench 155 is located in high concentration region 108 of SiC epitaxial layer 107 . More specifically, the bottom wall of each source trench 155 is located in the region between the bottom wall of each gate trench 142 and lightly doped region 109 .

The bottom wall of each source trench 155 faces the c-plane of the SiC single crystal. The bottom wall of each source trench 155 has an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

A bottom wall of each source trench 155 may be formed parallel to first main surface 103 of SiC semiconductor layer 102 . Of course, the bottom wall of each source trench 155 may be formed in a convex curve toward the second main surface 104 of the SiC semiconductor layer 102 .

The depth of each source trench 155 is greater than or equal to the depth of each gate trench 142 in this embodiment. The depth of each source trench 155 is more specifically greater than the depth of each gate trench 142 .

The bottom wall of each source trench 155 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142 . Of course, the depth of each source trench 155 may be equal to the depth of each gate trench 142 .

With respect to the normal direction Z, each source trench 155 may have a depth of 0.5 μm or more and 10 μm or less (for example, about 2 μm). A ratio of the depth of each source trench 155 to the depth of each gate trench 142 may be 1.5 or more. The ratio of the depth of each source trench 155 to the depth of each gate trench 142 is preferably 2 or more.

A first direction width of each source trench 155 may be substantially equal to a first direction width of each gate trench 142 . A first direction width of each source trench 155 may be greater than or equal to a first direction width of each gate trench 142 . The first direction width of each source trench 155 may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm).

A source insulating layer 156 and a source electrode layer 157 are formed in each source trench 155 . The source insulating layer 156 and the source electrode layer 157 are indicated by hatching in FIG.

The source insulating layer 156 contains at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). include.

Source insulating layer 156 may have a laminated structure including a SiN layer and a SiO ₂ layer laminated in this order from the first main surface 103 side of SiC semiconductor layer 102 . Source insulating layer 156 may have a laminated structure including a SiO ₂ layer and a SiN layer laminated in this order from the first main surface 103 side of SiC semiconductor layer 102 . The source insulating layer 156 may have a single layer structure consisting of a _SiO2 layer or a SiN layer. The source insulating layer 156 has a single layer structure consisting of a SiO ₂ layer in this embodiment.

The source insulating layer 156 is formed in a film shape along the inner wall surface of each source trench 155 so that a concave space is defined in each source trench 155 . The source insulating layer 156 includes a first region 156a and a second region 156b.

A first region 156 a is formed along the sidewall of each source trench 155 . A second region 156 b is formed along the bottom wall of each source trench 155 . The thickness Tsa of the first region 156a is smaller than the thickness Tsb of the second region 156b.

A ratio Tsb/Tsa of the thickness Tsb of the second region 156b to the thickness Tsa of the first region 156a may be 2 or more and 5 or less. The thickness Tsa of the first region 156a may be 0.01 μm or more and 0.2 μm or less. The thickness Tsb of the second region 156b may be 0.05 μm or more and 0.5 μm or less.

The thickness Tsa of the first region 156a may be substantially equal to the thickness Ta of the first region 156a of the gate insulating layer 148. FIG. The thickness Tsb of the second region 156b may be substantially equal to the thickness Tb of the second region 156b of the gate insulating layer 148. FIG. Of course, a source insulating layer 156 having a uniform thickness may be formed.

A source electrode layer 157 is embedded in each source trench 155 with a source insulating layer 156 interposed therebetween. More specifically, the source electrode layer 157 is embedded in a recessed space partitioned by the source insulating layer 156 in each source trench 155 . Source electrode layer 157 is controlled by a source voltage.

The source electrode layer 157 has an upper end located on the opening side of each source trench 155 . An upper end portion of source electrode layer 157 is formed below first main surface 103 of SiC semiconductor layer 102 . The upper end of source electrode layer 157 may be located above first main surface 103 of SiC semiconductor layer 102 .

The upper end portion of the source electrode layer 157 is formed in a concave curved shape that is depressed toward the bottom wall of each source trench 155 . The upper end of source electrode layer 157 may be formed parallel to first main surface 103 of SiC semiconductor layer 102 .

The top end of the source electrode layer 157 may protrude above the top end of the source insulating layer 156 . The top end of the source electrode layer 157 may be positioned below the top end of the source insulating layer 156 . Source electrode layer 157 may have a thickness of 0.5 μm or more and 10 μm or less (for example, about 1 μm).

Source electrode layer 157 preferably contains polysilicon having properties close to SiC. Thereby, the stress generated in the SiC semiconductor layer 102 can be reduced. Source electrode layer 157 includes p-type polysilicon doped with p-type impurities in this embodiment. In this case, the source electrode layer 157 can be formed simultaneously with the gate electrode layer 149 .

The p-type impurity concentration of source electrode layer 157 is equal to or higher than the p-type impurity concentration of body region 141 . More specifically, the p-type impurity concentration of source electrode layer 157 is higher than the p-type impurity concentration of body region 141 . The p-type impurity of source electrode layer 157 may contain at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

The p-type impurity concentration of the source electrode layer 157 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. The sheet resistance of the source electrode layer 157 may be 10 Ω/square or more and 500 Ω/square or less (about 200 Ω/square in this embodiment).

The p-type impurity concentration of source electrode layer 157 may be substantially equal to the p-type impurity concentration of gate electrode layer 149 . The sheet resistance of source electrode layer 157 may be approximately equal to the sheet resistance of gate electrode layer 149 .

Source electrode layer 157 may contain n-type polysilicon instead of or in addition to p-type polysilicon. Source electrode layer 157 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.

Thus, SiC semiconductor device 101 has multiple trench gate structures 161 and multiple trench source structures 162 . Each trench gate structure 161 includes a gate trench 142 , a gate insulating layer 148 and a gate electrode layer 149 . Each trench source structure 162 includes source trench 155 , source insulating layer 156 and source electrode layer 157 .

An n ⁺ -type source region 163 is formed along the side wall of each gate trench 142 in the surface layer portion of the body region 141 . The n-type impurity concentration of the source region 163 may be 1.0×10 ¹⁸ cm ⁻³ or more and 1.0×10 ²¹ cm ⁻³ or less. The n-type impurity of source region 163 may be phosphorus (P).

A plurality of source regions 163 are formed along one sidewall and the other sidewall of each gate trench 142 . The plurality of source regions 163 are each formed in a strip shape extending along the first direction X. As shown in FIG.

The plurality of source regions 163 are formed in a stripe shape as a whole in plan view. Each source region 163 is exposed from the sidewalls of each gate trench 142 and the sidewalls of each source trench 155 .

Thus, in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 , the region along the sidewall of the gate trench 142 has a source region extending from the first main surface 103 toward the second main surface 104 of the SiC semiconductor layer 102 . 163, body region 141 and drift region 135 are formed in this order.

A channel of the MISFET is formed in a region along the sidewall of gate trench 142 in body region 141 . A channel is formed in a region along the side wall facing the a-plane of the SiC single crystal in the gate trench 142 . ON/OFF of the channel is controlled by the gate electrode layer 149 .

A plurality of p ⁺ -type contact regions 164 are formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 in the active region 111 . Each contact region 164 is formed in a region between two gate trenches 142 adjacent to each other in plan view. Each contact region 164 is formed in a region opposite to the gate trench 142 with respect to each source region 163 .

Each contact region 164 is formed along the inner wall of each source trench 155 . In this form, a plurality of contact regions 164 are formed along the inner wall of each source trench 155 at intervals. Each contact region 164 is spaced from each gate trench 142 .

The p-type impurity concentration of each contact region 164 is higher than the p-type impurity concentration of body region 141 . Each contact region 164 may have a p-type impurity concentration of 1.0×10 ¹⁸ cm ⁻³ or more and 1.0×10 ²¹ cm ⁻³ or less. The p-type impurity of each contact region 164 may be aluminum (Al).

Each contact region 164 covers the sidewalls and bottom walls of each source trench 155 . The bottom of each contact region 164 may be formed parallel to the bottom wall of each source trench 155 . Each contact region 164 more specifically integrally includes a first surface region 164a, a second surface region 164b and an inner wall region 164c.

The first surface layer region 164 a covers one sidewall of the source trench 155 in the surface layer portion of the body region 141 . First surface layer region 164 a is electrically connected to body region 141 and source region 163 .

The first surface layer region 164 a is located in a region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom of the source region 163 . First surface layer region 164 a has a bottom extending parallel to first main surface 103 of SiC semiconductor layer 102 in this embodiment.

The bottom of the first surface layer region 164a is located in the region between the bottom of the body region 141 and the bottom of the source region 163 in this embodiment. The bottom of first surface layer region 164 a may be located in a region between first main surface 103 of SiC semiconductor layer 102 and the bottom of body region 141 .

The first surface region 164a is drawn from the source trench 155 toward the adjacent gate trench 142 in this embodiment. The first superficial region 164 a may extend to an intermediate region between the gate trench 142 and the source trench 155 . The first surface region 164a is formed spaced apart from the gate trench 142 on the source trench 155 side.

The second surface layer region 164 b covers the other sidewall of the source trench 155 in the surface layer portion of the body region 141 . Second surface layer region 164 b is electrically connected to body region 141 and source region 163 .

The second surface layer region 164 b is located in a region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom of the source region 163 . The second surface region 164b has a bottom extending parallel to the first main surface 103 of the SiC semiconductor layer 102 in this embodiment.

The bottom of the second surface layer region 164b is located in the region between the bottom of the body region 141 and the bottom of the source region 163 in this embodiment. The bottom of second surface layer region 164 b may be located in a region between first main surface 103 of SiC semiconductor layer 102 and the bottom of body region 141 .

In this embodiment, the second surface region 164b is drawn out from the side wall on the other side of the source trench 155 toward the adjacent gate trench 142 . Second surface region 164b may extend to an intermediate region between source trench 155 and gate trench 142 . The second surface region 164b is formed spaced apart from the gate trench 142 on the source trench 155 side.

The inner wall region 164c is located in a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the first surface layer region 164a and the second surface layer region 164b (bottom portion of the source region 163). Inner wall region 164 c is formed in a region along the inner wall of source trench 155 in SiC semiconductor layer 102 . Inner wall region 164 c covers the sidewall of source trench 155 .

Inner wall region 164 c covers corners connecting the sidewalls and bottom walls of source trench 155 . The inner wall region 164c covers the bottom wall of the source trench 155 from the side wall of the source trench 155 through the corner. The bottom of contact region 164 is formed by inner wall region 164c.

A plurality of deep well regions 165 are formed in the surface layer portion of first main surface 103 of SiC semiconductor layer 102 . Each deep well region 165 is also called a breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the active region 111 .

Each deep well region 165 is formed in SiC epitaxial layer 107 . More specifically, each deep well region 165 is formed in high concentration region 108 of SiC epitaxial layer 107 .

Each deep well region 165 is formed along the inner wall of each source trench 155 to cover each contact region 164 . Each deep well region 165 is electrically connected to each contact region 164 .

Each deep well region 165 is formed in a strip shape extending along each source trench 155 in plan view. Each deep well region 165 covers the sidewalls of each source trench 155 .

Each deep well region 165 covers the corners connecting the sidewalls and bottom walls of each source trench 155 . Each deep well region 165 covers the bottom wall of each source trench 155 from the side wall of each source trench 155 through the corner. Each deep well region 165 is contiguous with body region 141 at the sidewall of each source trench 155 .

Each deep well region 165 has a bottom located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142 . The bottom of each deep well region 165 may be formed parallel to the bottom wall of each source trench 155 .

The p-type impurity concentration of each deep well region 165 may be substantially equal to the p-type impurity concentration of body region 141 . The p-type impurity concentration of each deep well region 165 may exceed the p-type impurity concentration of body region 141 . The p-type impurity concentration of each deep well region 165 may be less than the p-type impurity concentration of body region 141 .

The p-type impurity concentration of each deep well region 165 may be less than or equal to the p-type impurity concentration of the contact region 164 . The p-type impurity concentration of each deep well region 165 may be less than the p-type impurity concentration of the contact regions 164 . Each deep well region 165 may have a p-type impurity concentration of 1.0×10 ¹⁷ cm ⁻³ or more and 1.0×10 ¹⁹ cm ⁻³ or less.

Each deep well region 165 forms a pn junction with SiC semiconductor layer 102 (high concentration region 108 of SiC epitaxial layer 107). A depletion layer spreads from this pn junction toward a region between a plurality of gate trenches 142 adjacent to each other. This depletion layer extends from the bottom wall of each gate trench 142 toward the region on the second main surface 104 side of SiC semiconductor layer 102 .

A depletion layer extending from each deep well region 165 may overlap the bottom wall of each gate trench 142 . A depletion layer extending from the bottom of each deep well region 165 may overlap the bottom wall of each gate trench 142 .

18 and 20, a p-type peripheral deep well region 166 is formed at the peripheral edge of active region 111. Referring to FIG. A peripheral deep well region 166 is formed in the SiC epitaxial layer 107 . More specifically, peripheral deep well region 166 is formed in high concentration region 108 of SiC epitaxial layer 107 .

A peripheral deep well region 166 is electrically connected to each deep well region 165 . The peripheral deep well region 166 has the same potential as each deep well region 165 . The peripheral deep well region 166 is integrally formed with each deep well region 165 in this form.

More specifically, the peripheral deep well region 166 is formed along the inner wall of the contact trench portion 144 of each gate trench 142 in the peripheral portion of the active region 111 .

A peripheral deep well region 166 lines the sidewalls of the contact trench portion 144 of each gate trench 142 . A peripheral deep well region 166 covers the corners connecting the sidewalls and bottom walls of each contact trench portion 144 .

The peripheral deep well region 166 covers the bottom wall of each contact trench portion 144 from the side wall of each contact trench portion 144 through the corners. Each deep well region 165 continues to the body region 141 on the side wall of each contact trench portion 144 . The bottom of peripheral deep well region 166 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each contact trench portion 144 .

The peripheral deep well region 166 overlaps the gate wiring layer 150 in plan view. The peripheral deep well region 166 faces the gate wiring layer 150 with the gate insulating layer 148 (third region 148c) interposed therebetween.

The peripheral deep well region 166 includes lead-out portions 166 a led out from each contact trench portion 144 to each active trench portion 143 . Lead portion 166 a is formed in high-concentration region 108 of SiC epitaxial layer 107 . The lead-out portion 166a extends along the side wall of each active trench portion 143 and covers the bottom wall of the active trench portion 143 through the corner portion.

The lead-out portion 166 a covers the sidewall of the active trench portion 143 of each gate trench 142 . The lead-out portion 166 a covers corners connecting the sidewalls and bottom walls of each active trench portion 143 .

The lead-out portion 166a covers the bottom wall of each active trench portion 143 from the side wall of each active trench portion 143 through the corner portion. The lead portion 166 a continues to the body region 141 on the side wall of each active trench portion 143 . The bottom of lead portion 166 a is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each active trench portion 143 .

The p-type impurity concentration of the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration of the body region 141 . The p-type impurity concentration of the peripheral deep well region 166 may exceed the p-type impurity concentration of the body region 141 . The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the body region 141 .

The p-type impurity concentration of the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration of each deep well region 165 . The p-type impurity concentration of the peripheral deep well region 166 may exceed the p-type impurity concentration of each deep well region 165 . The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of each deep well region 165 .

The p-type impurity concentration of the peripheral deep well region 166 may be less than or equal to the p-type impurity concentration of the contact region 164 . The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the contact region 164 . The peripheral deep well region 166 may have a p-type impurity concentration of 1.0×10 ¹⁷ cm ⁻³ or more and 1.0×10 ¹⁹ cm ⁻³ or less.

A SiC semiconductor device having only a pn junction diode has little problem of electric field concentration in the SiC semiconductor layer 102 because of its structure without a trench. Each deep well region 165 (peripheral deep well region 166) brings the trench gate type MISFET closer to the structure of a pn junction diode.

As a result, the electric field in the SiC semiconductor layer 102 can be relaxed in the trench gate type MISFET. Therefore, narrowing the pitch between the plurality of deep well regions 165 adjacent to each other is effective in alleviating electric field concentration.

Further, according to each deep well region 165 having a bottom portion on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142, the depletion layer appropriately concentrates the electric field on each gate trench 142. can be mitigated.

The distance between the bottom of each deep well region 165 and the second main surface 104 of SiC semiconductor layer 102 is preferably substantially constant. This can suppress variation in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 .

Therefore, it is possible to prevent the breakdown voltage (for example, breakdown resistance) of the SiC semiconductor layer 102 from being restricted by the form of each deep well region 165, so that the breakdown voltage can be appropriately improved.

In this form, high-concentration regions 108 of SiC epitaxial layer 107 are interposed in regions between a plurality of deep well regions 165 adjacent to each other. Thereby, JFET (Junction Field Effect Transistor) resistance can be reduced in the region between the plurality of deep well regions 165 adjacent to each other.

Furthermore, in this configuration, the bottom of each deep well region 165 is located within the heavily doped region 108 of the SiC epitaxial layer 107 . Thereby, the current path can be extended laterally from the bottom of each deep well region 165 in parallel with the first main surface 103 of the SiC semiconductor layer 102 . Thereby, the current spreading resistance can be reduced. Low-concentration region 109 of SiC epitaxial layer 107 increases the withstand voltage of SiC semiconductor layer 102 in such a structure.

By forming the source trenches 155 , p-type impurities can be introduced into the inner walls of the source trenches 155 . As a result, each deep well region 165 can be formed conformally with respect to the source trench 155, so that variations in the depth of each deep well region 165 can be appropriately suppressed. Moreover, by using each source trench 155, each deep well region 165 can be appropriately formed in a relatively deep region of the SiC semiconductor layer 102. FIG.

Referring to FIG. 21, a low resistance electrode layer 167 is formed on gate electrode layer 149 . The low resistance electrode layer 167 covers the upper end of the gate electrode layer 149 in each gate trench 142 .

Low resistance electrode layer 167 includes a conductive material having a sheet resistance less than that of gate electrode layer 149 . The sheet resistance of the low-resistance electrode layer 167 may be 0.01Ω/□ or more and 10Ω/□ or less.

The low resistance electrode layer 167 is formed in a film shape. The low-resistance electrode layer 167 has a connection portion 167a in contact with the upper end portion of the gate electrode layer 149 and a non-connection portion 167b on the opposite side. The connection portion 167 a and the non-connection portion 167 b of the low-resistance electrode layer 167 may be formed in a concave curved shape following the upper end portion of the gate electrode layer 149 . The connecting portion 167a and the non-connecting portion 167b of the low-resistance electrode layer 167 can take various forms.

The entire connection portion 167a of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102 . The entire connection portion 167 a of the low resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102 .

Connection portion 167 a of low-resistance electrode layer 167 may include a portion located above first main surface 103 of SiC semiconductor layer 102 . Connection portion 167 a of low-resistance electrode layer 167 may include a portion located below first main surface 103 of SiC semiconductor layer 102 .

For example, the central portion of connection portion 167a of low-resistance electrode layer 167 is located below first main surface 103 of SiC semiconductor layer 102, and the peripheral portion of connection portion 167a of low-resistance electrode layer 167 is located below SiC semiconductor layer 102. It may be located above the first major surface 103 .

The entire non-connection portion 167b of the low resistance electrode layer 167 may be positioned above the first main surface 103 of the SiC semiconductor layer 102 . The entire non-connection portion 167 b of the low resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102 .

Non-connection portion 167 b of low-resistance electrode layer 167 may include a portion located above first main surface 103 of SiC semiconductor layer 102 . Non-connection portion 167 b of low-resistance electrode layer 167 may include a portion located below first main surface 103 of SiC semiconductor layer 102 .

For example, the central portion of non-connection portion 167b of low-resistance electrode layer 167 is located below first main surface 103 of SiC semiconductor layer 102, and the peripheral portion of non-connection portion 167b of low-resistance electrode layer 167 is located below the SiC semiconductor layer. 102 may be located above the first major surface 103 .

The low resistance electrode layer 167 has an edge portion 167c in contact with the gate insulating layer 148. As shown in FIG. Edge 167c of low resistance electrode layer 167 is in contact with a corner connecting first region 148a and second region 148b in gate insulating layer 148 .

An edge portion 167c of the low-resistance electrode layer 167 is in contact with the third region 148c of the gate insulating layer 148. As shown in FIG. More specifically, edge portion 167 c of low-resistance electrode layer 167 is in contact with bulging portion 148 d of gate insulating layer 148 .

Edge portion 167 c of low-resistance electrode layer 167 is formed in a region on the first main surface 103 side of SiC semiconductor layer 102 with respect to the bottom portion of source region 163 . Edge portion 167 c of low-resistance electrode layer 167 is formed in a region closer to first main surface 103 of SiC semiconductor layer 102 than the boundary region between body region 141 and source region 163 .

Therefore, edge portion 167c of low-resistance electrode layer 167 faces source region 163 with gate insulating layer 148 interposed therebetween. Edge portion 167c of low-resistance electrode layer 167 does not face body region 141 with gate insulating layer 148 interposed therebetween.

Thereby, formation of a current path in a region between low-resistance electrode layer 167 and body region 141 in gate insulating layer 148 can be suppressed. A current path may be formed by unwanted diffusion of the electrode material of the low resistance electrode layer 167 to the gate insulating layer 148 .

In particular, the design of connecting the edge 167c of the low-resistance electrode layer 167 to the third region 148c (corner of the gate insulating layer 148) of the relatively thick gate insulating layer 148 reduces the risk of forming a current path. is valid on

With respect to the normal direction Z, the thickness Tr of the low-resistance electrode layer 167 is equal to or less than the thickness TG of the gate electrode layer 149 (Tr≦TG). The thickness Tr of the low-resistance electrode layer 167 is preferably less than the thickness TG of the gate electrode layer 149 (Tr<TG). More specifically, thickness Tr of low-resistance electrode layer 167 is preferably half or less of thickness TG of gate electrode layer 149 (Tr≦TG/2).

A ratio Tr/TG of the thickness Tr of the low-resistance electrode layer 167 to the thickness TG of the gate electrode layer 149 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 149 may be 0.5 μm or more and 3 μm or less. The thickness Tr of the low resistance electrode layer 167 may be 0.01 μm or more and 3 μm or less.

A current supplied into each gate trench 142 flows through the low resistance electrode layer 167 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 149 . As a result, the entire gate electrode layer 149 (the entire active region 111) can be rapidly switched from the off state to the on state, thereby suppressing delay in switching response.

In particular, in the case of the gate trench 142 having a length on the order of millimeters (length of 1 mm or longer), it takes time to transmit current, but the low-resistance electrode layer 167 can appropriately suppress delay in switching response. . That is, the low-resistance electrode layer 167 is formed as a current diffusion electrode layer that diffuses current in each gate trench 142 .

Further, as the cell structure becomes finer, the width, depth, cross-sectional area, etc. of the gate electrode layer 149 become smaller, so there is a concern that switching response may be delayed due to an increase in electrical resistance in each gate trench 142 . .

However, according to the low-resistance electrode layer 167, the entire gate electrode layer 149 can be rapidly switched from the off state to the on state, so that delay in switching response due to miniaturization can be appropriately suppressed.

Referring to FIG. 20, low-resistance electrode layer 167 also covers the upper end portion of gate wiring layer 150 in this embodiment. A portion of the low-resistance electrode layer 167 covering the upper end portion of the gate wiring layer 150 is formed integrally with a portion of the low-resistance electrode layer 167 covering the upper end portion of the gate electrode layer 149 . Thus, the low resistance electrode layer 167 covers the entire area of the gate electrode layer 149 and the entire area of the gate wiring layer 150 .

Therefore, a current supplied from gate pad 116 and gate fingers 117 and 118 to gate wiring layer 150 flows through gate electrode layer 149 and gate wiring layer 150 through low resistance electrode layer 167 having a relatively low sheet resistance. transmitted.

As a result, the entire gate electrode layer 149 (the entire active region 111) can be quickly switched from the off state to the on state via the gate wiring layer 150, so that delay in switching response can be suppressed.

In particular, in the case of the gate trench 142 having a length on the order of millimeters, the low-resistance electrode layer 167 covering the upper end portion of the gate wiring layer 150 can appropriately suppress delay in switching response.

Low resistance electrode layer 167 includes a polycide layer. The polycide layer is formed by siliciding the portion forming the surface layer portion of the gate electrode layer 149 with a metal material. The polycide layer is, more specifically, a p-type polycide layer containing p-type impurities added to the gate electrode layer 149 (p-type polysilicon). The polycide layer preferably has a specific resistance of 10 μΩ·cm or more and 110 μΩ·cm or less.

The sheet resistance in the gate trench 142 in which the gate electrode layer 149 and the low resistance electrode layer 167 are buried is less than the sheet resistance of the gate electrode layer 149 alone. The sheet resistance in the gate trench 142 is preferably less than the sheet resistance of n-type polysilicon doped with n-type impurities.

The sheet resistance in gate trench 142 approximates the sheet resistance of low resistance electrode layer 167 . That is, the sheet resistance in the gate trench 142 may be 0.01Ω/□ or more and 10Ω/□ or less. The sheet resistance in gate trench 142 is preferably less than 10Ω/square.

The low resistance electrode layer 167 may contain at least one of TiSi, TiSi ₂ , NiSi, CoSi, CoSi ₂ , MoSi ₂ and WSi ₂ . In particular, NiSi, CoSi ₂ and TiSi ₂ among these species are suitable as the polycide layer forming the low-resistance electrode layer 167 because of their relatively low resistivity and temperature dependence.

In first main surface 103 of SiC semiconductor layer 102 , source sub-trench 168 communicating with each source trench 155 is formed in a region along the upper end portion of source electrode layer 157 . Source sub-trench 168 forms part of the sidewall of each source trench 155 .

In this form, the source sub-trench 168 is formed in an endless shape (in this form, a square annular shape) surrounding the upper end portion of the source electrode layer 157 in plan view. The source sub-trench 168 borders the upper edge of the source electrode layer 157 .

Source sub-trench 168 is formed by digging down a portion of source insulating layer 156 . More specifically, source sub-trench 168 is formed by digging the upper end portion of source insulating layer 156 and the upper end portion of source electrode layer 157 from first main surface 103 of SiC semiconductor layer 102 .

The upper end portion of the source electrode layer 157 has a constricted shape with respect to the lower end portion of the source electrode layer 157 . A lower end portion of the source electrode layer 157 is a portion of the source electrode layer 157 located on the bottom wall side of each source trench 155 . The first direction width of the top end of the source electrode layer 157 may be less than the first direction width of the bottom end of the source electrode layer 157 .

The source sub-trench 168 is formed in a tapered shape in which the bottom area is smaller than the opening area in a cross-sectional view. A bottom wall of the source sub-trench 168 may be formed in a convex curve toward the second main surface 104 of the SiC semiconductor layer 102 .

Source region 163 , contact region 164 , source insulating layer 156 and source electrode layer 157 are exposed from the inner wall of source sub-trench 168 . From the inner walls of the source sub-trench 168, the first surface layer region 164a and the second surface layer region 164b of the contact region 164 are exposed.

At least the first region 156 a of the source insulating layer 156 is exposed from the bottom wall of the source sub-trench 168 . An upper end portion of the first region 156 a in the source insulating layer 156 is located below the first main surface 103 of the SiC semiconductor layer 102 .

Opening edge portion 169 of each source trench 155 includes an inclined portion 170 that slopes downward from first main surface 103 of SiC semiconductor layer 102 toward the inside of each source trench 155 . Opening edge portion 169 of each source trench 155 is a corner connecting first main surface 103 of SiC semiconductor layer 102 and the side wall of each source trench 155 . A sloped portion 170 of each source trench 155 is formed by a source sub-trench 168 .

In this embodiment, the inclined portion 170 is formed in a concave curved shape directed inward of the SiC semiconductor layer 102 . The inclined portion 170 may be formed in a convex curved shape directed inward of the source sub-trench 168 . The sloped portion 170 reduces electric field concentration on the opening edge portion 169 of each source trench 155 .

22 and 23, active region 111 has an active main surface 171 forming part of first main surface 103 of SiC semiconductor layer 102 . Outer region 112 has an outer major surface 172 that forms part of first major surface 103 of SiC semiconductor layer 102 . Outer main surface 172 is connected to side surfaces 105A to 105D of SiC semiconductor layer 102 in this embodiment.

The active main surface 171 and the outer main surface 172 each face the c-plane of the SiC single crystal. In addition, the active main surface 171 and the outer main surface 172 each have an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

Outer main surface 172 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to active main surface 171 . In this embodiment, outer region 112 is formed by digging down first main surface 103 of SiC semiconductor layer 102 toward second main surface 104 . Therefore, outer main surface 172 is formed in a region recessed toward second main surface 104 of SiC semiconductor layer 102 with respect to active main surface 171 .

The outer major surface 172 may be located on the second major surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142 . The outer major surface 172 may be formed at a depth position substantially equal to the bottom wall of each source trench 155 . Outer major surface 172 may be substantially coplanar with the bottom wall of each source trench 155 .

The distance between outer major surface 172 and second major surface 104 of SiC semiconductor layer 102 may be substantially equal to the distance between the bottom wall of each source trench 155 and second major surface 104 of SiC semiconductor layer 102 .

Outer main surface 172 may be located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155 . The outer main surface 172 may be located on the second main surface 104 side of the SiC semiconductor layer 102 within a range of 0 μm or more and 1 μm or less with respect to the bottom wall of each source trench 155 .

SiC epitaxial layer 107 is exposed from outer main surface 172 . More specifically, high concentration region 108 of SiC epitaxial layer 107 is exposed from outer main surface 172 of outer region 112 . Outer main surface 172 faces low concentration region 109 of SiC epitaxial layer 107 with high concentration region 108 of SiC epitaxial layer 107 interposed therebetween.

The active area 111 is plateau-shaped in this embodiment by an outer area 112 . The active region 111 is formed as a plateau-shaped active plateau 173 protruding upward from the outer region 112 .

Active plateau 173 includes active sidewalls 174 connecting active major surface 171 and outer major surface 172 . Active sidewalls 174 define the boundary area between active area 111 and outer area 112 . First main surface 103 of SiC semiconductor layer 102 is formed by active main surface 171 , outer main surface 172 and active sidewalls 174 .

The active sidewalls 174 extend along the normal direction Z of the active major surface 171 (outer major surface 172) in this configuration. Active sidewalls 174 are formed by the m-plane and a-plane of SiC single crystal.

The active sidewalls 174 may have sloped surfaces that slope downward from the active major surface 171 toward the outer major surface 172 . The inclination angle of active sidewall 174 is the angle formed between active sidewall 174 and active main surface 171 in SiC semiconductor layer 102 .

In this case, the inclination angle of the active sidewalls 174 may be greater than 90° and less than or equal to 135°. The slope angle of the active sidewalls 174 may be greater than 90° and less than or equal to 95°, 95° to 100°, 100° to 110°, 110° to 120°, or 120° to 135°. The inclination angle of the active sidewalls 174 is preferably greater than 90° and less than or equal to 95°.

The SiC epitaxial layer 107 is exposed from the active sidewalls 174 . More specifically, heavily doped regions 108 of SiC epitaxial layer 107 are exposed from active sidewalls 174 .

At least the body region 141 is exposed from the region of the active side wall 174 on the active main surface 171 side. FIGS. 22 and 23 show an example configuration in which active sidewalls 174 expose body region 141 and source region 163 .

In outer region 112, the surface layer portion of first main surface 103 (outer main surface 172) of SiC semiconductor layer 102 includes p ⁺ -type diode region 181 (impurity region), p-type outer deep well region 182 and p-type of field limit structures 183 are formed.

Diode region 181 is formed in the region between active sidewall 174 and side surfaces 105A-105D of SiC semiconductor layer 102 in outer region 112 . Diode region 181 is spaced from active sidewalls 174 and sides 105A-105D.

Diode region 181 extends in a strip shape along active region 111 in plan view. In this form, the diode region 181 is formed in an endless shape (in this form, a square ring shape) surrounding the active region 111 in plan view.

The diode region 181 overlaps the source lead-out wiring 123 in plan view. The diode region 181 is electrically connected to the source lead-out wiring 123 . Diode region 181 forms part of the avalanche current absorption structure.

Diode region 181 forms a pn junction with SiC semiconductor layer 102 . Diode region 181 is more specifically located within SiC epitaxial layer 107 . Diode region 181 thus forms a pn junction with SiC epitaxial layer 107 .

More specifically, diode region 181 is located within high-concentration region 108 of SiC epitaxial layer 107 . Diode region 181 thus forms a pn junction with heavily doped region 108 . Thereby, a pn junction diode Dpn having the diode region 181 as an anode and the SiC semiconductor layer 102 as a cathode is formed.

The entire diode region 181 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142 . The bottom of diode region 181 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155 .

The bottom of diode region 181 may be formed at a depth substantially equal to the bottom of contact region 164 . The bottom of diode region 181 may be substantially flush with the bottom of contact region 164 .

The p-type impurity concentration of diode region 181 is substantially equal to the p-type impurity concentration of contact region 164 . The p-type impurity concentration of diode region 181 is higher than the p-type impurity concentration of body region 141 . The p-type impurity concentration of the diode region 181 may be 1.0×10 ¹⁸ cm ⁻³ or more and 1.0×10 ²¹ cm ⁻³ or less.

Outer deep well region 182 is formed in a region between active sidewall 174 and diode region 181 in plan view. The outer deep well region 182 is spaced from the active sidewall 174 toward the diode region 181 side in this embodiment. The outer deep well region 182 is also called a breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the outer region 112 .

The outer deep well region 182 extends like a strip along the active region 111 in plan view. In this form, the outer deep well region 182 is formed in an endless shape (in this form, a quadrangular ring shape) surrounding the active region 111 in plan view.

The outer deep well region 182 is electrically connected to the source lead-out wiring 123 via the diode region 181 . Outer deep well region 182 may form part of a pn junction diode Dpn. Outer deep well region 182 may form part of an avalanche current absorbing structure.

The entire outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142 . The bottom of outer deep well region 182 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155 .

The bottom of outer deep well region 182 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom of diode region 181 . The bottom of the outer deep well region 182 may be formed at approximately the same depth as the bottom of each deep well region 165 . The bottom of outer deep well region 182 may be substantially flush with the bottom of each deep well region 165 .

The distance between the bottom of outer deep well region 182 and outer major surface 172 may be approximately equal to the distance between the bottom of each deep well region 165 and the bottom wall of each source trench 155 .

The distance between the bottom of outer deep well region 182 and second major surface 104 of SiC semiconductor layer 102 is substantially equal to the distance between the bottom of each deep well region 165 and second major surface 104 of SiC semiconductor layer 102 . good too.

Thereby, the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 and the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 It is possible to suppress the occurrence of variations between

Therefore, it is possible to prevent the breakdown voltage (for example, breakdown resistance) of SiC semiconductor layer 102 from being restricted by the configuration of outer deep well region 182 and the configuration of each deep well region 165, so that the breakdown voltage can be appropriately improved. .

The bottom of outer deep well region 182 may be located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom of each deep well region 165 . The bottom of the outer deep well region 182 may be located on the second main surface 104 side of the SiC semiconductor layer 102 within a range of 0 μm or more and 1 μm or less with respect to the bottom of each deep well region 165 .

The inner peripheral edge of outer deep well region 182 may extend to near the boundary region between active region 111 and outer region 112 . Outer deep well region 182 may traverse the boundary region of active region 111 and outer region 112 .

An inner peripheral edge of the outer deep well region 182 may cover the corner connecting the active sidewall 174 and the outer major surface 172 . The inner peripheral edge of outer deep well region 182 may also extend along active sidewall 174 and connect to body region 141 .

In this embodiment, the outer edge of outer deep well region 182 covers diode region 181 from the second main surface 104 side of SiC semiconductor layer 102 . The outer deep well region 182 may overlap the source lead-out wiring 123 in plan view. The outer edge of the outer deep well region 182 may be spaced from the diode region 181 toward the active sidewall 174 side.

The p-type impurity concentration of the outer deep well region 182 may be less than or equal to the p-type impurity concentration of the diode region 181 . The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the diode region 181 .

The p-type impurity concentration of outer deep well region 182 may be approximately equal to the p-type impurity concentration of each deep well region 165 . The p-type impurity concentration of outer deep well region 182 may be substantially equal to the p-type impurity concentration of body region 141 .

The p-type impurity concentration of outer deep well region 182 may exceed the p-type impurity concentration of body region 141 . The p-type impurity concentration of outer deep well region 182 may be less than the p-type impurity concentration of body region 141 .

The p-type impurity concentration of the outer deep well region 182 may be less than or equal to the p-type impurity concentration of the contact region 164 . The p-type impurity concentration of outer deep well region 182 may be less than the p-type impurity concentration of contact region 164 . The p-type impurity concentration of the outer deep well region 182 may be 1.0×10 ¹⁷ cm ⁻³ or more and 1.0×10 ¹⁹ cm ⁻³ or less.

Field limit structure 183 is formed in a region between diode region 181 and side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view. The field limit structures 183 are spaced apart from the side surfaces 105A to 105D toward the diode region 181 side in this embodiment.

Field limit structure 183 includes one or more (eg, 2 to 20) field limit regions 184 . Field limit structure 183, in this form, includes a group of field limit regions having a plurality (five) of field limit regions 184A, 184B, 184C, 184D and 184E.

The field limit regions 184A to 184E are formed in this order at intervals along the direction away from the diode region 181. As shown in FIG. Each of the field limit regions 184A to 184E extends like a strip along the periphery of the active region 111 in plan view.

More specifically, the field limit regions 184A to 184E are each formed in an endless shape (in this form, a square ring shape) surrounding the active region 111 in plan view. The field limit regions 184A to 184E are also called FLR (Field Limiting Ring) regions.

The bottoms of the field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of the diode region 181 in this embodiment.

The innermost field limit region 184A among the field limit regions 184A to 184E covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102 in this embodiment. The field limit region 184A may overlap the aforementioned source lead-out wiring 123 in plan view.

The field limit region 184A is electrically connected to the source lead-out line 123 via the diode region 181. As shown in FIG. Field limit region 184A may form part of pn junction diode Dpn. Field limit region 184A may form part of an avalanche current absorbing structure.

The entire field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. As shown in FIG. The bottoms of the field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155. As shown in FIG.

The field limit regions 184A-184E may be formed at approximately the same depth as each deep well region 165 (outer deep well region 182). The bottom of the field limit regions 184A-184E may be located substantially flush with the bottom of each deep well region 165 (outer deep well region 182).

The bottoms of the field limit regions 184A-184E may be located on the outer major surface 172 side with respect to the bottom of each deep well region 165 (outer deep well region 182). The bottoms of the field limit regions 184A-184E may be located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of each deep well region 165 (outer deep well region 182).

The widths between adjacent field limit regions 184A-184E may differ from each other. The width between adjacent field limit regions 184A-184E may increase in the direction away from active region 111. FIG. The width between adjacent field limit regions 184A-184E may decrease in the direction away from active region 111. FIG.

The depths of the field limit regions 184A-184E may differ from each other. The depth of field limit regions 184A-184E may decrease away from active area 111. FIG. The depth of field limit regions 184A-184E may increase in a direction away from active area 111. FIG.

The p-type impurity concentration of the field limit regions 184A-184E may be lower than the p-type impurity concentration of the diode region 181. FIG. The p-type impurity concentration of the field limit regions 184A-184E may be lower than the p-type impurity concentration of the diode region 181. FIG.

The p-type impurity concentration of the field limit regions 184A-184E may be less than or equal to the p-type impurity concentration of the outer deep well region 182. FIG. The p-type impurity concentration of the field limit regions 184A-184E may be less than the p-type impurity concentration of the outer deep well region 182. FIG.

The p-type impurity concentration of the field limit regions 184A-184E may be greater than or equal to the p-type impurity concentration of the outer deep well region 182. FIG. The p-type impurity concentration of the field limit regions 184A-184E may be greater than the p-type impurity concentration of the outer deep well region 182. FIG.

The p-type impurity concentration of the field limit regions 184A to 184E may be 1.0×10 ¹⁵ cm ⁻³ or more and 1.0×10 ¹⁸ cm ⁻³ or less. Preferably, the p-type impurity concentration of the diode region 181>the p-type impurity concentration of the outer deep well region 182>the p-type impurity concentration of the field limit regions 184A to 184E.

Field limit structure 183 relieves electric field concentration in outer region 112 . The number, width, depth, p-type impurity concentration, etc. of the field limit regions 184 can take various values according to the electric field to be relaxed.

In this embodiment, an example has been described in which field limit structure 183 includes one or more field limit regions 184 formed in regions between diode region 181 and side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view.

However, the field limit structure 183 is formed in a region between the active sidewall 174 and the diode region 181 in plan view instead of the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102. Multiple field limit regions 184 may be included.

The field limit structure 183 includes one or more field limit regions 184 formed in regions between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view, and active sidewalls 174 in plan view. and one or more field limit regions 184 formed in the region between the diode regions 181 .

An outer insulating layer 191 is formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112 . The outer insulating layer 191 forms part of the main surface insulating layer 113 . The outer insulating layer 191 forms part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113. As shown in FIG.

Outer insulating layer 191 selectively covers diode region 181 , outer deep well region 182 and field limit structure 183 in outer region 112 . The outer insulating layer 191 is formed like a film along the active sidewalls 174 and the outer main surface 172 . The outer insulating layer 191 is continuous with the gate insulating layer 148 over the active main surface 171 . More specifically, the outer insulating layer 191 continues to the third region 148 c of the gate insulating layer 148 .

Outer insulating layer 191 may include silicon oxide. Outer insulating layer 191 may include other insulating films such as silicon nitride. Outer insulating layer 191 is formed of the same insulating material type as gate insulating layer 148 in this embodiment.

The outer insulating layer 191 includes a first region 191a and a second region 191b. A first region 191 a of the outer insulating layer 191 covers the active sidewalls 174 . A second region 191 b of the outer insulating layer 191 covers the outer main surface 172 .

The thickness of the second region 191b of the outer insulating layer 191 may be less than or equal to the thickness of the first region 191a of the outer insulating layer 191 . The thickness of the second region 191 b of the outer insulating layer 191 may be less than the thickness of the first region 191 a of the outer insulating layer 191 .

The thickness of the first region 191 a of the outer insulating layer 191 may be approximately equal to the thickness of the first region 191 a of the gate insulating layer 148 . The thickness of the second region 191 b of the outer insulating layer 191 may be approximately equal to the thickness of the third region 148 c of the gate insulating layer 148 . Of course, an outer insulating layer 191 having a uniform thickness may be formed.

Referring to FIGS. 22 and 23, SiC semiconductor device 101 further includes sidewalls 192 covering active sidewalls 174 . Sidewalls 192 protect and reinforce the active plateau 173 from the outer region 112 side.

Moreover, the sidewalls 192 form a step relief structure that relieves the step formed between the active main surface 171 and the outer main surface 172 . When an overlying structure (covering layer) is formed to cover the boundary area between the active area 111 and the outer area 112 , the overlying structure covers the sidewalls 192 . Sidewalls 192 enhance the planarity of the overlying structure.

Sidewall 192 may have a sloped portion 193 that slopes down from active major surface 171 toward outer major surface 172 . The inclined portion 193 can moderate the step appropriately.

The inclined portion 193 of the sidewall 192 may be formed in a concave curved shape toward the SiC semiconductor layer 102 side. The sloped portion 193 of the sidewall 192 may be formed in a convex curve directed toward the side opposite to the SiC semiconductor layer 102 .

The inclined portion 193 of the sidewall 192 may extend planarly from the active main surface 171 side toward the outer main surface 172 side. The inclined portion 193 of the sidewall 192 may extend linearly from the active main surface 171 side toward the outer main surface 172 side.

The inclined portion 193 of the sidewall 192 may be formed in a descending step shape from the active main surface 171 toward the outer main surface 172 . The sloped portion 193 of the sidewall 192 may have one or more stepped portions recessed toward the outer major surface 172 side. The plurality of stepped portions increase the surface area of the sloped portion 193 of the sidewall 192 and enhance adhesion to the upper layer structure.

The sloped portion 193 of the sidewall 192 may include a plurality of ridges raised outwardly of the sidewall 192 . The multiple ridges increase the surface area of the sloping portion 193 of the sidewall 192 and enhance adhesion to the overlying structure.

The sloping portion 193 of the sidewall 192 may include a plurality of recesses recessed toward the inner side of the sidewall 192 . The plurality of depressions increases the surface area of the sloped portion 193 of the sidewall 192 and enhances adhesion to the overlying structure.

Sidewalls 192 are formed in self-alignment with active main surface 171 . Sidewalls 192 are more specifically formed along active sidewalls 174 . In this form, the sidewall 192 is formed in an endless shape (in this form, a square ring shape) surrounding the active region 111 in plan view.

Sidewalls 192 preferably include p-type polysilicon doped with p-type impurities. In this case, the sidewalls 192 can be formed simultaneously with the gate electrode layer 149 and the source electrode layer 157 .

The p-type impurity concentration of the sidewall 192 is higher than the p-type impurity concentration of the body region 141 . The p-type impurity concentration of sidewall 192 is more specifically higher than the p-type impurity concentration of body region 141 . The p-type impurity of sidewall 192 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

The sidewall 192 may have a p-type impurity concentration of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. The sheet resistance of the sidewall 192 may be 10 Ω/□ or more and 500 Ω/□ or less (about 200 Ω/□ in this embodiment).

The p-type impurity concentration of sidewall 192 may be substantially equal to the p-type impurity concentration of gate electrode layer 149 . The sheet resistance of sidewalls 192 may be approximately equal to the sheet resistance of gate electrode layer 149 .

Sidewalls 192 may include n-type polysilicon instead of or in addition to p-type polysilicon. Sidewalls 192 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.

Sidewalls 192 may include an insulating material. In this case, sidewalls 192 can increase the insulation of active region 111 from outer region 112 .

19 to 23, interlayer insulating layer 201 is formed on first main surface 103 of SiC semiconductor layer 102. Referring to FIGS. Interlayer insulating layer 201 forms part of main surface insulating layer 113 . Interlayer insulating layer 201 forms part of insulating side surfaces 114 A to 114 D of main surface insulating layer 113 . Principal surface insulating layer 113 has a laminated structure including gate insulating layer 148 (outer insulating layer 191 ) and interlayer insulating layer 201 .

An interlayer insulating layer 201 selectively covers the active area 111 and the outer area 112 . More specifically, the interlayer insulating layer 201 selectively covers the third region 148 c of the gate insulating layer 148 and the outer insulating layer 191 .

Interlayer insulating layer 201 is formed in a film shape along active main surface 171 and outer main surface 172 . Interlayer insulating layer 201 selectively covers trench gate structure 161 , gate wiring layer 150 and trench source structure 162 in active region 111 . Interlevel dielectric layer 201 selectively covers diode region 181 , outer deep well region 182 and field limit structure 183 in outer region 112 .

Interlayer insulating layer 201 is formed along the outer surface (inclined portion 193 ) of sidewall 192 in the boundary region between active region 111 and outer region 112 . The interlayer insulating layer 201 forms part of the upper layer structure covering the sidewalls 192 .

Interlayer insulating layer 201 may contain silicon oxide or silicon nitride. The interlayer insulating layer 201 may contain PSG (Phosphor Silicate Glass) and/or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.

Interlayer insulating layer 201 may have a laminated structure including a PSG layer and a BPSG layer laminated in this order from the first main surface 103 side of SiC semiconductor layer 102 . Interlayer insulating layer 201 may have a laminated structure including a BPSG layer and a PSG layer laminated in this order from the first main surface 103 side of SiC semiconductor layer 102 .

A gate contact hole 202 , a source contact hole 203 and a diode contact hole 204 are formed in the interlayer insulating layer 201 . Anchor holes 205 are formed in the interlayer insulating layer 201 .

Gate contact hole 202 exposes gate wiring layer 150 in active region 111 . The gate contact hole 202 may be formed in a strip shape along the gate wiring layer 150 . An opening edge portion of the gate contact hole 202 is formed in a convex curve toward the inside of the gate contact hole 202 .

Source contact hole 203 exposes source region 163 , contact region 164 and trench source structure 162 in active area 111 . The source contact hole 203 may be formed in a strip shape along the trench source structure 162 or the like. An opening edge portion of the source contact hole 203 is formed in a convex curve toward the inside of the source contact hole 203 .

Diode contact hole 204 exposes diode region 181 in outer region 112 . Diode contact hole 204 may be formed in a strip shape (more specifically, endless) extending along diode region 181 .

Diode contact holes 204 may expose outer deep well regions 182 and/or field limit structures 183 . An opening edge portion of the diode contact hole 204 is formed in a convex curved shape toward the inside of the diode contact hole 204 .

Anchor hole 205 is formed by digging down interlayer insulating layer 201 in outer region 112 . Anchor hole 205 is formed in a region between diode region 181 and side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view. More specifically, anchor hole 205 is formed in a region between field limit structure 183 and side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view.

Anchor hole 205 exposes first main surface 103 (outer main surface 172 ) of SiC semiconductor layer 102 . An opening edge portion of the anchor hole 205 is formed in a convex curve toward the inside of the anchor hole 205 .

Referring to FIG. 17, anchor hole 205 extends in a belt shape along active region 111 in plan view. In this form, the anchor hole 205 is formed in an endless shape (in this form, a square ring shape) surrounding the active region 111 in plan view.

In this embodiment, one anchor hole 205 is formed in a portion of interlayer insulating layer 201 covering outer region 112 . However, a plurality of anchor holes 205 may be formed in a portion of interlayer insulating layer 201 covering outer region 112 .

Main surface gate electrode layer 115 and main surface source electrode layer 121 are formed on interlayer insulating layer 201 . Main-surface gate electrode layer 115 and main-surface source electrode layer 121 each have a laminated structure including barrier electrode layer 206 and main electrode layer 207 laminated in this order from the first main surface 103 side of SiC semiconductor layer 102 . ing.

The barrier electrode layer 206 may have a single layer structure including a titanium layer or a titanium nitride layer. Barrier electrode layer 206 may have a laminated structure including a titanium layer and a titanium nitride layer laminated in this order from the first main surface 103 side of SiC semiconductor layer 102 .

The thickness of the main electrode layer 207 is greater than the thickness of the barrier electrode layer 206 . The main electrode layer 207 contains a conductive material having a resistance value smaller than that of the barrier electrode layer 206 . Main electrode layer 207 may include at least one of aluminum, copper, an aluminum alloy, or a copper alloy.

The main electrode layer 207 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy. The main electrode layer 207, in this form, comprises an aluminum-silicon-copper alloy.

Outer gate fingers 117 of main surface gate electrode layer 115 enter gate contact hole 202 from above interlayer insulating layer 201 . The outer gate finger 117 is electrically connected to the gate wiring layer 150 within the gate contact hole 202 . Thereby, an electrical signal from gate pad 116 is transmitted to gate electrode layer 149 through outer gate finger 117 .

Source pad 122 of main surface source electrode layer 121 enters source contact hole 203 and source sub-trench 168 from above interlayer insulating layer 201 . Source pad 122 is electrically connected to source region 163 , contact region 164 and source electrode layer 157 in source contact hole 203 and source sub-trench 168 .

Source electrode layer 157 may be formed using a partial region of source pad 122 . The source electrode layer 157 may be formed by a portion of the source pad 122 extending into each source trench 155 .

Source lead-out wiring 123 in main surface source electrode layer 121 enters diode contact hole 204 from above interlayer insulating layer 201 . The source lead-out wiring 123 is electrically connected to the diode region 181 inside the diode contact hole 204 .

Source connection portion 124 of main-surface source electrode layer 121 extends from active region 111 across sidewall 192 to outer region 112 . Source connection 124 forms part of an overlying structure covering sidewall 192 .

The passivation layer 125 described above is formed on the interlayer insulating layer 201 . Passivation layer 125 is formed in a film shape along interlayer insulating layer 201 . Passivation layer 125 selectively covers active region 111 and outer region 112 via interlayer insulating layer 201 .

Passivation layer 125 extends from active region 111 across sidewall 192 to outer region 112 . Passivation layer 125 forms part of the overlying structure covering sidewall 192 .

Referring to FIG. 22, passivation layer 125 extends into anchor hole 205 from above interlayer insulating layer 201 in outer region 112 . Passivation layer 125 is connected to first main surface 103 (outer main surface 172 ) of SiC semiconductor layer 102 in anchor hole 205 . A recess 211 is formed along the anchor hole 205 in a region located above the anchor hole 205 on the outer surface of the passivation layer 125 .

The resin layer 129 described above is formed on the passivation layer 125 . The resin layer 129 is formed like a film along the passivation layer 125 . Resin layer 129 selectively covers active region 111 and outer region 112 with passivation layer 125 and interlayer insulating layer 201 interposed therebetween.

Resin layer 129 extends from active region 111 across sidewall 192 to outer region 112 . The resin layer 129 forms part of the upper structure covering the sidewall 192 .

Referring to FIG. 22, resin layer 129 has an anchor portion that enters recess 211 of passivation layer 125 in outer region 112 . Thus, an anchor structure is formed in the outer region 112 to increase the connection strength of the resin layer 129 .

The anchor structure includes an uneven structure formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112 . The uneven structure (anchor structure) more specifically includes unevenness formed using the interlayer insulating layer 201 covering the outer main surface 172 . More specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in the interlayer insulating layer 201 .

The resin layer 129 meshes with this anchor hole 205 . The resin layer 129 meshes with the anchor hole 205 via the passivation layer 125 in this form. As a result, the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102 can be increased, so that peeling of the resin layer 129 can be suppressed.

As described above, SiC semiconductor device 101 can also achieve the same effects as those described for SiC semiconductor device 1 . According to SiC semiconductor device 101 , second main surface 104 of SiC semiconductor layer 102 extends from the boundary region (pn junction) between SiC semiconductor layer 102 and deep well region 165 to the bottom wall of gate trench 142 . The depletion layer can extend toward the region on the side.

Thereby, the current path of the short-circuit current flowing between the main surface source electrode layer 121 and the drain electrode layer 133 can be narrowed. Further, the depletion layer extending from the boundary region between the SiC semiconductor layer 102 and the deep well region 165 can reduce the feedback capacitance Crss inversely. Therefore, it is possible to provide the SiC semiconductor device 101 capable of improving the short-circuit resistance and reducing the feedback capacitance Crss.

A depletion layer extending from a boundary region (pn junction) between SiC semiconductor layer 102 and deep well region 165 may overlap the bottom wall of gate trench 142 . In this case, the depletion layer extending from the bottom of deep well region 165 may overlap the bottom wall of gate trench 142 .

Further, according to the SiC semiconductor device 101, the region occupied by the depletion layer in the SiC semiconductor layer 102 can be increased, so the feedback capacitance Crss can be reduced in inverse proportion. A feedback capacitance Crss is a capacitance between the gate electrode layer 149 and the drain electrode layer 133 .

Further, according to SiC semiconductor device 101, the distance between the bottom of each deep well region 165 and second main surface 104 of SiC semiconductor layer 102 is substantially constant. This can suppress variation in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 .

Therefore, the breakdown voltage (for example, breakdown resistance) of SiC semiconductor layer 102 can be suppressed from being restricted by the form of deep well region 165, so that the breakdown voltage can be appropriately improved.

Further, according to SiC semiconductor device 101 , diode region 181 is formed in outer region 112 . Diode region 181 is electrically connected to main surface source electrode layer 121 . Thereby, the avalanche current generated in outer region 112 can flow into main surface source electrode layer 121 via diode region 181 .

That is, the avalanche current generated in outer region 112 can be absorbed by diode region 181 and main surface source electrode layer 121 . As a result, it is possible to improve the stability of the operation of the MISFET.

Further, according to SiC semiconductor device 101 , outer deep well region 182 is formed in outer region 112 . Thereby, the breakdown voltage of the SiC semiconductor layer 102 can be adjusted in the outer region 112 .

In particular, according to SiC semiconductor device 101 , outer deep well region 182 is formed at a depth position substantially equal to deep well region 165 . More specifically, the bottom of outer deep well region 182 is substantially flush with the bottom of deep well region 165 .

The distance between the bottom of outer deep well region 182 and second major surface 104 of SiC semiconductor layer 102 is approximately equal to the distance between the bottom of deep well region 165 and second major surface 104 of SiC semiconductor layer 102 .

This reduces the distance between the bottom of outer deep well region 182 and second main surface 104 of SiC semiconductor layer 102 and the distance between the bottom of deep well region 165 and second main surface 104 of SiC semiconductor layer 102 . In between, it is possible to suppress the occurrence of variations.

Therefore, it is possible to prevent the breakdown voltage (for example, breakdown resistance) of SiC semiconductor layer 102 from being restricted by the form of outer deep well region 182 and the form of deep well region 165 . As a result, it is possible to appropriately improve the breakdown voltage.

In particular, in SiC semiconductor device 101 , outer region 112 is formed in a region on the second main surface 104 side of SiC semiconductor layer 102 with respect to active region 111 . Thereby, the position of the bottom of the outer deep well region 182 can be appropriately brought closer to the position of the bottom of the deep well region 165 .

That is, when forming outer deep well region 182 , it is not necessary to introduce a p-type impurity into a relatively deep position in the surface layer portion of first main surface 103 of SiC semiconductor layer 102 . Therefore, it is possible to appropriately prevent the position of the bottom of the outer deep well region 182 from greatly deviating from the position of the bottom of the deep well region 165 .

Moreover, in SiC semiconductor device 101 , outer main surface 172 of outer region 112 is positioned substantially flush with the bottom wall of source trench 155 . Thus, when p-type impurities are introduced into the bottom wall of source trench 155 and outer main surface 172 of outer region 112 with equal energy, deep well region 165 and outer deep well region 182 are positioned at approximately equal depths. can be formed to

As a result, it is possible to more appropriately prevent the position of the bottom of the outer deep well region 182 from greatly deviating from the position of the bottom of the deep well region 165 .

Further, according to SiC semiconductor device 101 , field limit structure 183 is formed in outer region 112 . Thereby, in the outer region 112, an electric field relaxation effect by the field limit structure 183 can be obtained. Therefore, the breakdown resistance of the SiC semiconductor layer 102 can be appropriately improved.

Further, according to the SiC semiconductor device 101 , the active region 111 is formed as a plateau-shaped active plateau 173 . Active plateau 173 includes active sidewalls 174 that connect active major surface 171 of active area 111 and outer major surface 172 of outer area 112 .

In the region between the active main surface 171 and the outer main surface 172, a step relief structure is formed to reduce the step between the active main surface 171 and the outer main surface 172. FIG. The step relief structure includes sidewalls 192 .

Thereby, the step between the active main surface 171 and the outer main surface 172 can be moderated appropriately. Therefore, the flatness of the upper layer structure formed on the sidewall 192 can be appropriately improved. In SiC semiconductor device 101, interlayer insulating layer 201, main surface source electrode layer 121, passivation layer 125 and resin layer 129 are formed as an example of an upper layer structure.

Further, according to SiC semiconductor device 101 , an anchor structure is formed in outer region 112 to increase the connection strength of resin layer 129 . The anchor structure includes an uneven structure formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112 .

The uneven structure (anchor structure) more specifically includes unevenness formed using interlayer insulating layer 201 formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112 . More specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in the interlayer insulating layer 201 .

The resin layer 129 meshes with this anchor hole 205 . The resin layer 129 meshes with the anchor hole 205 via the passivation layer 125 in this form. As a result, the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102 can be increased, so that peeling of the resin layer 129 can be suppressed appropriately.

Further, according to the SiC semiconductor device 101, the trench gate structure 161 is formed in which the gate electrode layer 149 is embedded in the gate trench 142 with the gate insulating layer 148 interposed therebetween. In this trench gate structure 161 , the gate electrode layer 149 is covered with a low resistance electrode layer 167 in the limited space of the gate trench 142 . According to such a structure, it is possible to obtain the effects described with reference to FIG. 24 .

FIG. 24 is a graph for explaining the sheet resistance within the gate trench 142. As shown in FIG. In FIG. 24, the vertical axis represents sheet resistance [Ω/□], and the horizontal axis represents items. FIG. 24 shows a first bar graph BL1, a second bar graph BL2 and a third bar graph BL3.

A first bar graph BL1 represents the sheet resistance in the gate trench 142 filled with n-type polysilicon. A second bar graph BL2 represents the sheet resistance in the gate trench 142 filled with p-type polysilicon.

A third bar graph BL3 represents the sheet resistance in the gate trench 142 in which the gate electrode layer 149 (p-type polysilicon) and the low resistance electrode layer 167 are buried. Here, the case where the low-resistance electrode layer 167 made of TiSi ₂ (p-type titanium silicide) as an example of polycide (silicide) is formed will be described.

Referring to the first bar graph BL1, the sheet resistance in the gate trench 142 filled with n-type polysilicon was 10Ω/□. Referring to the second bar graph BL2, the sheet resistance in the gate trench 142 filled with p-type polysilicon was 200Ω/□. Referring to the third bar graph BL3, the sheet resistance within the gate trench 142 in which the gate electrode layer 149 (p-type polysilicon) and the low-resistance electrode layer 167 were buried was 2Ω/□.

P-type polysilicon has a different work function than n-type polysilicon. According to the structure in which the p-type polysilicon is buried in the gate trench 142, the gate threshold voltage Vth can be increased by about 1V.

However, p-type polysilicon has a sheet resistance that is several tens of times (here, 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material of gate electrode layer 149, the energy loss remarkably increases as the parasitic resistance in gate trench 142 (hereinafter simply referred to as "gate resistance") increases.

On the other hand, according to the structure having the low-resistance electrode layer 167 on the gate electrode layer 149 (p-type polysilicon), the sheet resistance is reduced by 100 times compared to the case where the low-resistance electrode layer 167 is not formed. can be lowered to 1 or less. That is, according to the structure having the low-resistance electrode layer 167, the sheet resistance can be reduced to one-fifth or less of that of the gate electrode layer 149 containing n-type polysilicon.

Thus, according to the structure having the low-resistance electrode layer 167, the sheet resistance in the gate trench 142 can be reduced while increasing the gate threshold voltage Vth (for example, increasing by about 1V). As a result, the gate resistance can be reduced, and the current can be efficiently diffused along the trench gate structure 161 . As a result, the switching delay can be shortened.

Further, according to the structure having the low resistance electrode layer 167, it is not necessary to increase the p-type impurity concentration of the body region 141 and the p-type impurity concentration of the contact region 164. FIG. Therefore, it is possible to appropriately increase the gate threshold voltage Vth while suppressing an increase in channel resistance.

The low resistance electrode layer 167 may include at _least one of TiSi, TiSi2, NiSi, _CoSi , CoSi2, _MoSi2 or _WSi2 . In particular, NiSi, CoSi ₂ and TiSi ₂ among these species are suitable as the polycide layer forming the low-resistance electrode layer 167 because of their relatively low resistivity and temperature dependence.

As a result of further verification by the inventors of the present application, when TiSi ₂ was adopted as the material of the low-resistance electrode layer 167, an increase in leakage current between the gate and source was observed when a low electric field was applied. On the other hand, when CoSi ₂ was used, no increase in leakage current between the gate and source was observed when a low electric field was applied. Considering this point, CoSi ₂ is most preferable as the polycide layer forming the low-resistance electrode layer 167 .

Furthermore, according to the SiC semiconductor device 101 , the gate wiring layer 150 is covered with the low resistance electrode layer 167 . Thereby, the gate resistance in the gate wiring layer 150 can be reduced.

In particular, in the structure in which the gate electrode layer 149 and the gate wiring layer 150 are covered with the low-resistance electrode layer 167, current can be efficiently diffused along the trench gate structure 161. FIG. Therefore, it is possible to appropriately shorten the switching delay.

FIG. 25 is an enlarged view of a region corresponding to FIG. 18, showing a SiC semiconductor device 221 according to the fourth embodiment of the present invention. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 25. FIG. Hereinafter, structures corresponding to the structures described for SiC semiconductor device 101 are denoted by the same reference numerals, and descriptions thereof are omitted.

25 and 26 , SiC semiconductor device 221 includes an outer gate trench 222 formed in first main surface 103 of SiC semiconductor layer 102 in active region 111 . The outer gate trenches 222 extend in strips along the periphery of the active region 111 .

Outer gate trenches 222 are formed in regions immediately below outer gate fingers 117 on first main surface 103 of SiC semiconductor layer 102 . Outer gate trenches 222 extend along outer gate fingers 117 .

More specifically, outer gate trench 222 is formed along three sides 105A, 105B, 105D of SiC semiconductor layer 102 so as to partition the inner region of active region 111 from three directions. Outer gate trench 222 may be formed in an endless shape (for example, a square annular shape) surrounding the inner region of active region 111 .

The outer gate trench 222 communicates with the contact trench portion 144 of each gate trench 142 . Thus, the outer gate trench 222 and the gate trench 142 are formed by one trench.

A gate wiring layer 150 is embedded in the outer gate trench 222 . The gate wiring layer 150 is connected to the gate electrode layer 149 at the communicating portion between the gate trench 142 and the outer gate trench 222 .

A low resistance electrode layer 167 covering the gate wiring layer 150 is formed in the outer gate trench 222 . In this case, the low-resistance electrode layer 167 covering the gate electrode layer 149 and the low-resistance electrode layer 167 covering the gate wiring layer 150 are located in one trench.

As described above, the SiC semiconductor device 221 can also achieve the same effects as those described for the SiC semiconductor device 101 . Moreover, according to the SiC semiconductor device 221 , it is not necessary to extend the gate wiring layer 150 onto the first main surface 103 of the SiC semiconductor layer 102 .

This can prevent the gate wiring layer 150 from facing the SiC semiconductor layer 102 across the gate insulating layer 148 at the opening edge portion 146 of the gate trench 142 (the outer gate trench 222). As a result, electric field concentration at the opening edge portion 146 of the gate trench 142 (the outer gate trench 222) can be suppressed.

FIG. 27 is an enlarged view of a region corresponding to FIG. 21, showing a SiC semiconductor device 231 according to the fifth embodiment of the present invention. Hereinafter, structures corresponding to the structures described for SiC semiconductor device 101 are denoted by the same reference numerals, and descriptions thereof are omitted.

27, SiC epitaxial layer 107 in this embodiment includes high concentration region 108, low concentration region 109, and concentration gradient region 232 interposed between high concentration region 108 and low concentration region 109. Referring to FIG.

Gradient concentration region 232 is also formed in outer region 112 in addition to active region 111 in SiC epitaxial layer 107 . Gradient concentration region 232 is formed throughout SiC epitaxial layer 107 .

The concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually decreases from the high concentration region 108 toward the low concentration region 109 . In other words, the concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually increases from the low concentration region 109 toward the high concentration region 108 . Gradient concentration region 232 suppresses rapid fluctuations in the n-type impurity concentration in the region between high concentration region 108 and low concentration region 109 .

When SiC epitaxial layer 107 includes concentration gradient region 232 , the n-type impurity concentration of high-concentration region 108 is preferably 1.5 to 5 times the n-type impurity concentration of low-concentration region 109 . The n-type impurity concentration of the high concentration region 108 may be 3 times or more and 5 times or less of the n-type impurity concentration of the low concentration region 109 .

The thickness of the concentration gradient region 232 may be 0.5 μm or more and 2.0 μm or less. The thickness of the concentration gradient region 232 may be 0.5 μm to 1.0 μm, 1.0 μm to 1.5 μm, or 1.5 μm to 2.0 μm.

Although detailed description is omitted, the aforementioned gate trench 142 , source trench 155 , deep well region 165 , outer deep well region 182 , etc. are formed in the high concentration region 108 .

That is, the gate trench 142 , the source trench 155 , the deep well region 165 , the outer deep well region 182 , etc. described above are located on the first main surface 103 with respect to the boundary region between the high-concentration region 108 and the gradient concentration region 232 in the SiC semiconductor layer 102 . formed in the side area.

As described above, the SiC semiconductor device 231 can also achieve the same effects as those described for the SiC semiconductor device 101 .

FIG. 28 is an enlarged view of a region corresponding to FIG. 18, showing a SiC semiconductor device 241 according to the sixth embodiment of the present invention. Hereinafter, structures corresponding to the structures described for SiC semiconductor device 101 are denoted by the same reference numerals, and descriptions thereof are omitted.

Referring to FIG. 28, gate trench 142 is formed in a lattice shape in plan view in this embodiment. Gate trenches 142 more specifically include a plurality of first gate trenches 242 and a plurality of second gate trenches 243 . The plurality of first gate trenches 242 and the plurality of second gate trenches 243 form the active trench portion 143 .

The plurality of first gate trenches 242 are spaced apart in the second direction Y and formed in strips extending along the first direction X, respectively. The plurality of first gate trenches 242 are formed in a stripe shape as a whole in plan view.

The sidewalls forming the long sides of each first gate trench 242 are formed by the a-plane of SiC single crystal. The sidewalls forming the short sides of each first gate trench 242 are formed by the m-plane of SiC single crystal.

The plurality of second gate trenches 243 are formed in the first direction X at intervals and each formed in a band shape extending along the second direction Y. As shown in FIG. The plurality of second gate trenches 243 are formed in a stripe shape as a whole in plan view.

The sidewalls forming the long sides of each second gate trench 243 are formed by the m-plane of SiC single crystal. The sidewalls forming the short sides of each second gate trench 243 are formed by the a-plane of SiC single crystal.

The plurality of first gate trenches 242 and the plurality of second gate trenches 243 cross each other. As a result, one gate trench 142 having a lattice shape in plan view is formed. A plurality of cell regions 244 are defined in the region surrounded by the gate trenches 142 .

The plurality of cell regions 244 are arranged in a matrix at intervals in the first direction X and the second direction Y in plan view. The plurality of cell regions 244 are formed in a square shape in plan view. Body region 141 is exposed from the sidewall of gate trench 142 in each cell region 244 . Body region 141 is exposed from sidewalls formed by the SiC single crystal m-plane and a-plane in gate trench 142 .

Of course, the gate trench 142 may be formed in a honeycomb shape as one aspect of the lattice shape in plan view. In this case, the plurality of cell regions 244 may be arranged in a zigzag pattern at intervals in the first direction X and the second direction Y. FIG. Also, in this case, the plurality of cell regions 244 may be formed in a hexagonal shape in plan view.

Each source trench 155 is formed in the center of each cell region 244 in plan view. Each source trench 155 is formed in a pattern that one appears on a cut surface that appears when each cell region 244 is cut along the first direction X. As shown in FIG. In addition, each source trench 155 is formed in a pattern that one appears on a cut surface that appears when each cell region 244 is cut along the second direction Y. As shown in FIG.

More specifically, each source trench 155 is formed in a square shape in plan view. The four sidewalls of each source trench 155 are formed by m-plane and a-plane of SiC single crystal.

The planar shape of each source trench 155 is arbitrary. Each source trench 155 may be formed in a polygonal shape such as a triangular shape, a pentagonal shape, a hexagonal shape, a circular shape, or an elliptical shape in plan view.

A cross-sectional view along line XIX-XIX in FIG. 28 corresponds to the cross-sectional view shown in FIG. A cross-sectional view taken along line XX-XX in FIG. 28 corresponds to the cross-sectional view shown in FIG.

As described above, the SiC semiconductor device 241 can also achieve the same effects as those described for the SiC semiconductor device 101 .

While embodiments of the invention have been described, embodiments of the invention may also be embodied in other forms.

In each of the above-described embodiments, side surfaces 5A, 105A and side surfaces 5C, 105C of SiC semiconductor layers 2, 102 face the a-plane of the SiC single crystal, and side surfaces 5B, 105B and side surfaces 5D, 105D face the m-plane of the SiC single crystal. The form facing the However, a configuration may be adopted in which side surfaces 5A, 105A and side surfaces 5C, 105C face the m-plane of the SiC single crystal, and side surfaces 5B, 105B and side surfaces 5D, 105D face the a-plane of the SiC single crystal.

In each of the above-described embodiments, an example in which continuously extending belt-shaped reforming lines 22A to 22D are formed has been described. However, in each of the above-described embodiments, the reforming lines 22A to 22D in the form of dashed strips (broken lines) may be formed. In other words, the reforming lines 22A to 22D may be formed in strips extending intermittently. In this case, one, two or three of the reforming lines 22A to 22D may be formed in broken-line strips, and the rest may be formed in strips.

In the above-described third to sixth embodiments, examples were described in which a plurality of gate trenches 142 (first gate trenches 242) extending along the m-axis direction ([1-100] direction) of the SiC single crystal were formed. .

However, a plurality of gate trenches 142 (first gate trenches 242) extending along the a-axis direction ([11-20] direction) of the SiC single crystal may be formed. In this case, a plurality of source trenches 155 are formed extending along the a-axis direction ([11-20] direction) of the SiC single crystal.

In the above-described third to sixth embodiments, examples in which the source electrode layer 157 is embedded in the source trench 155 with the source insulating layer 156 interposed therebetween have been described. However, the source electrode layer 157 may be directly embedded in the source trench 155 without the source insulating layer 156 interposed therebetween.

In the above-described third to sixth embodiments, the example in which the source insulating layer 156 is formed along the sidewall and bottom wall of the source trench 155 has been described.

However, the source insulating layer 156 may be formed along the sidewalls of the source trenches 155 so as to expose the bottom walls of the source trenches 155 . Source insulating layer 156 may be formed along the sidewalls and bottom wall of source trench 155 so as to expose a portion of the bottom wall of source trench 155 .

Also, the source insulating layer 156 may be formed along the bottom wall of the source trench 155 so as to expose the sidewall of the source trench 155 . Source insulating layer 156 may be formed along the sidewall and bottom wall of source trench 155 so as to expose a portion of the sidewall of source trench 155 .

In the above-described third to sixth embodiments, examples were described in which the gate electrode layer 149 and the gate wiring layer 150 containing p-type polysilicon doped with p-type impurities were formed. However, if the increase in gate threshold voltage Vth is not important, gate electrode layer 149 and gate interconnection layer 150 may be formed of n-type polysilicon doped with n-type impurities instead of or in addition to p-type polysilicon. may contain

In this case, the low-resistance electrode layer 167 may be formed by siliciding a portion of the gate electrode layer 149 (n-type polysilicon) that forms the surface layer with a metal material. That is, the low-resistance electrode layer 167 may contain n-type polycide. With such a structure, the gate resistance can be reduced.

In the third to sixth embodiments described above, a p ⁺ -type SiC semiconductor substrate (106) may be employed instead of the n ⁺ -type SiC semiconductor substrate 106. FIG. According to this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of the MISFET. In this case, in each of the above-described embodiments, the "source" of the MISFET is read as the "emitter" of the IGBT, and the "drain" of the MISFET is read as the "collector" of the IGBT.

In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be employed. That is, the p-type portion may be n-type, and the n-type portion may be p-type.

Each of the above embodiments can also be applied to a semiconductor device using a semiconductor material different from SiC. The semiconductor material different from SiC may be a compound semiconductor material. The compound semiconductor material may be either or both of gallium nitride (GaN) and gallium oxide (Ga ₂ O ₃ ).

For example, the third to sixth embodiments described above may be compound semiconductor devices including vertical compound semiconductor MISFETs employing compound semiconductor materials instead of SiC. In compound semiconductors, magnesium may be employed as a p-type impurity (acceptor). Also, germanium (Ge), oxygen (O), or silicon (Si) may be employed as the n-type impurity (donor).

Examples of features extracted from this specification and drawings are shown below.

[A1] Containing a SiC single crystal, having a first main surface as an element forming surface, a second main surface opposite to the first main surface, and a side surface connecting the first main surface and the second main surface a SiC semiconductor layer; an insulating layer that includes an insulating material, covers the first main surface of the SiC semiconductor layer, and has an insulating side surface that is flush with the side surface of the SiC semiconductor layer; A SiC semiconductor device, comprising: an electrode formed on a layer; and a modified layer formed on the side surface of the SiC semiconductor layer and modified to have properties different from those of the SiC single crystal.

According to this SiC semiconductor device, in the structure in which the modified layer is formed on the side surface of the SiC semiconductor layer, the insulating layer can increase the insulation between the side surface of the SiC semiconductor layer and the electrode. Thereby, the stability of the electrical characteristics of the SiC semiconductor layer can be enhanced.

[A2] The SiC semiconductor device according to A1, wherein the modified layer is formed at a middle portion in the thickness direction of the SiC semiconductor layer spaced apart from the insulating layer.

[A3] The SiC semiconductor layer includes a SiC semiconductor substrate and a SiC epitaxial layer, and has a laminated structure in which the first main surface is formed by the SiC epitaxial layer, and the insulating layer is the SiC epitaxial layer. The SiC semiconductor device according to A1 or A2, wherein the modified layer is formed in a region of the SiC semiconductor substrate.

[A4] The SiC semiconductor device according to A3, wherein the modified layer is formed on the SiC semiconductor substrate while avoiding the SiC epitaxial layer.

[A5] The SiC semiconductor device according to A3 or A4, wherein the SiC epitaxial layer has a thickness equal to or less than the thickness of the SiC semiconductor substrate.

[A6] According to any one of A3 to A5, the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less. SiC semiconductor device.

[B1] preparing a SiC semiconductor wafer including a SiC single crystal and having a first main surface in which a device formation region having a plurality of sides is set and a second main surface opposite to the first main surface; By irradiating the interior of the SiC semiconductor wafer with laser light along the plurality of sides of the device formation region, a plurality of modified lines modified to have properties different from those of the SiC single crystal are formed in the device formation region. Manufacture of a SiC semiconductor device, comprising the steps of: forming one layer each in a one-to-one correspondence relationship with respect to the plurality of sides of the SiC semiconductor device; and cutting the SiC semiconductor wafer along the plurality of modification lines. Method.

According to this manufacturing method, the SiC single crystal is included, and the first main surface as the element forming surface, the second main surface opposite to the first main surface, and the first main surface and the second main surface are connected. a SiC semiconductor layer having a plurality of side surfaces, one layer formed on each of the side surfaces of the SiC semiconductor layer, each extending in a strip shape along a tangential direction of the first main surface of the SiC semiconductor layer, and the SiC single A SiC semiconductor device can be manufactured and provided, including a plurality of modified lines modified to have properties different from those of the crystal.

[B2] The method for manufacturing a SiC semiconductor device according to B1, further including the step of grinding the second main surface of the SiC semiconductor wafer prior to the step of cutting the SiC semiconductor wafer.

[B3] The method for manufacturing a SiC semiconductor device according to B2, wherein the modifying line forming step is performed prior to the grinding step.

[B4] The method for manufacturing a SiC semiconductor device according to B2, wherein the modifying line forming step is performed after the grinding step.

[B5] The step of preparing the SiC semiconductor wafer includes the step of preparing the SiC semiconductor wafer having a thickness exceeding 150 μm, and the grinding step includes grinding the SiC semiconductor wafer until the SiC semiconductor wafer has a thickness of 40 μm or more and 150 μm or less. The method for manufacturing a SiC semiconductor device according to any one of B2 to B4, including a step of grinding a semiconductor wafer.

[B6] According to any one of B1 to B5, the step of forming the modification line includes a step of irradiating the interior of the SiC semiconductor wafer with a laser beam from the first main surface side of the SiC semiconductor wafer. method for manufacturing a SiC semiconductor device.

[B7] According to any one of B1 to B5, the step of forming the modified lines includes the step of irradiating the interior of the SiC semiconductor wafer with a laser beam from the second main surface side of the SiC semiconductor wafer. method for manufacturing a SiC semiconductor device.

[B8] preparing a SiC semiconductor wafer including a SiC single crystal and having a first main surface in which a device formation region having a plurality of sides is set and a second main surface opposite to the first main surface; forming an insulating layer on the first main surface of the SiC semiconductor wafer; forming an electrode on the insulating layer; A step of forming a plurality of modified layers modified to have properties different from those of the SiC single crystal by irradiating the interior of the with a laser beam, and the SiC along with the insulating layer along the plurality of modified layers and cutting a semiconductor wafer.

According to this manufacturing method, the SiC single crystal is included, and the first main surface as the element forming surface, the second main surface opposite to the first main surface, and the first main surface and the second main surface are connected. and an insulating layer containing an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface flush with the side surface of the SiC semiconductor layer. and a main surface electrode layer formed on the insulating layer, and a modified layer formed on the side surface of the SiC semiconductor layer and modified to have properties different from those of the SiC single crystal, SiC We can manufacture and provide semiconductor devices.

[B9] preparing a SiC semiconductor wafer including a SiC single crystal and having a first main surface in which a device formation region having a plurality of sides is set and a second main surface opposite to the first main surface; forming an insulating layer on the first main surface of the SiC semiconductor wafer; partially removing the insulating layer to form openings in the insulating layer to expose the plurality of sides of the device formation region; and irradiating the interior of the SiC semiconductor wafer with laser light along the plurality of sides of the device formation region, thereby forming a plurality of modified layers modified to have properties different from those of the SiC single crystal. and cutting the SiC semiconductor wafer along the plurality of modified layers.

[B10] The method for manufacturing a SiC semiconductor device according to B8 or B9, further including the step of grinding the second main surface of the SiC semiconductor wafer.

[B11] The method for manufacturing a SiC semiconductor device according to B10, wherein the modifying line forming step is performed prior to the grinding step.

[B12] The method for manufacturing a SiC semiconductor device according to B10, wherein the modifying line forming step is performed after the grinding step.

[B13] The step of preparing the SiC semiconductor wafer includes the step of preparing the SiC semiconductor wafer having a thickness exceeding 150 μm, and the grinding step includes grinding the SiC semiconductor wafer until the SiC semiconductor wafer has a thickness of 40 μm or more and 150 μm or less. The method for manufacturing a SiC semiconductor device according to any one of B10 to B12, including the step of grinding a semiconductor wafer.

[C1] It contains a SiC single crystal, and has a first main surface as an element forming surface, a second main surface opposite to the first main surface, and a side surface connecting the first main surface and the second main surface. a SiC semiconductor layer, and a space from the first main surface of the SiC semiconductor layer to the second main surface such that a surface layer portion of the first main surface of the SiC semiconductor layer is exposed from the side surface of the SiC semiconductor layer; and a plurality of modified layers formed with a gap therebetween and modified to have properties different from those of the SiC single crystal.

Since the modified layer is formed by modifying the SiC single crystal of the SiC semiconductor layer to have other properties, the modified layer tends to be a starting point of cracks. In particular, since stress tends to concentrate at corners connecting the first main surface and the side surface of the SiC semiconductor layer, cracks may occur at the corners of the SiC semiconductor layer in a structure in which the modified layer is formed at the corners of the SiC semiconductor layer. increased risk of occurrence.

According to this SiC semiconductor device, the modified layer extends from the first main surface to the second main surface of the SiC semiconductor layer so as to expose the surface layer portion of the first main surface of the SiC semiconductor layer from the side surface of the SiC semiconductor layer. formed with a gap. Therefore, it is possible to reduce the risk of cracks occurring at the corners of the SiC semiconductor layer on the first main surface side.

[C2] Containing a SiC single crystal, having a first main surface as an element forming surface, a second main surface opposite to the first main surface, and a side surface connecting the first main surface and the second main surface a SiC semiconductor layer, and a space from the second main surface of the SiC semiconductor layer to the first main surface such that a surface layer portion of the second main surface of the SiC semiconductor layer is exposed from the side surface of the SiC semiconductor layer; and a plurality of modified layers formed with a gap therebetween and modified to have properties different from those of the SiC single crystal.

Since the modified layer is formed by modifying the SiC single crystal of the SiC semiconductor layer to have other properties, the modified layer tends to be a starting point of cracks. In particular, since stress tends to concentrate at corners connecting the second main surface and the side surface of the SiC semiconductor layer, cracks may occur at the corners of the SiC semiconductor layer in a structure in which the modified layer is formed at the corners of the SiC semiconductor layer. increased risk of occurrence.

According to this SiC semiconductor device, the modified layer extends from the second main surface of the SiC semiconductor layer to the first main surface so as to expose the surface layer portion of the second main surface of the SiC semiconductor layer from the side surface of the SiC semiconductor layer. formed with a gap. Therefore, it is possible to reduce the risk of cracks occurring at the corners of the SiC semiconductor layer on the second main surface side.

The modified line is formed by modifying the SiC single crystal of the SiC semiconductor layer to another property. Therefore, considering the influence of the modified lines on the SiC semiconductor layer, it is not desirable to form a plurality of modified lines on the entire side surface of the SiC semiconductor layer. Examples of the influence on the SiC semiconductor layer caused by the modified lines include fluctuations in the electrical characteristics of the SiC semiconductor layer caused by the modified lines and the occurrence of cracks in the SiC semiconductor layer originating from the modified lines. be.

[D1] to [D20] and [E1] to [E20] below aim to provide a SiC semiconductor device capable of reducing the influence of the modification line on the SiC semiconductor layer.

[D1] A first main surface as an element formation surface, a second main surface opposite to the first main surface, and a plurality of surfaces connecting the first main surface and the second main surface, including a SiC single crystal. and a SiC semiconductor layer formed on each of the side surfaces of the SiC semiconductor layer, each extending in a strip shape along a tangential direction of the first main surface of the SiC semiconductor layer, and the SiC single crystal and and a plurality of modified lines modified to have different properties. According to this SiC semiconductor device, only one modified line is formed on each side surface of the SiC semiconductor layer. Therefore, the influence on the SiC semiconductor layer caused by the modified lines can be reduced.

[D2] The SiC semiconductor device according to D1, wherein the SiC semiconductor layer has a thickness of 40 μm or more and 200 μm or less.

[D3] The SiC semiconductor device according to D1 or D2, wherein the second main surface of the SiC semiconductor layer is a ground surface.

[D4] The SiC semiconductor device according to any one of D1 to D3, wherein each of the modified lines is formed with a gap from the first main surface to the second main surface of the SiC semiconductor layer. .

[D5] The SiC semiconductor device according to any one of D1 to D4, wherein each modification line is formed with a gap from the second main surface to the first main surface of the SiC semiconductor layer. .

[D6] The SiC semiconductor layer includes a corner connecting the two side surfaces, and the plurality of modification lines includes two modification lines connected at the corner of the SiC semiconductor layer, D1 to The SiC semiconductor device according to any one of D5.

[D7] The SiC semiconductor device according to any one of D1 to D6, wherein the plurality of modified lines are integrally formed to surround the SiC semiconductor layer.

[D8] The SiC semiconductor device according to any one of D1 to D7, wherein each modification line extends linearly or curvedly.

[D9] Each of the modified lines extends in a normal direction of the first main surface of the SiC semiconductor layer, and a plurality of modified portions facing each other in a tangential direction of the first main surface of the SiC semiconductor layer. The SiC semiconductor device according to any one of D1 to D8, comprising:

[D10] The SiC semiconductor device according to any one of D1 to D9, wherein each side surface of the SiC semiconductor layer is a cleaved surface.

[D11] The SiC semiconductor device according to any one of D1 to D10, wherein the SiC single crystal is a hexagonal crystal.

[D12] The SiC semiconductor device according to D11, wherein the SiC single crystal is a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[D13] The SiC semiconductor device according to D11 or D12, wherein the first main surface of the SiC semiconductor layer faces the c-plane of the SiC single crystal.

[D14] Any one of D11 to D13, wherein the first main surface of the SiC semiconductor layer has an off angle of 0° or more and 10° or less with respect to the c-plane of the SiC single crystal. The SiC semiconductor device according to one.

[D15] The SiC semiconductor device according to D14, wherein the off angle is 5° or less.

[D16] The SiC semiconductor device according to D14 or D15, wherein the off-angle is greater than 0° and less than 4°.

[D17] The SiC semiconductor layer includes a SiC semiconductor substrate and a SiC epitaxial layer, and has a laminated structure in which the first main surface is formed by the SiC epitaxial layer, and the modification line is the SiC semiconductor The SiC semiconductor device according to any one of D1 to D16, formed in a region on a substrate.

[D18] The SiC semiconductor device according to D17, wherein the modified line is formed in the SiC semiconductor substrate while avoiding the SiC epitaxial layer.

[D19] The SiC semiconductor device according to D17 or D18, wherein the SiC epitaxial layer has a thickness equal to or less than the thickness of the SiC semiconductor substrate.

[D20] According to any one of D17 to D19, the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less. SiC semiconductor device.

[E1] includes a SiC single crystal, and connects a first main surface as an element formation surface, a second main surface opposite to the first main surface, and the first main surface and the second main surface; A SiC semiconductor substrate having a plurality of side surfaces each consisting of a cleaved surface and forming part of the second main surface and the side surfaces, and a SiC epitaxial substrate forming part of the first main surface and the side surfaces. a SiC semiconductor layer having a laminated structure including a layer, and a layer formed on each of the side surfaces of the SiC semiconductor layer at a portion formed of the SiC semiconductor substrate with a space from the SiC epitaxial layer toward the second main surface. and a plurality of modified lines each extending in a strip shape along a tangential direction of the first main surface of the SiC semiconductor layer and modified to have properties different from those of the SiC single crystal.

[E2] The SiC semiconductor device according to E1, further including an insulating layer covering the SiC epitaxial layer on the first main surface and having an insulating sidewall continuous with each of the side surfaces.

[E3] The SiC semiconductor device according to E2, further including a first electrode formed on the insulating layer and spaced inwardly from each of the side surfaces.

[E4] The SiC semiconductor device according to E3, further including a resin layer formed on the insulating layer with an inward space from each of the side surfaces and having an opening exposing the first electrode.

[E5] The SiC semiconductor device according to any one of E1 to E4, further including a second electrode covering the entire second main surface.

[E6] The SiC semiconductor device according to any one of E1 to E5, wherein the SiC semiconductor layer has a thickness of 40 μm or more and 200 μm or less.

[E7] The SiC semiconductor device according to any one of E1 to E6, wherein the second main surface of the SiC semiconductor layer is a ground surface.

[E8] The SiC semiconductor according to any one of E1 to E7, wherein each modification line is formed with a gap from the second main surface of the SiC semiconductor layer to the first main surface side. Device.

[E9] The SiC semiconductor layer includes a corner connecting the two side surfaces, and the plurality of modification lines includes two modification lines connected at the corner of the SiC semiconductor layer, E1 to The SiC semiconductor device according to any one of E8.

[E10] The SiC semiconductor device according to any one of E1 to E9, wherein the plurality of modification lines are integrally formed so as to surround the SiC semiconductor layer.

[E11] The SiC semiconductor device according to any one of E1 to E10, wherein each modification line extends linearly or curvedly.

[E12] Each of the modified lines extends in a normal direction of the first main surface of the SiC semiconductor layer, and a plurality of modified portions facing each other in a tangential direction of the first main surface of the SiC semiconductor layer. The SiC semiconductor device according to any one of E1 to E11, comprising:

[E13] The SiC semiconductor device according to any one of E1 to E12, wherein the SiC single crystal is hexagonal.

[E14] The SiC semiconductor device according to E13, wherein the SiC single crystal is a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[E15] The SiC semiconductor device according to E13 or E14, wherein the first main surface of the SiC semiconductor layer faces the c-plane of the SiC single crystal.

[E16] Any one of E13 to E15, wherein the first main surface of the SiC semiconductor layer has an off angle of 0° or more and 10° or less with respect to the c-plane of the SiC single crystal. The SiC semiconductor device according to one.

[E17] The SiC semiconductor device according to E16, wherein the off angle is 5° or less.

[E18] The SiC semiconductor device according to E16 or E17, wherein the off-angle is greater than 0° and less than 4°.

[E19] The SiC semiconductor device according to any one of E1 to E18, wherein the SiC epitaxial layer has a thickness equal to or less than the thickness of the SiC semiconductor substrate.

[E20] According to any one of E1 to E19, the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less. SiC semiconductor device.

[F1] A SiC semiconductor having a laminated structure including a SiC semiconductor substrate and a SiC epitaxial layer, and having an element forming surface formed by the SiC epitaxial layer and a side surface formed by the SiC semiconductor substrate and the SiC epitaxial layer. a chip, and a single modified layer formed on a portion of the SiC semiconductor substrate spaced apart from the SiC epitaxial layer on the side surface and modified to have a property different from that of the SiC semiconductor substrate; SiC semiconductor device.

[F2] The SiC semiconductor device according to F1, wherein the modified layer is formed in a band shape extending along the element formation surface.

[F3] The SiC semiconductor device according to F1 or F2, wherein the side surface is a cleaved surface.

[F4] The SiC semiconductor device according to any one of F1 to F3, wherein the SiC semiconductor chip has a ground back surface formed of the SiC semiconductor substrate.

[F5] The SiC semiconductor device according to F4, wherein the modified layer is formed with a space from the back surface to the element formation surface side.

[F6] The SiC semiconductor device according to any one of F1 to F5, wherein the modified layer is formed in a strip shape extending linearly or in a strip shape extending curvedly.

[F7] Each of the modified layers of F1 to F6 is formed by an assembly of a plurality of modified portions extending in a normal direction of the element formation surface and facing each other in a tangential direction of the element formation surface. The SiC semiconductor device according to any one of the above.

[F8] The SiC semiconductor device according to any one of F1 to F7, wherein the SiC semiconductor chip is made of hexagonal crystal.

[F9] The SiC semiconductor device according to any one of F1 to F8, wherein the SiC semiconductor chip is made of 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal or 6H-SiC single crystal.

[F10] The SiC semiconductor device according to any one of F1 to F9, wherein the element formation surface faces the c-plane of the SiC single crystal.

[F11] The SiC semiconductor device according to any one of F1 to F10, wherein the element formation surface has an off angle.

[F12] The SiC semiconductor device according to F11, wherein the off-angle is greater than 0° and less than 4°.

[F13] The SiC semiconductor device according to any one of F1 to F12, wherein the SiC semiconductor chip has a thickness of 40 μm or more and 200 μm or less.

[F14] The SiC semiconductor device according to any one of F1 to F13, wherein the SiC epitaxial layer has a thickness less than the thickness of the SiC semiconductor substrate.

[F15] According to any one of F1 to F14, the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less. SiC semiconductor device.

[F16] The SiC semiconductor device according to any one of F1 to F15, further including an insulating layer formed on the element formation surface, and an electrode formed on the insulating layer.

[F17] The SiC semiconductor device according to F16, wherein the electrode is formed on the insulating layer with a space from the side surface.

[F18] The SiC semiconductor device according to F16 or F17, wherein the insulating layer has an insulating side surface continuous with the side surface.

[F19] The SiC semiconductor device according to any one of F16 to F18, further including a passivation layer covering the electrode and a resin layer covering the passivation layer.

[F20] a SiC semiconductor chip having a first principal surface as an element formation surface, a second principal surface opposite to the first principal surface, and side surfaces; a first conductivity type first impurity region formed in a surface layer portion of the first main surface; and a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the first impurity region; A first conductivity type conductive layer formed in a region on the second main surface side with respect to the first impurity region so as to be exposed from the main surface and the side surfaces and electrically connected to the first impurity region. A second impurity region and a single modification formed on the side surface at a portion where the second impurity region is exposed at a distance from the first impurity region and modified to have a property different from that of the SiC semiconductor chip. A SiC semiconductor device, comprising: a layer;

This specification does not limit any combination of features shown in the first to sixth embodiments. The first to sixth embodiments can be combined in any manner and in any form among them. In other words, a form in which the features shown in the first to sixth embodiments are combined in any aspect and any form may be employed.

In addition, various design changes can be made within the scope of the matters described in the claims.

1 SiC semiconductor device 2 SiC semiconductor layer 3 First main surface of SiC semiconductor layer 4 Second main surface of SiC semiconductor layer 5A Side surface 5B of SiC semiconductor layer Side surface 5C of SiC semiconductor layer Side surface 5D of SiC semiconductor layer 6 SiC semiconductor substrate 7 SiC epitaxial layer 22A Modified line 22B Modified line 22C Modified line 22D Modified line 28 a-plane modified portion (modified portion)
29 m surface reforming section (reforming section)
81 SiC semiconductor device 101 SiC semiconductor device 102 SiC semiconductor layer 103 SiC semiconductor layer first main surface 104 SiC semiconductor layer second main surface 105A SiC semiconductor layer side surface 105B SiC semiconductor layer side surface 105C SiC semiconductor layer side surface 105D SiC Side surface 106 of semiconductor layer SiC semiconductor substrate 107 SiC epitaxial layer θ Off angle Z Normal direction X First direction (m-axis direction)
Y second direction (a-axis direction)

Claims (20)

a SiC semiconductor chip having a laminated structure including a SiC semiconductor substrate and a SiC epitaxial layer, and having an element forming surface formed by the SiC epitaxial layer and a side surface formed by the SiC semiconductor substrate and the SiC epitaxial layer;
a single modified layer formed in a portion of the SiC semiconductor substrate on the side surface at a distance from the SiC epitaxial layer and modified to have properties different from those of the SiC semiconductor substrate. . 2. The SiC semiconductor device according to claim 1, wherein said modified layer is formed in a band shape extending along said element formation surface. 3. The SiC semiconductor device according to claim 1, wherein said side surface is a cleaved surface. 4. The SiC semiconductor device according to claim 1, wherein said SiC semiconductor chip has a back surface which is a ground surface formed by said SiC semiconductor substrate. 5. The SiC semiconductor device according to claim 4, wherein said modified layer is formed with a space from said rear surface to said element formation surface side. The SiC semiconductor device according to any one of claims 1 to 5, wherein said modified layer is formed in a strip shape extending linearly or in a strip shape extending curvedly. 7. The modified layer according to any one of claims 1 to 6, wherein the modified layer is formed by an assembly of a plurality of modified portions extending in a normal direction of the element formation surface and facing each other in a tangential direction of the element formation surface. The SiC semiconductor device according to claim 1. The SiC semiconductor device according to any one of claims 1 to 7, wherein said SiC semiconductor chip is made of hexagonal crystal. 9. The SiC semiconductor device according to claim 1, wherein said SiC semiconductor chip is made of 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal or 6H-SiC single crystal. The SiC semiconductor device according to any one of claims 1 to 9, wherein said element formation surface faces a c-plane of a SiC single crystal. The SiC semiconductor device according to any one of claims 1 to 10, wherein said element formation surface has an off angle. 12. The SiC semiconductor device according to claim 11, wherein said off angle is more than 0[deg.] and less than 4[deg.]. The SiC semiconductor device according to any one of claims 1 to 12, wherein said SiC semiconductor chip has a thickness of 40 µm or more and 200 µm or less. The SiC semiconductor device according to claim 1, wherein said SiC epitaxial layer has a thickness less than the thickness of said SiC semiconductor substrate. The SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less,
The SiC semiconductor device according to claim 1, wherein said SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less. an insulating layer formed on the element formation surface;
The SiC semiconductor device according to any one of claims 1 to 15, further comprising an electrode formed on said insulating layer. 17. The SiC semiconductor device according to claim 16, wherein said electrode is formed on said insulating layer spaced from said side surface. 18. The SiC semiconductor device according to claim 16, wherein said insulating layer has an insulating side surface continuous with said side surface. a passivation layer covering the electrode;
19. The SiC semiconductor device according to claim 16, further comprising a resin layer covering said passivation layer. a SiC semiconductor chip having a first main surface as an element forming surface, a second main surface opposite to the first main surface, and side surfaces;
a first conductivity type first impurity region formed in a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface;
has a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the first impurity region, is exposed from the second main surface and the side surfaces, and is electrically connected to the first impurity region; a second impurity region of a first conductivity type formed in a region on the second main surface side with respect to the first impurity region, and
a single modified layer formed on the side surface where the second impurity region is exposed at a distance from the first impurity region and modified to have a property different from that of the SiC semiconductor chip; SiC semiconductor device.

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