JP2021152811A - Memory control device - Google Patents

Abstract

To reduce waiting time for main access from a host and enable read-ahead without degrading performance.SOLUTION: A control circuit reads data from a memory in response to a read instruction from a host and transmits the data to the host that originates instructions. The control circuit comprises: an access control unit that has a function of controlling access to the memory to perform read-ahead to a continuous address of the read instruction following the read instruction from the host even if there is no read instruction from the host; a read-ahead recording unit that records a value and address read ahead by the access control unit; and an address comparison unit that compares the address of the read instruction with the address recorded in the read-ahead recording unit. To perform the read-ahead, the access control unit repeats the access with a size smaller than the read instruction, and stops the read-ahead and accesses the address of the read instruction from the host if receiving from the host the read instruction that is in a discontinuous address of the read instruction during the read-ahead.SELECTED DRAWING: Figure 1

Description

The present invention relates to a memory control device.

Conventionally, a Flash ROM or the like has been used as a recording device for storing programs and data, but since the transfer speed of the recording device is slower than the execution speed of the CPU, it may become a performance bottleneck. Therefore, various measures have been considered for a long time to hide the transfer speed of the recording device, and a technology of predicting the data to be accessed next, pre-reading it, and storing it in a cache memory or the like is common. Is known for.

For example, in Patent Document 1, the data size of one read request is recorded in a control circuit that reads data from a recording device and transmits the data to the command source host in response to a read command from the host. A technique for suppressing unnecessary pre-reading by pre-reading the data size is disclosed.

Japanese Unexamined Patent Publication No. 2015-06945

However, in the prior art disclosed in the above-mentioned patent document, when a new read instruction is issued from the host during read-ahead from the recording device, the main access from the host is waited until the read-ahead access is completed. There is a risk of performance degradation.

Therefore, an object of the present invention is to reduce the waiting time for main access from the host and to enable pre-reading without deteriorating the performance.

In order to solve the above problems, the memory control device of the present invention is a control circuit that reads data from a recording device and transmits the data to the instruction source host in response to a read command from the host. An access control unit that controls access to the device and has a function of pre-reading the continuous address of the read instruction even if there is no read instruction from the host following the read instruction from the host, and the access control. The read-ahead recording unit that records the pre-read value and the address, and the address comparison unit that compares the address of the read instruction with the address recorded in the pre-reading recording unit, and the pre-reading performed by the access control unit is performed by the access control unit. If access is repeated with a size smaller than the read instruction and a read instruction with an address discontinuous from the read instruction is received from the host during read-ahead, the read-ahead is stopped and the address of the read instruction from the host is accessed. I made it.

According to the present invention, it is possible to reduce the waiting time for main access from the host and perform look-ahead without degrading the performance.

It is a block diagram of the control apparatus equipped with the memory controller in Example 1. FIG. It is a flowchart of the control apparatus equipped with the memory controller in Example 1. FIG. It is a flowchart of the control device equipped with the memory controller in Example 2. FIG. 5 is a timing chart of a control device equipped with a memory controller according to the first embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, the control device equipped with the memory controller according to the first embodiment of the present invention will be described with reference to FIG. The CPU 100 is a general CPU and has a function of executing a program recorded in the ROM 103. Reference numeral 101 denotes a general bus, and the CPU 100 has a function of exchanging information with the memory controller 102 via the bus 101.

Reference numeral 102 denotes a memory controller, which has a function of reading and writing data to and from the ROM 103, and is composed of an access control unit 1020, an address comparison unit 1021, and a look-ahead recording unit 1022. The access control unit 1020 has a function of transferring data according to the transfer protocol of the ROM 103. It also has a function of pre-reading from the ROM 103 even if there is no access request from the CPU 100 and storing the pre-read data in the pre-reading recording unit 1022.

The address comparison unit 1021 determines whether or not the address of the access request destination from the CPU 100 is already stored in the look-ahead recording unit 1022. If it is stored, it has a function of reading data from the look-ahead recording unit 1022 and returning the data to the CPU 100, and if it is not stored, it has a function of returning the data read from the ROM 103 to the CPU 100 via the access control unit 1020.

The look-ahead recording unit 1022 has a function of storing the look-ahead data and its address, and is composed of SRAM or the like, but is not limited thereto. The ROM 103 has a function of storing programs and data. Here, in this embodiment, a ROM capable of efficiently performing READ access to consecutive addresses is assumed, and a SerialNORFlashROM (hereinafter referred to as SROM) or the like is applicable. Efficient means that when READ access is normally performed to the SROM, when a command / address is issued, the data is read out after a predetermined cycle. However, when continuously accessing consecutive addresses, the data of the incremented address is read only by supplying the clock, so that the issuance of commands / addresses can be omitted and efficient access becomes possible.

Although not explicitly shown in FIG. 1, the host module that accesses the ROM 103 may exist other than the CPU 100, and a plurality of host modules can be accessed by the control of the bus 101.

Next, with reference to the flowchart of FIG. 2, an example of reducing the waiting time of the main access from the host and performing look-ahead without deteriorating the performance according to the first embodiment will be described. First, in step S201, the CPU 100 issues a READ access request to the ROM 103. Next, in step S202, the address comparison unit 1021 that has received the access request determines whether or not the data has already been recorded by the look-ahead recording unit 1022 by comparing the access destination addresses. If there is no data in the look-ahead recording unit 1022, the process proceeds to step S203, and if there is data, the process proceeds to step S204.

Next, in step S203, the access control unit 1020 performs data READ from the ROM 103 and returns the READ data to the CPU 100. If the data exists in the look-ahead recording unit 1022, in step S204, the address comparison unit 1021 READs the data from the look-ahead recording unit 1022, returns the READ data to the CPU 100, and ends the process.

Next, in step S205, it is determined whether or not there is the next access request. The determination method may be such that the address comparison unit 1021 can receive a plurality of access requests, or after returning the READ data to the CPU 100, waits for several cycles to determine whether or not there is a next request. It is not limited to that. If it is determined that there is a next access request, the process returns to step S202, and it is determined whether or not there is data in the look-ahead recording unit. On the other hand, if it is determined that there is no next access request, the process proceeds to step S206.

Next, in step S206, the access control unit 1020 performs READ from consecutive addresses of the addresses accessed in step S203. At this time, access is performed in units of the smallest accessible bytes. In the case of SROM, random access in 1-byte units is possible, so access is performed in 1-byte units, and READ data is recorded in the look-ahead recording unit 1022.

Next, in step S207, the access control unit 1020 determines whether or not the look-ahead is completed. The determination method may be such that the data size to be read ahead can be set by a register or the like, or may be read ahead by the same size as the access request from the CPU 100, and is not limited. If it is determined that the look-ahead is completed, the process is terminated, and if it is not completed, the process returns to step S205, and it is determined whether or not a new access request has been generated from the CPU 100. This is the end of the explanation of the flowchart of FIG.

As described above, by repeating the look-ahead in the minimum byte unit, even if there is a new access request from the CPU 100, it is sufficient to wait for the time when the read-ahead access in the minimum byte unit ends, so that the waiting time for the main access is reduced. can do.

Hereinafter, with reference to FIG. 3, a flow of reducing the waiting time for main access from the host and performing look-ahead without degrading the performance will be described according to the second embodiment. Since the block diagram is the same as that in FIG. 1, the description is omitted.

First, since steps S301 to S305 perform the same processing as steps S201 to S205 in the flowchart FIG. 2 of the first embodiment, the description thereof will be omitted. Next, in step 306, the access control unit 1020 performs READ from consecutive addresses of the addresses accessed in step S303. At this time, as a unit for pre-reading, it is possible to READ by the time from latching the READ data to returning the READ data to the CPU 100 and the time required to determine whether or not there is a new access request and the continuity of the address. Do it in bytes. This is because, depending on the circuit configuration, the above processing may take several cycles, and it may be more efficient to continue reading the data from the SROM during that time than to read ahead in the minimum byte unit.

This will be described with reference to the timing chart of FIG. The READDATA 402 is read out and returned to the CPU 100 in accordance with the READ request 400 from the CPU 100, and the period (1) in FIG. 4 is the period from latching the READDATA 401 to returning to the CPU 100. Further, in the period (2), it is determined whether or not there is a new access request and the continuity of the address is determined, and since there is no new access request, the look-ahead request 410 is executed. At this time, since it is inefficient not to transfer data to and from the SROM until the read-ahead request 410 is issued, the look-ahead is performed in advance in the possible units during the periods (1) and (2), and the look-ahead DATA411 is performed. I'm reading. Further, at the timing of (3), since the READ request 450 (the address is discontinuous from the READ request 400) exists as a new access request, the look-ahead is immediately interrupted and the access of the READ request 450 is SROM. I'm going to.

Since step S307 performs the same processing as step S207 in FIG. 2 of the flowchart of the first embodiment, the description thereof will be omitted. This is the end of the explanation of the flowchart of FIG.

As described above, by adjusting the read-ahead unit, it is possible to improve the efficiency of access to the SROM and reduce the waiting time for the main access.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and modifications can be made within the scope of the gist thereof.

100 CPU
101 Bus 102 Memory controller 103 ROM
1020 Access control unit 1021 Address comparison unit 1022 Look-ahead recording unit

Claims (5)

A memory control device that reads data from a memory and sends the data to the host that is the command source in response to a read command from the host.
An access control unit having a function of controlling access to the memory and performing a read-ahead to a continuous address of the read instruction even if there is no read instruction from the host following the read instruction from the host.
A look-ahead recording unit that records the value and address read-ahead by the access control unit,
It has an address comparison unit that compares the address of the read instruction with the address recorded in the look-ahead recording unit.
The look-ahead performed by the access control unit repeats access with a size smaller than that of the read instruction, and when a read command with an address discontinuous from the read command is received from the host during the look-ahead, the look-ahead is stopped and the read-ahead is stopped from the host. A memory control device characterized by accessing the address of a read instruction of. The memory control device according to claim 1, wherein the memory is accessed in the minimum accessible size in terms of the memory transfer protocol as an access having a size smaller than that of the read instruction. As an access with a size smaller than the read instruction
Latch processing of the data read from the memory and
Determining whether or not there is the next read instruction from the host,
Determining whether the next read instruction from the host is an access to the consecutive addresses of the read instruction,
The memory control device according to claim 1, wherein the memory has a size that can be read from the memory while at least one of the above is being executed. The memory control device according to any one of claims 1 to 3, wherein the memory is a Serial NOR Flash ROM. The memory control device according to any one of claims 1 to 4, wherein the transfer protocol is any one of a SPI protocol, a Quad SPI protocol, and an Octal SPI protocol.

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