JP2021089531A - Electronic control device - Google Patents

Abstract

To provide an electronic control device capable of reducing a latency time of processing performed by each of a plurality of CPUs.SOLUTION: An electronic control device 2 for controlling vehicles comprises: a plurality of CPUs (Central Processing Unit) 52; a shared memory 51 shared by the plurality of CPUs and including a first data region 511(1) in which data is stored by a first CPU 52(1) among the plurality of CPUs and a second data region 511(2) in which data is stored by a second CPU 52(2) among the plurality of CPUs; and a control unit 53 which suppresses competition between data stored in the first data region and the second data region.SELECTED DRAWING: Figure 2

Description

The present invention relates to an electronic control device.

Conventionally, a vehicle is provided with a plurality of electronic control devices (hereinafter, may be referred to as an ECU (Electronic Control Unit)) for operating an electronic vehicle control device. The ECUs are connected to each other via an in-vehicle LAN (Local Area Network) so that bidirectional communication is possible.

In order to calculate the data acquired from the sensor, the ECU is provided with a multi-core microcontroller (hereinafter, may be abbreviated as a microcomputer) equipped with a plurality of CPUs (Central Processing Units). In the microcomputer, the data stored in the shared memory may be shared and used between the CPUs. The shared memory is a dual port RAM (Random Access Memory) or the like.

When writing data to or reading data from shared memory, contention may occur in shared memory. As a result, a technique for avoiding data races is required.

In the technique of Patent Document 1, the shared memory is divided into a plurality of blocks. The state of each block is individually indicated by a pointer. The storage device switches the state of each block for updating or referencing by using a pointer. The storage device can prepare the block being updated and the block being referenced in different areas.

The storage device excludes the pointer memory while updating the pointer. Since the pointer is stored in an area separate from the shared memory, the storage device does not need to be exclusive between the shared memory update process or the reference process. The storage device does not need to wait for the reference process during the update process, and does not need to wait for the update process during the reference process. As a result, the storage device can minimize the waiting time.

Japanese Unexamined Patent Publication No. 2009-110063

In Patent Document 1, when the update process or the reference process is executed, the block state is switched. However, exclusive control is used for updating and referencing the pointer, and the CPU that newly accesses the pointer has a waiting time. In vehicle control, which requires real-time performance, it is required to reduce the waiting time due to exclusive control.

The present invention is for solving the above-mentioned problems, and an object of the present invention is to provide an electronic control device capable of reducing the waiting time for processing executed by a plurality of CPUs.

The electronic control device that controls the vehicle includes a plurality of CPUs (Central Processing Units) and a shared memory shared by the plurality of CPUs, and the shared memory is a first CPU among the plurality of CPUs in which data is stored. It includes one data area, a second data area in which data is stored by the second CPU among a plurality of CPUs, and a control unit that suppresses conflict of data stored in the first data area and the second data area. The plurality of CPUs have a processing configuration in which an update process for saving data in the first to second data areas, a reference process for referencing data from the first to second data areas, and a process configuration for executing the update process to the reference process in order. When the first CPU saves the first data in the first data area, the control unit uses the second CPU for a period from when the first data is saved until the reference process is executed by the first CPU. In the suppression value setting unit that sets the suppression value for suppressing storage in the 1 data area in the first data area, and when the first data is referred to by the first CPU in the reference processing, the first data is referenced. A release value setting unit that changes the suppression value saved in one data area to a release value is provided, and when the second CPU executes a process of saving the second data in the first data area, the suppression value is stored in the first data area. If is set, the second CPU stores the second data in the second data area, and executes a synchronization process of copying the value of the second data area to the first data area when the second data area is referred to.

According to the present invention, it is possible to reduce the waiting time for processing executed by each of the plurality of CPUs.

Explanatory drawing of vehicle control processing. Explanatory drawing of the microcomputer. The hardware configuration diagram of the ECU. Sequence diagram of processing of the microcomputer. CPU processing flow chart. Flow chart of data buffer update process. Flow chart of data buffer reference processing. Explanatory drawing of E2E protection of shared data.

The present embodiment relates to an ECU capable of reducing the waiting time for processing executed by a plurality of (for example, two) CPUs.

FIG. 1 is an explanatory diagram of vehicle control processing. The vehicle is provided with, for example, an in-vehicle sensor 1, an ECU 2, and an actuator 3. The vehicle may be provided with a plurality of ECUs 2. The in-vehicle sensor 1, the ECU 2, and the actuator 3 are connected by an in-vehicle LAN so that they can communicate in both directions.

The in-vehicle sensor 1 is, for example, an engine rotation sensor that detects the rotation speed of the engine. The in-vehicle sensor 1 is not limited to the engine rotation sensor. The in-vehicle sensor 1 transmits sensor information to the ECU 2. The sensor information indicates, for example, switch input, engine speed, intake air amount, and the like.

The ECU 2 controls an engine, a transmission, an inverter, or the like based on sensor information. The ECU 2 includes, for example, an input circuit 4, a microcomputer 5, and a driver IC (Integrated Circuit) 6.

The input circuit 4 converts a digital input signal or an analog input signal into a signal level or a digital value that can be input to the microcomputer 5. The input circuit 4 is composed of, for example, an input buffer, an AD converter, or the like.

As shown in FIG. 2, the microcomputer 5 is a multi-core microcomputer including a first CPU 52 (1) and a second CPU 52 (2). The microcomputer 5 acquires various input signals, parameter values, and the like from the input circuit 4. The microcomputer 5 calculates the control amount of the actuator 3 based on the information acquired from the input circuit 4. The microcomputer 5 generates an output signal to the driver IC 6.

The driver IC 6 generates a control signal for the actuator 3 from the output signal of the microcomputer 5. The driver IC 6 may generate, for example, voltage amplification, ON / OFF output, pulse output, PWM (Pulse Width Modulation) output, or the like.

The actuator 3 is, for example, a component such as a solenoid valve, a motor, or a relay. The actuator 3 drives, for example, a fuel injection device, an ignition device, and the like.

FIG. 2 is an explanatory diagram of the microcomputer 5. The microcomputer 5 includes, for example, a shared memory 51, a first CPU 52 (1), a second CPU 52 (2), a data buffer control unit 53 as an example of a “control unit”, and a determination value storage unit 54. When not particularly distinguished, the first CPU 52 (1) and the second CPU 52 (2) may be referred to as the CPU 52.

The shared memory 51 is shared and used by each CPU 52. The shared memory 51 is provided with, for example, a first data buffer 511 (1) as an example of the "first data area" and a second data buffer 511 (2) as an example of the "second data area". The first data buffer 511 (1) and the second data buffer 511 (2) may be referred to as a data buffer 511 unless otherwise distinguished.

In the data buffer 511, for example, control values required for controlling the actuator 3 are stored. The control value includes sensor information transmitted from the vehicle-mounted sensor 1. The control values stored in the data buffer 511 are updated and referenced by each CPU 52.

Each CPU 52 updates and refers to the data in the data buffer 511 based on the first determination value 541 (1) and the second determination value 541 (2). The first determination value 541 (1) and the second determination value 541 (2) may be indicated as a determination value 541 unless otherwise specified.

The first CPU 52 (1) executes a predetermined process including an update process and a reference process at a predetermined cycle. The second CPU 52 (2) executes a predetermined process by an event trigger as an example of the “predetermined signal”.

The determination value 541 determines whether each CPU 52 can store data in the data buffer 511. Each determination value 541 is stored in, for example, the determination value storage unit 54. The first determination value 541 (1) is set corresponding to the first data buffer 511 (1). The second determination value 541 (2) is set corresponding to the second data buffer 511 (2).

The determination value 541 may indicate whether or not it can be saved by, for example, the flags indicated by "0" and "1". The CPU 52 may store data in the data buffer 511 in which the determination value 541 indicates "0". The CPU 52 is suppressed from storing data in the data buffer 511 in which the determination value 541 indicates "1".

That is, when the first determination value 541 (1) indicates "0", the CPU 52 may store the data in the first data buffer 511 (1), for example. When the first determination value 541 (1) indicates "1", the CPU 52 is suppressed from storing the data in the first data buffer 511 (1), for example.

The data buffer control unit 53 sets the determination value 541. The data buffer control unit 53 includes, for example, a suppression value setting unit 531 and a release value setting unit 532.

The suppression value setting unit 531 sets the determination value 541 to "1" when the data buffer 511 is updated by the CPU 52. For example, when the CPU 52 updates the first data buffer 511 (1), the suppression value setting unit 531 sets the first determination value 541 (1) to "1" as an example of the "suppression value".

The release value setting unit 532 sets the determination value 541 to "0" when the data buffer 511 is referred to by the CPU 52. For example, when the CPU 52 refers to the first data buffer 511 (1), the release value setting unit 532 sets the first determination value 541 (1) to "0" as an example of the "release value".

Further, the release value setting unit 532 sets the determination value 541 corresponding to the data buffer 511 of the duplication source to "0" when the synchronization process (S45, see FIG. 7) described later is executed. For example, when the data in the second data buffer 511 (2) is replicated in the first data buffer 511 (1) by the synchronization process (S45), the release value setting unit 532 sets the second data buffer 511 (2). The second determination value 541 (2) corresponding to is set to "0".

FIG. 3 is a hardware configuration diagram of the ECU 2. The ECU 2 is, for example, a data transmission line that connects two CPUs 52, a storage unit 55, a memory 50, an input circuit 4, a driver IC 6, and functions 4, 6, 50, 52, 55 in two-way communication. It includes 56.

For example, the program of the data buffer control unit 53 is stored in the storage unit 55. In the storage unit 55, for example, the database of the determination value storage unit 54 is stored. The memory 50 is, for example, a volatile storage medium such as a RAM.

Hereinafter, the processing (S1 to S5) of the microcomputer 5 shown in FIGS. 5 and 5 will be described with reference to FIG. FIG. 4 is a sequence diagram of processing of the microcomputer 5. FIG. 4 shows, for example, a case where the first CPU 52 (1) executes the update process (S3) earlier than the second CPU 52 (2).

FIG. 5 is a flow chart of the CPU 52. The CPU 52 determines whether to execute the processes (S2 to S5) (S1). The first CPU 52 (1) executes processing (S2 to S5) at a predetermined cycle. The second CPU 52 (2) executes the process (S2 to S5) based on the event signal acquired from the outside.

The CPU 52 acquires sensor information from the vehicle-mounted sensor 1 by the input circuit 4 (S2). The first CPU 52 (1) acquires, for example, the sensor information data “AA”. The second CPU 52 (2) acquires, for example, the sensor information data “BB”. The CPU 52 performs a data buffer update process (S3).

FIG. 6 is a flow chart of the data buffer update process (S3). The CPU 52 acquires the first determination value 541 (1) corresponding to the first data buffer 511 (1), and determines whether the data can be saved (S31).

When the first determination value 541 (1) is "0" (S31: Yes), the CPU 52 saves the data in the first data buffer 511 (1) (S32). For example, the first CPU 52 (1) stores the data “AA” in the first data buffer 511 (1) because the first determination value 541 (1) is “0”. The suppression value setting unit 531 sets the first determination value 541 (1) to "1" (S33).

When the first determination value 541 (1) is "1" (S31: No), the CPU 52 saves the data in the second data buffer 511 (2) (S34). For example, the second CPU 52 (2) stores the data “BB” in the second data buffer 511 (2) because the first determination value 541 (1) is “1”.

The suppression value setting unit 531 sets the second determination value 541 (2) to "1" (S35). The CPU 52 ends the data buffer update process (S3) after the process (S33) or the process (S35) is completed. The CPU 52 may execute an arithmetic process for updating or referencing the load data of the header portion or the footer portion after the data buffer update process (S3) is completed.

Returning to FIG. 5, the CPU 52 executes the data buffer reference process (S4). FIG. 7 is a flow chart of the data buffer reference process (S4). Each CPU 52 refers to the first data buffer 511 (1) (S401). When referring to the data stored in the shared memory, each CPU 52 refers to the first data buffer 511 (1) instead of the second data buffer 511 (2).

That is, the first data buffer 511 (1) is an area of memory used for reference. The second data buffer 511 (2) is an area of memory that is temporarily stored when the update of the first data buffer 511 (1) is suppressed.

Each CPU 52 can select the first data buffer 511 (1) or the second data buffer 511 (2) as the data update destination, but selects the first data buffer 511 (1) as the data reference destination.

The CPU 52 determines whether the first determination value 541 (1) is "0" (S42). When the first determination value 541 (1) is "0" (S42: Yes), the CPU 52 ends the data buffer reference process (S4).

When the first determination value 541 (1) is "1" (S42: No), the release value setting unit 532 sets the first determination value 541 (1) to "0" (S43). For example, when the first CPU 52 (1) refers to the data “AA” of the first data buffer 511 (1), the release value setting unit 532 sets the first determination value 541 (1) to “0”.

Each CPU 52 determines whether the second determination value 541 (2) is "0" (S44). When the second determination value 541 (2) is "0" (S44: Yes), the ECU 2 ends the data buffer reference process (S4).

When the second determination value 541 (2) is "1" (S44: No), each CPU 52 replicates the data of the second data buffer 511 (2) to the first data buffer 511 (1) ( S45). For example, since the second determination value 541 (2) is "1", the first CPU 52 (1) duplicates the data "BB" in the first data buffer 511 (1).

The release value setting unit 532 sets the second determination value 541 (2) to "0" (S46). The ECU 2 ends the data buffer reference process (S4). Returning to FIG. 5, the CPU 52 outputs a control value to the driver IC 6 using the referenced data (S6).

FIG. 8 is an explanatory diagram of E2E (End-to-End) protection of shared data. When the shared data stored in the plurality of data buffers 511 in the shared memory 51 is ASIL (Automotive Safety Intelligence Level) level communication data specified in the automobile functional safety standard (ISO 26262), the ECU 2 performs , It is required to meet the specified failure detection rate.

The E2E protection function for protecting communication data includes, for example, a cyclic redundancy check (CRC) and the like. The ECU 2 includes a data transmitting unit 7 and a data receiving unit 8. The data transmission unit 7 includes a shared memory 51 (1), communication data 57, a CRC calculation unit 58 (1), and an error detection code 59 (1).

Communication data 57 is stored in the shared memory 51 (1). The communication data 57 is transmitted to the data receiving unit 8 and input to the CRC calculation unit 58 (1).

The CRC calculation unit 58 (1) calculates the error detection code 59 (1) for the communication data 57. The error detection code 59 (1) is added to the communication data 57 and transmitted to the data receiving unit 8.

The data receiving unit 8 includes a shared memory 51 (2), communication data 57, a CRC calculation unit 58 (2), an error detection code 59 (1), an error detection code 59 (2), and a code comparison unit 60. And a data processing unit 61. The communication data 57 is data transmitted from the data transmission unit 7, and is input to the data processing unit 61 and the CRC calculation unit 58 (2).

The error detection code 59 (1) is a code added to the communication data 57 and transmitted from the data transmission unit 7, and is input to the code comparison unit 60. The CRC calculation unit 58 (2) calculates the error detection code 59 (2) for the communication data 57. The error detection code 59 (2) is input to the code comparison unit 60.

The code comparison unit 60 compares the error detection code 59 (1) with the error detection code 59 (2), and inputs the code comparison result to the data processing unit 61. The data processing unit 61 refers to the code comparison result from the code comparison unit 60.

If there is no problem, the data processing unit 61 stores the communication data 57 in the shared memory 51 (2). When there is a problem, the data processing unit 61 stores fixed data in the shared memory 51 (2) instead of the communication data 57. As a result, data can be protected between the data transmitting unit 7 and the data receiving unit 8.

Returning to FIG. 4, when the second CPU 52 (2) overwrites and updates the value updated by the first CPU 52 (1) before the first CPU 52 (1) refers to it, the first CPU 52 (1) has the updated value. You will refer to different values. As a result, the CPU 52 is required to avoid data races.

Exclusive control is known as a method for avoiding data races. Exclusive control realizes that the timing of accessing shared data does not occur at the same time. For exclusive control, for example, a semaphore or the like is used.

The CPU 52 acquires the semaphore before accessing the shared data. When the acquisition of the semaphore is successful, the CPU 52 updates or refers to the data. The CPU 52 releases the semaphore after the data has been updated or referenced. The CPU or task that has acquired the semaphore can release the semaphore.

For example, when a predetermined CPU 52 is acquiring a semaphore, if another CPU 52 tries to acquire the semaphore, it will be in a waiting state until the semaphore is released. When the semaphore is released by the predetermined CPU 52, one CPU 52 in the other CPU 52 acquires the semaphore. The semaphore between multiple cores is realized by, for example, hardware in which a plurality of CPUs 52 cannot acquire the semaphore at the same time.

However, when the predetermined CPU 52 has acquired the semaphore, the processing of the other CPU 52 is stopped. The process of controlling the vehicle is required to be real-time in order to ensure the safety of the vehicle. As a result, it may be difficult for the CPU 52 waiting for processing to exhibit real-time performance by exclusive control by the semaphore.

Further, the capacity of the sensor information transmitted from the vehicle-mounted sensor 1 increases with the development of technologies such as automatic driving. The microcomputer 5 is required to secure time for processing sensor information in order to exhibit real-time performance. As a result, the microcomputer 5 is required to reduce the load on the CPU 52.

By providing the data buffer control unit 53, the ECU 2 shown above can avoid data contention based on the determination value 541 of the data buffer 511. As a result, each CPU 52 can accurately refer to the data stored in the data buffer 511.

In the reference process (S4), data consistency can be achieved between the data buffers 511 by executing the synchronous process (S45). As a result, each CPU 52 can refer to accurate data.

By setting each CPU 52 to refer to the data from the first data buffer 511 (1), it is not necessary to specify the CPU 52 in which the data is stored in the update process. As a result, the specific processing of the CPU 52 can be reduced, so that the load factor of the CPU 52 can be reduced.

The present invention is not limited to the above-described examples, and includes various modifications. For example, the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

It is possible to add / delete / replace other configurations with respect to a part of the configurations of each embodiment. Each of the above configurations, functions, processing units, processing means, etc. may be realized by hardware by designing a part or all of them by, for example, an integrated circuit. Each of the above configurations, functions, and the like may be realized by software by the processor interpreting and executing a program that realizes each function.

The present invention can include the electronic control methods shown below. When the first CPU stores the first data in the first data area in the shared memory, the second CPU is stored in the first data area from the time when the first data is saved until it is referenced by the first CPU. An electronic control method for suppressing storage of second data and releasing the first data area from the first CPU when the first data is referenced from the first data area by the first CPU.

The present invention can include the computer programs shown below. When the first CPU stores the first data in the first data area in the shared memory on the computer, the computer program for operating the computer as an electronic control device is described after the first data is saved. A function of suppressing the second CPU from storing the second data in the first data area before being referred by the first CPU, and a case where the first data is referred to from the first data area by the first CPU. To realize the function of releasing the first data area from the first CPU.

1 ... In-vehicle sensor, 2 ... Electronic control device, 3 ... Actuator, 4 ... Input circuit, 5 ... Microcomputer, 50 ... Memory, 51 ... Shared memory, 511 (1) ) ... 1st data buffer, 511 (2) ... 2nd data buffer, 52 (1) ... 1st CPU, 52 (2) ... 2nd CPU, 53 ... Control unit, 531. .. Suppression value setting unit, 532 ... Release value setting unit, 54 ... Judgment value storage unit, 541 (1) ... 1st judgment value, 541 (2) ... 2nd judgment value, 6・ ・ ・ Driver IC

Claims (8)

An electronic control device that controls a vehicle
The electronic control device is
A plurality of CPUs (Central Processing Units) and a shared memory shared by the plurality of CPUs are included, and the shared memory includes a first data area in which data is stored by the first CPU among the plurality of CPUs, and the said. A second data area in which data is stored by the second CPU among a plurality of CPUs is provided.
Further, it is provided with a control unit that suppresses conflict of data stored in the first data area and the second data area.
The plurality of CPUs execute an update process for storing data in the first to second data areas, a reference process for referencing data from the first to second data areas, and a process for sequentially executing the update process to the reference process. With composition,
The control unit
When the first CPU stores the first data in the first data area, the second CPU is stored in the first data area during the period from when the first data is saved until the reference process is executed by the first CPU. A suppression value setting unit that sets the suppression value that suppresses saving in the first data area,
In the reference process, when the first data is referenced from the first data area by the first CPU, the release value setting unit that changes the suppression value stored in the first data area to the release value, and the release value setting unit.
With
If the suppression value is set in the first data area when the second CPU executes the process of storing the second data in the first data area, the second CPU stores the second data in the second data area and the second To execute a synchronization process that copies the value of the second data area to the first data area when the data area is referenced.
An electronic control device characterized by. The electronic control device according to claim 1, wherein in the update process, when the suppression value is set in the first data area, the second CPU stores the second data in the second data area. The electronic control device according to claim 2, wherein the suppression value setting unit sets the suppression value in the second data area when the second CPU stores the second data in the second data area. The release value setting unit according to claim 3 sets the release value in the second data area when the second data stored in the second data area is stored in the first data area. The electronic control device described. The electronic control device according to claim 1, wherein the first CPU executes the predetermined process at a predetermined cycle. The electronic control device according to claim 1, wherein the second CPU executes the predetermined process by a predetermined signal. The electronic control device according to claim 1, wherein the data stored in the shared memory is a control value used for controlling an in-vehicle device. The electronic control device according to claim 1, further comprising an automobile security unit that protects data based on a predetermined automobile safety standard.

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