JP2021039489A - Control device for electronic circuit, image processing device with control device, and method of controlling electronic circuit - Google Patents

Abstract

To save the electric power when an electronic circuit has a transition in an operation mode.SOLUTION: A control device controls an electronic circuit, and has: voltage control means (139) which controls an operation voltage of the electronic circuit; frequency control means (138) which controls an operation frequency of the electronic circuit; memory means (137) which controls an operation rate of a memory that the electronic circuit can access; and control signal output means (144) which outputs a control signal to start controlling the voltage control means, the frequency control means, and the memory control means respectively according to a transition in an operation mode.SELECTED DRAWING: Figure 1

Description

The present invention relates to a control device capable of executing power control of an electronic circuit, an image processing device having the control device, and a control method of the electronic circuit.

Patent Document 1 discloses an information processing device having a processor, a storage unit, an operating system, and an operating frequency / operating voltage control unit. The storage unit stores a predetermined operating frequency and operating voltage for each of a plurality of service processes operating in the privileged mode. When any of the plurality of service processes is called, the operating system reads the operating frequency and operating voltage corresponding to the called service process from the storage unit. The operating frequency / operating voltage control unit changes the operating frequency and operating voltage of the processor to the operating frequency and operating voltage corresponding to the called service processing read by the operating system.

Japanese Unexamined Patent Publication No. 2014-186615

Since Patent Document 1 does not mention a procedure for controlling the operating frequency and operating voltage of an electronic circuit, power consumption during control is not taken into consideration.

An object of the present invention is to make it possible to reduce power consumption when the operation mode of an electronic circuit changes.

The control device of the present invention is a control device for controlling an electronic circuit, wherein the voltage control means for controlling the operating voltage of the electronic circuit, the frequency control means for controlling the operating frequency of the electronic circuit, and the electronic circuit A memory control means for controlling the operation rate of the accessible memory and a control signal for starting control of the voltage control means, the frequency control means, and the memory control means according to the transition of the operation mode are output. It has a control signal output means to be used.

According to the present invention, it is possible to reduce the power consumption when the operation mode changes.

It is a block diagram which shows the structural example of the image pickup apparatus. It is a flowchart which shows the control method of the image pickup apparatus. It is a figure which shows an example of the setting value table. It is a figure which shows an example of the control time table. It is a sequence diagram which shows the control method of an image pickup apparatus. It is a sequence diagram which shows the control method of an image pickup apparatus. It is a sequence diagram which shows the control method of an image pickup apparatus. It is a block diagram which shows the structural example of the image pickup apparatus. It is a figure which shows an example of the setting value table. It is a figure which shows an example of the control time table. It is a sequence diagram which shows the control method of an image pickup apparatus.

(First Embodiment)
FIG. 1 is a block diagram showing a configuration example of the image pickup apparatus 100 according to the first embodiment. The image pickup apparatus 100 includes an optical unit 11, an image pickup unit 12, an image processing chip 13, a display unit 15, a recording unit 16, a memory 17, a power supply IC 18, a shutter button 19, and a power supply button 20.

The optical unit 11 is a lens, and irradiates the image pickup unit 12 with the captured light. The image pickup unit 12 is an image sensor such as a CMOS image sensor, converts the light emitted from the optical unit 11 into an image signal, and outputs the image signal to the image processing chip 13.

The image processing chip 13 includes an internal bus 131, an input unit 132, an image processing unit 133, a CPU 134, a display control unit 135, a recording control unit 136, a memory control unit 137, a frequency control unit 138, a voltage control unit 139, and a control instruction unit. It is a semiconductor integrated circuit having 14. The image processing chip 13 is an electronic circuit that performs image processing and controls the display unit 15, the recording unit 16, the memory 17, and the power supply IC 18. Further, the image processing chip 13 is an image processing device that processes an image signal acquired from the image pickup unit 12.

The display unit 15 is, for example, a liquid crystal display, and displays a live view image input from the image processing chip 13 and displays an image recorded on the recording unit 16.

The recording unit 16 is a removable portable memory such as a memory card, records a captured image input from the image processing chip 13, and outputs the recorded captured image to the image processing chip 13. The captured image is, for example, a JPEG file or a RAW file in the case of a still image, and is, for example, an MP4 file in the case of a moving image.

The memory 17 temporarily records an image being processed by the image processing chip 13, and stores a program executed by the CPU 134 and various parameters. The memory 17 is, for example, a volatile memory such as DRAM (Dynamic Random Access Memory) or a non-volatile memory such as MRAM (Magnetoresistive Random Access Memory). The memory 17 is a memory having a sleep mode that stops a data signal when there is no access to save power. The memory 17 has one or more channels, and sleep mode and accessible mode can be set for each channel. The memory 17 mounted on the image pickup apparatus 100 may be one or a plurality. The memory operating rate is the ratio of the channels in the accessible mode among all the channels of the memory 17.

The power supply IC 18 is a power supply that supplies an operating voltage to the image processing chip 13, and the operating voltage supplied to the image processing chip may be controlled by inputting a command from the image processing chip 13, or the power supply IC 18 itself. The operating voltage may be controlled by the judgment of.

The shutter button 19 is operated by the user of the image pickup apparatus 100 and has three states: a no input state, a half-pressed state, and a fully-pressed state. The state of the shutter button 19 is notified to the image processing chip 13. The power button 20 is a button for turning on or off the power of the image pickup apparatus 100.

Next, the internal configuration of the image processing chip 13 will be described. The internal bus 131 includes a control bus for transferring control signals, an address bus for transferring address signals, and a data bus for transferring various data, and is composed of a plurality of buses. The internal bus 131 connects the input unit 132, the image processing unit 133, the CPU 134, the display control unit 135, the recording control unit 136, and the memory control unit 137.

The input unit 132 inputs an image signal from the image pickup unit 12, and outputs the image signal to the image processing unit 133 and the memory control unit 137 via the internal bus 131.

The image processing unit 133 performs correction processing of the optical unit 11 and the imaging unit 12 for the image signal, development processing of the live view image displayed on the display unit 15, data coding processing of the image recorded on the recording unit 16, and data. Perform decryption processing and so on.

The CPU 134 is a CPU (Central Processing Unit) and executes a program recorded in the memory 17. Further, the CPU 134 detects a change in the state of the shutter button 19 and the completion of recording in the recording unit 16 and notifies the control instruction unit 14 of them.

The display control unit 135 processes the image processing unit 133, inputs the image signal recorded in the memory 17, generates a display image to be displayed on the display unit 15, and outputs the display image to the display unit 15. ..

The recording control unit 136 processes the image processing unit 133, writes and reads the image signal and file system information recorded in the memory 17 to the recording unit 16, and completes the recording of the image signal output to the recording unit 16. It detects that it has been done and notifies the CPU 134 of it.

The memory control unit 137 inputs a request from each processing unit, executes writing and reading of various data to the memory 17, switches between a sleep mode and an accessible mode for each channel of the memory 17, and performs memory. The memory operating rate of 17 is controlled.

The frequency control unit 138 controls the operating frequency supplied to the image processing unit 133. The voltage control unit 139 controls the operating voltage of the power supply IC 18.

The control instruction unit 14 includes a set value storage unit 141, a control time storage unit 142, an instruction timing calculation unit 143, and a control signal output unit 144. The control instruction unit 14 outputs control instructions to the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 according to the operation mode transition of the image processing chip 13.

It can be said that the memory control unit 137, the frequency control unit 138, the voltage control unit 139, and the control instruction unit 14 that controls these are control devices that control the power consumed by the image processing chip 13.

The control instruction unit 14 informs the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 so as to suppress the power consumption of the image processing chip 13 when the operation mode of the image processing chip 13 changes (transitions). On the other hand, the timing of starting control is determined.

When the control instruction unit 14 transitions to the operation mode having higher power consumption, the longer the control time required for the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 to control each of the operation modes is longer. , The timing of output of the control signal to each control unit is controlled so that the timing of starting control is earlier.

For example, the control time required for the voltage control unit 139 to complete the change of the operating voltage according to the transition of the operation mode is for the frequency control unit 138 to complete the change of the operating frequency according to the transition of the operation mode. Suppose it is longer than the required control time. In this case, the control instruction unit 14 outputs the control signal instructing the change of the operating voltage to the voltage control unit 139 at a timing earlier than the timing of outputting the control signal instructing the frequency control unit 138 to change the operating frequency. Further, the control time required for the memory control unit 137 to complete the change in the operating rate according to the transition of the operation mode is required for the voltage control unit 139 to complete the change in the operating voltage according to the transition of the operation mode. It is assumed that the control time is shorter than the required control time and is longer than the control time required for the frequency control unit 138 to complete the change of the operating frequency according to the transition of the operating mode. In this case, the control instruction unit 14 outputs control signals in the order of the voltage control unit 139, the memory control unit 137, and the frequency control unit 138.

Further, when the control instruction unit 14 transitions to the operation mode with lower power consumption, the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 take the control time required for each control accompanying the transition of the operation mode. Regardless, the timing of output of the control signal to each control unit is controlled.

Next, the operation mode and the operation mode transition of the image processing chip 13 will be described. The image processing chip 13 has three operation modes: a low frame rate live view mode, a high frame rate live view mode, and a shooting mode.

The low frame rate live view mode is a mode in which the image processing chip 13 processes the image input through the optical unit 11 and displays it on the display unit 15 at a low frame rate, and the image processing chip 13 does not record. The frame rate is, for example, 30 fps.

The high frame rate live view mode is a mode in which the image processing chip 13 processes the image input through the optical unit 11 and displays it on the display unit 15 at a high frame rate. The high frame rate live view mode is a mode in which the display frame rate is higher than that of the low frame rate live view mode. The frame rate is, for example, 60 fps. Even in the high frame rate live view mode, the image processing chip 13 does not record, but automatically focuses on the subject, so-called autofocus.

In the low frame rate live view mode and the high frame rate live view mode, the image processing chip 13 performs pixel addition reading and line thinning reading from the image pickup unit 12 according to the resolution of the display unit 15, and the number of pixels per frame is small. Read the image of. In the high frame rate live view mode, considering that the user is trying to shoot a subject, the image processing chip 13 focuses by using the signal of the phase difference detection pixel read from the image pickup unit 12, the contrast of the image, and the like. , Perform autofocus processing. Since the image processing chip 13 uses the memory 17 for the autofocus processing, it is necessary to increase the memory operation rate.

The shooting mode is a mode in which the image processing chip 13 processes an image input through the optical unit 11 and records the processed image in the recording unit 16. The shooting mode includes a still image shooting mode, a still image continuous shooting mode, and a moving image shooting mode. In the shooting mode, since the image processing chip 13 reads the image of the total number of pixels from the imaging unit 12, the image size is increased as compared with the low frame rate live view mode and the high frame rate live view mode. In the shooting mode, the image processing chip 13 performs image data coding processing such as JPEG processing. In the low frame rate live view mode and the high frame rate live view mode, the image processing chip 13 does not perform image data coding processing such as JPEG processing. In the shooting mode, the image processing chip 13 has a larger image size than the low frame rate live view mode and the high frame rate live view mode, and requires a large capacity memory 17 to perform image data coding processing. It becomes.

The transition from the low frame rate live view mode to the high frame rate live view mode is performed by changing the shutter button 19 from the no input state to the half-pressed state. Further, when the shutter button 19 is released and the state is changed from the half-pressed state to the no-input state, the transition from the high frame rate live view mode to the low frame rate live view mode is performed. The transition from the high frame rate live view mode to the shooting mode is performed by changing the shutter button 19 from the half-pressed state to the fully-pressed state. The transition from the shooting mode to the low frame rate live view mode is performed by completing the recording of the image at the time of shooting to the recording unit 16.

The set value storage unit 141 stores the operating voltage, operating frequency, and memory operating rate of the image processing chip 13 to be set for each of the plurality of operating modes of the image processing chip 13 in a table, and stores them according to the operation mode transition. The value is output to the control signal output unit 144.

The control time storage unit 142 stores in a table the time required for control by the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 for each operation mode transition of the image processing chip 13. Then, the control time storage unit 142 outputs the storage control time to the instruction timing calculation unit 143 according to the operation mode transition.

The instruction timing calculation unit 143 describes the following when the operation mode of the image processing chip 13 transitions from the low frame rate live view mode to the high frame rate live view mode or from the high frame rate live view mode to the shooting mode. Perform processing. The instruction timing calculation unit 143 sends control signals to the memory control unit 137, the frequency control unit 138, and the voltage control unit 139, respectively, using the time input from the control time storage unit 142 according to the transition of the operation mode. Calculate the output timing. Then, the instruction timing calculation unit 143 outputs the calculation result to the control signal output unit 144.

The control signal output unit 144 stores the value stored in the set value storage unit 141 in the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 according to the timing calculated by the instruction timing calculation unit 143 at the time of the operation mode transition. It is used to output a control signal. The control signal output unit 144 uses the voltage control unit 139, the frequency control unit 138, and the memory control using the operation voltage, the operation frequency, and the memory control rate stored in the set value storage unit 141 according to the transition of the operation mode. A control signal for starting each control of the unit 137 is output.

In recent years, with the increase in the number of pixels and the frame rate of the image pickup apparatus (digital camera) 100, it has been desired to reduce the power consumption of the image processing chip 13 for processing image data. In particular, since the proportion of mirrorless cameras is increasing in the market, the power consumption of the image processing chip 13 during live view is important from the viewpoint of battery life. Therefore, as a technique for reducing the power consumption of the image processing chip 13, it is effective to apply DVFS (Dynamic Voltage and Frequency Scaling). DVFS is a technology that dynamically controls the operating voltage according to a change in the operating frequency to reduce power consumption.

When DVFS is applied to the image processing chip 13, the image processing chip 13 controls the operating voltage and the operating frequency according to the transition of the operating mode, and controls the memory operating rate. At the time of transition of the operation mode, the image processing chip 13 consumes more than the minimum necessary power if the control procedure of the operating voltage, the operating frequency, and the memory operating rate is not defined. For example, the time required for control to raise the operating voltage is longer than the time required for control to raise the operating frequency and control the memory operating rate. In that case, if the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 are all started to be controlled at the same time, the control of the operating frequency and the memory operating rate is completed before the control of the operating voltage is completed. Since the image processing chip 13 is in a state of high operating rate, excess electric power is generated by the time the control of the operating voltage is completed.

In the present embodiment, the image processing chip 13 aims to clarify the control procedure of the operating voltage, the operating frequency, and the memory operating rate, and to reduce the power consumption at the time of the operation mode transition.

FIG. 2 is a flowchart showing a control method of the image pickup apparatus 100, and shows an operation mode transition process of the image processing chip 13.

First, in step S200, the image processing chip 13 operates in the low frame rate live view mode.

Next, in step S201, the CPU 134 determines whether or not the shutter button 19 is in the half-pressed state. The CPU 134 waits until the shutter button 19 is half-pressed, and when the shutter button 19 is half-pressed, the process proceeds to step S202.

In step S202, the image processing chip 13 starts the transition from the low frame rate live view mode to the high frame rate live view mode. The instruction timing calculation unit 143 reads the operating voltage, operating frequency, and time required for controlling the memory operating rate from the control time storage unit 142, and outputs control instructions to the voltage control unit 139, the frequency control unit 138, and the memory control unit 137. The timing is calculated, and the process proceeds to step S203. The detailed calculation of the instruction timing calculation unit 143 in step S202 will be described later.

In step S203, the control signal output unit 144 transmits the control signal to the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 according to the calculation result of the instruction timing calculation unit 143 and the set value stored in the set value storage unit 141. Output and proceed to step S204.

In step S204, the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 control the memory operating rate, the operating frequency, and the operating voltage by the control signal output in step S203, and when the control is completed, the step Proceed to S205.

In step S205, the image processing chip 13 operates in the high frame rate live view mode.

Next, in step S206, the CPU 134 determines whether or not the shutter button 19 is in the fully pressed state. The CPU 134 proceeds to step S212 when the shutter button 19 is not in the fully pressed state, and proceeds to step S207 when the shutter button 19 is in the fully pressed state.

In step S207, the image processing chip 13 starts the transition from the high frame rate live view mode to the shooting mode. The instruction timing calculation unit 143 reads the operating voltage, operating frequency, and time required for controlling the memory operating rate from the control time storage unit 142, and outputs control instructions to the voltage control unit 139, the frequency control unit 138, and the memory control unit 137. The timing is calculated and the process proceeds to step S208. The detailed calculation of the instruction timing calculation unit 143 in step S207 will be described later.

In step S208, the control signal output unit 144 transmits the control signal to the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 according to the calculation result of the instruction timing calculation unit 143 and the set value stored in the set value storage unit 141. Output and proceed to step S209.

In step S209, the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 control the memory operating rate, the operating frequency, and the operating voltage by the control signal output in step S208, and the control is completed. Then, the process proceeds to step S210.

In step S210, the image processing chip 13 starts operation in the shooting mode. Next, in step S211 the CPU 134 determines whether or not the image processing chip 13 has completed recording to the recording unit 16 in the shooting mode. The CPU 134 waits until the recording is completed, and when the recording is completed, the process proceeds to step S213.

In step S212, the CPU 134 determines whether or not the shutter button 19 is in the half-pressed state. The CPU 134 proceeds to step S213 when the shutter button 19 is not in the half-pressed state, and proceeds to step S206 when the shutter button 19 is in the half-pressed state.

In step S213, the image processing chip 13 starts the transition from the shooting mode or the high frame rate live view mode to the low frame rate live view mode. The control signal output unit 144 simultaneously outputs a control signal to the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 according to the set value stored in the set value storage unit 141, and proceeds to step S214.

In step S214, the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 perform all control of the memory operating rate, the operating frequency, and the operating voltage by the control signal output in step S213, and all the controls. Is completed, the process proceeds to step S215.

In step S215, the CPU 134 determines whether or not the power off is instructed by the power button 20. If the power off is not instructed, the CPU 134 returns to step S200, and if the power off is instructed, the CPU 134 ends the process of the flowchart of FIG.

As described above, when the shutter button 19 changes from the no input state to the half-pressed state, the operation mode starts the transition from the low frame rate live view mode to the high frame rate live view mode. Further, when the shutter button 19 changes from the half-pressed state to the fully-pressed state, the operation mode starts the transition from the high frame rate live view mode to the shooting mode. Further, when the recording of the captured image is completed, the operation mode starts the transition from the shooting mode to the low frame rate live view mode. Further, when the shutter button changes from the half-pressed state to the no input state, the operation mode starts the transition from the high frame rate live view mode to the low frame rate live view mode.

Next, the operation of the control instruction unit 14 when the operation mode of the image processing chip 13 transitions from the low frame rate live view mode to the high frame rate live view mode and then from the high frame rate live view mode to the shooting mode. Will be explained. This operation mode transition is an operation when the user presses the shutter button 19 halfway and then takes a picture by pressing the shutter button 19 fully. Hereinafter, the sequence of FIG. 5 will be described with reference to the examples of the values of FIGS. 3 and 4.

FIG. 3 is a diagram showing an example of a set value table stored in the set value storage unit 141. The operation mode is three or more operation modes of a low frame rate live view mode, a high frame rate live view mode, and a shooting mode. The low frame rate live view mode, the high frame rate live view mode, and the shooting mode differ in at least one of the operating voltage, the operating frequency, and the memory operating rate.

First, the operating voltage, operating frequency, and memory operating rate in the low frame rate live view mode will be described. In the low frame rate live view mode, the image processing unit 133 processes the live view image at 30 fps at a low operating frequency of 300 MHz because the number of pixels to be processed is small, and at a low operating voltage of 500 mV because the operating frequency is low. It is operational. The memory operating rate in the low frame rate live view mode requires 50%.

Next, the operating voltage, operating frequency, and memory operating rate in the high frame rate live view mode will be described. The high frame rate live view mode doubles the frame rate and doubles the number of frames to be processed as compared with the low frame rate live view mode. Therefore, in the high frame rate live view mode, the image processing unit 133 operates at an operating frequency of 600 MHz, and as the operating frequency increases, the operating voltage also increases to 700 mV, and it becomes necessary to reduce the logic delay time. The memory operating rate in the high frame rate live view mode is 70%, which is 20% higher than the memory operating rate in the low frame rate live view mode by the increase in the autofocus processing.

Next, the operating voltage, operating frequency, and memory operating rate of the shooting mode will be described. In the shooting mode, the image processing chip 13 must read all the pixels, which increases the image size. Therefore, in the shooting mode, the operating frequency is 1000 MHz and the operating voltage rises to 1000 mV. In the shooting mode, the image processing chip 13 performs image data coding processing such as JPEG processing, which was not performed in the low frame rate live view mode and the low frame rate live view mode, so that a large capacity memory 17 is required. The memory operating rate is 100%.

FIG. 4 is a diagram showing an example of a control time table stored in the control time storage unit 142. The control time storage unit 142 sets the operation voltage control time of the voltage control unit 139, the operation frequency control time of the frequency control unit 138, and the memory operation rate control time of the memory control unit 137 for each operation mode transition. Remember.

First, the control time of the voltage control unit 139, the frequency control unit 138, and the memory control unit 137 when the image processing chip 13 transitions from the low frame rate live view mode to the high frame rate live view mode will be described. The voltage control unit 139 controls the operating voltage. Due to the stability of the PLL (Phase Locked Loop) built into the image processing chip 13 (not shown), the slew rate is specified for the transition of the operating voltage, and a sudden change in the operating voltage is not allowed. It takes time according to the transition amount. For example, the voltage control unit 139 has a control time of 80 μs for the transition from an operating voltage of 500 mV in the low frame rate live view mode to an operating voltage of 700 mV in the high frame rate live view mode.

The frequency control unit 138 can change the operating frequency supplied to the image processing unit 133 by a method of changing the multiplication factor of the PLL or a method of changing the frequency division ratio of the clock. For example, the frequency control unit 138 can quickly change the operating frequency by changing the frequency division ratio of the clock. For example, the frequency control unit 138 has a control time of 1 μs for the transition from the operating frequency of 300 MHz in the low frame rate live view mode to the operating frequency of 600 MHz in the high frame rate live view mode.

The control time of the memory operation rate is the recovery time from the self-refresh mode of the memory (DRAM) 17. For example, the memory control unit 137 has a memory operation rate control time of 15 μs.

Next, the control time of the voltage control unit 139, the frequency control unit 138, and the memory control unit 137 when the image processing chip 13 transitions from the high frame rate live view mode to the shooting mode will be described.

For example, the voltage control unit 139 has a control time of 100 μs for the transition from the operating voltage of 700 mV in the high frame rate live view mode to the operating voltage of 1000 mV in the photographing mode.

For example, the frequency control unit 138 has a control time of 1 μs for the transition from the operating frequency of 600 MHz in the high frame rate live view mode to the operating frequency of 1000 MHz in the shooting mode.

For example, the memory control unit 137 has a memory operation rate control time of 15 μs.

5 (a) to 5 (d) are diagrams showing a sequence at the time of operation mode transition of the image processing chip 13. FIG. 5A is a diagram showing an operating voltage of the image processing chip 13 controlled by the voltage control unit 139. FIG. 5B is a diagram showing an operating frequency of the image processing chip 13 controlled by the frequency control unit 138. FIG. 5C is a diagram showing the memory operating rate of the memory 17 controlled by the memory control unit 137. FIG. 5D is a diagram showing an operation mode of the image processing chip 13. The horizontal axis of FIGS. 5A to 5D is time.

The operation mode of FIG. 5D will be described. At times T500 to T501, the operating mode is the low frame rate live view mode. At times T501 to T504, the operation mode is in the process of transitioning from the low frame rate live view mode to the high frame rate live view mode. At times T504 to T505, the operating mode is a high frame rate live view mode. At times T505 to T508, the operation mode is in the process of transitioning from the high frame rate live view mode to the shooting mode. After the time T508, the operation mode is the shooting mode.

At time T500, the image processing chip 13 is operating in the low frame rate live view mode, the operating voltage is 500 mV, the operating frequency is 300 MHz, and the memory operating rate is 50%.

At time T501, the user changes the shutter button 19 from the no input state to the half-pressed state. Then, the CPU 134 notifies the instruction timing calculation unit 143 and the control signal output unit 144 that the operation mode of the image processing chip 13 shifts from the low frame rate live view mode to the high frame rate live view mode. The instruction timing calculation unit 143 reads out from the control time storage unit 142 the control time (80 μs) of the operation voltage, the control time (1 μs) of the operation frequency, and the control time (15 μs) of the memory operation rate at the time of this operation mode transition. Find the magnitude relationship of that time. For example, there is a magnitude relationship of operating voltage control time (80 μs)> memory operating rate control time (15 μs)> operating frequency control time (1 μs). The instruction timing calculation unit 143 subtracts the control time (15 μs) of the other memory operating rate and the control time (1 μs) of the operating frequency from the control time (80 μs) of the operating voltage having the longest control time. .. For example, the instruction timing calculation unit 143 performs subtraction of 80 μs-15 μs = 65 μs and subtraction of 80 μs-1 μs = 79 μs.

Using the above subtraction result, the instruction timing calculation unit 143 obtains the instruction timing of the time T502 at which the memory operation rate control is started after 80 μs-15 μs = 65 μs from the operation voltage control start time T501. The waiting time at times T501 to T502 is 65 μs. The control time of the memory operating rate at times T502 to T504 is 15 μs.

Further, the instruction timing calculation unit 143 uses the above subtraction result to obtain the instruction timing of the operation frequency control start time T503 after 80 μs-1 μs = 79 μs from the operation voltage control start time T501. The waiting time at times T501 to T503 is 79 μs. The control time of the operating frequency at times T503 to T504 is 1 μs. The instruction timing calculation unit 143 outputs the calculation result of the instruction timing to the control signal output unit 144.

At time T501, the control signal output unit 144 uses the operating voltage (700 mV) stored in the set value storage unit 141 with respect to the voltage control unit 139 controlled by the control time (80 μs) of the operating voltage having the longest control time. And output the control signal.

As described above, at time T501, when the shutter button 19 changes from the no input state to the half-pressed state, the operation mode starts the transition from the low frame rate live view mode to the high frame rate live view mode.

At the time T502, the control signal output unit 144 uses the memory operation rate (70%) stored in the set value storage unit 141 65 μs after the time T501 according to the calculation result of the instruction timing calculation unit 143, and the memory control unit 137. Output the control signal to.

At the time T503, the control signal output unit 144 controls the frequency control unit 138 using the operating frequency (600 MHz) stored in the set value storage unit 141 after 79 μs from the time T501 according to the calculation result of the instruction timing calculation unit 143. Output a signal.

At time T504, the voltage control unit 139, the memory control unit 137, and the frequency control unit 138, which output control signals at times T501, T502, and T503, complete control, and the operation mode of the image processing chip 13 is a high frame rate live view. Transition to mode. The operating voltage is 700 mV, the operating frequency is 600 MHz, and the memory operating rate is 70%.

The control signal output unit 144 together with the voltage control unit 139 so that the control of the operating voltage of the voltage control unit 139, the control of the operating frequency of the frequency control unit 138, and the control of the memory operating rate of the memory control unit 137 are completed substantially at the same time. A control signal is output to the frequency control unit 138 and the memory control unit 137.

At time T505, the user changes the shutter button 19 from a half-pressed state to a fully-pressed state. Then, the CPU 134 notifies the instruction timing calculation unit 143 and the control signal output unit 144 that the operation mode of the image processing chip 13 shifts from the high frame rate live view mode to the shooting mode. Further, the instruction timing calculation unit 143 outputs the control time (100 μs) of the operation voltage, the control time (1 μs) of the operation frequency, and the control time (15 μs) of the memory operation rate at the time of this operation mode transition from the control time storage unit 142. Read and find the magnitude relationship of the time. For example, there is a magnitude relationship of operating voltage control time (100 μs)> memory operating rate control time (15 μs)> operating frequency control time (1 μs). The instruction timing calculation unit 143 subtracts the control time (15 μs) of the other memory operating rate and the control time (1 μs) of the operating frequency from the control time (100 μs) of the operating voltage having the longest control time. .. For example, the instruction timing calculation unit 143 uses the above subtraction result to obtain the instruction timing at the time T506 from which the control of the memory operating rate is started 100 μs-15 μs = 85 μs after the operation voltage control start time T505. The waiting time at times T505 to T506 is 85 μs. The control time of the memory operating rate at times T506 to T508 is 15 μs.

Further, the instruction timing calculation unit 143 uses the above subtraction result to obtain the instruction timing of the operation frequency control start time T507 after 100 μs-1 μs = 99 μs from the operation voltage control start time T505. The waiting time at times T505 to T507 is 99 μs. The control time of the operating frequency at times T507 to T508 is 1 μs. The instruction timing calculation unit 143 outputs the calculation result of the instruction timing to the control signal output unit 144.

At time T505, the control signal output unit 144 controls the voltage control unit 139, which is controlled by the control time of the operating voltage having the longest control time, by using the operating voltage (1000 mV) stored in the set value storage unit 141. Output a signal.

As described above, at time T505, when the shutter button 19 changes from the half-pressed state to the fully-pressed state, the operation mode starts the transition from the high frame rate live view mode to the shooting mode.

At the time T506, the control signal output unit 144 uses the memory operation rate (100%) stored in the set value storage unit 141 after 85 μs from the time T505 according to the calculation result of the instruction timing calculation unit 143, and uses the memory operation rate (100%) of the memory control unit 137. Output the control signal to.

At the time T507, the control signal output unit 144 controls the frequency control unit 138 using the operating frequency (1000 MHz) stored in the set value storage unit 141 99 μs after the time T505 according to the calculation result of the instruction timing calculation unit 143. Output a signal.

At time T508, the voltage control unit 139, the memory control unit 137, and the frequency control unit 138, which output control signals at times T505, T506, and T507, complete the control, and the operation mode of the image processing chip 13 shifts to the shooting mode. .. The operating voltage is 1000 mV, the operating frequency is 1000 MHz, and the memory operating rate is 100%.

The control signal output unit 144 together with the voltage control unit 139 so that the control of the operating voltage of the voltage control unit 139, the control of the operating frequency of the frequency control unit 138, and the control of the memory operating rate of the memory control unit 137 are completed substantially at the same time. A control signal is output to the frequency control unit 138 and the memory control unit 137.

As described above, the instruction timing calculation unit 143 calculates so that the control of the voltage control unit 139, the memory control unit 137, and the frequency control unit 138 is completed at the optimum timing. As a result, the voltage control unit 139, the memory control unit 137, and the frequency control unit 138 can operate at a high operating rate as short as possible, and can reduce excess power consumption.

6 (a) to 6 (d) are diagrams for explaining the operation of the control instruction unit 14 when the operation mode of the image processing chip 13 shifts from the shooting mode to the low frame rate live view mode. This operation mode transition automatically starts the transition from the shooting mode to the low frame rate live view mode when the recording in the shooting mode is completed regardless of the user's operation. The value stored in the set value storage unit 141 is the same as that in FIG.

FIG. 6A is a diagram showing an operating voltage of the image processing chip 13 controlled by the voltage control unit 139. FIG. 6B is a diagram showing the operating frequency of the image processing chip 13 controlled by the frequency control unit 138. FIG. 6C is a diagram showing the memory operating rate of the memory 17 controlled by the memory control unit 137. FIG. 6D is a diagram showing an operation mode of the image processing chip 13. The horizontal axis of FIGS. 6A to 6D is time.

First, the operation mode of FIG. 6D will be described. At times T600 to T601, the operation mode is the shooting mode. At times T601 to T604, the operation mode is transitioning from the shooting mode to the low frame rate live view mode. After time T604, the operation mode is the low frame rate live view mode.

At time T600, the image processing chip 13 operates in the shooting mode, the operating voltage is 1000 mV, the operating frequency is 1000 MHz, and the memory operating rate is 100%.

At time T601, the recording control unit 136 records the captured image in the recording unit 16, and the CPU 134 causes the control signal output unit 144 to change the operation mode of the image processing chip 13 from the shooting mode to the low frame rate live view mode. Notify that the transition will occur. The control signal output unit 144 uses the operating voltage (500 mV), operating frequency (300 MHz), and memory operating rate (50%) stored in the set value storage unit 141 to control the voltage control unit 139, the frequency control unit 138, and the memory. A control signal is output to unit 137 at the same time.

At time T602, the frequency control unit 138 completes the control of the operating frequency. The operating frequency will be 300 MHz.

At time T603, the memory control unit 137 completes the control of the memory operating rate. The memory operating rate is 50%.

At time T604, the voltage control unit 139 completes the control of the operating voltage. The operating voltage is 500 mV. At time T604, the operation mode of the image processing chip 13 shifts to the low frame rate live view mode.

As described above, the instruction timing calculation unit 143 does not calculate the instruction timing in the operation mode transition in which the operation voltage, the operation frequency, and the memory operation rate of the image processing chip 13 become low. At time T601, the control signal output unit 144 outputs a control signal to all of the voltage control unit 139, the frequency control unit 138, and the memory control unit 137 at the same time.

7 (a) to 7 (d) show that the operation mode of the image processing chip 13 transitions from the low frame rate live view mode to the high frame rate live view mode, and then from the high frame rate live view mode to the low frame rate live view. The case of transitioning to the mode is shown. Hereinafter, the operation of the control instruction unit 14 in that case will be described. This operation mode transition is an operation when the user releases the shutter button 19 from the shutter button 19 after half-pressing the shutter button 19 without taking a picture by pressing the shutter button 19 fully. The value stored in the set value storage unit 141 is the same as in FIG. 3, and the value stored in the control time storage unit 142 is the same as in FIG.

FIG. 7A is a diagram showing an operating voltage of the image processing chip 13 controlled by the voltage control unit 139. FIG. 7B is a diagram showing the operating frequency of the image processing chip 13 controlled by the frequency control unit 138. FIG. 7C is a diagram showing the memory operating rate of the memory 17 controlled by the memory control unit 137. FIG. 7D is a diagram showing an operation mode of the image processing chip 13. The horizontal axis of FIGS. 7A to 7D is time.

The operation of the times T500 to T504 in FIGS. 7 (a) to 7 (d) is the same as the operation of the times T500 to T504 in FIGS. 5 (a) to 5 (d). At times T504 to T705, the operating mode is the high frame rate live view mode. At times T705 to T708, the operation mode is transitioning from the high frame rate live view mode to the low frame rate live view mode. At time T708, the operating mode is the low frame rate live view mode.

At time T705, the CPU 134 notifies the control signal output unit 144 that the operation mode of the image processing chip 13 changes from the high frame rate live view mode to the low frame rate live view mode. The control signal output unit 144 uses the operating voltage (500 mV), operating frequency (300 MHz), and memory operating rate (50%) stored in the set value storage unit 141 to control the voltage control unit 139, the frequency control unit 138, and the memory. A control signal is output to unit 137 at the same time.

At time T706, the frequency control unit 138, to which the control signal is output at time T705, completes the control of the operating frequency. The operating frequency will be 300 MHz.

At time T707, the memory control unit 137, to which the control signal is output at time T705, completes the control of the memory operating rate. The memory control rate is 50%.

At time T708, the voltage control unit 139 from which the control signal was output at time T705 completes the control of the operating voltage, and the operating mode of the image processing chip 13 shifts to the low frame rate live view mode. The operating voltage is 500 mV.

If the time stored in the control time storage unit 142 is fixed, the instruction timing calculation unit 143 may store the instruction timing at the time of the operation mode transition once calculated. In that case, the instruction timing calculation unit 143 can use the stored instruction timing as the calculation result without performing a new calculation when the same operation mode transition is performed from the second time onward. That is, the instruction timing calculation unit 143 stores the calculated timing, and then, in the case of the transition of the same operation mode, does not newly calculate the timing, and uses the above-mentioned stored timing as the calculation result.

As described above, the image pickup apparatus 100 has the image processing chip 13 that dynamically changes the operating voltage and the operating frequency, and can reduce the electric power generated at the time of the operation mode transition of the image processing chip 13.

(Second Embodiment)
FIG. 8 is a block diagram showing a configuration example of the image pickup apparatus 100 according to the second embodiment. The image pickup apparatus 100 of FIG. 8 is obtained by deleting the recording unit 16 and adding the post-stage chip 80, the power supply IC 81, the memory 82, and the recording unit 83 to the imaging apparatus 100 of FIG. The image processing chip 13 of FIG. 8 is obtained by deleting the recording control unit 136 and adding the output unit 503 and the input unit 504 to the image processing chip 13 of FIG. Hereinafter, the difference between the second embodiment and the first embodiment will be described.

Next, the internal configuration of the image processing chip 13 will be described. The internal bus 131 connects the input unit 132, the image processing unit 133, the CPU 134, the display control unit 135, the memory control unit 137, the output unit 503, and the input unit 504. A low drive rate shooting mode is added to the operation mode of the image processing chip 13.

The image processing unit 133 performs correction processing of the optical unit 11 and the imaging unit 12, development processing of the live view image to be displayed on the display unit 15, and pre-stage processing of the image for recording with respect to the image signal. Specifically, the pre-stage processing of the recording image is rearrangement of pixel signals input from the imaging unit 12, scratch correction, RAW noise reduction processing, and RAW compression. The RAW image is an image in a raw format as input from the imaging unit 12, for example, an image of a Bayer array. Subsequent image processing such as data coding processing of the image to be recorded is performed by the subsequent chip 80.

The output unit 503 outputs the RAW image processed by the image processing unit 133 to the subsequent chip 80. The input unit 504 inputs the image recorded in the recording unit 83, which will be described later, via the subsequent chip 80.

The control instruction unit 14 includes a set value storage unit 141, a control time storage unit 142, an instruction timing calculation unit 143, and a control signal output unit 144. The control instruction unit 14 outputs control instructions to the memory control unit 137, the frequency control unit 138, and the voltage control unit 139 according to the operation mode transition of the image processing chip 13.

The control instruction unit 14 of FIG. 8 adds a function of calculating the mode transition timing to the control instruction unit 14 of FIG. The control time storage unit 142 of FIG. 8 further stores the time required for the subsequent chip 80 to start up with respect to the control time storage unit 142 of FIG. The instruction timing calculation unit 143 of FIG. 8 further calculates the timing of transition from the low drive rate shooting mode to the shooting mode with respect to the instruction timing calculation unit 143 of FIG.

The voltage control unit 139 controls the operating voltage set in the power supply IC 18. Further, the voltage control unit 139 controls on / off of the operating voltage supply from the power supply IC 81 to the subsequent chip 80.

The latter-stage chip 80 is a semiconductor integrated circuit having an internal bus 801, an input unit 802, an image processing unit 803, a CPU 804, a memory control unit 805, a recording control unit 806, and an output unit 807. The control of the unit 83 is performed. The latter-stage chip 80 records the image input from the image processing chip 13 in the recording unit 83.

Next, the internal configuration of the latter-stage chip 80 will be described. The internal bus 801 connects the input unit 802, the image processing unit 803, the CPU 804, the memory control unit 805, the recording control unit 806, and the output unit 807.

The input unit 802 inputs the RAW image from the image processing chip 13, and outputs the RAW image to the image processing unit 803 and the memory control unit 805 via the internal bus 801.

The image processing unit 803 performs post-stage processing of the recording image processed by the image processing chip 13. The latter-stage processing includes RAW development processing, data coding processing, data decoding processing, and the like of the image to be recorded in the recording unit 83. Specifically, the data coding process is an image data coding process such as a JPEG process.

The CPU 804 is a CPU (Central Processing Unit) and executes a program recorded in the memory 82.

The memory control unit 805 inputs a request from each processing unit, and writes and reads various data to the memory 82.

The recording control unit 806 processes the image processing unit 803 and writes or reads the image or file system information recorded in the memory 82 to or from the recording unit 83. The output unit 807 outputs the image recorded in the recording unit 83 to the image processing chip 13.

The power supply IC 81 is a power supply that supplies an operating voltage to the subsequent chip 80, and inputs a command from the image processing chip 13 to control the operating voltage supplied to the subsequent chip 80. Here, the operating voltage supplied by the power supply IC 81 to the subsequent chip 80 is in two states of on / off of the operating voltage supply.

The memory 82 is a memory used as a storage unit for temporarily recording an image during image processing, a program executed by the CPU 804, and various parameters. The recording unit 83 is a removable portable memory such as a memory card, and is connected to the subsequent chip 80.

The operation mode of the image processing chip 13 includes a low frame rate live view mode, a high frame rate live view mode, a shooting mode, and a low drive rate shooting mode. The operation mode of the image processing chip 13 transitions from the low frame rate live view mode to the high frame rate live view mode, then from the high frame rate live view mode to the low drive rate shooting mode, and then to the low drive rate shooting mode. To the shooting mode. The operation of the control instruction unit 14 in that case will be described. This operation mode transition is an operation when the user presses the shutter button 19 halfway and then takes a picture by pressing the shutter button 19 fully. Hereinafter, the sequence of FIG. 11 will be described with reference to the values of FIGS. 9 and 10.

FIG. 9 is a diagram showing an example of a transition time table stored in the set value storage unit 141. The transition time table of FIG. 9 is obtained by adding the operating voltage, the operating frequency, and the memory operating rate of the low drive rate shooting mode to the transition time table of FIG. The shooting mode is a high drive rate shooting mode. The shooting mode has a low frame rate live view mode, a high frame rate live view mode, a low drive rate shooting mode, and a shooting mode (high drive rate shooting mode).

In the low drive rate shooting mode, the image processing chip 13 waits until the subsequent chip 80 is activated for processing. Therefore, the operating voltage in the low drive rate shooting mode is 300 mV, which is lower than the operating voltage in the shooting mode. The operating frequency of the low drive rate shooting mode is 100 MHz, which is lower than the operating frequency of the shooting mode. Since the memory 17 holds the image to be output to the subsequent chip 80, the memory operating rate of the memory 17 in the low drive rate shooting mode needs to be 100%.

FIG. 10 is a diagram showing an example of a control time table stored in the control time storage unit 142. This control time table shows the transition from the low frame rate live view mode to the high frame rate live view mode in FIG. 4, the transition from the high frame rate live view mode to the low drive rate shooting mode, and the transition from the low drive rate shooting mode. A transition to the shooting mode has been added.

The control time of the operating voltage, the control time of the operating frequency, and the control time of the memory operating rate in the transition from the low frame rate live view mode to the high frame rate live view mode in FIG. 10 are the same as those in FIG.

Next, the control time of the operating voltage, the control time of the operating frequency, the control time of the memory operating rate, and the startup time of the subsequent chip 80 in the transition from the high frame rate live view mode to the low drive rate shooting mode will be described. In order for the operating voltage to transition from 700 mV to 300 mV, the control time of the operating time is 120 μs. In order for the operating frequency to transition from 600 MHz to 100 MHz, the operating frequency control time is 1 μs. In order for the memory operating rate to transition from 70% to 100%, the control time of the memory operating rate is 15 μs. The startup time of the latter-stage chip 80 requires 100 ms. The latter-stage chip 80 is used for starting the OS (Operating System), connecting the image processing chip 13 and the latter-stage chip 80, and making the recording unit 83 recordable from the time when the operating voltage is applied to the time when the startup is completed. A startup time is required to make the settings.

Next, the control time of the operating voltage, the control time of the operating frequency, the control time of the memory operating rate, and the start-up time of the subsequent chip 80 in the transition from the low drive rate shooting mode to the shooting mode will be described. In order for the operating voltage to transition from 300 mV to 1000 mV, the control time of the operating time is 180 μs. In order for the operating frequency to transition from 100 MHz to 1000 MHz, the operating frequency control time is 1 μs. The memory operating rate remains 100%. The post-stage chip 80 maintains the activated state.

FIG. 11A is a diagram showing an operating voltage of the image processing chip 13 controlled by the voltage control unit 139. FIG. 11B is a diagram showing an operating frequency of the image processing chip 13 controlled by the frequency control unit 138. FIG. 11C is a diagram showing the memory operating rate of the memory 17 controlled by the memory control unit 137. FIG. 11D is a diagram showing an operation mode of the image processing chip 13. FIG. 11E is a diagram showing a state of the post-stage chip 80. The horizontal axis of FIGS. 11A to 11E is time.

The operations of the times T500 to T504 in FIGS. 11 (a) to 11 (d) are the same as the operations of the times T500 to T504 in FIGS. 5 (a) to 5 (d). At times T504 to T1105, the operating mode is the high frame rate live view mode. At times T1105 to T1108, the operation mode is in the process of transitioning from the high frame rate live view mode to the low drive rate shooting mode. At times T1108 to T1109, the operation mode is a low drive rate shooting mode. At times T1109 to T1111, the operation mode is in the process of transitioning from the low drive rate shooting mode to the shooting mode. After the time T1111, the operation mode is the shooting mode.

Next, the state of the latter-stage chip 80 of FIG. 11 (e) will be described. At times T500 to T1105, the latter-stage chip 80 is in a stopped state. At times T1105 to T1111, the latter-stage chip 80 is in activation control. After the time T1111, the latter-stage chip 80 is in the operating state. The start-up time of the latter-stage chip 80 of the time T1105 to T1111 is 100 ms.

At time T1105, the user changes the shutter button 19 from a half-pressed state to a fully-pressed state. Then, the CPU 134 notifies the instruction timing calculation unit 143 and the control signal output unit 144 that the operation mode of the image processing chip 13 shifts from the high frame rate live view mode to the low drive rate shooting mode.

The low drive rate shooting mode is an operation mode from when the shutter button 19 is fully pressed until the activation of the subsequent chip 80 is completed. In the low drive rate shooting mode, when the image processing chip 13 generates an image to be output to the subsequent chip 80, the image processing unit 133 is operated at a low drive rate until the subsequent chip 80 is activated, and is held in the memory 17. It is a mode to put.

The control signal output unit 144 outputs a control signal to the voltage control unit 139 for starting the supply of the operating voltage to the subsequent chip 80. When the voltage control unit 139 inputs a control signal for starting the supply of the operating voltage to the subsequent chip 80 to the power supply IC 81, the voltage control unit 139 controls the power supply IC 81 to start supplying the operating voltage to the subsequent chip 80. .. Since this operation mode transition is a transition in which the operating voltage and the operating frequency decrease, the control signal output unit 144 immediately uses the operating voltage (300 mV) and the operating frequency (100 MHz) stored in the set value storage unit 141 to obtain a voltage. A control signal is output to the control unit 139 and the frequency control unit 138.

Further, since this operation mode transition is a transition in which the memory operation rate increases, the instruction timing calculation unit 143 sends the control time storage unit 142 to the control time of the operation voltage, the control time of the operation frequency, and the memory at the time of the transition of the operation mode. The control time of the operation rate is read out, and the magnitude relationship is obtained. For example, there is a magnitude relationship of operating voltage control time (120 μs)> memory operating rate control time (15 μs)> operating frequency control time (1 μs). The instruction timing calculation unit 143 subtracts the control time (15 μs) of the memory operating rate from the control time (120 μs) of the operating voltage having the longest control time. The instruction timing calculation unit 143 obtains the instruction timing of the time T1107 from which the control of the memory operating rate is started after 120 μs-15 μs = 105 μs from the operation voltage control start time T1105, and causes the control signal output unit 144 to calculate the instruction timing. Is output. The waiting time at times T1105 to T1107 is 105 μs. The control time of the memory operating rate at times T1107 to T1108 is 15 μs. The control time of the operating voltage at times T1105 to T1108 is 120 μs.

Further, the instruction timing calculation unit 143 reads out from the control time storage unit 142 the start-up time of the subsequent chip, the control time of the operating voltage at the transition from the low drive rate shooting mode to the shooting mode, and the control time of the operating frequency. The instruction timing calculation unit 143 has the operating voltage control time (180 μs), which is the longer of the operating voltage control time (180 μs) and the operating frequency control time (1 μs) from the start-up time (100 ms) of the subsequent chip. ) Is subtracted. The instruction timing calculation unit 143 calculates the time (timing) T1109 at which the transition from the low drive rate shooting mode to the shooting mode starts after 100 ms-180 μs = 99 m 820 μs from the time T1105 at which the operating voltage of the subsequent chip 80 starts to be supplied. .. The standby time at times T1105-T1109 is 99 m 820 μs. The transition from the low drive rate shooting mode to the shooting mode is performed according to the calculation result of the instruction timing calculation unit 143.

As described above, the control signal output unit 144 has the voltage control unit 139 and the frequency control unit 138 so that the control of the operating voltage of the voltage control unit 139 and the control of the operating frequency of the frequency control unit 138 are completed substantially at the same time. A control signal for starting each control is output. At about the same time, the control signal output unit 144 outputs a control signal to the voltage control unit 139 for starting the supply of the operating voltage to the subsequent chip 80.

At time T1106, the frequency control unit 138 completes the control of the operating frequency. The operating frequency will be 100 MHz. The control time of the operating frequency at times T1105 to T1106 is 1 μs.

At the time T1107, the control signal output unit 144 controls the memory using the memory operation rate (100%) stored in the set value storage unit 141 105 μs after the time T1105 according to the calculation result of the instruction timing calculation unit 143. A control signal is output to unit 137.

At time T1108, the voltage control unit 139 and the memory control unit 137 for which control signals were output at times T1105 and T1107 complete control of the operating voltage and the memory operating rate, and the operation mode of the image processing chip 13 is low drive rate shooting. Transition to mode. The operating voltage is 300 mV. The memory operating rate is 100%.

The control signal output unit 144 completes the control of the longest operating voltage control time and the control of the memory operating rate substantially at the same time among the operating voltage control time, the operating frequency control time, and the memory operating rate control time. , Outputs a control signal for starting the control of the memory control unit 137.

At time T1109, the operation mode of the image processing chip 13 is changed from the low drive rate shooting mode to the shooting mode 99 m 820 μs after the time T1105 of the start of supply of the operating voltage of the subsequent chip 80 according to the calculation result of the instruction timing calculation unit 143. Start the transition.

The instruction timing calculation unit 143 reads out the control time of the operation voltage and the control time of the operation frequency at the time of the transition of the operation mode from the control time storage unit 142, and obtains the magnitude relationship between them. For example, there is a magnitude relationship of operating voltage control time (180 μs)> operating frequency control time (1 μs). The instruction timing calculation unit 143 subtracts the control time (1 μs) of the operating frequency from the control time (180 μs) of the operating voltage having the longest control time. The instruction timing calculation unit 143 obtains the instruction timing of the operation frequency control start time T1110 after 180 μs-1 μs = 179 μs from the operation voltage control start time T1109, and outputs the instruction timing calculation result to the control signal output unit 144. Output. The control signal output unit 144 outputs a control signal to the voltage control unit 139 that is controlled by the control time of the operating voltage having the longest control time, using the operating voltage (1000 mV) stored in the set value storage unit 141. .. The control time of the operating voltage at times T1109 to T1111 is 180 μs. The standby time at times T1109 to T1110 is 179 μs. The control time of the operating frequency at times T111 to T1111 is 1 μs.

At the time T1110, the control signal output unit 144 uses the operating frequency (1000 MHz) stored in the set value storage unit 141 after 179 μs from the time T1109 according to the calculation result of the instruction timing calculation unit 143, and uses the frequency control unit 138. Output the control signal to.

At time T1111, the post-stage chip 80 to which the operating voltage is supplied at time T1105 starts operation. The voltage control unit 139 and the frequency control unit 138, to which the control signals are output at the times T1109 and T1110, complete the control of the operating voltage and the operating frequency, and the operating mode of the image processing chip 13 shifts to the photographing mode. The operating voltage is 1000 mV. The operating frequency will be 1000 MHz. The shooting mode is an operation mode after the shutter button 19 is fully pressed and the activation of the post-stage chip 80 is completed. The image processing chip 13 processes the image input through the optical unit 11, and the processed image is processed in the post-stage. This is a mode for outputting to the chip 80.

As described above, the control signal output unit 144 has the voltage control unit 139 and the frequency control unit 138 so that the control of the operating voltage of the voltage control unit 139 and the control of the operating frequency of the frequency control unit 138 are completed substantially at the same time. A control signal for starting each control is output.

When the shutter button 19 changes from the no input state to the half-pressed state, the operation mode starts the transition from the low frame rate live view mode to the high frame rate live view mode. Further, when the shutter button 19 is changed from the half-pressed state to the fully-pressed state, the operation mode starts the transition from the high frame rate live view mode to the low drive rate shooting mode, and the subsequent chip 80 starts to start. Further, when the time T1109 is obtained by subtracting the longer control time of the operating voltage control time and the operating frequency control time from the start-up time of the subsequent chip 80, the operation mode changes from the low drive rate shooting mode to the shooting mode. Start the transition.

When the image processing chip 13 transitions from the high frame rate live view mode to the shooting mode, the image processing chip 13 operates at a low drive rate in the low drive rate shooting mode until the subsequent chip 80 is activated, thereby reducing power consumption. can do.

The image processing chip 13 can display the captured image recorded on the recording unit 83 on the display unit 15. The display control unit 135 transmits the captured image recorded on the recording unit 83 via the recording control unit 806 of the subsequent chip 80, the internal bus 801 and the output unit 807, and the input unit 504 and the internal bus 131 of the image processing chip 13. Input and output the captured image to the display unit 15.

The image pickup apparatus 100 includes an image processing chip 13 that dynamically changes an operating voltage, an operating frequency, and a memory operating rate, and a post-stage chip 80 that switches between an operating state and a stopped state. Since it takes a predetermined time for the subsequent chip 80 to start up in the image pickup apparatus 100, when the image processing chip 13 is operated at a high drive rate, a high operating voltage and a high operating frequency are required, and surplus electric power is generated. Therefore, the image processing chip 13 operates at a low drive rate in the low drive rate shooting mode according to the time until the subsequent chip 80 is activated, and the operating voltage can be reduced to reduce the electric power.

According to the first and second embodiments, when the image processing chip 13 is applied with DVFS, the image pickup apparatus 100 reduces the electric power when the operation mode is changed and increases the number of images taken by the image pickup apparatus 100. Can be done.

The image pickup device 100 is applicable to smartphones, tablets, industrial cameras, medical cameras, in-vehicle cameras, and the like, in addition to digital cameras and video cameras.

(Other embodiments)
The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

It should be noted that all of the above embodiments merely show examples of embodiment in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from the technical idea or its main features.

11 Optical unit, 12 Imaging unit, 13 Image processing chip, 14 Control indicator unit, 15 Display unit, 16 Recording unit, 17 Memory, 18 Power supply IC, 19 Shutter button, 20 Power supply button, 131 Internal bus, 132 Input unit, 133 Image processing unit, 134 CPU, 135 display control unit, 136 recording control unit, 137 memory control unit, 138 frequency control unit, 139 voltage control unit, 141 set value storage unit, 142 control time storage unit, 143 instruction timing calculation unit, 144 Control signal output unit

Claims (20)

A control device that controls electronic circuits
A voltage control means for controlling the operating voltage of the electronic circuit and
A frequency control means for controlling the operating frequency of the electronic circuit and
A memory control means for controlling the operating rate of a memory accessible to the electronic circuit,
A control device having a control signal output means for outputting a control signal for initiating control of each of the voltage control means, the frequency control means, and the memory control means according to a transition of an operation mode. The control signal output means, the voltage control means, the frequency control means, when the operation mode of the electronic circuit changes from the first operation mode to the second operation mode in which the power consumption is higher than that of the first operation mode. The control device according to claim 1, wherein the longer the control time required for the transition of the operation mode among the memory control means, the earlier the timing of outputting the control signal. The control device according to claim 2, wherein the second operation mode is a mode in which the operating voltage, the operating frequency, and the operating rate of the memory are higher than those of the first operating mode. The control signal output means is the voltage control means and the frequency control means when the operation mode of the electronic circuit transitions from the second operation mode to the third operation mode having lower power consumption than the second operation mode. The control device according to claim 2 or 3, wherein a control signal is output regardless of the control time required for the transition of the operation mode among the memory control means. Further, it has a timing calculation means for calculating the timing of outputting a control signal to each of the voltage control means, the frequency control means, and the memory control means according to the transition of the operation mode.
The control signal output means outputs a control signal for starting control of the voltage control means, the frequency control means, and the memory control means according to the timing calculated by the timing calculation means. The control device according to any one of 4. Control time storage means for storing the control time of the operating voltage of the voltage control means, the control time of the operation frequency of the frequency control means, and the control time of the operation rate of the memory of the memory control means for each transition of the operation mode. Have more
The timing calculation means determines the control time of the operating voltage of the voltage control means stored in the control time storage means, the control time of the operating frequency of the frequency control means, and the operation rate of the memory of the memory control means. The control device according to claim 5, wherein the timing of outputting a control signal to each of the voltage control means, the frequency control means, and the memory control means is calculated based on the control time. The timing calculation means is described in claim 5 or 6, wherein the calculated timing is stored, and then, in the case of a transition of the same operation mode, the timing is not newly calculated and the stored timing is used as the calculation result. Control device. The control device according to any one of claims 1 to 7, wherein the operating rate of the memory is a ratio of channels in an accessible mode among all channels of the memory. An image processing device having the electronic circuit and the control device according to any one of claims 1 to 8 and processing an image signal output from an imaging means. The first integrated circuit includes the voltage control means, the frequency control means, the memory control means, and the control signal output means.
The image processing device according to claim 9, wherein the image processing device further includes a second integrated circuit that records an image input from the first integrated circuit in a recording means. The control signal output means outputs a control signal for starting the supply of the operating voltage to the second integrated circuit to the voltage control means according to the transition of the operation mode.
When the voltage control means inputs a control signal for starting the supply of the operating voltage to the second integrated circuit, the voltage control means controls the second integrated circuit to start supplying the operating voltage. The image processing apparatus according to claim 10. The operation mode has a first operation mode, a second operation mode, a third operation mode, and a fourth operation mode.
The second operation mode is a mode in which the operation voltage, the operation frequency, and the operation rate of the memory are higher than those of the first operation mode.
The third operating mode is a mode in which the operating voltage and the operating frequency are lower and the operating rate of the memory is higher than that of the second operating mode.
The image processing apparatus according to claim 10 or 11, wherein the fourth operation mode is a mode in which the operating voltage and the operating frequency are higher than those of the third operating mode and the operating rate of the memory is the same. The control signal output means
When transitioning from the first operation mode to the second operation mode, control of the operation voltage of the voltage control means, control of the operation frequency of the frequency control means, and operation of the memory of the memory control means. A control signal for starting the control of the voltage control means, the frequency control means, and the memory control means is output so that the control of the rate is completed substantially at the same time.
When transitioning from the second operation mode to the third operation mode, the voltage is controlled so that the control of the operation voltage of the voltage control means and the control of the operation frequency of the frequency control means are completed substantially at the same time. A control signal for starting the control of the control means and the frequency control means is output, and at the same time, the voltage control means is started to supply the operating voltage to the second integrated circuit. The control time for the operation voltage, the control time of the operation frequency, and the control time of the operation rate of the memory, which is the longest, and the operation rate of the memory are controlled at substantially the same time. A control signal for starting the control of the memory control means is output so as to be completed.
When transitioning from the third operation mode to the fourth operation mode, the voltage is controlled so that the control of the operation voltage of the voltage control means and the control of the operation frequency of the frequency control means are completed substantially at the same time. The image processing apparatus according to claim 12, wherein a control signal for initiating control of each of the control means and the frequency control means is output. Further, it has a timing calculation means for calculating the timing of outputting a control signal to each of the voltage control means, the frequency control means, and the memory control means according to the transition of the operation mode.
When the timing calculation means transitions from the third operation mode to the fourth operation mode, the operation voltage control time and the operation frequency control time are obtained from the start time of the second integrated circuit. The image processing apparatus according to claim 12 or 13, wherein the timing for starting the transition from the third operation mode to the fourth operation mode is calculated by subtracting the longer control time. The operation mode has a low frame rate live view mode, a high frame rate live view mode, a low drive rate shooting mode, and a high drive rate shooting mode.
When the shutter button changes from the no input state to the half-pressed state, the operation mode starts the transition from the low frame rate live view mode to the high frame rate live view mode.
When the shutter button is changed from the half-pressed state to the fully-pressed state, the operation mode starts the transition from the high frame rate live view mode to the low drive rate shooting mode, and the second integrated circuit starts to start. And
When the time obtained by subtracting the longer control time of the control time of the operating voltage and the control time of the operating frequency from the start-up time of the second integrated circuit, the operation mode is the low drive rate imaging mode. The image processing apparatus according to any one of claims 10 to 14, wherein the transition to the high drive rate photographing mode is started from the above. A voltage control means that controls the operating voltage of an electronic circuit,
A frequency control means for controlling the operating frequency of the electronic circuit and
A method for controlling an electronic circuit, which comprises a memory control means for controlling the operating rate of a memory accessible to the electronic circuit.
A control method including a control signal output step that outputs a control signal for initiating control of each of the voltage control means, the frequency control means, and the memory control means according to a transition of an operation mode. In the control signal output step, when the operation mode of the electronic circuit changes from the first operation mode to the second operation mode in which the power consumption is higher than that of the first operation mode, the voltage control means, the frequency control means, and the like. The control method according to claim 16, wherein the longer the control time required for the transition of the operation mode among the memory control means, the earlier the timing of outputting the control signal. The control method according to claim 17, wherein the second operation mode is a mode in which the operating voltage, the operating frequency, and the operating rate of the memory are higher than those of the first operating mode. In the control signal output step, when the operation mode of the electronic circuit transitions from the second operation mode to the third operation mode having lower power consumption than the second operation mode, the voltage control means and the frequency control means. The control method according to claim 17 or 18, wherein a control signal is output regardless of the control time required for the transition of the operation mode among the memory control means. It further has a timing calculation step of calculating the timing of outputting a control signal to each of the voltage control means, the frequency control means, and the memory control means according to the transition of the operation mode.
The control signal output step outputs a control signal for starting control of the voltage control means, the frequency control means, and the memory control means according to the timing calculated by the timing calculation step. The control method according to any one of 18.

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