JP2021013048A - Spiking neural network by 3d network on-chip - Google Patents

Abstract

To provide a spiking neural network by multicast spike routing algorithm that leverages the unique 3D structure of a brain and reduces communication delay between neurons for enabling seamless implementation of a large-scale SNN (Spiking Neural Network)-based computing system.SOLUTION: A spiking neural network randomly determines a plurality of barycenters, calculates distances from each of a plurality of transmission destination routers implemented in a 3D network on-chip to each of the barycenters, assigns the plurality of transmission destination routers to any of a plurality of subgroups corresponding to the respective barycenters based on the calculated distances, re-determines a plurality of barycenters based on an assignment result, identifies a transmission path of a packet based on the re-determined barycenters, and transmits the packet using the identified transmission path.SELECTED DRAWING: Figure 2

Description

The present invention relates to a spiking neural network using a three-dimensional network on chip.

In recent years, neuroscience research has revealed much about the structure and behavior of individual neurons, and medical tools have made it possible to understand how neural activity in different regions of the brain follows sensory stimuli. .. In addition, advances in software-based artificial intelligence (AI) have brought us to the forefront of technology for building devices and systems with brain-like functions that overcome the bottlenecks of traditional von Neumann computing styles. I'm letting you.

The main difference between a neuroinspired or neuromorphic system and a conventional information processing system is that the neuroinspired or neuromorphic system uses a memory structure and organization. Systems based on the von Neumann style have one or more central processing units physically separated from the main memory area, whereas biological (spiking) neural network systems and artificial neural network systems. In each of these, co-localized memory and computational distribution are performed. Neuroinspired technology based on spiking neural networks (hereinafter referred to as SNNs) is focused on gaining a better understanding of the brain and exploring new biology-inspired calculations. I'm collecting. SNN has been successfully applied to some applications such as visual recognition tasks and classification tasks (Non-Patent Document 1). The implementation of neuromorphic hardware also makes it possible to run large networks in real time. This is an important requirement in some applications, including neurorobotics control, brain-machine interfaces and robotic decision making.

SNN attempts to mimic information processing in the mammalian brain based on a parallel array of neurons that communicate via spike events. Unlike typical multi-layer perceptron networks, where neurons fire in each propagation cycle, neurons in the SNN model fire only when the membrane potential reaches a certain value. In SNN, information is encoded by using various coding methods such as match coding, rate coding, and time coding (Patent Document 1). In SNNs, an integrated firing neuron model that produces voltage spikes (duration per spike of about 1 ms) that allows neurons to transmit nerve fibers when sufficiently stimulated by external stimuli from other neurons. Non-patent documents 2 and 3) are adopted. These pulses differ in amplitude, shape and duration, but are generally treated as the same event. Also, Hodgkin-Huxley conductance-based neurons (Non-Patent Document 4) are often used to efficiently model the non-linear and stochastic forces of ion channels in biological neurons. However, the Hodgkin-Huxley model has the problem that it is too complex to use for large-scale simulations and hardware implementations.

In recent years, a large number of deep SNNs have been proposed (Non-Patent Document 5). These are composed of many spiking neurons and have been successful in various pattern recognition tasks (Non-Patent Documents 1 and 6). However, it should be noted that these models, known as multi-layers, do not have many trainable layers compared to traditional deep neural networks. This is because there is no efficient learning rule for directly training the spiking deep network like the conventional back propagation of ANN (Artificial Neural Networks) (Non-Patent Document 5). Large-scale SNNs, on the other hand, are required to simulate complex brain activity. For example, there is a 2.5 million neuron model called Spain (Non-Patent Document 7). Spanu captures many aspects of neuroanatomy, neurophysiology and psychological behavior and also accurately performs numerical recognition tasks. In deep SNNs, communication between neurons plays an essential role during implementation. By mapping a large number of neurons to a planar structure and stacking the resulting planar dies using through silicon vias (TSVs: Through-Silicon Via), it is possible to significantly reduce communication latency. ..

SNN software simulations are a good way to investigate the behavior of neurosystems. However, software simulation of large (deep) SNN systems is slow. Another approach is a hardware implementation that provides the possibility to accurately generate independent spikes while simultaneously outputting spikes in real time. Hardware implementation has the advantage of higher computational speed than software simulation, so it is possible to take full advantage of the advantages of performing unique parallel processing. A special hardware texture having a plurality of neurocores can realize a high processing speed with low power by utilizing the parallel processing peculiar to the neural network. Therefore, SNNs are suitable for embedded neuromorphic devices and control applications.

The challenges that need to be resolved when building a spiking neural network architecture (neuromorphic) with a large number of synapses in hardware include a small massively parallel architecture with low power consumption, an efficient neurocoding scheme, and so on. It also includes the construction of lightweight on-chip learning algorithms. Another major challenge is on-chip communication and routing networks that allow data to communicate between the neurocore and the off-chip data transferred to that core. Further, the number of connected neurons is at least 103 times the number of PEs (Processing Elements) that need to be interconnected in the current multi-core / multi-processor System on a Chip (SoC) platform (Non-Patent Document 8). ). Due to the above restrictions, the development of such a brain-like IC (Integrated Circuit) becomes a difficult on-chip interconnection problem (Non-Patent Document 9). In the SNN, each neuron maintains an internal membrane potential that is a function of several parameters including input spikes, synaptic weights, current membrane potentials, and constant leakage coefficients (Non-Patent Document 10). Neuronal activity is constrained by neuronal connectivity, which plays an important role in determining the functional properties of neurons and neural systems. Brain connectivity is generally described on several scales: (1) individual synaptic connections that link individual neurons on a microscale, and (2) a population of neurons on the mesoscale. And (3) macroscale brain regions connected by fibrous pathways.

In an efficient SNN with an appropriate neuron and network model, synaptic inputs such as the Dirac Delta function to the neuron and the post-orthopedic synaptic potential (EPSP: Excitatory PostSynaptic Potential / IPSP: Inhibitory PostSynaptic Potential) It has a great effect on the output (spiking) time of. As a result, as shown in FIG. 1, timing violations affect the proper functioning (firing) of spiking neurons and the on-chip learning function of the entire system.

Shared buses as communication media are not suitable for implementing large and complex SNN chips / systems with multicast routing. This is because the addition of neurons reduces the communication capacity of the chip and also increases the length of the shared bus, which can affect the firing rate of neurons. Also, the increase in non-linearity in neural connections is very important in direct implementation using a dedicated point-to-point communication method.

Two-dimensional packet-switched network-on-chip (2D-Noc: Two-dimensional packet-switched Network-on-Chip) has the potential to address the interconnect problems found in previously proposed SNN-based shared communication media. It has been considered as a solution (Non-Patent Documents 9 and 12). However, such interconnect strategies make it difficult to achieve high scalability with low power consumption, especially in large SNN chips. Circuit-switched NoCs, separate from packet-switched NoCs, allow the performance of various routing / switching mechanisms to be investigated. Circuit switching NoC has less hardware complexity and higher energy efficiency than packet switching, but requires longer setup time.

Over the last few years, the advantages of 3D-ICs and mesh-based NoCs have been combined with promising architectures that open up new areas of IC design, especially on AI-equipped chips. NoC parallelism can be enhanced in three dimensions thanks to the short wire length and the low power consumption of the 3D-IC interconnect. As a result, the 3D-NoC paradigm is considered to be one of the most advanced and convenient architectures for future IC design. 3D-NoC provides a very high bandwidth and low power consumption interconnect (Non-Patent Document 13), making it possible to meet the high requirements of new artificial intelligence (AI) applications. When 3D-NoC and SNN are combined, spiking neurons can be considered as PE (neurocore). Connectivity between neurons is implemented by sending spike packets over an scalable interconnect network. In this case, PE refers to an SNPC (Spiking Nueron Processing Core) connected to a 3D-NoC router, the NoC channel resembles a neuron synapse, and the NoC topology is a neuron network. Refers to the way they are interconnected within.

One of the main issues with hardware implementation of SNNs is their reliability potential. SNNs are said to have some unique fault tolerance properties, thanks to the large, parallel structures inspired by biological neural models, but not necessarily in practice (in practice). Non-Patent Document 14). In fact, the challenges inherited from the continuous shrinkage of semiconductor components expose the implementation of SNNs in hardware to a variety of obstacles (Non-Patent Document 14). When yield is a major issue, failure risk becomes even more important as large-scale SNN integration for embedded systems progresses (Non-Patent Document 15). When considering the reliability of interneuron communication, failures can affect system performance, especially when occurring in critical applications (aerospace, self-driving cars, biomedicine, etc.). Such obstacles can have unwanted inaccuracies or irreversible and serious consequences. In SNN, when the connection between neurons is impaired, the postsynaptic neurons become unresponsive or nearly unresponsive (low firing activity state). As shown in FIG. 1 (c), if there is a broken link in the connection from N1 to N4, the potential membrane of N4 will reach the threshold for firing the output spike, as in FIG. 1 (b). Not reachable. This reduces the firing rate of postsynaptic neurons.

Therefore, it may affect the overall performance of the SNN model based on the rate coding method (Non-Patent Document 16). Neurons with low firing rates are susceptible to the noise of firing rates and the temporary jitter of spikes that increase dispersion (Non-Patent Document 17). As a result, efficient fault-tolerant technology is required. With such a mechanism, recovery time is one of the important requirements. As shown in FIG. 1 (d), the long waiting time of the fault-tolerant routing method may affect the firing rate. In particular, it can affect SNN models that use temporary coding methods based on the relative timing between spikes.

Therefore, the challenge of finding an efficient fault-tolerant solution becomes more important with the large-scale integration of SNNs into silicon.

U.S. Patent Application Publication No. 2014/0351190 JP-A-2015-119387

Y. Cao, Y. Chen, and D. Khosla, “Spiking deep convolutional neural networks for energy-efficient object recognition,” Int. J. Comput. Vision, vol. 113, no. 1, pp. 54-66, May 2015. N. Burkitt, “A review of the integrate-and-_re neuron model: I.homogeneous synaptic input,” Biol. Cybern., Vol. 95, no. 1, pp. 1-19, Jun. 2006. [Online] . Available: http://dx.doi.org/10.1007/s00422-006-0068-6 K. Suzuki, Y. Okuyama, and AB Abdallah, “Hardware design of a leaky integrate and fire neuron core towards the design of a low-power neuro-inspired spike-based multicore soc,” in Information Processing Society Tohoku Branch Conference, February 2018. J. H Goldwyn, N. S Imennov, M. Famulare, and E. Shea-Brown, "Stochastic differential equation models for ion channel noise in hodgkin-huxley neurons," in Phys. Rev. E, vol. 83, no. 1, 2011, pp. 4190-4208. A. Tavanaei, M. Ghodrati, S. R. Kheradpisheh, T. Masquelier, and A. Maida, “Deep learning in spiking neural networks,” Neural Networks, 04 2018. P. Diehl and M. Cook, “Unsupervised learning of digit recognition using spike-timing-dependent plasticity,” Frontiers in Computational Neuroscience, vol. 9, p. 99, 2015. C. Eliasmith, TC Stewart, X. Choo, T. Bekolay, T. DeWolf, Y. Tang, and D. Rasmussen, “A large-scale model of the functioning brain.” Science, vol. 338 6111, pp. 1202 -1205, 2012. S. Furber and S. Temple, “Neural systems engineering,” Journal of the Royal Society Interface, vol. 4, no. 13, pp. 193-206, Sep 2006. S. Carrillo, J. Harkin, LJ McDaid, F. Morgan, S. Pande, S. Cawley, and B. McGinley, “Scalable hierarchical network-on-chip architecture for spiking neural network hardware implementations,” IEEE Transactions on Parallel and Distributed Systems, vol. 24, no. 12, pp. 2451-2461, Dec 2013. W. Maas, “Networks of spiking neurons: The third generation of neural network models,” Trans. Soc. Comput. Simul. Int., Vol. 14, no. 4, pp. 1659-1671, Dec. 1997. [Online ]. Available: http://dl.acm.org/citation.cfm?id=281543.281637 A. Ben Abdallah, Advanced Multicore Systems-On-Chip Architecture, On-Chip Network, Design. Springer, 2017. R. Hojabr, M. Modarressi, M. Daneshtalab, A. Yasoubi, and A. Khonsari, “Customizing clos network-on-chip for neural networks,” IEEE Transactions on Computers, vol. 66, no. 11, pp. 1865 -1877, Nov 2017. KN Dang, AB Ahmed, Y. Okuyama, and BA Abderazek, “Scalable design methodology and online algorithm for tsv-cluster defects recovery in highly reliable 3d-noc systems,” IEEE Transactions on Emerging Topics in Computing, pp. 1-1, 2017. C. Torres-Huitzil and B. Girau, “Fault and error tolerance in neural networks: A review,” IEEE Access, vol. 5, pp. 17322-17341, 2017. P. M. Furth and A. G. Andreou, “On fault probabilities and yield models for vlsi neural networks,” IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1284-1287, Aug 1997. PU Diehl, D. Neil, J. Binas, M. Cook, S. Liu, and M. Pfeiffer, “Fast-classifying, high-accuracy spiking deep networks through weight and threshold balancing,” in 2015 International Joint Conference on Neural Networks ( IJCNN), July 2015, pp. 1-8. M. Pfeiffer and T. Pfeil, “Deep learning with spiking neurons: Opportunities and challenges,” Frontiers in Neuroscience, vol. 12, p. 774, 2018. [Online]. Available: https://www.frontiersin.org/ article / 10.3389 / funins.2018.00774 D. Vainbrand and R. Ginosar, “Scalable network-on-chip architecture for configurable neural networks,” Microprocess. Microsyst., Vol. 35, no. 2, pp. 152-166, Mar. 2011. [Online]. Available : http://dx.doi.org/10.1016/j.micpro.2010.08.005 BA Akram and BA Abderazek, “Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3d-noc systems,” J. Parallel Distrib. Comput., Vol. 93, no. C, pp. 30-43, Jul. 2016. W. Gerstner and W. Kistler, Spiking Neuron Models: Single Neurons, Populations, Plasticity. Cambridge University Press, 2002. KN Dang, M. Meyer, Y. Okuyama, and AB Abdallah, “Reliability assessment and quantitative evaluation of soft-error resilient 3d network-on-chip systems,” in 2016 IEEE 25th Asian Test Symposium (ATS), Nov 2016, pp . 161-166. X. Lin and L. M. Ni, “Multicast communication in multicomputer networks,” IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 10, pp. 1105-1117, Oct 1993. S. H. Strogatz, “Exploring complex networks,” vol. 410, pp. 268-276, 03 2001. F. Akopyan, J. Sawada, A. Cassidy, R. Alvarez-Icaza, J. Arthur, P. Merolla, N. Imam, Y. Nakamura, P. Datta, GJ Nam, B. Taba, M. Beakes, B . Brezzo, JB Kuang, R. Manohar, WP Risk, B. Jackson, and DS Modha, “Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 10, pp. 1537-1557, Oct 2015.

Routing algorithms are considered one of the most efficient recovery mechanisms in SNNs because they play an important role in the performance of neuronal communication. The routing algorithm can affect the load distribution of the entire network and the overall delay of the system in a fault-free scenario (Non-Patent Document 11). The use of traditional unicast-based routing in large SNNs is non-existent because the traffic pattern of a given SNN is a one-to-many way for presynaptic neurons to send spikes to a subset of postsynaptic neurons. It is efficient (Non-Patent Document 18). In addition, when considering fault tolerance requirements, routing algorithms must be carefully selected to minimize delays in interneuron communication. Otherwise, the accuracy of the postsynaptic node can be reduced despite the fact that the failure has been avoided. FIG. 1 (d) shows a clear example of such a case. The figure shows that long latency due to improper routing can prevent timely firing of output spikes by postsynaptic neurons.

Therefore, an object of the present invention is to utilize a unique 3D structure of the brain to propose a new multicast spike routing algorithm that enables seamless implementation of a large-scale SNN-based computing system, thereby communicating between neurons. It is to reduce the delay.

In one aspect of the present invention, it is a spiking neural network by a three-dimensional network on-chip, and a plurality of centers of gravity are randomly determined, and the plurality of destination routers mounted on the three-dimensional network on-chip are selected. The distances to each of the centers of gravity are calculated, and based on the calculated distances, the plurality of destination routers are assigned to any of the plurality of subgroups corresponding to the plurality of centers of gravity, and the plurality of subgroups are assigned. Based on the allocation result of the plurality of destination routers to, the plurality of center of gravity is redetermined, and the first transmission included in the plurality of destination routers from the source router mounted on the three-dimensional network on chip. When a packet is transmitted to the destination router, the transmission route of the packet is specified based on the redetermined plurality of center of gravity, and the packet is transmitted using the specified transmission route.

It reduces communication delays between neurons by leveraging the unique 3D structure of the brain and proposing a new multicast spiking routing algorithm that enables seamless implementation of large-scale SNN-based computing systems.

FIG. 1 is a diagram showing an example of the effect of a connection failure on the ignition rate. FIG. 2 is a diagram showing an outline of the system architecture. FIG. 3 is a diagram showing the SNPC architecture. FIG. 4 is a diagram showing the FTMC-3DR architecture. FIG. 5 is a diagram showing an algorithm of the KMCR multicast routing pseudo code. FIG. 6 is a diagram showing an example of a 6 × 3 × 2 mesh 3D NoC KMCR algorithm. FIG. 7 is a diagram showing a primary branch and a backup branch. FIG. 8 is a diagram showing the FTMP-KMCR algorithm for offline calculation of the primary branch and the backup branch. FIG. 9 is a diagram showing a failure management algorithm applied to each router corresponding to “son”, “father”, and “grandfather” at the time of backup.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Each embodiment is prepared for a better understanding of the present invention. However, such embodiments do not limit the technical scope of the present invention. In addition, the scope of the present invention covers the scope of claims and the equivalent thereof.

First, the 3DFT-SNN architecture according to the present invention based on the low-latency multicast routing scheme for spike traffic routing will be described. FIG. 2 is a diagram showing an outline of the system architecture.

As shown in FIG. 2, the system 100 (3DFT-SNN system 100) consists of several stacked 2D layers of spiking neural tiles 10 and is based on a conventional 3D-NoC architecture (Non-Patent Document). 13 and 19). Specifically, FIG. 2 shows an example in which spiking neural tiles 10 composed of 4 × 4 2D layers are stacked.

The spiking neural tile 10 is composed of a spiking neural processing core (hereinafter also referred to as SNPC1) and a fault-tolerant multicast router (hereinafter also referred to as FTMC-3DR2). .. In relation to SNNs, spike neurons point to PEs, interneuron connections are implemented in the form of sending spikes (packets) via scalable 3D-NoCs, and the topology is in the network. It refers to the way neurons are interconnected. As shown in FIG. 3, each SNPC1 in the 3DFT-SNN system 100 uses an array of spiking neurons to process incoming spikes.

The SNPC 1 is the main processing unit of the system 100. In the example shown in FIG. 3, the input spikes are first decoded to determine their postsynaptic neurons. Weight values are accumulated in the sequence of LIF (Leaky Integrate-and-Fire) neurons via crossbar-based synapses (Non-Patent Document 20).

SNPC1 is based on a crossbar approach. Here, an on-chip SRAM is used to implement an N × N crossbar (where N is the number of neurons). Each synapse is represented by 5 bits, 1 bit is used for synaptic type (ie excitatory and inhibitory) and 4 bits are used for weighting. Hereinafter, the main components of SNPC1 will be described.

The decoder 11 determines postsynaptic neurons for each incoming spike (packet). Upon arriving at the destination neural tile, the incoming spike is forwarded by the local router to the local SNPC1. The decoder 11 searches a look-up table (LUT: Lookup Table) based on the neuron ID to determine a postsynaptic neuron. This information is transmitted to the control unit 12 for neural calculation.

The control unit 12 is designed to control the overall operation of the neural core. The control unit 12 controls both the configuration mode and the operation mode of the neural core. The control unit 12 ensures that neurons are updated during a single time step.

The synaptic crossbar contains a synaptic crosspoint sequence. Each synapse is a bit that displays a connection (synapse) between rows (axises) and columns (dendrites) and stores bits that can be read, set, or reset. This bit is read for neural computation while being written after the decoding is complete.

The synapse memory 13 (hereinafter, also referred to as sym_mem13) is a place for storing synapse information used for setting the crossbar and synapse intensity. Synaptic information is updated during the training phase and read during inference operations.

The neural memory 14 (hereinafter, also referred to as neu_mem14) is used for the neural parameters. Each parameter is read for neural calculation. Then, after the neural calculation is performed, each parameter is updated to save the current state of the neuron.

The LIF array 15 is the main computational unit of the neutron core on which neural computations are performed. Data are read from the synaptic crossbar and sym_mem13 and neu_mem14 are calculated in this unit. Here, a plurality of LIF neurons are implemented. More precisely, a physical LIF computing unit is implemented while multiple neurons are executed sequentially. This not only takes advantage of the high speed operation of digital logic, but also reduces area costs and power consumption.

The encoder 16 is designed to pack the spikes generated from the LIF array 15. When a neuron's membrane potential exceeds a threshold, the neuron produces spikes (firing). This spike is transmitted to the encoder 16 where it is packed into packets before being introduced into the network through the local router.

The configuration information 17 is used to configure the neural core. This information includes configuration parameters related to synaptic and neuron models. Neural core construction is performed before the system is up and running while the application is mapped.

Next, the fault-tolerant multicast 3D router (Fault-Tolarant Multicast 3D Router: hereinafter, FTMC-3DR2) architecture will be described. FIG. 4 is a diagram showing the FTMC-3DR architecture.

Since each neuron can connect to thousands of other neurons, FTMC-3DR2 supports multicast routing for efficient spike delivery. FTMC-3DR2 is based on a conventional 3DR architecture (Non-Patent Documents 13, 19 and 21). The delay of FTMC-3DR2 should be very short as the spike time is used to encode the information. Each router 2 of the system 10 has a maximum of 7 input ports and 7 output ports, 6 of which are dedicated to neighboring routers and 1 input / output port connects the switch to SNPC1. Used for. The FTMC-3DR2 includes, in addition to the switch allocator 22, seven input port modules 21 corresponding to each of the directions. The FTMC-3DR2 also includes a crossbar module 23 that processes the transfer of spikes to the next SNPC1. The input port module is composed of two main elements, an input buffer 21a and a multicast routing module 21b.

Router 2 is designed with four pipeline stages: buffer write (BW), routing calculation (RC), switch arbitration (SA), and crossbar crossing (CT). In the first stage, the incoming spike (packet) is stored in the input buffer 21a before being processed. Then, the source address of the packet _{(X S; Y S; Z} S) is extracted and calculated, the output port is determined. After the routing calculation, a request (sw_request signal) is sent to the switch allocator 22 to use the selected output port. The switch allocator 22 includes two main components: a general Stall / Go flow control 22a (Non-Patent Document 11) and a Matrix-arbiter scheduler 22b. Here, the Matrix-arbiter, which has the lowest priority, is adopted in order to provide high-speed calculation, inexpensive implementation, and strong fairness (Non-Patent Document 11). Finally, the packet is allowed (via the sw_grant signal) and then sent to the desired output port through the crossbar 23.

In addition to soft errors in the routing pipeline stage (Non-Patent Document 21), router 2 is used for system reconfiguration using redundant structural resources to handle hardware defects in the input buffer 21a, crossbar 23, and links. It relies on advanced recovery techniques based on it (Non-Patent Documents 13 and 19). These mechanisms are aimed at mitigating the failures that occur in the system.

Next, K-means clustering (hereinafter referred to as KMCR) based on the multicast spike routing algorithm will be described.

As described above, the NoC of the 3D mesh is suitable for creating a large-scale network by stacking a plurality of 2D-NN layers in a state of being expandable. In SNNs, one neuron is usually connected to many other neurons. Therefore, there is a large amount of one-to-many communication between the neural processing cores.

The routing algorithm in the present invention is based on a combination of K-means clustering and tree-based routing. The tree-based mechanism is a common method used in multicast communication. In this routing mechanism, destination groups are split from source nodes to form a "tree" routing path for packets. One of the main drawbacks of the tree-based method is traffic contention due to the high likelihood that packets will be blocked at intermediate nodes (Non-Patent Document 22). In order to deal with this problem, the present invention employs K-means that divides the destination set into subsets. The adoption of K-means comes from the observation that postsynaptic neurons are often adjacent to each other. Previous studies have shown that SNN's interneuron communication is highly localized (Non-Patent Document 23). This allows neuron groups within the same area to share incoming spikes. Therefore, when mapped to a 3D-NoC system, neurons in the SNN layer are distributed in one core or nearby cores. This makes it possible to make the best use of K-means to acquire an effective partition, balance the traffic load, and alleviate the high congestion of the NoC system.

Therefore, as shown in the algorithm of FIG. 5, the proposed routing method first divides the destination into several subgroups. To do this, the proposed routing method employs a K-means clustering mechanism to find the centroid of the subset and its labeled destination. The center of gravity here is the node with the smallest average distance to everything else in its subgroup.

The algorithm first randomly selects a center of gravity from the available targets in order to determine the center of gravity. The algorithm then calculates the next step.

(1) As shown in the 10th line of the algorithm of FIG. 5, the distance from each destination to the center of gravity is calculated using the Manhattan distance.

(2) Based on these distances, destinations are assigned to the subgroup with the closest center of gravity.

(3) Finally, after the subgroup is temporarily formed, the position of the center of gravity is updated by averaging all the elements. Then, these updates are repeated until the center of gravity does not change.

After determining the center of gravity, the routing path from the source node to the target is formed in two steps. In the first step, a route from each source to the center of gravity is determined using a general method, dimensional order routing (hereinafter referred to as DOR) (Non-Patent Document 11). From this point, the same route from the given source to the centroid is merged. This makes it possible to reduce the number of spike packets that need to be sent from the source compared to the unicast-based method. The use of a particular variation of DOR, such as XYZ or ZYX, depends on the application mapping method for obtaining optimized and balanced traffic, as further illustrated in the example shown in FIG. Note that ZYX means that the Z dimension is executed first in the routing calculation, and then Y and X are executed. Then, at the end of this stage, a part of the "tree" from the source to the center of gravity is formed. Subsequently, in the second stage, the same routing calculation as in the first stage is performed to establish another part of the "tree" from the center of gravity to the destination. After two steps, a "tree" route from a given source node to its destination is built, and the calculated routing information is used to update the routing table connected to the router.

Next, an example of an 18x18 fully connected SNN application mapped to a 6x3x2 3D NoC-SNN system will be described. Here we assume that each spiking tile has one neuron in the SNPC.

As shown in FIG. 6, the tile / node (source node) in L1 transmits an output to all the nodes (destination node) in L2. In a specific case, the node 3 which is the source node in the layer L1 (hereinafter, in such a case, the node 3 is referred to as “3”) needs to transmit the spike packet to all the nodes in the layer L2. When the number of clusters k is 2, the destination set is divided into two subsets having "26" and "29" as the centers of gravity (FIG. 6A). Next, a "tree" route from the source to both centroids is determined, as shown in FIG. 6 (b). In this mapping method, the ZYX version in DOR is selected. As a result, the spikes pass through the plurality of interlayer links, so that the traffic contention of the intermediate nodes (that is, "8" and "11") of the first layer can be mitigated. On the other hand, when using either XYZ or YXZ, all source nodes in L1 need to send spikes to the center of gravity (ie, "26" and "29") via "11" and "8". is there. Therefore, high traffic congestion occurs in the links between the layers "11" and "26" and the links between the layers "8" and "29". As shown in FIG. 6 (c), after the route from the center of gravity to the destination is calculated, other parts of the tree are formed. Finally, as shown in FIG. 6D, a routing "tree" from "3" to each in L2 is formed.

Choosing the Optimal Number of Clusters: As mentioned above, the number of clusters (k) needs to be determined before applying the proposed routing algorithm (KMCR). Intuitively, if k is small, the destination set is divided into large subsets. As a result, the congestion at the intermediate node (that is, the center of gravity) becomes large, and the congestion of the network may become large. On the other hand, when k is large, each source node can send multiple copies of a given packet to the centroid. This may increase the waiting time. If k is equal to the number of destinations, the routing algorithm in the present invention behaves like unicast-based multicast. It is important to note that the choice of k depends primarily on the distribution of destination nodes. Fortunately, there are some good observations that can be employed to select the optimal value for k. First, as mentioned above, SNNs have high locality of interneuron communication. This creates a situation where neurons in the same group (layer) are mapped to nearby neural processing cores. This makes it possible for the K-means clustering algorithm to work efficiently. Second, the number of destination nodes in a typical SNN application is not large. In fact, the number of neurons in a layer can range from hundreds to thousands for deep learning based on a multi-layer model, each of which can contain hundreds of neurons (256 neurons in the case of SNPC). It is possible to accommodate it in the core of (Non-Patent Document 24). Therefore, after mapping the SNN application, it is possible to determine the number of clusters by visualizing the distribution of destinations. However, in order to select the optimum value of k in a particular case, it is necessary to evaluate the performance system by a different value other than k.

Based on the above observations, the optimum k can be determined by the following two steps.

(1) After mapping the SNN application, find the number of clusters by visualizing the destination set.

(2): The system is evaluated by varying the value of k (including the number of clusters found in (1) and some other values) and the optimal case is selected.

Next, K-means clustering (Shortest Path K-means clustering: hereinafter referred to as SP-KMCR) of the shortest path based on the multicast routing algorithm will be described.

As described above, in KMCR, the source node transmits the spike packet to the center of gravity, and then the center of gravity transmits the spike to the destination. In the use of the center of gravity, the total distance from the center of gravity to the destination is guaranteed to be minimal. However, this can result in traffic congestion on the link to the centroid because traffic from different sources is concentrated in the centroid.

In order to deal with this problem, the present invention proposes a new routing method. After determining the destination subset by adopting K-means, the present invention first calculates the number of hops from a given source to all the nodes in the subset. The present invention then selects the node with the shortest path to the source for each subset. Unlike the case of KMCR, the source sends the spike packet to the shortest path node of each subset instead of the centroid node. Hereinafter, this method is referred to as SP-KMCR. This eliminates the potential problem of traffic congestion and reduces average latency. Note that the new method requires more calculations to find the shortest path when compared to KMCR. However, both the new method and the KMCR calculations are performed offline. Therefore, the run-time overhead is the same for both algorithms.

Next, K-means clustering (Fault-Tolerant Shortest Path K-means Clustering: hereinafter referred to as FTSP-KMCR) of the shortest path in fault tolerance based on the multicast routing algorithm will be described. The FTSP-KMCR is based on the SP-KMCR.

The basic idea of FTSP-KMCR is as follows.

(1) Offline calculation of the primary routing tree and backup routing branch from a given source node to its destination is performed.

(2) After the offline calculation, the routing table is constructed.

FIG. 7 is a diagram showing primary and backup routing branches. If a failed primary branch is detected, a pre-planned backup branch is used to avoid the failed link. The SP-KMCR mechanism is used to calculate the primary branch (solid line). The backup branch, on the other hand, is an alternative route to the primary branch. Then, for the router under consideration (ie, "son"), the backup branch (dashed line) used in the event of a failure in the primary connection is calculated. For example, if there is a failure in the primary connection between "father" and "son" (ie pl ₁ ), bl ₁ and bl ₂ are to maintain traffic between "father" and "son". The backup branch used for. This is true even if both pl ₂ and pl ₁ are impaired.

In the algorithm, calculating the primary and backup routes is an important computational task. These calculations are performed offline. This makes it possible to reduce the runtime overhead of the proposed routing algorithm and avoid timing violations that may occur in the SNN. As shown in the algorithm of FIG. 8, the source and destination addresses (S; T) and the number of subsets (k) are predefined as inputs, and the output portion is the primary tree from each source to the destination. P _pr ) and backup branch (P _bc ).

After that, the routing is calculated according to the following procedure.

Step 1: As shown in the 6th to 19th lines, K-means is adopted from the destination address to determine the destination subset.

Step 2: Find the shortest path from each source to each subset of nodes, as shown on lines 20-25.

Step 3: The first part of the primary tree is formed from the source node to the SP node. This is done by adopting a dimensional order routing (DOR) algorithm from the source to each SP node and merging it with the same route. It then adopts an alternative variation of DOR to calculate the backup branch and ensure that the backup branch is separated from the primary root. For example, if a ZYX DOR is used in the formation of the primary tree, other variations of the DOR such as YZX or XZY are used for the backup branch.

Step 4: According to the same calculation as in step 2, calculate the second part of the primary tree and the backup branch from the SP node to its destination in the same group.

It should be noted that only the primary and backup routing paths are offline calculations. The results of these calculations are used to configure the routing table in the router. Since the configuration process is done during pre-execution application mapping, it does not affect the category of online learning processes where synaptic enhancements (weights) are updated. In addition, this ensures that the computational overhead of the backup branch does not affect the recovery time of the proposed routing algorithm and reduces the hardware cost required for the system.

Next, the fault management algorithm will be described. After the routing information is configured, a fault management algorithm is implemented to process the incoming packet, as shown in FIG.

S1: For a given incoming packet, a fruit_flag_val is extracted to indicate whether the packet is in the primary branch or the backup branch. At the same time, the source address is also used to calculate the expected primary output port.

S2 and S3: If fruit_flag_val = 0 (ie, if the router is acting as a "father" or "grandfather"), the calculated output port should use the fault detector connected to each router. Determines if there is a failure.

S4: When the expected output port is determined, a packet_flag_val is added to the packet before forwarding.

S5: Otherwise, the output port is switched to use the backup branch, and the initial value (hop in the backup path) is set to the default_flag_val to notify the next backup router that this packet is on the backup branch. Set a value equal to the number).

S6: If fruit_flag_val ≠ 0 (ie, if the router role is a backup or "son" router), the output port is routed through the backup route, and further_flag_val is 0 and the backup path is It is reduced by 1 until it finishes.

1: SNPC
2: FTMC-3DR
10: Spiking neural tile 100: 3DFT-SNN system

Claims (9)

3D network On-chip spiking neural network
Randomly determine multiple centers of gravity,
The distances from each of the plurality of destination routers mounted on the three-dimensional network on-chip to each of the plurality of centroids are calculated.
Based on the calculated distance, the plurality of destination routers are assigned to any of the plurality of subgroups corresponding to the plurality of centers of gravity.
Based on the allocation results of the plurality of destination routers to the plurality of subgroups, the plurality of centers of gravity are redetermined.
When a packet is transmitted from a source router mounted on the three-dimensional network on chip to a first destination router included in the plurality of destination routers, the packet is transmitted based on the redetermined centers of gravity of the plurality of destination routers. Identify the transmission route of the packet and
The packet is transmitted using the specified transmission path.
A spiking neural network with a three-dimensional network on-chip. In claim 1,
In the allocation process,
For each of the plurality of destination routers, the first center of gravity having the shortest calculated distance among the plurality of centers of gravity is specified.
Each of the plurality of destination routers is assigned to a subgroup corresponding to the first center of gravity corresponding to each destination router.
A spiking neural network with a three-dimensional network on-chip. In claim 1,
In the calculation process, the Manhattan distance from each of the plurality of destination routers to each of the plurality of centers of gravity is calculated.
A spiking neural network with a three-dimensional network on-chip. In claim 1,
In the redetermination process, the centers of gravity of the plurality of destination routers assigned to each subgroup are calculated for each of the plurality of subgroups.
A spiking neural network with a three-dimensional network on-chip. In claim 1,
The calculation process, the allocation process, and the redetermination process are repeated until the reselected plurality of centers of gravity are not changed.
A spiking neural network with a three-dimensional network on-chip. In claim 1,
In the specifying process, the transmission route of the packet is specified so as to pass through the center of gravity corresponding to the first destination router among the plurality of redetermined centers of gravity.
A spiking neural network with a three-dimensional network on-chip. In claim 1,
In the specific process,
The first center of gravity corresponding to the first destination router among the redetermined centers of gravity is specified.
Among the plurality of destination routers assigned to the subgroup corresponding to the specified first center of gravity, the second destination router having the shortest distance from the source router is specified.
The transmission route of the packet is specified so as to pass through the specified second destination router.
A spiking neural network with a three-dimensional network on-chip. In claim 6 or 7,
In the specifying process, a plurality of transmission routes between the third destination router and the fourth destination router located between the source router and the first destination router are specified.
In the transmission process, when the first transmission path among the specified plurality of transmission paths is available, the packet is transmitted using the first transmission path, and the first transmission path is used. If not available, the packet is transmitted using the second transmission path of the plurality of identified transmission paths.
A spiking neural network with a three-dimensional network on-chip. In claim 8.
In the process of transmitting,
When the fifth destination router located between the third destination router and the fourth destination router receives the packet from another destination router, the hop given to the received packet. Extract the number,
If the number of extracted hops is not 0, the packet obtained by subtracting 1 from the number of hops is transmitted using the second transmission path.
When the number of the extracted hops is 0, it is determined whether or not the transmission route ahead of the fifth destination router in the first transmission route can be used, and the destination transmission route is determined. When it is determined that the packet can be used, the packet is transmitted using the first transmission route, and when it is determined that the destination transmission route is not available, the unusable transmission among the destination transmission routes is performed. The packet to which the number of hops corresponding to the route is given is transmitted using the second transmission route.
A spiking neural network with a three-dimensional network on-chip.