JP2020098565A - Interface circuit and communication device - Google Patents

Abstract

To allow for reducing the circuit scale and power consumption.SOLUTION: An interface circuit 1 is provided, comprising a plurality of communication devices 10-1, 10-2, an A-D converter circuit 20 for AD converting an analog signal into digital data, and a control circuit 30 configured to read digital data in response to a read request signal from the plurality of communication devices 10-1, 10-2.SELECTED DRAWING: Figure 1

Description

The present invention relates to an interface circuit and a communication device.

In recent years, mobile communication terminals such as mobile phones and smartphones are required to have multiple bands and multiple modes that support a plurality of frequencies and wireless systems with one terminal. A communication device compatible with such multi-band and multi-mode conversion is required to process a plurality of transmission/reception signals at high speed without degrading the quality. For example, LAA (Licensed-Assisted Access) that improves throughput by using an unlicensed band of 5 GHz band used in a wireless LAN as a secondary cell of carrier aggregation (CA) in LTE-Advanced is standardized.

The communication device is generally configured to monitor the temperature and compensate the gain due to the temperature change. For example, a configuration has been disclosed in which an analog signal from one temperature sensor is AD-converted and captured (for example, Patent Document 1).

US Patent No. 8526995

For example, in a configuration in which a communication device for wireless LAN and a communication device for LTE are mixed, if a temperature sensor and an AD conversion circuit are provided for each communication device, there is a problem that the circuit scale and power consumption increase.

The present invention has been made in view of the above, and an object of the present invention is to realize an interface circuit and a communication device capable of reducing the circuit scale and power consumption.

An interface circuit according to an aspect of the present invention includes a plurality of communication devices, one AD conversion circuit that AD-converts an analog signal into digital data, and the digital data according to read request signals from the plurality of communication devices. And a control circuit for reading.

In this configuration, a plurality of communication devices share the AD conversion circuit. As a result, the circuit scale and power consumption of the interface circuit can be reduced.

A communication device according to one aspect of the present invention includes the interface circuit, a power amplifier circuit that amplifies a high frequency signal, and a sensor that detects the temperature of the power amplifier circuit and outputs the detected value as the analog signal. Prepare

With this configuration, the circuit scale and power consumption of the communication device can be reduced by sharing the AD conversion circuit among a plurality of communication devices.

According to the present invention, it is possible to provide an interface circuit and a communication device capable of reducing the circuit scale and power consumption.

FIG. 3 is a block diagram showing an example of a schematic configuration of an interface circuit according to the embodiment. It is a figure which shows an example of the principal part structure of the communication apparatus which concerns on embodiment. It is a block diagram which shows an example of an internal structure of a starting circuit. 6 is a timing chart showing a basic first operation example of a starting circuit. 7 is a timing chart showing a basic second operation example of the starting circuit. It is a timing chart which shows the basic 3rd example of operation of a starting circuit. 9 is a timing chart showing a basic fourth operation example of the starting circuit. 6 is a timing chart showing a specific first operation example of the interface circuit according to the embodiment. 7 is a timing chart showing a specific second operation example of the interface circuit according to the embodiment. 6 is a timing chart showing a specific third operation example of the interface circuit according to the embodiment. 9 is a timing chart showing a specific fourth operation example of the interface circuit according to the embodiment. 9 is a timing chart showing a specific fifth operation example of the interface circuit according to the embodiment. 9 is a timing chart showing a specific sixth operation example of the interface circuit according to the embodiment. 9 is a timing chart showing a specific seventh operation example of the interface circuit according to the embodiment. 9 is a timing chart showing a specific eighth operation example of the interface circuit according to the embodiment. FIG. 16 is a diagram showing an output target of digital data in each operation example shown in FIGS. 8 to 15. It is a figure which shows the structural example which shares an AD conversion circuit with six communication devices. FIG. 18 is a diagram showing an output target example of digital data in the configuration example shown in FIG. 17.

Hereinafter, the interface circuit and the communication device according to the embodiment will be described in detail with reference to the drawings. The present invention is not limited to this embodiment. It is needless to say that each embodiment is an exemplification, and partial replacements or combinations of the configurations shown in different embodiments are possible. In the second and subsequent embodiments, description of matters common to the first embodiment will be omitted, and only different points will be described. In particular, similar effects obtained by the same configuration will not be sequentially described for each embodiment.

(Embodiment 1)
FIG. 1 is a block diagram showing an example of a schematic configuration of an interface circuit according to the embodiment. FIG. 2 is a diagram illustrating an example of a main configuration of the communication device according to the embodiment. As shown in FIG. 1, the interface circuit 1 includes communication devices 10-1 and 10-2, an AD conversion circuit 20, and a control circuit 30. In the present disclosure, the communication device 10-1 is, for example, a 5 GHz band LTE communication device, and the communication device 10-2 is, for example, a WiFi communication device. Further, in the present disclosure, the AD conversion circuit 20 AD-converts the analog signal A_sig from the sensor 2 into digital data ts_data. In the present disclosure, the sensor 2 and the AD conversion circuit 20 are shared by the two communication devices 10-1 and 10-2. In the following description, since the two communication devices 10-1 and 10-2 and their constituent elements are the same, the two communication devices 10a and 10b and their constituent elements are denoted by reference numerals unless it is necessary to distinguish them. , "-1", "-2", "_1", and "_2" are omitted.

As shown in FIG. 2, when the interface circuit 1 according to the embodiment is applied to the communication device 100, the sensor 2 is, for example, a temperature sensor that detects the temperature of the power amplifier circuit 4 for high frequency amplification. However, the ultrasonic sensor, the infrared sensor, and the shock sensor may be used. Furthermore, the sensor 2 may be an analog circuit, and may be, for example, a voltmeter or an ammeter.

The communication device 10 outputs a read request signal of digital data ts_data obtained by AD-converting the analog signal A_sig which is the detection value of the sensor 2.

The control circuit 30 reads the digital data ts_data from the AD conversion circuit 20 and outputs the digital data ts_data to the communication device 10 in response to a read request signal (a start signal tkick and a capture signal catch described later) output from the communication device 10.

As shown in FIG. 1, the communication device 10-1 includes a communication interface 3-1, a startup circuit 11-1, and a register 12-1. The communication device 10-2 includes a communication interface 3-2, a starting circuit 11-2, and a register 12-2.

In the present disclosure, the communication interface 3-1 is, for example, a serial communication interface in the LTE communication device 10-1 in the 5 GHz band, and the communication interface 3-2 is, for example, the serial communication interface in the WiFi communication device 10-2. Is.

The communication interface 3-1 outputs the read command wr_1 of the digital data ts_data and the communication clock signal clk_1 to the activation circuit 11-1. The communication interface 3-2 outputs the read command wr_2 of the digital data ts_data and the communication clock signal clk_2 to the activation circuit 11-2. In the present disclosure, the communication clock signal clk_1 and the communication clock signal clk_2 are clock signals that are asynchronous with each other. The communication clock signal clk_1 and the communication clock signal clk_2 may be synchronized.

The start-up circuit 11-1 receives the read command wr_1 from the communication interface 3-1 and, based on the read command wr_1, generates and outputs a start signal tkick_1 for generating an enable signal ts_en described later. The enable signal ts_en is a signal output from the control circuit 30 to activate the AD conversion circuit 20. The activation signal tkick_1 is output to the control circuit 30 and the activation circuit 11-2.

The starting circuit 11-2 receives the read command wr_2 from the communication interface 3-2, and based on the read command wr_2, generates and outputs the start signal tkick_2 for generating the enable signal ts_en. The activation signal tkick_2 is output to the control circuit 30 and the activation circuit 11-1.

Further, when the data of the read command wr_1 from the communication interface 3-1 and the activation signal tkick_2 from the activation circuit 11-2 is “1”, the activation circuit 11-1 replaces the activation signal tkick_1 with the AD conversion circuit 20. The capture signal catch_1 for capturing the digital data ts_data from is generated and output. The capture signal catch_1 is output to the control circuit 30.

Further, when the data of the read command wr_2 from the communication interface 3-2 and the activation signal tkick_1 from the activation circuit 11-1 is “1”, the activation circuit 11-2 replaces the activation signal tkick_2 with the AD conversion circuit 20. The capture signal catch_2 for capturing the digital data ts_data from is generated and output. The capture signal catch_2 is output to the control circuit 30.

The control circuit 30 receives the activation signal tkick_1 and the capture signal catch_1 received as the read request signal from the activation circuit 11-1, and the activation signal tkick_2 and the capture signal catch_2 received as the read request signal from the activation circuit 11-2. The AD conversion circuit 20 is controlled based on the above. Further, the control circuit 30 outputs the digital data ts_data AD-converted by the AD conversion circuit 20 to the register 12-1 as the fetched data data_1. Further, the control circuit 30 outputs the digital data ts_data AD-converted by the AD conversion circuit 20 to the register 12-2 as the fetched data data_2.

The register 12-1 outputs the fetched data data_1 from the control circuit 30 to the communication interface 3-1.

The register 12-2 outputs the fetched data data_2 from the control circuit 30 to the communication interface 3-2.

Next, the basic operation of the starting circuit 11-1 and the starting circuit 11-2 will be described. FIG. 3 is a block diagram showing an example of the internal configuration of the starting circuit. FIG. 4 is a timing chart showing a basic first operation example of the starting circuit. FIG. 5 is a timing chart showing a basic second operation example of the starting circuit. FIG. 6 is a timing chart showing a basic third operation example of the starting circuit. FIG. 7 is a timing chart showing a basic fourth operation example of the starting circuit. FIG. 4 shows an example in which the read command wr_1 is output from the communication interface 3-1. FIG. 5 shows an example in which the read command wr_2 is output from the communication interface 3-2 during the predetermined period P′ after the read command wr_1 is output from the communication interface 3-1. FIG. 6 shows an example in which the read command wr_2 is output from the communication interface 3-2 after the predetermined period P′. FIG. 7 shows an example in which the read command wr_2 is output from the communication interface 3-2 in the two-cycle period of the communication clock signal clk_2 after the read command wr_1 is output from the communication interface 3-1.

As shown in FIG. 4, when the control signal generation circuit 111-1 of the activation circuit 11-1 receives the read command wr_1 from the communication interface 3-1, the activation signal tkick_1 is synchronized with the rising edge of the communication clock signal clk_1. The data value of is set to "1".

The synchronization circuit 112-2 of the activation circuit 11-2 sets the data value of the activation synchronization signal sync_tkick_1 to "1" in synchronization with the rise of the activation signal tkick_1 after two cycles of the communication clock signal clk_2.

After the elapse of the predetermined period P, the control signal generation circuit 111-1 sets the data value of the activation signal tkick_1 to “0” in synchronization with the rising of the activation reset signal tkick_1_rst output from the control circuit 30.

The synchronization circuit 112-2 sets the data value of the activation synchronization signal sync_tkick_1 to "0" in synchronization with the rise of the activation clock tkick_1 after two cycles of the communication clock signal clk_2.

Further, as shown in FIG. 5, the control signal generation circuit 111-2 of the start-up circuit 11-2 outputs the control signal from the communication interface 3-2 during the predetermined period P′ in which the data value of the start-up synchronization signal sync_tkick_1 is “1”. When receiving the read command wr_2, the data value of the capture signal catch_2 is set to "1" in synchronization with the rising edge of the communication clock signal clk_2. After that, the control signal generation circuit 111-2 sets the data value of the capture signal catch_2 to “0” in synchronization with the rising edge of the capture reset signal catch_rst output from the control circuit 30.

Further, as shown in FIG. 6, the control signal generation circuit 111-2 has a predetermined period P in which the data value of the activation signal tkick_1 is “1” and a predetermined period P in which the data value of the activation synchronization signal sync_tkick_1 is “1”. When the read command wr_2 is received from the communication interface 3-2 in a period that is not included in any of', the data value of the activation signal tkick_2 is set to "1" in synchronization with the rising edge of the communication clock signal clk_2.

As shown in FIG. 7, the control signal generation circuit 111-2 uses the communication clock from when the data value of the activation signal tkick_1 becomes “1” to when the data value of the activation synchronization signal sync_tkick_1 becomes “1”. When the read command wr_2 is received from the communication interface 3-2 in the 2-cycle period of the signal clk_2, the data value of the activation signal tkick_2 is set to "1" in synchronization with the rising edge of the communication clock signal clk_2. Then, the control signal generation circuit 111-2 sets the data value of the activation signal tkick_2 to “0” in synchronization with the rising of the activation reset signal tkick_2_rst output from the control circuit 30 after the lapse of the predetermined period p.

The synchronization circuit 112-1 sets the data value of the activation synchronization signal sync_tick_2 to “0” in synchronization with the rise of the activation signal tkick_2 after two cycles of the communication clock signal clk_1.

Next, a specific operation of the interface circuit 1 according to the embodiment will be described. FIG. 8 is a timing chart showing a specific first operation example of the interface circuit according to the embodiment. FIG. 9 is a timing chart showing a specific second operation example of the interface circuit according to the embodiment. FIG. 10 is a timing chart showing a specific third operation example of the interface circuit according to the embodiment. FIG. 11 is a timing chart showing a specific fourth operation example of the interface circuit according to the embodiment. FIG. 12 is a timing chart showing a specific fifth operation example of the interface circuit according to the embodiment. FIG. 13 is a timing chart showing a specific sixth operation example of the interface circuit according to the embodiment. FIG. 14 is a timing chart showing a specific seventh operation example of the interface circuit according to the embodiment. FIG. 15 is a timing chart showing a specific eighth operation example of the interface circuit according to the embodiment. FIGS. 8 to 11 show diagrams starting from the point in time when the read command wr_1 is output from the communication interface 3-1 and the data value of the activation signal tkick_1 becomes “1”. 12 to 15 show diagrams starting from the point in time when the read command wr_2 is output from the communication interface 3-2 and the data value of the activation signal tkick_2 becomes “1”.

In the present disclosure, the clock cycles of the communication clock signal clk_1 and the communication clock signal clk_2 are considered to be sufficiently smaller than the clock cycle of the sampling clock signal ts_clk in the AD conversion circuit 20. That is, the predetermined periods P, P', p, p'shown in FIGS. 4 to 7 are considered to be substantially equal. Further, as illustrated in FIGS. 8 to 15, in the present disclosure, the AD conversion circuit includes a period including 10 clock cycles of the sampling clock signal ts_clk after the data value of the activation signal tkick_1 or the activation signal tkick_2 becomes “1”. 20 is a “waiting period P1”, a period including eight clock cycles of the sampling clock signal ts_clk after the waiting period P1 is a total period of the “AD conversion period P2”, the waiting period P1 and the AD conversion period P2 in the AD conversion circuit 20. , The AD conversion circuit 20 is set to be “operating period P0”. The control circuit 30 has a function of counting the sampling clock signal ts_clk in the AD conversion circuit 20. The waiting period P1 corresponds to the predetermined periods P, P', p, p'shown in FIGS. 4 to 7.

Note that the number of clock cycles included in the standby period P1 and the number of clock cycles included in the AD conversion period P2 are examples, and are not limited to the above. For example, the number of clock cycles included in the waiting period P1 may be the number of clock cycles that ensures the time until the AD conversion in the AD conversion circuit 20 becomes stable. Further, although the present embodiment exemplifies the case where the digital data ts_data in the AD conversion circuit 20 is 8-bit data, for example, when the digital data ts_data in the AD conversion circuit 20 is 12-bit data, the AD conversion period It suffices for P2 to have a mode including 12 clock cycles of the sampling clock signal ts_clk. The present disclosure is not limited by the number of clock cycles included in the standby period P1 and the number of clock cycles included in the AD conversion period P2.

In FIG. 8 to FIG. 11, when the read command wr_1 is output from the communication interface 3-1 and the data value of the activation signal tkick_1 output from the activation circuit 11-1 becomes “1”, the standby period P1, AD An example is shown in which counting of the conversion period P2 and the operation period P0 is started. That is, in the example shown in FIGS. 8 to 11, the digital data ts_data after AD conversion is fetched into the register 12-1 as fetched data data_1 based on the read command wr_1 from the communication interface 3-1.

The control circuit 30 starts the output of the sampling clock signal ts_clk in the AD conversion circuit 20 and sets the data value of the enable signal ts_en to “1” when the data value of the activation signal tkick_1 becomes “1”, and the sampling value is set to “1”. The counting of the clock signal ts_clk is started.

When 10 clock cycles of the sampling clock signal ts_clk elapse in the standby period P1, the control circuit 30 sets the data value of the AD conversion command xTCONV to “1” and starts in synchronization with the falling edge of the sampling clock signal ts_clk. The reset signal tkick_1_rst is output. As a result, the data value of the activation signal tkick_1 is reset to "0".

The AD conversion circuit 20 AD-converts the analog signal A_sig from the sensor 2 into digital data ts_data in eight clock cycles of the sampling clock signal ts_clk in the subsequent AD conversion period P2.

When eight clock cycles of the sampling clock signal ts_clk elapse in the AD conversion period P2, the control circuit 30 reads the AD-converted digital data ts_data from the AD conversion circuit 20, and outputs the digital data ts_data to the register 12-1 as the captured data data_1. .. Further, the control circuit 30 sets the data value of the enable signal ts_en and the AD conversion command xTCONV to “0” in synchronization with the falling edge of the sampling clock signal ts_clk.

In the example illustrated in FIGS. 8 and 9, in the standby period P1, the data value of the activation signal tkick_2 output from the activation circuit 11-2 is “0”, that is, the read instruction wr_2 is output from the communication interface 3-2. Absent. In this case, the control circuit 30 does not output the digital data ts_data after AD conversion to the register 12-2.

FIG. 9 illustrates an example in which the data value of the activation signal tkick_2 output from the activation circuit 11-2 is “1”, that is, the read instruction wr_2 is output from the communication interface 3-2 in the AD conversion period P2. .. In this case, the control circuit 30 starts counting 10 clock cycles of the sampling clock signal ts_clk in the new waiting period P1 when the data value of the activation signal tkick_2 becomes “1”. Further, in this case, the control circuit 30 maintains the data value “1” of the enable signal ts_en.

FIG. 10 shows an example in which the data value of the capture signal catch_2 output from the activation circuit 11-2 is “1”, that is, the read command wr_2 is output from the communication interface 3-2 in the standby period P1. .. In this case, the control circuit 30 outputs the digital data ts_data after AD conversion as the taken-in data data_1 to the register 12-1 and also as the taken-in data data_2 to the register 12-2.

Further, in the AD conversion period P2, when 8 clock cycles of the sampling clock signal ts_clk elapse, the control circuit 30 synchronizes the data value of the enable signal ts_en and the AD conversion command xTCONV in synchronization with the fall of the sampling clock signal ts_clk. At the same time, the fetch reset signal catch_rst is output. As a result, the data value of the capture signal catch_2 is reset to "0".

In FIG. 11, an example in which the data value of the activation signal tkick_1 output from the activation circuit 11-1 is “1” and the data value of the activation signal tkick_2 output from the activation circuit 11-2 is “1” at the same time Shows. Here, when the data value of the activation signal tkick_1 and the data value of the activation signal tkick_2 simultaneously become “1”, as shown in FIG. 7, the data value of the activation signal tkick_1 becomes “1” This indicates that the read command wr_2 from the communication interface 3-2 is input during the two-cycle period of the communication clock signal clk_2 until the data value of the synchronization signal sync_tkick_1 becomes "1". In this case, the control circuit 30 outputs the digital data ts_data after AD conversion as the taken-in data data_1 to the register 12-1 and also as the taken-in data data_2 to the register 12-2.

In FIGS. 12 to 15, when the read command wr_2 is output from the communication interface 3-2 and the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes “1”, the standby period P1, AD An example is shown in which counting of the conversion period P2 and the operation period P0 is started. That is, in the examples shown in FIGS. 12 to 15, the digital data ts_data after AD conversion is fetched into the register 12-2 as the fetched data data_2 based on the read command wr_2 from the communication interface 3-2.

The control circuit 30 starts outputting the sampling clock signal ts_clk in the AD conversion circuit 20 and sets the data value of the enable signal ts_en to “1” when the data value of the activation signal tkick_2 becomes “1”, The counting of the clock signal ts_clk is started.

When 10 clock cycles of the sampling clock signal ts_clk elapse in the standby period P1, the control circuit 30 sets the data value of the AD conversion command xTCONV to “1” and starts in synchronization with the falling edge of the sampling clock signal ts_clk. The reset signal tkick_2_rst is output. As a result, the data value of the activation signal tkick_2 is reset to "0".

The AD conversion circuit 20 AD-converts the analog signal A_sig from the sensor 2 into digital data ts_data in eight clock cycles of the sampling clock signal ts_clk in the subsequent AD conversion period P2.

When eight clock cycles of the sampling clock signal ts_clk elapse during the AD conversion period P2, the control circuit 30 reads the AD-converted digital data ts_data from the AD conversion circuit 20 and outputs it as the captured data data_2 to the register 12-2. .. Further, the control circuit 30 sets the data values of the enable signal ts_en and the AD conversion command xTCONV to “0” in synchronization with the falling edge of the sampling clock signal ts_clk.

In the example illustrated in FIGS. 12 and 13, in the standby period P1, the data value of the activation signal tkick_1 output from the activation circuit 11-1 is “0”, that is, the read instruction wr_1 is output from the communication interface 3-1. Absent. In this case, the control circuit 30 does not output the digital data ts_data after AD conversion to the register 12-1.

FIG. 13 shows an example in which the data value of the activation signal tkick_1 output from the activation circuit 11-1 is “1”, that is, the read command wr_1 is output from the communication interface 3-1 in the AD conversion period P2. .. In this case, the control circuit 30 starts counting 10 clock cycles of the sampling clock signal ts_clk in the new waiting period P1 when the data value of the activation signal tkick_1 becomes “1”. Further, in this case, the control circuit 30 maintains the data value “1” of the enable signal ts_en.

FIG. 14 illustrates an example in which the data value of the capture signal catch_1 output from the activation circuit 11-1 is “1”, that is, the read command wr_1 is output from the communication interface 3-1 in the standby period P1. .. In this case, the control circuit 30 outputs the AD-converted digital data ts_data as the capture data data_2 to the register 12-2 and also outputs the capture data data_1 to the register 12-1.

Further, in the AD conversion period P2, when 8 clock cycles of the sampling clock signal ts_clk elapse, the control circuit 30 synchronizes the data value of the enable signal ts_en and the AD conversion command xTCONV in synchronization with the fall of the sampling clock signal ts_clk. At the same time, the fetch reset signal catch_rst is output. As a result, the data value of the capture signal catch_1 is reset to "0".

In FIG. 15, an example in which the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes “1” and the data value of the activation signal tkick_1 output from the activation circuit 11-1 becomes “1” at the same time. Shows. In this case, the control circuit 30 outputs the AD-converted digital data ts_data as the capture data data_2 to the register 12-2 and also outputs the capture data data_1 to the register 12-1.

FIG. 16 is a diagram showing an output target of digital data in each operation example shown in FIGS. 8 to 15. As illustrated in FIG. 16, the control circuit 30 sets the communication device 10-1 as the output target of the digital data ts_data when the data value of the activation signal tkick_1 output from the activation circuit 11-1 becomes “1”. Set. Further, the control circuit 30 outputs from the activation circuit 11-2 during the standby period P1 of the AD conversion circuit 20 immediately after the data value of the activation signal tkick_1 output from the activation circuit 11-1 becomes “1”. When the data value of the capture signal catch_2 becomes “1”, the communication device 10-2 is set as the output target of the digital data ts_data.

As shown in FIG. 16, the control circuit 30 outputs the digital data ts_data to the communication device 10-2 when the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes “1”. Set as the target. Further, the control circuit 30 outputs from the activation circuit 11-1 in the standby period P1 of the AD conversion circuit 20 immediately after the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes “1”. When the data value of the capture signal catch_1 becomes “1”, the communication device 10-1 is set as the output target of the digital data ts_data.

In FIG. 15, the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes “1”, and at the same time, the data value of the activation signal tkick_1 output from the activation circuit 11-1 becomes “1”. Although an example is shown, in FIG. 16, the data value of the activation signal tkick_1 output from the activation circuit 11-1 becomes “1”, and at the same time, the data value of the activation signal tkick_2 output from the activation circuit 11-2 becomes “1”. In the case of “1”, the control circuit 30 outputs the AD-converted digital data ts_data as the capture data data_1 to the register 12-1 and the capture data data_2 to the register 12-2.

In the present embodiment, as described above, since the AD conversion circuit 20 is shared by the two communication devices 10-1 and 10-2, the circuit scale and power consumption of the communication device 100 can be reduced. Specifically, this embodiment is different from the configuration in which an analog circuit and an AD conversion circuit are provided for each communication device (that is, a configuration including a plurality of analog circuits, a plurality of AD conversion circuits, and a plurality of communication devices). Then, the AD conversion circuit 20 is shared by the two communication devices 10-1 and 10-2. By reducing the number of AD conversion circuits, the circuit area can be reduced. Further, by reducing the number of AD conversion circuits, it is possible to reduce the power consumed by the plurality of AD conversion circuits.

In addition, it is possible to shorten the time required to read the digital data ts_data. Specifically, in the present embodiment, not only one AD conversion circuit is shared, but also a control circuit for reading digital data according to a read request signal from a plurality of communication devices is provided. By simply sharing the AD conversion circuit, after the operation of one communication device is completed, the operation of another communication device is started. As a result, the operation period of the AD conversion circuit requires the number of communication devices. However, in the embodiment of the present application, the operation period of the AD conversion circuit 20 is shortened by controlling the control circuit as described above.

In addition, in the above-described embodiment, an example in which the AD conversion circuit 20 is shared by the two communication devices 10-1 and 10-2 has been described, but the AD conversion circuit 20 is shared by three or more communication devices. Is also possible.

FIG. 17 is a diagram illustrating a configuration example in which an AD conversion circuit is shared by six communication devices. FIG. 18 is a diagram showing an output target example of digital data in the configuration example shown in FIG.

In the configuration example illustrated in FIG. 17, as illustrated in Example 1 of FIG. 18, the communication device 10-1 outputs the activation signal tkick_1 and the communication device 10-5 outputs the capture signal catch_5 in the standby period P1. In this case, the control circuit 30 sets the communication device 10-1 and the communication device 10-5 as output targets of the digital data ts_data.

Further, in the configuration example illustrated in FIG. 17, as illustrated in Example 2 in FIG. 18, the communication device 10-4 outputs the activation signal tkick_4, and the communication device 10-1 outputs the capture signal catch_1 in the standby period P1. When the capture signal catch_6 is output from the communication device 10-6, the control circuit 30 sets the communication device 10-1, the communication device 10-4, and the communication device 10-6 as the output target of the digital data ts_data. To do.

In the configuration example illustrated in FIG. 17, the activation signal tkick_2 is output from the communication device 10-2 and the acquisition signal catch_3 is output from the communication device 10-3 in the standby period P1 as illustrated in Example 3 in FIG. 18. When the capture signal catch_5 is output from the communication device 10-5, the control circuit 30 sets the communication device 10-2, the communication device 10-3, and the communication device 10-5 as output targets of the digital data ts_data. To do.

Further, in the configuration example illustrated in FIG. 17, as illustrated in Example 4 in FIG. 18, the communication device 10-5 outputs the activation signal tkick_5, and the communication device 10-1 outputs the capture signal catch_1 in the standby period P1. When the communication device 10-2 outputs the capture signal catch_2 and the communication device 10-6 outputs the capture signal catch_6, the control circuit 30 controls the communication device 10-1, the communication device 10-2, and the communication device 10-2. The device 10-5 and the communication device 10-6 are set as output targets of the digital data ts_data.

Further, in the configuration example shown in FIG. 17, when the activation signal tkick_3 and the activation signal tkick_6 are simultaneously output from the communication device 10-3 and the communication device 10-6, as shown in Example 5 of FIG. , The communication device 10-3 and the communication device 10-6 are set as output targets of the digital data ts_data.

As described above, in the interface circuit 1 according to the embodiment, the AD conversion circuit 20 can be shared by the plurality of communication devices 10. As a result, the circuit scale and power consumption of the communication device 100 can be reduced. In addition, the time taken to read the data can be shortened.

The above-described embodiments are for facilitating the understanding of the present invention and are not for limiting the interpretation of the present invention. The present invention can be modified/improved without departing from the spirit thereof and includes the equivalents thereof.

Further, the present disclosure may have the following configurations as described above or instead of the above.

(1) An interface circuit according to one aspect of the present invention includes: a plurality of communication devices; one AD conversion circuit that AD-converts an analog signal into digital data; and a read request signal from the plurality of communication devices. And a control circuit for reading digital data.

In the configuration in which each of the plurality of communication devices is provided with the AD conversion circuit, the current consumption of the plurality of AD conversion circuits is required. In the above configuration, the AD conversion circuit is shared by the plurality of communication devices. As a result, the circuit scale and power consumption of the interface circuit can be reduced as compared with the configuration in which the AD conversion circuit is provided for each of the plurality of communication devices.

(2) In the interface circuit according to (1), the control circuit instructs the first communication device among the plurality of communication devices to receive a read request signal from the first communication device. The digital data is output, and when the read request signal of the second communication device different from the first communication device is received, the digital data is output to the second communication device.

With this configuration, the AD conversion circuit can be shared by a plurality of communication devices.

(3) In the interface circuit according to (1), the control circuit requires a waiting period after the AD conversion circuit receives a read request signal from the first communication device among the plurality of communication devices. When the read request signal from the second communication device different from the first communication device is received during the standby period, the digital data is output to the second communication device.

By simply sharing the AD conversion circuit, after the operation of one communication device is completed, the operation of another communication device is started. As a result, the operation period of the AD conversion circuit requires the number of communication devices. With the interface circuit of this configuration, the time taken to read data can be shortened by the above processing.

(4) In the interface circuit of (1) above, the communication device outputs a communication command that outputs a read command for the digital data, and a start signal for starting the AD conversion circuit according to the read command, or And a start-up circuit for generating a capture signal for capturing the digital data as the read request signal, the communication device comprising a first communication device and a second communication device different from the first communication device. And a start-up circuit of the second communication device, wherein the AD conversion circuit requires a waiting period after the start-up signal is output from the starting circuit of the first communication device. , The capture signal is output when the read command output from the communication interface of the second communication device is received.

With this configuration, digital data is simultaneously output to both the communication device that has output the activation signal and the communication device that has output the capture signal during the standby period. As a result, the time required to read the data can be shortened. Further, the circuit scale of the starting circuit can be reduced.

(5) A communication device according to one aspect of the present invention detects the temperature of the interface circuit according to any one of (1) to (4), a power amplifier circuit that amplifies a high frequency signal, and the temperature of the power amplifier circuit, A sensor that outputs the detected value as the analog signal.

In the interface circuit configured to include the AD conversion circuit for each of the plurality of communication devices, the current consumption of the plurality of AD conversion circuits is consumed. In the configuration using the interface circuit of this configuration in which the plurality of communication devices share the AD conversion circuit, the circuit scale and the power consumption of the interface circuit are reduced as compared with the configuration in which each of the plurality of communication devices is provided with the AD conversion circuit. can do. Therefore, the circuit scale and power consumption of the communication device can be reduced. Further, if the AD conversion circuit is simply shared, the operation of one communication device is completed and then the operation of another communication device is started. As a result, the operation period of the AD conversion circuit requires the number of communication devices. In the configuration using the interface circuit of this configuration, the time required for reading data can be shortened by the above processing.

According to the present disclosure, the circuit scale and power consumption can be reduced, and further, the time taken to read data can be shortened.

DESCRIPTION OF SYMBOLS 1 Interface circuit 2 Sensor 3-1 and 3-2 Communication interface 4 Power amplifier circuit 10,10-1,10-2,10-3,10-4,10-5,10-6 Communication device 11-1,11 -2 starter circuit 12-1, 12-2 register 20 AD conversion circuit 30 control circuit 100 communication device 111-1, 111-2 control signal generation circuit 112-1, 112-2 synchronization circuit

Claims (5)

Multiple communication devices,
One AD conversion circuit for AD converting an analog signal into digital data,
A control circuit for reading the digital data in response to a read request signal from the plurality of communication devices;
An interface circuit including. The interface circuit according to claim 1, wherein
The control circuit is
When a read request signal is received from the first communication device among the plurality of communication devices, the digital data is output to the first communication device, and the first communication device is different from the first communication device. An interface circuit that outputs the digital data to the second communication device when a read request signal from the second communication device is received. The interface circuit according to claim 1, wherein
The control circuit is
Of the plurality of communication devices, the AD conversion circuit requires a waiting period after receiving a read request signal from the first communication device, and in the waiting period, a second communication device different from the first communication device is used. An interface circuit that outputs the digital data to the second communication device when receiving a read request signal from the communication device. The interface circuit according to claim 1, wherein
The communication device is
A communication interface that outputs a read command of the digital data,
A start-up circuit for generating, as the read-out request signal, a start-up signal for starting up the AD conversion circuit or a take-in signal for taking in the digital data in accordance with the read command;
Equipped with
The communication device is
A first communication device and a second communication device different from the first communication device,
The starting circuit of the second communication device comprises:
The AD conversion circuit requires a waiting period after the starting signal is output from the starting circuit of the first communication device, and the read command output from the communication interface of the second communication device in the waiting period. An interface circuit that outputs the acquisition signal when receiving the. An interface circuit according to any one of claims 1 to 4,
A power amplifier circuit that amplifies high frequency signals,
A sensor that detects the temperature of the power amplifier circuit and outputs the detected value as the analog signal;
A communication device including.

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