JP2020068250A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

To provide a semiconductor device manufacturing method and a semiconductor device which are suitable for achieving a multilayered semiconductor element.SOLUTION: A semiconductor device manufacturing method of the present invention includes steps of: preparing a wafer 11 and a reinforcement wafer 12R having a laminated structure of a wafer 12/a temporary adhesive layer 13/a support substrate S; bonding the wafer 12 of the reinforcement wafer 12R to a surface 11a of the wafer 11 through an adhesive layer 21; forming a resin layer 31 on a surface 11b of the wafer 11; and detaching the support substrate S from the reinforcement wafer 12R that has been subjected to the step of bonding. A semiconductor device of the present invention has a laminated structure including wafers 11, 12, an adhesive layer 21 and a resin layer 31. The wafer 11 has surfaces 11a, 11b. The wafer 12 is located on a surface 11a side of the wafer 11 and is thinner than the wafer 11. The adhesive layer 21 is interposed between the wafers 11, 12. The resin layer 31 is in close contact with the surface 11b of the wafer 11.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  In recent years, mainly for the purpose of further increasing the density of semiconductor devices, development of a technique for manufacturing a semiconductor device having a three-dimensional structure in which a plurality of semiconductor chips or semiconductor elements are integrated in the thickness direction has been advanced. ing. A so-called WOW (Wafer on Wafer) process is known as one of such techniques. In the WOW process, a series of steps including a step of bonding and laminating a wafer to another wafer via an adhesive layer and various processing steps for the laminated wafer are performed a predetermined number of times. . In the wafer bonding process, for example, a thin wafer obtained through a transistor manufacturing process, a wiring forming process, and a thinning process may be stacked on a thick base wafer, or another thin wafer already stacked on the base wafer after the wafer bonding process. The thin wafer is bonded and laminated via an adhesive layer. A wafer laminated body obtained by laminating a predetermined number of wafers is singulated into semiconductor devices having a structure in which a plurality of semiconductor chips are laminated. It is done by cutting. Such WOW process is described in, for example, Patent Documents 1 to 3 below.

JP-A-2015-73128 JP, 2015-119111, A JP, 2015-164160, A

  In the WOW process, for example, as described above, when wafers having different thicknesses are bonded to each other via the adhesive layer, this bonding is achieved through a predetermined high temperature condition for curing the adhesive layer. . Further, the thermal expansion coefficient of the adhesive layer after curing is larger than the thermal expansion coefficient of the wafer, and the difference between the two thermal expansion coefficients is considerably large. Therefore, for example, in a wafer stack that has reached room temperature after the wafer bonding process, warpage is likely to occur due to the difference in coefficient of thermal expansion between the wafer and the adhesive layer. Specifically, an adhesive layer that hardens between a thick base wafer and a thin wafer to be laminated thereon under a predetermined high temperature condition to bond the wafers together is, for example, However, for example, in a wafer stack that has reached room temperature, the edge of the stack tends to warp to the side of a thin wafer whose resistance to shrinkage of the adhesive layer is smaller than that of the base wafer. The degree of this warpage tends to increase as the number of wafers laminated via the adhesive layer decreases, and also tends to increase cumulatively as the number of thin wafers laminated increases. Since there is an upper limit on the degree of warpage that can be allowed for each of various processing steps for a wafer stack, according to the WOW process, the number of stackable wafers, that is, semiconductors that can be multilayered in a semiconductor device for manufacturing purposes. The total number of elements will be limited by the upper limit.

  The present invention has been devised under the circumstances described above, and provides a semiconductor device manufacturing method and a semiconductor device suitable for increasing the number of layers of semiconductor elements.

  According to a first aspect of the present invention, a method for manufacturing a semiconductor device is provided. This semiconductor device manufacturing method includes a preparing step, a wafer bonding step, a resin layer forming step, and a removing step. In the preparing step, the first wafer and the reinforcing second wafer are prepared. The first wafer has a first surface and a second surface opposite to the first surface. The reinforcing second wafer has a laminated structure including a second wafer thinner than the first wafer, a supporting substrate for reinforcement, and a temporary adhesive layer between the second wafer and the supporting substrate. The temporary adhesive layer on the reinforced second wafer is for realizing a temporary adhesive state between the second wafer and the supporting substrate that can be released afterwards. In the wafer bonding step, the second wafer of the reinforcing second wafer is bonded to the first surface of the first wafer via the adhesive layer. This joining is realized, for example, under a predetermined high temperature condition for curing the adhesive layer. Prior to such a wafer bonding step, the first surface of the first wafer and / or the planned surface of the second wafer to be bonded in the reinforcing second wafer is for improving the adhesiveness with the adhesive layer to be formed. Surface treatment such as silane coupling agent treatment may be applied. In the resin layer forming step after the wafer bonding step, the resin layer is formed on the second surface of the first wafer. The resin layer is made of, for example, a curable material, and as the constituent material of the resin layer, for example, an adhesive having the same composition as the adhesive for forming the above-mentioned adhesive layer for wafer bonding may be used. The resin layer is formed, for example, under a predetermined high temperature condition for curing the resin layer. Prior to such a resin layer forming step, the second surface of the first wafer may be subjected to a surface treatment such as a silane coupling agent treatment for improving the adhesion with the resin layer to be formed. Then, in the removal step, the temporary adhesion state of the temporary adhesive layer between the support substrate and the second wafer is released, and the support substrate is removed.

  In the above-mentioned wafer bonding step in the present semiconductor device manufacturing method, the relatively thin second wafer in which the supporting substrate is bonded via the temporary adhesive layer is bonded to the relatively thick first wafer by the adhesive. Bonded through layers. In a wafer stack including the first and second wafers (including the supporting substrate bonded to the second wafer) obtained through such a wafer bonding process, for example, when the temperature is lowered to room temperature, the cured adhesive The resistance of the second wafer itself to shrinkage of the layer is less than the resistance of the first wafer to shrinkage of the adhesive layer, since the second wafer is thinner than the first wafer. However, the support substrate bonded to the second wafer may supplement the second wafer for resistance to shrinkage of the cured adhesive layer. Even if the difference in thickness between the first and second wafers is large, and the resistance of the second wafer itself to shrinkage of the adhesive layer after curing is significantly smaller than the resistance of the first wafer, The support substrate bonded to the side of the second wafer opposite to the side of the first wafer can supplement the second wafer for resistance to shrinkage of the adhesive layer after curing. Therefore, in the wafer stack (with the supporting substrate bonded to the second wafer), the difference in the coefficient of thermal expansion between the first and second wafers and the adhesive layer and the difference between the two wafers and the adhesive layer. The occurrence of warpage due to the asymmetrical laminated structure is suppressed.

  In addition, in the present semiconductor device manufacturing method, as described above, the resin layer is formed on the second surface of the first wafer before the step of separating and removing the supporting substrate from the second wafer (removing step). The step (resin layer forming step) is performed. In the wafer laminate at room temperature, for example, through the resin layer forming step and the subsequent removing step, the shrinkage stress of the cured adhesive layer acts on the first surface of the first wafer, and The shrinkage stress of the cured resin layer acts on the second surface (second surface opposite to the first surface) of the first wafer. Therefore, even if the difference between the thicknesses of the first and second wafers is large and the resistance of the second wafer to the shrinkage of the adhesive layer after curing is considerably smaller than the resistance of the first wafer, The contraction stress of the adhesive layer after curing which acts on the first surface of the first wafer (acts so as to deform the end of the first wafer toward the first surface) is applied to the second surface of the first wafer. It is possible to reduce or offset by the shrinkage stress of the resin layer after curing which acts on the surface. Therefore, the above-described configuration in which the resin layer forming step and the subsequent removing step are performed is performed by the relatively thick first wafer, the relatively thin second wafer, and the space between the first and second wafers. It is suitable for suppressing the occurrence of warpage after the removal step in the wafer laminated body including the adhesive layer.

  As described above, the present semiconductor device manufacturing method is suitable for suppressing the occurrence of warpage in the wafer stack during the manufacturing process. Then, the smaller the degree of warpage in the wafer stack during the manufacturing process, the easier it is to perform various types of processing on the wafer stack with high accuracy, and the multilayer structure of the wafer stack, and thus the semiconductor element in the manufactured semiconductor device. It is easy to make multiple layers. Therefore, the present semiconductor device manufacturing method is suitable for increasing the number of layers of semiconductor elements.

  This semiconductor device manufacturing method preferably further includes at least one wafer addition step, at least one resin layer addition step performed for each wafer addition step, and at least one removal step performed for each wafer addition step. Including. In the wafer adding step, the second wafer in the reinforcing second wafer having a laminated structure including a second wafer thinner than the first wafer, a supporting substrate for reinforcement, and a temporary adhesive layer between the second wafer and the supporting substrate. The wafer is bonded to another second wafer on the first wafer via an adhesive layer. Another second wafer on the first wafer is the second wafer bonded to the first surface of the first wafer in the above-described wafer bonding step, or additionally on the first wafer in the preceding wafer adding step. It is a laminated second wafer. The temporary adhesive layer on the reinforced second wafer is for realizing a temporary adhesive state between the second wafer and the supporting substrate that can be released afterwards. Bonding in the wafer addition step is realized, for example, under a predetermined high temperature condition for curing the adhesive layer. Prior to such a wafer adding step, the planned joining surface of the second wafer on the first wafer and / or the planned joining surface of the second wafer on the reinforcing second wafer is in close contact with the adhesive layer to be formed. A surface treatment such as a silane coupling agent treatment for improving the properties may be performed. In the resin layer adding step after the wafer adding step, the additional resin layer is formed on the resin layer on the second surface side of the first wafer. The resin layer is made of, for example, a curable material, and as a constituent material of the resin layer, for example, an adhesive having the same composition as the adhesive for forming the adhesive layer for wafer bonding may be used. The resin layer is formed, for example, under a predetermined high temperature condition for curing the resin layer. By such a resin layer addition step, a multilayer resin portion including a plurality of resin layers stacked in the thickness direction of the first wafer and being in close contact with the second surface is formed. The number of resin layers included in this multilayer resin portion is the same as the total number of adhesive layers between the wafers. Prior to such a resin layer adding step, the surface of the resin layer on the second surface side of the first wafer is subjected to a surface treatment such as a silane coupling agent treatment for improving the adhesion with the resin layer to be additionally formed. May be given. Then, in the removal step after the resin layer addition step, the temporary adhesion state by the temporary adhesive layer between the support substrate and the second wafer in the reinforcing second wafer that has undergone the wafer addition step is released and the support substrate is removed. Done.

  In the above-mentioned wafer addition step in the present semiconductor device manufacturing method, the second wafer joined to the relatively thick first wafer through the adhesive layer in the above-mentioned wafer joining step or the preceding wafer adding step is used. A relatively thin new second wafer in which the support substrate is bonded via the temporary adhesive layer is bonded via the new adhesive layer. In a wafer stack including a first wafer and a plurality of second wafers (including a supporting substrate bonded to the second wafer stacked most later) obtained through such a wafer adding step, for example, at room temperature. When the temperature is lowered, the resistance of each second wafer itself to shrinkage of each cured adhesive layer is smaller than that of the first wafer to shrinkage of the adhesive layer because each second wafer is thinner than the first wafer. ,small. However, the support substrate in the reinforced second wafer may supplement each second wafer for resistance to shrinkage of each cured adhesive layer. Even if the difference between the thicknesses of the first and second wafers is large, and the resistance of the second wafers themselves against shrinkage of the adhesive layers after curing is considerably smaller than the resistance of the first wafer. Even so, the support substrate in the reinforced second wafer can supplement each second wafer for resistance to shrinkage of each adhesive layer after curing. Therefore, in the wafer stack obtained through the respective wafer adding steps (with the supporting substrate bonded to the second wafer stacked last), the first wafer and the plurality of second wafers exhibiting different thermal expansion coefficients from each other. The occurrence of warpage due to the predetermined asymmetrical laminated structure of the wafer and the plurality of adhesive layers is suppressed.

  In addition, in the above-described preferable configuration of the present semiconductor device manufacturing method, the first wafer is provided before the step (removing step) in which the supporting substrate is separated and removed from the second wafer in the reinforcing second wafer that has undergone the wafer adding step. A step of forming an additional resin layer on the resin layer on the second surface side (resin layer adding step) is performed. In the wafer laminate at room temperature, for example, through the resin layer adding step and the subsequent removing step, the shrinkage stress of each adhesive layer located on the first surface side of the first wafer is directly or It acts on the first surface of the first wafer indirectly, and acts on the second surface of the first wafer due to the combined shrinkage stress of the resin layers of the multilayer resin portion that are in close contact with the second surface of the first wafer. To do. The total number of adhesive layers on the first surface side of the first wafer and the total number of resin layers on the second surface side of the wafer stack during the manufacturing process without the supporting substrate of the reinforcing second wafer. Is the same as. Therefore, even if the difference between the thicknesses of the first and second wafers is large and the resistance of each second wafer to the contraction of each adhesive layer after curing is considerably smaller than the resistance of the first wafer. However, the total contraction stress of each adhesive layer that acts on the first surface side of the first wafer (acts so as to deform the end portion of the first wafer toward the first surface side) is It is possible to reduce or cancel by the total shrinkage stress of each resin layer acting on the second surface side of the wafer. Therefore, in the above-described configuration in which the resin layer adding step and the subsequent removing step are performed for each wafer adding step, the relatively thick first wafer and the plurality of relatively thin second wafers are respectively provided. It is suitable for suppressing the occurrence of warpage after a removal step in a wafer laminated body including a plurality of adhesive layers interposed between wafers.

  As described above, the above-described preferable configuration of the present semiconductor device manufacturing method is suitable for suppressing the occurrence of warpage in a wafer stack during a manufacturing process in which wafers are multi-layered. In the WOW process, as the number of stacked wafers increases, the degree of warp of the wafer stack tends to increase cumulatively. However, the above-described preferable configuration of the present semiconductor device manufacturing method has a degree of such warp. It is suitable for suppressing.

  The semiconductor device manufacturing method preferably further includes a step (grinding step) of thinning the first wafer by grinding the second surface side of the first wafer. By this grinding step, it is possible to remove the multilayer resin portion on the second surface of the first wafer and then thin the first wafer to a predetermined thickness.

  According to a second aspect of the present invention, a semiconductor device is provided. This semiconductor device has a laminated structure including a first wafer, a second wafer, an adhesive layer, and a resin layer. The first wafer has a first surface and a second surface opposite to the first surface. The second wafer is located on the first surface side of the first wafer and is thinner than the first wafer. The adhesive layer is interposed between the first wafer and the second wafer. The adhesive layer is, for example, one that is cured under a predetermined high temperature condition. The resin layer is in close contact with the second surface of the first wafer. The resin layer is cured, for example, under a predetermined high temperature condition.

  In the semiconductor device having such a configuration, for example, at room temperature, the shrinkage stress of the adhesive layer located on the first surface side of the first wafer acts on the first surface of the first wafer, and The contraction stress of the resin layer located on the second surface side acts on the second surface of the first wafer. Therefore, in the present semiconductor device, even if the difference in thickness between the first and second wafers is large and the resistance of the second wafer to the contraction of the adhesive layer is considerably smaller than the resistance of the first wafer. Even if there is, the contracting stress of the adhesive layer that acts on the first surface of the first wafer (acts so as to deform the end portion of the first wafer toward the first surface) is applied to the first wafer. The shrinkage stress of the resin layer acting on the second surface can reduce or cancel the shrinkage stress. Therefore, the present semiconductor device is suitable for suppressing the occurrence of warpage. The present semiconductor device, which is suitable for suppressing the occurrence of warpage, can be easily processed with high accuracy, for example, when further processing is required, and can be appropriately manufactured as a semiconductor device in which semiconductor elements are multilayered. Therefore, the present semiconductor device is suitable for increasing the number of layers of semiconductor elements.

  According to a third aspect of the present invention, a semiconductor device is provided. This semiconductor device has a laminated structure including a first wafer, a plurality of second wafers, a plurality of adhesive layers, and a multilayer resin portion. The first wafer has a first surface and a second surface opposite to the first surface. Each of the plurality of second wafers is thinner than the first wafer, is located on the first surface side of the first wafer, and is arranged in the thickness direction of the first wafer. Each of the plurality of adhesive layers is interposed between the adjacent wafers to bond the wafers. Each adhesive layer is cured, for example, under a predetermined high temperature condition. The multilayer resin portion includes a plurality of resin layers stacked in the thickness direction of the first wafer and is in close contact with the second surface of the first wafer. Each resin layer of the multilayer resin portion is cured, for example, under a predetermined high temperature condition. The number of resin layers contained in such a multilayer resin portion is the same as the total number of adhesive layers interposed between the wafers.

  In the semiconductor device having such a configuration, for example, at room temperature, the shrinkage stress of each adhesive layer located on the first surface side of the first wafer acts directly or indirectly on the first surface of the first wafer. At the same time, the contraction stress of the multilayer resin portion located on the second surface side of the first wafer acts on the second surface of the first wafer. In this semiconductor device, the total number of adhesive layers on the first surface side of the first wafer and the total number of resin layers included in the multilayer resin portion on the second surface side are the same. Therefore, in the present semiconductor device, even if the difference in thickness between the first and second wafers is large, the resistance of each second wafer to the contraction of each adhesive layer is considerably smaller than the resistance of the first wafer. Even in this case, the total shrinkage stress of each adhesive layer acting on the first surface of the first wafer (acting so as to deform the end portion of the first wafer toward the first surface) is It is possible to reduce or cancel by the total shrinkage stress of the multilayer resin portion acting on the second surface of the first wafer. Therefore, the present semiconductor device is suitable for suppressing the occurrence of warpage. In the WOW process, as the number of stacked wafers increases, the degree of warpage of the wafer stack tends to increase cumulatively, but since the present semiconductor device is suitable for suppressing such a degree of warpage. is there. The present semiconductor device, which is suitable for suppressing the occurrence of warpage, can be easily processed with high accuracy, for example, when further processing is required, and can be appropriately manufactured as a semiconductor device in which semiconductor elements are multilayered. Therefore, the present semiconductor device is suitable for increasing the number of layers of semiconductor elements.

3 shows some steps in the semiconductor device manufacturing method according to the embodiment of the present invention. 3 shows some steps in the semiconductor device manufacturing method according to the embodiment of the present invention. 3 shows some steps in the semiconductor device manufacturing method according to the embodiment of the present invention. 3 shows some steps in the semiconductor device manufacturing method according to the embodiment of the present invention. 3 shows some steps in the semiconductor device manufacturing method according to the embodiment of the present invention. 3 shows some steps in the semiconductor device manufacturing method according to the embodiment of the present invention. 3 shows some steps in the semiconductor device manufacturing method according to the embodiment of the present invention. 3 shows some steps in the semiconductor device manufacturing method according to the embodiment of the present invention. 3 shows some steps in the semiconductor device manufacturing method according to the embodiment of the present invention.

  1 to 9 show a semiconductor device manufacturing method according to an embodiment of the present invention. This manufacturing method is a method for manufacturing a semiconductor device having a three-dimensional structure in which semiconductor elements are integrated in the thickness direction, and FIGS. 1 to 9 are partial cross-sectional views showing the manufacturing process.

  In the present semiconductor device manufacturing method, first, as shown in FIG. 1A, the wafer 11 and the reinforcing wafer 12R are prepared (preparation step).

  The wafer 11 has a surface 11a and an opposite surface 11b. The wafer 11 is a semiconductor wafer in which various semiconductor elements (not shown) are already formed on the side of the surface 11a and wiring structures (not shown) necessary for the semiconductor element are already formed on the surface 11a. is there. As a constituent material of the semiconductor wafer for forming the wafer 11, for example, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP). Is mentioned. The thickness of such a wafer 11 is preferably 300 μm or more, more preferably 500 μm or more, and more preferably 700 μm or more from the viewpoint of ensuring the strength of the wafer laminated body including the wafer 11 during the manufacturing process. . From the viewpoint of shortening the grinding time in the grinding step described later, the thickness of the wafer 11 is preferably 1000 μm or less, more preferably 900 μm or less, and more preferably 800 μm or less.

  The reinforcing wafer 12R has a laminated structure including the wafer 12, the supporting substrate S, and the temporary adhesive layer 13 between the wafer 12 and the supporting substrate S.

  The wafer 12 has a surface 12a and an opposite surface 12b. The wafer 12 is a semiconductor wafer in which various semiconductor elements (not shown) are already formed on the side of the surface 12a and wiring structures (not shown) necessary for the semiconductor element are already formed on the surface 12a. is there. Alternatively, the wafer 12 has various semiconductor elements (not shown) already formed on the side of the surface 12a, and the wiring structure and the like necessary for the semiconductor element are formed later on the surface 12a. It may be. As the constituent material of the semiconductor wafer for forming the wafer 12, for example, those listed above as the constituent material of the semiconductor wafer for forming the wafer 11 can be adopted. Further, the wafer 12 is thinner than the above-mentioned wafer 11. The thickness of the wafer 12 is preferably 100 μm or less, more preferably 50 μm or less, more preferably 30 μm or less, and more preferably 10 μm or less from the viewpoint of thinning and miniaturizing the manufactured semiconductor device. The thickness of the wafer 12 is preferably 1 μm or more, more preferably 2 μm or more, and still more preferably 2.5 μm or more from the viewpoint of ensuring the characteristics of the semiconductor element to be built.

  The support substrate S on the reinforcing wafer 12R is for reinforcing the thin wafer 12. Examples of the support substrate S include a silicon wafer and a glass wafer. The thickness of the support substrate S is preferably 300 μm or more, more preferably 500 μm or more, and more preferably 700 μm or more from the viewpoint of ensuring the function as a reinforcing element. The thickness of the support substrate S is, for example, 800 μm or less. Such a support substrate S is bonded to the surface 12 a side of the wafer 12 via the temporary adhesive layer 13.

  The temporary adhesive layer 13 is for realizing a temporary adhesive state between the wafer 12 and the support substrate S that can be released afterwards. The adhesive for forming such a temporary adhesive layer 13 is, for example, a polymer material that exhibits tackiness or adhesiveness in the temporary adhesive layer 13 in a predetermined temperature range and exceeds the temperature range. Containing a polymer material having a softening point in a high temperature range, the adhesive strength withstands the grinding process described below for forming the wafer 12, the heat resistance capable of withstanding the wafer bonding process described below involving heating, and the like. An adhesive having a light peeling function for properly performing the removing process is used. As the adhesive for forming the temporary adhesive layer 13, for example, a silicone adhesive, an acrylic adhesive, or a wax type adhesive can be adopted. As the adhesive for forming the temporary adhesive layer 13, those described in JP2008-13589A, JP2008-13590A, or JP2008-49443A may be used. The thickness of the temporary adhesive layer 13 as described above is, for example, 1 to 20 μm.

The reinforced wafer 12R having such a configuration can be manufactured, for example, through the following steps. First, as shown in FIG. 2A, the temporary adhesive layer 13 is formed on the support substrate S. Specifically, the adhesive composition for forming the temporary adhesive layer 13 is applied onto the supporting substrate S by, for example, spin coating to form a temporary adhesive composition layer, and the composition layer is dried by heating. The temporary adhesive layer 13 can be formed. The heating temperature is, for example, 100 to 300 ° C., and the heating time is, for example, 30 seconds to 30 minutes. Next, as shown in FIGS. 2B and 2C, the support substrate S and the wafer 12 ′ are bonded via the temporary adhesive layer 13. The wafer 12 'has a surface 12a and an opposite surface 12b'. The wafer 12 ′ is a semiconductor wafer in which various semiconductor elements (not shown) are already formed on the side of the surface 12 a and wiring structures (not shown) necessary for the semiconductor element are already formed on the surface 12 a. Is. In the main bonding step, for example, the support substrate S and the wafer 12 ′ are bonded together while being pressed via the temporary adhesive layer 13, and then the temporary adhesive layer 2 is solidified by heating, and the support substrate S and the wafer 12 ′ are solidified. 12 'and the temporary adhesive layer 2 are bonded. In the bonding, the pressure is, for example, 300 to 5000 g / cm ² , and the temperature is, for example, 30 to ²⁰⁰ ° C. Moreover, in the adhesion by the temporary adhesive layer 13, the heating temperature is, for example, 100 to 300 ° C., and the heating time is, for example, 30 seconds to 30 minutes. Then, the wafer 12 'is thinned to form the above-mentioned wafer 12 as shown in FIG. Specifically, the wafer 12 'supported by the support substrate S is ground from the side of the surface 12b' using a grind device so that the wafer 12 'has a predetermined thickness. The wafer 12 can be formed by making the wafer 12 thin. As described above, the reinforcing wafer 12R having a laminated structure including the wafer 12, the support substrate S, and the temporary adhesive layer 13 between them can be manufactured. The surface 12b of the wafer 12 in the reinforced wafer 12R may be subjected to a surface treatment such as a silane coupling agent treatment for improving the adhesion with the adhesive layer 21 described later.

  In the present semiconductor device manufacturing method, next, for example, after the adhesive layer 21 is formed on the surface 11a of the wafer 11 as shown in FIG. 1B, the adhesive layer 21 is formed as shown in FIG. The wafer 11 and the wafer 12 of the reinforcing wafer 12R are bonded via the adhesive layer 21 (wafer bonding step).

  The adhesive layer 21 is for realizing a bonded state between the wafers 11 and 12, and is made of a thermosetting adhesive. Examples of the pressure-sensitive adhesive main component for forming the thermosetting adhesive include polyorganosilsesquioxane, benzocyclobutene (BCB) resin, and novolac epoxy resin. From the viewpoint of achieving good heat resistance and crack resistance that can withstand the temperature environment in the present method including various heating conditions and temperature fluctuations, polyorganosilsesquioxane-containing thermosetting is used to form the adhesive layer 21. It is preferable to employ a mold adhesive. As the polyorganosilsesquioxane-containing thermosetting adhesive, for example, the adhesive described in WO2016 / 204114 can be adopted. Regarding the heat resistance of the thermosetting adhesive for forming the adhesive layer 21, the thermal decomposition temperature of the adhesive is preferably 200 ° C. or higher, more preferably 260 ° C. or higher, and more preferably 300 ° C. or higher. . The thermal decomposition temperature is a curve obtained by thermogravimetric analysis using a differential thermogravimetric simultaneous measurement apparatus, that is, a curve showing the temperature dependence of thermogravimetricity in a predetermined temperature rising range of a sample to be analyzed. , The tangent line of the part where there is no weight loss at the beginning of the heating process or it decreases slightly at a constant rate, and the inflection in the part where significant weight loss occurs in the middle of the heating process following the beginning of the heating process The temperature is indicated by the intersection with the tangent line at the point. As the differential thermogravimetric simultaneous measurement device, for example, a trade name “TG-DTA6300” manufactured by Seiko Instruments Inc. can be used. In the formation of such an adhesive layer 21, for example, the adhesive composition for forming the adhesive layer 21 is applied to the surface 11a of the wafer 11 by spin coating to form an adhesive composition layer, and the adhesive composition layer is formed by heating. The composition layer is dried and solidified. The heating temperature at this time is, for example, 50 to 150 ° C., and the heating time is, for example, 5 to 120 minutes. Prior to the formation of the adhesive layer 21 as described above, the surface 11 a of the wafer 11 may be subjected to a surface treatment such as a silane coupling agent treatment for improving the adhesiveness with the adhesive layer 21. Further, in the present embodiment, instead of forming the adhesive layer 21 on the surface 11 a of the wafer 11, the adhesive layer 21 may be formed on the surface 12 b of the wafer 12.

In the wafer bonding step, specifically, the wafer 11 and the reinforcing wafers 12R to 12 are bonded together while being pressed via the adhesive layer 21, and then the adhesive layer 21 is cured by heating. In the bonding, the pressure is, for example, 300 to 5000 g / cm ² , and the temperature is, for example, 30 to ²⁰⁰ ° C. In curing the adhesive layer 21, the heating temperature is, for example, 30 to 200 ° C., and the heating time is, for example, 5 to 120 minutes. The thickness of the adhesive layer 21 is, for example, 0.5 to 20 μm.

  In the present semiconductor device manufacturing method, next, the resin layer 31 is formed as shown in FIG. 1D (resin layer forming step). The resin layer 31 is made of, for example, a curable material, and as the constituent material of the resin layer 31, for example, a thermosetting adhesive having the same composition as the adhesive for forming the adhesive layer 21 described above may be adopted. it can. In the formation of the resin layer 31, for example, the adhesive composition for forming the resin layer 31 is applied to the surface 11b of the wafer 11 by spin coating to form an adhesive composition layer, and the composition layer is dried by heating. And cure the curing components in the composition. The heating temperature at this time is, for example, 30 to 200 ° C., and the heating time is, for example, 5 to 120 minutes. Prior to the formation of such a resin layer 31, the surface 11b of the wafer 11 may be subjected to a surface treatment such as a silane coupling agent treatment for improving the adhesion with the resin layer 31.

  Next, the temporary adhesion state by the temporary adhesive layer 13 between the wafer 12 and the support substrate S is released, and the support substrate S is removed from the wafer 12 as shown in FIG. 3 (removal step). Specifically, after performing the heating for light peeling on the above-mentioned temporary adhesive layer 13 whose adhesive strength is reduced by heating at a predetermined high temperature, the support substrate S is slid on the wafer 12, for example. Thus, the support substrate S can be separated and removed from the wafer 12 or a wafer stack including the wafer 12. In this step, the heating temperature is, for example, 130 to 250 ° C., and the heating time is, for example, 30 seconds to 15 minutes. When the wafer 12 in the above-mentioned reinforcing wafer 12R does not have a wiring structure or the like including an insulating film or a wiring pattern on the surface 12a side, a wiring structure or the like is formed on the surface 12a of the wafer 12 after the main removing step. To be done. The same is true after the removal step described later.

  Next, as shown in FIG. 4, through-electrodes 41 for forming electrical connection between semiconductor elements formed on different wafers (wafer 11 and wafer 12) are formed in the wafer stack obtained through the removing step. To be done. For example, formation of an opening penetrating the wafer 12 and the adhesive layer 21 to reach the wiring structure (not shown) on the wafer 11, formation of an insulating film (not shown) on the inner wall surface of the opening, insulation A barrier layer (not shown) is formed on the surface of the film, a seed layer for electroplating (not shown) is formed on the surface of the barrier layer, and a conductive material such as copper is filled in the opening by electroplating. Thus, the through electrode 41 can be formed. The wiring structure (not shown) formed on the surface 11a side of the wafer 11 and the wiring structure (not shown) formed on the surface 12a side of the wafer 12 are electrically connected by the through electrode 41. To be done.

  In the present semiconductor device manufacturing method, next, after the adhesive layer 21 is formed on the surface 12a of the wafer 12 in the wafer laminated body obtained as described above, for example, as shown in FIG. As shown in FIG. 5B, the wafer 12 and the wafer 12 of the new reinforcing wafer 12R (additional wafer 12) are bonded via the adhesive layer 21 (wafer adding step).

  In the formation of the adhesive layer 21 in the wafer adding step, for example, the adhesive composition for forming the adhesive layer 21 is applied to the surface 12a of the wafer 12 in the wafer bonded body by spin coating to form the adhesive composition layer. Then, the composition layer is solidified by heating. The heating temperature is, for example, 50 to 150 ° C., and the heating time is, for example, 5 to 120 minutes. Prior to the formation of such an adhesive layer 21, the surface 12a of the wafer 12 in the wafer bonded body is subjected to a surface treatment such as a silane coupling agent treatment for improving the adhesion with the adhesive layer 21. Good.

  The reinforcing wafer 12R used in the wafer adding step has a laminated structure including the additional wafer 12, the supporting substrate S, and the temporary adhesive layer 13 between them. The structure and manufacturing method of the reinforcing wafer 12R are the same as the structure and manufacturing method of the reinforcing wafer 12R described above regarding the wafer bonding process. The above-mentioned adhesive layer 21 formed in the wafer adding step may be formed on the surface 12b of the additional wafer 12 in the reinforcing wafer 12R.

In the wafer adding step, specifically, the wafer 12 and the new reinforcing wafer 12R or the additional wafer 12 are bonded together while being pressed via the adhesive layer 21, and then the adhesive layer 21 is heated to heat the adhesive layer 21. Let it harden. In the bonding, the pressure is, for example, 300 to 5000 g / cm ² , and the temperature is, for example, 30 to ²⁰⁰ ° C. In curing the adhesive layer 21, the heating temperature is, for example, 30 to 200 ° C., and the heating time is, for example, 5 to 120 minutes. The thickness of the adhesive layer 21 is, for example, 0.5 to 20 μm.

  In the present semiconductor device manufacturing method, next, as shown in FIG. 5C, an additional resin layer 31 is formed (resin layer adding step). The resin layer 31 is made of, for example, a curable material, and as the constituent material of the resin layer 31, for example, a thermosetting adhesive having the same composition as the adhesive for forming the adhesive layer 21 described above may be adopted. it can. In the formation of the resin layer 31, for example, the adhesive composition for forming the resin layer 31 is applied by spin coating on the resin layer 31 already formed on the surface 11b side of the wafer 11 to form the adhesive composition layer. Is formed, the composition layer is dried by heating, and the curing component in the composition is cured. The heating temperature at this time is, for example, 30 to 200 ° C., and the heating time is, for example, 5 to 120 minutes. Prior to such formation of the additional resin layer 31, the surface of the resin layer 31 already formed on the surface 11b side of the wafer 11 has a silane coupling for improving adhesion with the additional resin layer 31. Surface treatment such as agent treatment may be performed. By the resin layer adding step as described above, the multilayer resin portion 30 including the plurality of resin layers 31 stacked in the thickness direction of the wafer 11 and being in close contact with the surface 11b is formed. The resin layer adding step is performed for each wafer adding step, and the number of resin layers 31 included in the multilayer resin portion 30 is the same as the total number of adhesive layers 21 interposed between the wafers.

  Next, the temporary adhesive state by the temporary adhesive layer 13 between the wafer 12 and the supporting substrate S in the reinforcing wafer 12R is released, and the supporting substrate S is transferred from the uppermost wafer 12 in the figure as shown in FIG. Removed (removal process). Specifically, the support substrate S is removed in the same manner as the removing step described above with reference to FIG.

  Next, as shown in FIG. 7, through-electrodes 41 for electrical connection between semiconductor elements formed on different wafers are formed in the wafer laminated body obtained through the removing step. For example, formation of an opening that penetrates the additional wafer 12 and the adhesive layer 21 immediately below it to reach the above wiring structure (not shown) on the wafer 12, and an insulating film (not shown) on the inner wall surface of the opening. ), A barrier layer (not shown) on the surface of the insulating film, a seed layer for electroplating (not shown) on the surface of the barrier layer, and a conductive material such as copper in the opening by electroplating. The through electrode 41 can be formed through, for example, filling. For example, a wiring structure (not shown) formed by the through electrode 41 on the side 12a of the upper wafer 12 in the figure and a wiring formed on the side 12a of the lower wafer 12 in the figure. The structure (not shown) is electrically connected.

  In the present semiconductor device manufacturing method, the wafer adding step described above with reference to FIGS. 5A and 5B, the resin layer adding step described above with reference to FIG. A series of steps including the removing step described above with reference to and the through electrode forming step described above with reference to FIG. 7 are performed a predetermined number of times according to the number of stacked semiconductor elements of the semiconductor device to be manufactured. The resin layer adding step and the subsequent removing step are performed for each wafer adding step. FIG. 8 shows, as an example, a wafer stack obtained by performing the series of processes twice.

  In the present semiconductor device manufacturing method, next, a grinding step is performed as shown in FIG. Specifically, after removing the multilayer resin portion 30 by grinding the surface 11b side of the wafer 11, the wafer 11 is thinned to a predetermined thickness. The thickness of the thinned wafer 11 is, for example, 5 to 400 μm. After that, external connection bumps (not shown) may be formed on the surface 12a side of the wafer 12 which is laminated most later. Alternatively, a through electrode (not shown) that penetrates the thinned wafer 11 and is electrically connected to a wiring structure (not shown) on the surface 11a side of the wafer 11 is formed, and the through electrode is electrically connected to the through electrode. Externally connected bumps (not shown) may be formed on the surface 11b side of the wafer 11.

  As described above, a semiconductor device in which semiconductor elements are multi-layered in the thickness direction can be manufactured. This semiconductor device may be diced into individual pieces.

  In the wafer bonding process described above with reference to FIGS. 1B and 1C in the semiconductor device manufacturing method, the support substrate S is relatively bonded with the temporary adhesive layer 13 interposed therebetween. The thin wafer 12 is bonded to the relatively thick wafer 11 via the adhesive layer 21. In the wafer stack including the wafers 11 and 12 (including the supporting substrate S bonded to the wafer 12) obtained through such a wafer bonding process, for example, when the temperature is lowered to room temperature, the cured adhesive layer 21 The resistance of the wafer 12 itself to the shrinkage of the wafer is smaller than the resistance of the wafer 11 to the shrinkage of the adhesive layer 21 because the wafer 12 is thinner than the wafer 11. However, the support substrate S bonded to the wafer 12 may supplement the wafer 12 for resistance to shrinkage of the cured adhesive layer 21. Even if the difference between the thicknesses of the two wafers 11 and 12 is large and the resistance of the wafer 12 itself to the shrinkage of the adhesive layer 21 after curing is considerably smaller than the resistance of the wafer 11, The support substrate S bonded to the side of the wafer 12 opposite to the wafer 11 bonding side can supplement the wafer 12 with respect to resistance to shrinkage of the adhesive layer 21 after curing. Therefore, in the wafer stack (accompanied by the supporting substrate S bonded to the wafer 12) obtained through the wafer bonding process, the difference in the coefficient of thermal expansion between the wafers 11 and 12 and the adhesive layer 21 and the wafer 11 The occurrence of warpage due to the asymmetrical laminated structure of the adhesive layers 12, 12 and the adhesive layer 21 is suppressed.

In the present semiconductor device manufacturing method, as described above with reference to FIG. 3, the step of separating and removing the support substrate S from the wafer 12 (removal step) is described with reference to FIG. Thus, the step of forming the resin layer 31 on the surface 11b of the wafer 11 (resin layer forming step) is performed. After the resin layer forming step and the subsequent removing step, for example, in a wafer laminated body at room temperature, the shrinkage stress of the adhesive layer 21 after curing acts on the surface 11a of the wafer 11 and also after the curing. The contraction stress of the resin layer 31 acts on the surface 11b of the wafer 11. Therefore, even if the difference in thickness between the two wafers 11 and 12 is large and the resistance of the wafer 12 to the shrinkage of the adhesive layer 21 after curing is considerably smaller than the resistance of the wafer 11, The contraction stress of the adhesive layer 21 after curing which acts on the surface 11a of 11 (acts so as to deform the end portion of the wafer 11 toward the surface 11a side) cures on the surface 11b of the wafer 11. It is possible to reduce or cancel the shrinkage stress of the resin layer 31 later. Therefore, in the above-described configuration in which the resin layer forming step and the subsequent removing step are performed, the relatively thick wafer 11, the relatively thin wafer 12, and the adhesive layer 21 between the wafers 11 and 12 are provided. It is suitable for suppressing the occurrence of warpage after the removal step in the wafer stack including the above. From the viewpoint that the shrinkage stress of the cured adhesive layer 21 acting on the surface 11a of the wafer 11 is offset or sufficiently reduced by the shrinkage stress of the cured resin layer 31 acting on the surface 11b of the wafer 11. Is a parameter related to the stress acting on the adherend by the adhesive layer 21, which is expressed by the coefficient of thermal expansion (α ₁ ), the elastic modulus (E ₁ ) and the thickness (t ₁ ) of the adhesive layer 21. The resin layer 31 expressed by the coefficient of thermal expansion (α ₂ ), the elastic modulus (E ₂ ) and the thickness (t ₂ ) of the resin layer 31 with respect to σ ₁ (= α ₁ × E ₁ × t ₁ ). The ratio value (σ ₂ / σ ₁ ) of the parameter σ ₂ (= α ₂ × E ₂ × t ₂ ) relating to the stress acting on the adherend is preferably 0.8 to 1.2, more preferably It is 0.9 to 1.1, and more preferably 0.95 to 1.05.

  In the semiconductor device manufacturing method, in the wafer adding step described above with reference to FIGS. 5A and 5B, the adhesive is applied on the relatively thick wafer 11 in the wafer joining step or the preceding wafer adding step. A relatively thin additional wafer 12 in which the support substrate S is bonded via the temporary adhesive layer 13 to the wafer 12 bonded via the layer 21 has a new adhesive layer 21 interposed therebetween. Are joined together. In the wafer stack including the wafer 11 and the plurality of wafers 12 (including the support substrate S bonded to the wafer 12 stacked most after) obtained through such a wafer adding step, the temperature is lowered to, for example, room temperature. In this case, the resistance of each wafer 12 itself to the shrinkage of each cured adhesive layer 21 is smaller than the resistance of the wafer 11 to the shrinkage of the adhesive layer 21 because each wafer 12 is thinner than the wafer 11. However, the support substrate S in the reinforced wafer 12R may supplement each wafer 12 in terms of resistance to shrinkage of the cured adhesive layer 21. For example, when the difference in thickness between the wafer 11 and each wafer 12 is large and the resistance of each wafer 12 itself to the contraction of each adhesive layer 21 after curing is considerably smaller than the resistance of the wafer 11. However, the support substrate S in the reinforcing wafer 12R can supplement each wafer 12 with respect to the resistance to the shrinkage of each adhesive layer 21 after curing. Therefore, in the wafer laminated body (with the supporting substrate S bonded to the wafer 12 laminated most afterward) obtained through each wafer adding step, the wafer 11 and the plurality of wafers 12 exhibiting different thermal expansion coefficients from each other. The occurrence of warpage due to a predetermined asymmetric laminated structure with the plurality of adhesive layers 21 is suppressed.

In the present semiconductor device manufacturing method, before the step of removing the supporting substrate S from the wafer 12 in the reinforced wafer 12R that has undergone the wafer adding step (removing step), the resin layer 31 on the surface 11b side of the wafer 11 is formed. The step of forming the additional resin layer 31 (resin layer addition step) is performed. Through such a resin layer adding step and the subsequent removing step, for example, in a wafer laminate at room temperature, the shrinkage stress of each adhesive layer 21 located on the surface 11a side of the wafer 11 is directly or indirectly. The shrinkage stress of each resin layer 31 of the multilayer resin portion 30 that is in contact with the surface 11a of the wafer 11 and is closely attached to the surface 11b of the wafer 11 acts on the surface 11b of the wafer 11 together. The total number of adhesive layers 21 on the surface 11a side of the wafer 11 and the total number of resin layers 31 on the surface 11b side in a state where the wafer stack during the manufacturing process is not accompanied by the supporting substrate S of the reinforcing wafer 12R. Are the same. Therefore, even if the difference in thickness between the wafer 11 and each wafer 12 is large, the resistance of each wafer 12 to the contraction of each adhesive layer 21 after curing is considerably smaller than the resistance of the wafer 11. However, the total shrinkage stress of each adhesive layer 21 acting on the surface 11a side of the wafer 11 (acting so as to deform the end portion of the wafer 11 toward the surface 11a side) is applied to the surface 11b of the wafer 11. It is possible to reduce or cancel by the total shrinkage stress of each resin layer 31 acting on the side. Therefore, in the above-described configuration in which the resin layer adding process and the subsequent removing process are performed for each wafer adding process, the relatively thick wafer 11 and the relatively thin wafers 12 are interposed between the wafers. It is suitable for suppressing the occurrence of warpage after the removal step in a wafer laminated body including a plurality of adhesive layers 21 that are formed. The total shrinkage stress of each adhesive layer 21 acting on the surface 11a of the wafer 11 is offset or sufficiently reduced by the total shrinkage stress of the multilayer resin portion 30 or each resin layer 31 acting on the surface 11b of the wafer 11. From the viewpoint, it is expressed by the coefficient of thermal expansion (α ₁ ), the elastic modulus (E ₁ ), and the thickness (t ₁ ) of the one adhesive layer 21 additionally formed in each wafer adding step. For the parameter σ ₁ (= α ₁ × E ₁ × t ₁ ) related to the stress applied to the adherend by the adhesive layer 21, the adhesive layer 21 is additionally formed in the resin layer addition step performed in accordance with the wafer addition step. The stress applied to the adherend by the resin layer 31 expressed by the coefficient of thermal expansion (α ₂ ), the elastic modulus (E ₂ ) and the thickness (t ₂ ) of the resin layer 31. The value of the ratio of the parameter σ ₂ (= α ₂ × E ₂ × t ₂ ) (σ ₂ / σ ₁ ) is preferably 0.8 to 1.2, more preferably 0.9 to 1.1, and more preferably 0.95 to 1.05.

  As described above, the present semiconductor device manufacturing method is suitable for suppressing the occurrence of warpage in the wafer stack during the manufacturing process. In the WOW process, as the number of stacked wafers increases, the degree of warp of the wafer stack tends to increase cumulatively. However, the present semiconductor device manufacturing method suppresses the degree of such warp. It is suitable. Then, the smaller the degree of warpage in the wafer stack during the manufacturing process, the easier it is to perform various types of processing (for example, the various types of processing described above for forming the through electrode 41) on the wafer stack with high accuracy, and It is easy to increase the number of layers of the laminated body, and thus the number of semiconductor elements in the manufactured semiconductor device. Therefore, the present semiconductor device manufacturing method is suitable for increasing the number of layers of semiconductor elements. The wafer laminated body or the semiconductor device obtained through the above-mentioned resin layer forming step in the present semiconductor device manufacturing method is suitable for increasing the number of semiconductor elements.

[Example 1]
<Preparation of adhesive composition>
100 parts by mass of an epoxy group-containing polyorganosilsesquioxane obtained as described below, 115 parts by mass of propylene glycol monomethyl ether acetate, and an antimony sulfonium salt (trade name “SI-150L”, Sanshin Chemical Industry Co., Ltd.) 0.1 part by mass of (manufactured by the company) and 0.01 part by mass of (4-hydroxyphenyl) dimethylsulfonium methyl sulfite (trade name "San-Aid SI auxiliary", manufactured by Sanshin Chemical Industry Co., Ltd.) are mixed and bonded. An agent composition (adhesive composition C) was obtained.

<Synthesis of polyorganosilsesquioxane>
In a 300 mL flask equipped with a reflux condenser, a nitrogen gas introduction tube, a stirrer, and a thermometer, while introducing nitrogen gas, 2- (3,4-epoxycyclohexyl) ethyltrimethoxysilane 161. 5 mmol (39.79 g), phenyltrimethoxysilane 9 mmol (1.69 g), and acetone 165.9 g as a solvent were mixed, and the temperature was raised to 50 ° C. Next, 4.7 g of a 5% aqueous potassium carbonate solution (1.7 mmol as potassium carbonate) was added dropwise to the mixture over 5 minutes, and subsequently 1700 mmol (30.6 g) of water was added dropwise over 20 minutes. During the dropping operation, the temperature of the mixture did not rise significantly. After the dropping operation, a polycondensation reaction was performed at 50 ° C. for 4 hours while introducing nitrogen gas into the flask. When the product in the reaction solution after the polycondensation reaction was analyzed, the number average molecular weight was 1900, and the molecular weight dispersity was 1.5. Then, with respect to the reaction solution that has been allowed to stand and is cooled, after repeatedly washing with water until the lower layer liquid (aqueous phase) generated by phase separation becomes neutral, the upper layer liquid is fractionated and the solvent is added under the conditions of 1 mmHg and 40 ° C. The solvent was distilled off from the upper layer solution until the amount became 25% by mass to obtain a colorless and transparent liquid product (epoxy group-containing polyorganosilsesquioxane).

<Fabrication of wafer stack>
First, a first silicon wafer and a reinforced second silicon wafer were prepared. The first silicon wafer has a diameter of 300 mm, a thickness of 775 μm, and has one surface treated with a silane coupling agent. In the silane coupling agent treatment of the first silicon wafer, one surface of the first silicon wafer is spin-coated with a silane coupling agent (trade name "KBE403", manufactured by Shin-Etsu Chemical Co., Ltd.), and thereafter, Heating at 120 ° C. for 5 minutes was performed. The reinforced second silicon wafer was manufactured as follows.

First, an adhesive composition for forming a temporary adhesive layer is applied by spin coating on a silicon substrate (diameter 300 mm, thickness 775 μm), which is a supporting substrate, to form a temporary adhesive composition layer. The composition layer was dried by heating for 2 minutes and then heating at 230 ° C. for 4 minutes to form a temporary adhesive layer. The adhesive composition for forming the temporary adhesive layer was prepared by adding 0.24 parts by mass of diethylene glycol divinyl ether and a p-hydroxystyrene / styrene copolymer (trade name "Marcalinker CST-50", p-hydroxystyrene and styrene. Is 50:50, the weight average molecular weight is 4400, the softening point is 150 ° C., made by Maruzen Petrochemical Co., Ltd., and 5.4 parts by mass, and polyvinyl butyral resin (trade name “ESREC KS-1”, molecular weight is 2). 1.8 × 10 ⁴ , a thermoplastic resin having a softening point of 200 ° C., manufactured by Sekisui Chemical Co., Ltd., and polycaprolactone (trade name “Placcel H1P”, weight average molecular weight of 10,000, softening point of 100). 1.8 parts by weight of a thermoplastic resin (manufactured by Daicel Co., Ltd.) and trans-cinnamic acid (pKa is 4.44, Wako Pure Chemical Industries, Ltd.) as a polymerization accelerator. 0.18 parts by mass, fluorine-based oligomer (trade name “F-554”, manufactured by DIC Corporation) as a surfactant, 0.045 parts by mass, and cyclohexanone as a solvent 22 parts by mass are mixed. It was prepared. Next, the silicon substrate and the second silicon wafer (diameter 300 mm, thickness 775 μm) were bonded together via a temporary adhesive layer. Specifically, the silicon substrate and the second silicon wafer are bonded together via a temporary adhesive layer while applying pressure at a temperature of 150 ° C. and a pressure of 3000 g / cm ² , and then heated at 230 ° C. for 5 minutes. After that, the silicon substrate and the second silicon wafer were bonded via the temporary adhesive layer. Next, the second silicon wafer supported by the silicon substrate was ground using a grind device (manufactured by DISCO Co., Ltd.) to reduce the thickness of the second silicon wafer to 10 μm. . Next, after applying a silane coupling agent (trade name "KBE403", manufactured by Shin-Etsu Chemical Co., Ltd.) to the surface (grinding surface) of the thinned second silicon wafer by spin coating, 5 at 120 ° C. Heating was performed for 1 minute (treatment with a silane coupling agent). The above-mentioned reinforced second silicon wafer is manufactured in this way.

In the production of the wafer laminate, next, the adhesive composition C was applied by spin coating to the silane coupling agent-treated surface (first surface) of the first silicon wafer to form an adhesive composition layer. Thereafter, the first silicon wafer with this composition layer was heated at 80 ° C. for 4 minutes, and subsequently heated at 100 ° C. for 2 minutes. Thereby, the adhesive composition layer was dried to form an adhesive layer having a thickness of 2.5 μm on the first surface of the first silicon wafer. Next, the first silicon wafer with the adhesive layer and the thinned wafer of the reinforcing wafer described above are bonded together while being pressed through the adhesive layer on the first silicon wafer, and then at 150 ° C. for 30 minutes. Heating was carried out, and then heating was carried out at 170 ° C. for 30 minutes, whereby the adhesive layer was cured and joined. The bonding was performed under the conditions of a temperature of 50 ° C. and a pressure of 3000 g / cm ² .

  In the production of the wafer laminate, next, a resin layer was formed on the surface (second surface) of the first silicon wafer opposite to the second silicon wafer bonding surface (first surface). Specifically, first, a silane coupling agent (trade name “KBE403”, manufactured by Shin-Etsu Chemical Co., Ltd.) is applied to the second surface of the first silicon wafer by spin coating, and then heated at 120 ° C. for 5 minutes. Was performed (treatment with a silane coupling agent). Next, the adhesive composition C for forming a resin layer is applied to the silane coupling agent-treated surface (second surface) of the first silicon wafer by spin coating to form an adhesive composition layer, and then at 80 ° C. The adhesive composition layer was dried by heating for 4 minutes and then at 100 ° C. for 2 minutes. Next, the first silicon wafer with the composition layer was heated at 150 ° C. for 30 minutes, and subsequently heated at 170 ° C. for 30 minutes. Thus, the adhesive composition layer was dried and cured to form a resin layer having a thickness of 2.5 μm on the second surface of the first silicon wafer.

  Next, the temporary adhesion state by the temporary adhesive layer between the silicon substrate as the support substrate and the thinned second silicon wafer was released, and the silicon substrate was removed from the second silicon wafer. Specifically, after the heat treatment at 235 ° C. for 5 minutes, the silicon substrate is slid at a relative speed of 1 mm / sec with respect to the second silicon wafer, and the second silicon wafer or a wafer laminated body including the second silicon wafer. The silicon substrate was removed from. Then, the temporary adhesive residue on the second silicon wafer was removed by washing with propylene glycol monomethyl ether. The wafer laminated body of Example 1 was manufactured as described above.

  With respect to the wafer laminated body of this embodiment, an SORI (warp) defined by SEMI standard (specifically, SEMI MF1451-0707) is used by using a shape measuring device (trade name "LTV-3000", manufactured by Kobelco Kaken Co., Ltd.) The amount) was measured and found to be 9.5 μm. In the main measurement, the least-squares reference plane is calculated from the surface shape data of the measurement object obtained by correcting the deflection of the measurement object by its own weight, and the maximum value of the deviation from the least-squares reference plane in the surface shape data. The amount of warp corresponds to the difference between the minimum value and the minimum value.

<Film thickness measurement>
The adhesive composition C was applied onto a silicon wafer (diameter 300 mm, thickness 775 μm) by spin coating to form an adhesive composition layer. The adhesive composition C used for one spin coating was 20 g, and the rotation speed for spin coating was 1200 rpm. Then, the adhesive composition layer on the base material was heated at 80 ° C. for 4 minutes, and subsequently heated at 100 ° C. for 2 minutes to dry the adhesive composition layer. Next, heating was performed at 150 ° C. for 30 minutes, followed by heating at 170 ° C. for 30 minutes, thereby forming a cured coating film on the substrate. The thickness of the formed coating film was measured using a fine shape measuring machine (trade name "Surfcoder ET 4000A", manufactured by Kosaka Laboratory Ltd.), and it was 2.5 µm. The above-mentioned wafer laminate of Example 1 includes such a cured coating film as an adhesive layer for joining the first and second silicon wafers, and further adheres to the second surface of the first silicon wafer. The resin layer is also included.

<Measurement of coefficient of thermal expansion>
The adhesive composition C is applied onto a silicon wafer (diameter 300 mm, thickness 775 μm) by spin coating to form an adhesive composition layer, and then the adhesive composition layer on the substrate is heated to 80 ° C. For 4 minutes, followed by heating at 100 ° C. for 2 minutes to dry the adhesive composition layer. Next, heating was performed at 150 ° C. for 30 minutes, followed by heating at 170 ° C. for 30 minutes, thereby forming a cured coating film (thickness 2.5 μm) on the substrate. The coefficient of thermal expansion of this coating film was determined based on the film thickness data from 25 ° C. to 250 ° C. measured using a thermal expansion coefficient measuring device (trade name “spectral ellipsometer”, manufactured by SCI). It was 68 ppm / ° C.

<Measurement of elastic modulus>
The above adhesive composition C was applied on a silicon wafer (diameter 300 mm, thickness 775 μm) by spin coating to form an adhesive composition layer, followed by heating at 80 ° C. for 4 minutes, and subsequently at 100 ° C. Was heated for 2 minutes to dry the adhesive composition layer. Next, the adhesive composition layer on the substrate was heated at 150 ° C. for 30 minutes, and then at 170 ° C. for 30 minutes, whereby a cured coating film (thickness 2.5 μm ) Was formed on the substrate. The elastic modulus of this coating film was measured using a micro hardness meter (trade name "ENT-2100", manufactured by Elionix Co., Ltd.) and found to be 4.9 GPa.

[Comparative Example 1]
A wafer laminate of Comparative Example 1 was produced in the same manner as the wafer laminate of Example 1 except that the resin layer was not formed on the second surface of the first silicon wafer. With respect to the wafer laminated body of this comparative example, the amount of warpage was measured using a shape measuring device (trade name “LTV-3000”, manufactured by Kobelco Kaken Co., Ltd.) in the same manner as the wafer laminated body of Example 1. It was 47.4 μm.

[Evaluation]
In the wafer laminated body of Example 1, the warpage was reduced to about 1/5 as compared with the wafer laminated body of Comparative Example 1. Further, in the wafer laminated body of Example 1, the thickness (t ₁ ) of the adhesive layer between the wafers was 2.5 μm as described above, and from the results of the thermal expansion coefficient measurement and the elastic modulus measurement described above. As can be seen, the coefficient of thermal expansion (α ₁ ) of the adhesive layer or coating is 68 ppm / ° C. and the modulus of elasticity (E ₁ ) is 4.9 GPa. At the same time, in the wafer stack of Example 1, the thickness (t ₂ ) of the resin layer formed on the second surface of the first silicon wafer is 2.5 μm as described above, and As can be understood from the results of the expansion coefficient measurement and the elastic modulus measurement, the thermal expansion coefficient (α ₂ ) of the resin layer or the coating film is 68 ppm / ° C. and the elastic modulus (E ₂ ) is 4.9 GPa. That is, in the wafer laminated body of Example 1, the first silicon wafer of the first silicon wafer with respect to the parameter σ ₁ (= α ₁ × E ₁ × t ₁ ) related to the stress that the adhesive layer between the wafers acts on the adherend. The ratio value (σ ₂ / σ ₁ ) of the parameters σ ₂ (= α ₂ × E ₂ × t ₂ ) related to the stress applied to the adherend by the resin layers on the two surfaces is 1. Therefore, in the wafer stacked body of Example 1, the contraction stress of the cured adhesive layer acting on the first surface of the first silicon wafer is equal to that of the cured resin layer acting on the second surface of the first silicon wafer. It is sufficiently reduced by the shrinkage stress of.

S support substrate 11 wafer (first wafer)
11a surface (first surface)
11b surface (2nd surface)
12R Reinforcement wafer (Reinforcement second wafer)
12 wafers (second wafer)
12a surface 12b surface 13 temporary adhesive layer 21 adhesive layer 30 multilayer resin portion 31 resin layer 41 through electrode

Claims (5)

A first wafer having a first surface and a second surface opposite to the first surface, a second wafer thinner than the first wafer, a support substrate, and temporary adhesion between the second wafer and the support substrate A step of preparing a reinforced second wafer having a laminated structure including an agent layer;
Bonding the second wafer of the reinforced second wafer to the first surface of the first wafer via an adhesive layer;
Forming a resin layer on the second surface of the first wafer;
A method of manufacturing a semiconductor device, comprising the step of releasing a temporary adhesion state between the support substrate and the second wafer by the temporary adhesive layer and removing the support substrate. The second wafer in the reinforced second wafer having a laminated structure including a second wafer thinner than the first wafer, a support substrate, and a temporary adhesive layer between the second wafer and the support substrate At least one wafer addition step of bonding to a second wafer on the wafer via an adhesive layer;
Forming at least one additional resin layer on the second surface-side resin layer of the first wafer, which is performed in each of the wafer adding steps;
At least one of each of the wafer adding steps, the step of releasing the temporary adhesion state by the temporary adhesive layer between the support substrate and the second wafer to remove the support substrate. Item 2. A semiconductor device manufacturing method according to Item 1.   The semiconductor device manufacturing method according to claim 1, further comprising a step of thinning the first wafer by grinding the second surface side of the first wafer. A first wafer having a first surface and a second surface opposite to the first surface;
A second wafer located on the first surface side of the first wafer and thinner than the first wafer;
An adhesive layer interposed between the first and second wafers,
A semiconductor device having a laminated structure including a resin layer in close contact with the second surface of the first wafer. A first wafer having a first surface and a second surface opposite to the first surface;
A plurality of second wafers, each of which is thinner than the first wafer and is located on the first surface side of the first wafer and arranged in the thickness direction of the first wafer;
A plurality of adhesive layers, each of which is interposed between adjacent wafers to bond the wafers together,
A multi-layer resin portion that includes the same number of resin layers as the total number of the adhesive layers that are stacked in the thickness direction of the first wafer, and that is in close contact with the second surface of the first wafer. A semiconductor device having a laminated structure including.

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