JP2020057362A - Information processing apparatus, information processing circuit, information processing system, and information processing method - Google Patents

Abstract

To make it possible, in an information processing apparatus that performs filtering for pattern matching, to efficiently perform processing compared with a conventional example.SOLUTION: In an information processing system, a sensor device comprises a pre-information processing circuit that creates a finite state machine on the basis of a predetermined matching condition related to sequence data of an event to be input, and outputs sequence data that is processed to substantially remove data not matching the matching condition from the sequence data by using the created finite state machine.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an information processing apparatus that performs filtering for pattern matching, an information processing system including the information processing apparatus, and an information processing method.

  For example, in Patent Document 1, a time-series correlation extraction device that performs filtering of time-series data, and can prevent processing from taking a lot of time even when the number of transactions increases. Is disclosed. The time-series correlation extraction device according to this conventional example, when searching for a combination of records from a set of records composed of a plurality of attributes, a plurality of events each defining that a predetermined attribute in the record takes a specific value, Specifying means for specifying a search pattern using an order relationship between the plurality of events defined based on the order of the attribute values, and searching for a combination of records corresponding to the specified search pattern from a set of records A time-series filter unit having a search unit that performs search and an output unit that outputs a search result, and a function of extracting a time-series correlation rule by a time-series correlation engine unit.

JP-A-2004-110327 WO 2004/038620 pamphlet International Publication No. 2012/057170 pamphlet

Eugene Asarin, Oded Maler, Dejan Nickovic, and Dogan Ulus, 2017, Combining the Temporal and Epistemic Dimensions for MTL Monitoring.A. Abate and G. Geeraerts (Eds.), 2017, Proc. FORMATS. LNCS, Vol. 10419.Springer . M. Krichen and S. Tripakis, 2009, Conformance testing for real-time systems, FMSD 34, 3 (2009), 238-304. Leena Salmela, Jorma Tarhio, and Jari Kytojoki, 2006, Multi-pattern string matching with q-grams, ACM Journal of Experimental Algorithmics 11 (2006). D. Ulus, T. Ferrere, E. Asarin, and O. Maler, 2014, Timed Pattern Matching, In Proc. FORMATS, (LNCS), A. Legay and M. Bozga (Eds.), Vol. 8711, Springer, 222-236. Masaki Waga, Ichiro Hasuo, and Kohei Suenaga, 2017, Efficient Online Timed Pattern Matching by Automata-Based Skipping, 224-243.

  However, the time-series correlation extraction apparatus according to the conventional example generates a finite state machine such as a Moore machine based on an automaton describing a matching condition and performs filtering using the generated finite state machine. Therefore, there is a problem that the processing cannot be performed efficiently.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and in an information processing apparatus, an information processing system, and an information processing method for performing filtering for pattern matching, pattern matching is more efficiently performed by using filtering than in the related art. An information processing apparatus, an information processing system, and an information processing method capable of performing the information processing are provided.

  The information processing apparatus according to one embodiment of the present invention generates a finite state machine based on a predetermined matching condition regarding sequence data of an input event, and uses the generated finite state machine to generate the finite state machine from the sequence data. An information processing circuit for outputting sequence data processed so as to substantially remove data that does not match the matching condition is provided.

  Therefore, according to the information processing apparatus, the information processing system, and the information processing method according to the present invention, pattern matching can be performed more efficiently by using filtering than in the conventional example. In particular, by using filtering in comparison with conventional real-time constrained pattern matching (without performing preprocessing by filtering) (for example, Non-Patent Document 4), efficient processing can be performed, and performance can be significantly improved. Can be improved. Also, as compared with a conventional example of pattern matching using filtering (for example, Non-Patent Document 4), a broader automaton can be allowed as a pattern when there is no real-time constraint, and a real-time Can handle constraints.

It is a block diagram showing the example of composition of the physical information system (CPS) concerning an embodiment. It is a conceptual diagram showing the relationship between the pattern matching process and the filtering process. 6 is a timing chart showing a moving process before and after in pattern matching used in the embodiment. FIG. 10 is a plan view showing an example of a position plot in pattern matching in a conventional document. FIG. 3C is a plan view illustrating the specification of a section in the position plot of FIG. 3B. It is a key map showing padding processing of filtering in an embodiment. FIG. 4 is a conceptual diagram illustrating a filtering process by a Moore machine in the embodiment. It is a figure showing an example of a pattern which is a non-deterministic finite automaton (NFA) concerning an embodiment. It is a figure showing an example of the non-buffer part of the Moore machine filter concerning an embodiment. FIG. 8 is a diagram illustrating a run of a Moore machine filter for a predetermined character string. 3 is a block diagram illustrating an example of a processing circuit of the pre-information processing circuit according to the embodiment. FIG. 3 is a diagram illustrating an example of a Moore machine filter for data of a vehicle torque sensor according to the first embodiment. FIG. 3 is a diagram illustrating an example of a Moore machine filter for data of a gear sensor of the vehicle according to the first embodiment. FIG. 4 is a diagram illustrating an example of a Moore machine filter for data of an accelerator sensor of the vehicle according to the first embodiment. 6 is a graph showing a simulation result of a Moore machine filter with respect to the data of the torque sensor of the vehicle according to the first embodiment, and showing a filtered character string length with real time with respect to an input character string length with real time. 4 is a graph showing a simulation result of a Moore machine filter with respect to data of a gear sensor of the vehicle according to the first embodiment, and showing a filtered real-time character string length with respect to an input real-time character string length. 6 is a graph showing a simulation result of a Moore machine filter with respect to data of an accelerator sensor of the vehicle according to the first embodiment, showing a filtered character string length with a real time with respect to an input character string length with a real time. 5 is a graph showing a simulation result of a Moore machine filter with respect to data of a vehicle torque sensor according to the first embodiment, showing execution time with respect to an input character string length with real time. 4 is a graph showing a simulation result of a Moore machine filter with respect to data of a gear sensor of an automobile according to the first embodiment, and is a graph showing an execution time with respect to an input character string length with real time. 5 is a graph showing a simulation result of a Moore machine filter with respect to data of an accelerator sensor of the vehicle according to the first embodiment, and is a graph showing an execution time with respect to an input character string length with real time. 4 is a graph showing a simulation result of a Moore machine filter with respect to data of a vehicle torque sensor according to the first embodiment, showing a memory usage amount with respect to an input character string length with real time. 4 is a graph showing a simulation result of a Moore machine filter with respect to data of a gear sensor of the vehicle according to the first embodiment, and showing a memory usage amount with respect to an input character string length with real time. 4 is a graph showing a simulation result of a Moore machine filter with respect to data of an accelerator sensor of the vehicle according to the first embodiment, and showing a memory usage amount with respect to an input real-time character string length. 10 is a graph showing simulation results of a tool according to a comparative example with respect to data of a vehicle torque sensor, and showing execution time with respect to an input character string length with real time. 10 is a graph showing simulation results of a tool according to a comparative example with respect to data of a gear sensor of an automobile, and showing execution time with respect to an input character string length with real time. 9 is a graph showing simulation results of a tool according to a comparative example with respect to data of an accelerator sensor of an automobile, and showing execution time with respect to an input character string length with real time. FIG. 9 is a block diagram illustrating a configuration example of a pre-information processing circuit according to a second embodiment. FIG. 3 is a diagram illustrating a configuration example of a buffer unit. It is a figure showing an example of a state transition diagram of an automaton. It is a figure showing an example of a state transition diagram of an automaton described using a state with a counter. FIG. 14 is a diagram illustrating an example of a state transition diagram of the Moore machine according to the second embodiment. FIG. 14 is a diagram illustrating an example of a state transition table of the Moore machine according to the second embodiment. FIG. 19 is a diagram illustrating an example of a state management table of the moor machine according to the second embodiment. FIG. 9 is a diagram illustrating each functional block included in a front information processing circuit according to a second embodiment. 9 is a flowchart illustrating a flow of a process performed by a front information processing circuit according to a second embodiment. It is a flow chart which shows a flow of processing at the time of a state transition of a Moore machine. It is a flowchart which shows the flow of a process of the front information processing circuit when the real-time constrained Moore machine is used. It is a flowchart which shows the flow of the process at the time of the state transition of the Moore machine with a real time constraint. It is a flowchart which shows the determination process of a real-time automaton. It is a flowchart which shows the approximation process which approximates the automaton with real-time restrictions to a real-time automaton. FIG. 13 is a block diagram illustrating a configuration example of an automobile control system having an automatic stop mechanism at the time of abnormality according to a third embodiment. FIG. 14 is a block diagram illustrating a configuration example of a vehicle control system having a traveling route optimization mechanism for a semi-connected car according to a fourth embodiment. FIG. 18 is a block diagram illustrating a configuration example of a communication system having a mechanism for monitoring an attack on a server device and an access blocking mechanism according to a fifth embodiment.

  Hereinafter, embodiments and examples according to the present invention will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals.

Embodiment.
Monitoring forms the basis of real-time, runtime verification techniques for embedded physical information systems. Mathematically, the monitoring problem is formulated as a pattern matching problem for a pattern automaton. The present inventors are motivated by embedded applications (especially those having a limited capacity of a communication path between a sensor and a processor monitoring the sensor), and are studying filtering as a pre-processing of monitoring. For a given pattern automaton, we propose a method to configure a Moore machine that functions as a filter.

  Its construction is automaton-theoretic, and we have found that the use of Moore machines is particularly suitable for embedded applications. This is not only because the sequential calculation by the Moore machine is relatively low cost, but also because the Moore machine is compatible with hardware acceleration by a dedicated circuit. We also demonstrate soundness (don't miss a match). We perform this study in the following situation setting. One is a setting without real-time constraints, and the pattern is described by a non-deterministic finite automaton (NFA). The other is a setting with a real-time constraint. A pattern is described by an automaton with a real-time constraint. Extending a timeless configuration to a timed configuration is technically complex, but the following embodiments and examples will demonstrate its practical benefits. In the embodiment, a chapter number and a section number are assigned for convenience of explanation.

1. Introduction 1.1 Monitoring and real-time constrained pattern matching

  The physical information system (Cyber Physical System; CPS) is becoming more and more complex. This is also due to the rapidly developing digital control that realizes new functions such as autonomous driving as well as efficiency such as fuel efficiency of automobiles. Therefore, properly understanding such systems remains an important and challenging task.

  Due to the complexity of physical information systems (CPS) and other reasons, such as black-box parts provided by other suppliers, formal verification in the traditional sense can be applied to real-world physical information systems (CPS). It is difficult to apply. For this reason, researchers and practitioners have turned their attention to so-called lightweight formal verification. Runtime verification is one such approach, in which the execution result sequence of a given system is checked against a given specification. Various algorithms for monitoring have been proposed for this purpose.

Mathematically speaking, there is a pattern matching problem as one of the general formulations of the monitoring problem. (Another general formulation is what we call the pattern search problem. Pattern search Is easier than pattern matching, but gives less information.) When the execution result column is given by the string _{w = a 1 a 2 ... a} n, an output to be expected, the subscript (i, j) of the string w that satisfies the given pattern pat a set of limits A set of things representing

である。パターンｐａｔは文字列、文字列の集合、正規表現、あるいはオートマトンなどによって与えられる。また上の式（１）は、ｉ番目からｊ番目までの文字列がパターンｐａｔと一致することを意味する。

It is. The pattern pat is given by a character string, a set of character strings, a regular expression, an automaton, or the like. Expression (1) above means that the i-th to j-th character strings match the pattern pat.

(Example 1.1): Consider a regular expression given by a character string w1 = abbbbbaab and A1 = a (a *) b. Here, there are three matchings, and Match (w ₁ , A ₁ ) = {(1, 2), (7, 9), (8, 9)}.

In physical information systems (CPS), an important issue is the handling of real-time limited time versions of pattern matching. In one common formulation, the execution result sequence is given by a time-stamped string. This is a character string (character string) with a time record. For example, the character string w ₂ = (a, 0.1) (b, 2.5) (a, 3.5) (b, 4.8) ). The pattern pat is given by a real-time-constrained automaton (TA). Under the time-pattern (t, t ′) representing the restriction of the character string w, the restriction is set to the real-time constrained automaton (TA). The set of things as accepted by A

が計算される。時間なしの設定とは異なり、実時間制約付きオートマトン（ＴＡ）Ａではさまざまな実時間についての制約を表現することができ、物理情報システム（ＣＰＳ）の実行結果列のよりきめ細かい分析ができるようになる。

Is calculated. Unlike the setting without time, the real-time constrained automaton (TA) A can express various real-time constraints and allow a more detailed analysis of the execution result sequence of the physical information system (CPS). Become.

(Example 1.2): Character string w ₂ with time stamp = (a, 0.1) (b, 2.5) (a, 3.5) (b, 4.8) and pattern “b is a Appears within 2 seconds after appearing "(the real-time constrained automaton (TA) corresponding to this pattern is essentially the same as in FIG. 9). Any matching involves a second run of a and b. Note that the first run is too far away. Such matching is given, for example, by a character string w ₂ | _(3,5) , but there are uncountable infinite number of such matchings. This set of matchings is symbolically represented as {(t, t ′) | 2.5 ≦ t <3.5, 4.8 <t ′}.

  Despite obvious applications to various aspects of the design and deployment of physical information systems (CPS), research on real-time constrained pattern matching has only recently begun. , 4, 6). Therefore, the practical application of the real-time constrained pattern matching in the industrial world is extremely limited.

1.2 Remote monitoring of embedded applications This embodiment proposes filtering for pattern matching with real-time constraints or pattern matching without real-time constraints. This is preprocessing applied to the input character string.

  The motivation for this research comes from embedded applications. In an embedded system, which is an important aspect of a physical information system (CPS), it is common for sensors and processors (which perform monitoring calculations) to be in physically separate locations. In addition, these channels often have limited capacity (see FIG. 1).

  FIG. 1 is a block diagram illustrating a configuration example of a physical information system (CPS) according to the embodiment.

  In FIG. 1, a physical information system (CPS) includes a sensor device 1 and a monitor device 2, which are connected via a communication line 10 having a limited communication capacity such as a CAN bus or a wireless network. Connected. Here, the sensor device 1 includes a sensor 3 and a front information processing circuit 4 having a lower speed processor, and the monitor device 2 includes a rear information processing circuit 5 having a higher speed processor. The display unit 6 is provided.

  Examples of such situations can be seen, for example, in modern automobiles. There, a sensor device 1 in the engine collects data and transmits it to a monitor device 2 having a remotely mounted processor, for example, to avoid heat and vibration of the engine. The sensor device 1 and the monitor device 2 are connected to each other via a communication line 10 such as a controller area network (CAN). This communication line 10 is subject to severe performance restrictions for cost reduction. Another example can be found in IoT (Internet of Things) devices such as home appliances and automobiles connected to a communication line 10 such as a network. The IoT device constantly transmits its state to the server device, and the server device installed in the cloud monitors the device. The wireless communication line is limited by, for example, the battery capacity of the device.

  In the present embodiment, the pre-information processing circuit 4 is an automaton describing a predetermined matching condition regarding sequence data of an input real-time time-stamped event (automaton with real-time constraint or without real-time constraint). Generating a Moore machine based on, and using the generated Moore machine, performing filtering to substantially remove data that does not match the matching condition from the sequence data, outputting sequence data of a filtering result, and outputting The serial digital data is transmitted to the downstream information processing circuit 5 via the communication line 10. In response, the post-processing unit 5 extracts sequence data that matches the matching condition from the sequence data of the filtering result and outputs the sequence data to the display unit 6.

1.3 Filtering for Real-Time Constrained Pattern Matching In such remote monitoring situations, it is a natural idea to reduce the amount of data sent from the sensor to the processor so as not to affect the monitoring results. . Many sensors have built-in processors, which can be used for preprocessing. Here, it is assumed that the preprocessor (with built-in sensors, FIG. 1) is much slower than the processor that performs the actual monitoring. That is, the preprocessing must be cheap in terms of computational complexity.

FIG. 2 conceptually shows a relationship between a pattern matching process performed in the physical information system (CPS) shown in FIG. 1 and a filtering process. In FIG. 2, a filter unit (M _{N, A} ) 7 is a functional block included in the sensor device 1, for example, a functional block realized by the front information processing circuit 4. The pattern matching unit 8 is a functional block provided in the monitor device 2, for example, a functional block realized by the post-processing unit 5. That is, as shown in FIG. 2, in the workflow proposed by the present inventors, the filtering unit (M _{N, A} ) 7 is used to apply inexpensive filtering to the input character string in terms of computational complexity. This reduces the load on the communication line 10 for transmitting data from the front information processing circuit 4 to the processor of the rear information processing circuit 5, and further reduces the load on the processor.

1.4 Moore machine as a filter

In this embodiment, two settings for monitoring are addressed:
(1) Setting without real-time constraint: The execution result sequence is a character string w∈Σ *, and the pattern is given by a nondeterministic finite automaton (NFA) A on Σ.
(2) Setting with real-time constraint: The execution result sequence is a character string with a real-time constraint, and the pattern is given by a real-time-constrained automaton (Timed Automaton; TA). The technical contribution of the present inventors is to provide a filter M _{A, N} realized as a Moore machine based on the pattern automaton A and the buffer size N (natural number). A Moore machine is a well-known model of stateful computation, and is an automaton with an additional state-dependent output function. This works well sequentially and synchronously, reading one input character, moving to the next state, and outputting one character. This characteristic is particularly suitable for logic synthesis of a digital circuit, and hardware acceleration by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuits) can be used.

The sequential operation of such a Moore machine is in sharp contrast to the operation of pattern matching. Since the pattern is given by the automaton A in our setting, the matching length (for example, | w | _{[i, j]} | = j such that w | _{[i, j]} ｉL (A) is satisfied) −i + 1) is not fixed. Therefore, it is necessary to try the input character string w while moving the matching window back and forth at different sizes and different positions (see FIG. 3A). FIG. 3A is a timing chart showing the back and forth movement processing in the pattern matching used in the embodiment.

This is because the (sequential) filtering operation by the front-end information processing circuit 4 having a relatively low-speed preprocessor and the back-end information processing circuit 5 having a relatively high-speed main processor, as shown in FIG. This indicates that there is a qualitative difference between the pattern matching operation and the moving operation. In the configuration of the present inventors, a Moore machine without a real-time constraint is generated as the filters MA _{and N} even if the setting has a real-time constraint.

The output of the Moore machine filter MA _{, N} is the same as the input (real-time constrained) string except that some characters are masked with the unused character ⊥ ⊥ means a character that cannot be included in a set of characters constituting a character string (input character string) input to the Moore machine filter MA _{, N} ). For example, under the pattern A = aa * b, w = abbbbbbaab is processed to ab⊥⊥⊥⊥aab. The binary representation of the length of successive ⊥ reduces the size of the data exponentially. Furthermore, if only the matched partial character string w | _{[i, j]} is interested (that is, if the subscripts i and j are not interested), the continuous 潰 can be reduced to one ⊥. Note that removing all ⊥ in the filtering stage may cause fake matching in the pattern matching stage (see FIG. 2).

The Moore machine filter M _{A, N} of the present inventors is composed of a pattern automaton A and a positive integer N representing a buffer size. Depending on the parameter N, the user can increase the cost of filtering (as N is increased, the number of states of the Moore machine filter MA _{, N} is increased) and the size of the filtered character string (as N is increased, 増 え is increased. (The multiplied character string becomes smaller). This flexibility makes the algorithm suitable for various hardware configurations.

We implement this configuration and show experimental results for settings with real-time constraints (this is more difficult). Examples are from the automotive sector. As a result, for the pattern A (real-time constrained automaton (TA)) A and the input time-stamped character string w according to the actual problem, the filtered character string is 2 to 100 times as large as the original character string w. See what can be shorter. Further, it is experimentally confirmed that the execution of the Moore machine filter MA _{, N} is light in calculation amount. Further, it can be seen that the use of the filter unit 7 in FIG. 2 accelerates the pattern matching with real-time constraints by 1.2 to 2 times.

  With a theoretical analysis of this configuration, we demonstrate soundness, ie, that all matching of the original input string is preserved by the filter. This soundness is proven both with and without real-time constraints. Note, however, that soundness is satisfied by a trivial identity filter. Therefore, the benefits of filtering are not very obvious from the soundness itself. In addition to experiments, we describe some theoretical results on the performance of filtering in a real-time unconstrained setting. This is as follows.

  When the language L (A) is finite (setting of multiple character string matching), the completeness (meaning that all unnecessary character strings are masked) and the monotonicity (the filtering result improves as N increases). Since the setting with the real-time constraint has the same basic idea as the setting without the real-time constraint, these results also show the performance advantage of the configuration with the real-time constraint.

  The construction of our filter is automaton theoretical and consists of the following two basic steps. (1) Prepare a buffer (of size N), and (2) Decide. For a second step in a real-time constrained setup, a given real-time constrained automaton (TA) is overestimated by a one-clock deterministic TA; (See Section 5.3 of Non-Patent Document 2).

1.5 Contribution The contributions of the present inventors (Special Technical Features (STF), which is a feature of the embodiment), are summarized as follows.
(1) Configuration of filters MA _{and N} for pattern matching without any real-time restriction on automaton A. The filters are provided on a Moore machine and thus operate simply, sequentially and synchronously. Further, it is compatible with hardware acceleration by a logic circuit. The parameter N allows the user to adjust the trade-off between the computation cost and the filtering effect.
(2) Configuration of Moore machine filters MA _{and N} for pattern matching with real-time constraints. Given a real-time constrained automaton A as a pattern and a buffer size, (without real-time restrictions) form a Moore machine filter MA _{, N.} This configuration is more general because it is an extension of the one without real-time constraints, and utilizes a zone-based configuration of the automaton with pattern real-time constraints. Considering practicality, we consider this real-time constrained configuration to be a major contribution of this embodiment.
(3) Soundness (preservation of all matches) is proved by setting with real-time constraints and no real-time constraints.
(4) In a setting with real-time constraints, further demonstrate our theoretical results on the performance of our filters.
(5) Experiments showing the implementation of the real-time constrained configuration and the benefits of our filter configuration.

1.6 Pattern Matching vs. Pattern Search Another mathematical formulation of monitoring (ie another option for pattern matching) is what we call the pattern search problem. This asks whether the matching set (see section 1.2) is empty or not. The pattern search is attractive because it can easily be reduced to an assignment determination problem. Roughly speaking, when the pattern automaton A is given, a self-loop may be added to the initial state so that the prefix of the input character string can be ignored, and then it may be monitored whether the accepting state becomes active. . Pattern search is already well studied in the context of monitoring.

  Pattern matching requires memorizing subscripts (FIG. 3A) and is computationally more expensive than pattern search. However, there are strong implications for real-world monitoring applications (especially in remote monitoring as in Example 1.3 below). Note that remote monitoring is often simply quasi-online. The logs may be large chunks and reach the monitor in short bursts. Therefore, it is essential to be able to extract which part of the received log gives the warning.

  The applicability of pattern matching to monitoring applications is well recognized by the community, and the literature has been rapidly increasing in recent years (for example, see Non-Patent Documents 4 and 5).

Example 1.3 (Semi-Online Remote Monitoring): As a specific example of remote monitoring (FIG. 1), consider a semi-network connected vehicle. This stores an operation log in a memory and transmits the log to the center via the Internet when the vehicle stops in a range of a known wireless network. Log analysis is performed at the center. The driving log is a time-stamped character string containing information on the position, speed, and accelerator of the vehicle. One such time-stamped string w (taken from ROSBAGSTORE, rosbag.tier4.jp) looks like FIG. 3B when plotting the position of the car.

  FIG. 3B is a plan view showing an example of a position plot in pattern matching in a conventional document, and FIG. 3C is a plan view showing the specification of a section in the position plot of FIG. 3B.

  Here, "the plot is discontinuous" means that data may be lost due to, for example, loss of the GPS signal. Among such road sections, it is assumed that the user is interested in a section in which the accelerator exceeds a certain threshold for 10 seconds or more. The real-time constrained pattern matching is performed on the character string w using an appropriate pattern automaton A. By mapping the specified time section to the plot of the position, the section of the road that the user wanted to know can be specified (see FIG. 3C, the hatched portion is generated by the tool MONAA).

(Configuration of the Embodiment) Terms are defined in Chapter 2. Chapter 3 constitutes a Moore machine filter for pattern matching without real-time constraints. In addition, they demonstrate properties such as soundness. The same idea is used in Chapter 4 for filtering for more complex problems, real-time constrained pattern matching. Here we prove its soundness. Chapter 5 shows the implementation and experimental results for the case with real-time constraints. Related studies are discussed in Chapter 6.

2. Preparation

  set

はΣ上の文字列の集合である。文字列ｗ＝ａ_１ａ_２…ａ_ｎ（ここで、ａ_ｉ∈Σ）の長さｎは｜ｗ｜と書かれる。

Is a set of character strings on Σ. The length n of the character string w = a ₁ a ₂ ... _An (here, a _i ∈Σ) is written as | w |.

Non-deterministic finite automata _{(NFA) A = (Σ,} S, s 0, S F, E) and, for the string w∈Σ * on common alphabet Σ, of the automaton A on the string w run (RUN)

は列

Is a column

であって、任意のｉ∈［１，｜ｗ｜］について（ｓ_ｉ−１，ｗ_ｉ，ｓ_ｉ）∈Ｅが成り立つもののことである。ラン

And (s _i−1 , w _i , s _i ) ∈E holds for any i∈ [1, | w |]. run

はｓ_｜ｗ｜∈Ｓ_Ｆが成り立つとき受理する（受理状態となる）という。

The _{s | w |} ∈S _F is accepted when satisfied that (the accepting state).

The power set of X is written P (X). The union of X and Y is XUY. For the alphabet Σ, the set Σ which is expanded with unused symbols _⊥ is written as Σ ｛⊥｝.

  The set {1, 2,..., N} is used as the value range of the counter. This is written as Z / NZ because it uses its algebraic structure (eg addition with modulo N).

Moore machine _{M = (Σ in, Σ out} , Q, q 0, Δ, Λ) is. Here, _{ｉｎ in} and Σ _out are alphabets of input and output, Q is a finite set of states, q ₀ ∈Q is an initial state, Δ: Q × Σ _in → Q is a transition function, and Λ: Q → Σ _out is Output function. For the Moore machine M and the input character string w = a ₁ a ₂ ... _An ∈Σ * _in (where a _{i in} ), the run of the Moore machine M on the character string w

は列

Is a column

であって、任意のｉ∈［１，｜ｗ｜］についてｑ_ｉ＝Δ（ｑ_ｉ−１，ａ_ｉ）を満足するものである。このとき、文字列ｗ上のムーアマシンＭの出力文字列ｗ'∈Σ＊_ｏｕｔは、ｗ'＝Λ（ｑ_０）Λ（ｑ_１）…Λ（ｑ_ｎ−１）∈Σ＊_ｏｕｔである。

And satisfies q _i = Δ (q _i−1 , a _i ) for an arbitrary i∈ [1, | w |]. At this time, the output character string w′∈Σ * _out of the Moore machine M on the character string w is w ′ = Λ (q ₀ ) Λ (q ₁ )... Λ (q _n−1 ) ∈Σ * _out . .

3. Moore machine filtering for pattern matching 1: no real-time constraints

3.1 Formulation of the problem (definition 3.1) (no real-time constraints pattern matching): For non-deterministic finite automaton on the alphabet Σ (NFA) A and a string _{a 1 a 2 ... a n ∈Σ} *, pattern Matching problem is a matching set

を問うものである。ただし、ｗ｜_{［ｉ，ｊ］}＝ａ_ｉａ_ｉ＋１…ａ_ｊである。

Is to ask. _{However, w} | a _{[i, j] = a i} a i + 1 ... a j.

  Our goal is the workflow shown in FIG. The input / output type of the filter unit 7 will be defined by the following general definition.

(Definition 3.2) (Moore machine for pattern matching without real-time constraints): Let automaton A be a non-deterministic finite automaton (NFA) on alphabet Σ and N be a positive integer. The filter buffer size N of the automaton A, Moore machine filter _{M = (Σ in, Σ out} , Q, q 0, Δ, Λ) a, and satisfies the following.

(1) _{ｉｎ in} = Σ _out = Σ _⊥
(2) Consider a character string w ^N where w = a ₁ ... An _n * is an arbitrary character string and 終端 is added at the end. The output string of Moore machine M for this string w⊥ ^N should not to be in the form of a ⊥ ^{N w} '. However, the character string w ′ = b ₁ ... B _n , and the character b _i is either the mask ⊥ or the character a _i for an arbitrary i. Character _{a i} at position i is that has passed _{when b} i = _{a i} is established. Otherwise (ie, if b _i = ｂ), the character a _i is said to be masked.

  The Moore machine filter M is said to be sound when all the matching sections are kept. this is,

となる任意のｋ∈［１，ｎ］についてｂ_ｋ＝ａ_ｋが成立するという意味である。

This means that b _k = _ak holds for any k∈ [1, n] such that

  FIG. 4 is a conceptual diagram illustrating padding processing of filtering in the embodiment.

And the buffer size N, tried to explain about the afterthought in ⊥ ^N of input and output string. The addition means that filtering is performed with a delay of N steps in the method illustrated in FIG. This delay is due to the way our Moore machine operates. This is because the Moore machine reads the input string from left to right, stores N characters in a FIFO buffer in a format encoded in the state space Q, and uses it as an output string when extracting characters from the FIFO buffer. Output. That is why a delay of N steps occurs.

  FIG. 5 is a conceptual diagram showing a filtering process by the Moore machine in the embodiment.

5, first, the buffer are exhausted filled with ⊥ (step S0 in FIG. 5), which is why the prefix ⊥ ^N appears at the output string ⊥ ^{N w} '. Trailing afterthought ⊥ ^N of the input string W⊥ ^N is required to retrieve the contents of the buffer (step S (n + 1) from the step S (n + N)). During the process of FIG. 5, some of the characters of the character string w = a ₁ ... A _N are masked (b _i = ⊥), but are not explicitly shown in FIG.

3.2 Configuration of Moore Machine Filter MA _{, N}

(Definition 3.3) ((No real time constraint) Moore machine filter M _{A, N} for pattern matching): Let Σ be an alphabet, N be a positive integer, and A = (Σ, S, s ₀ , S _F) , E) is a nondeterministic finite automaton (NFA). The Moore machine filter M _{A, N} = (Σ _⊥ , Σ _，, Q, q ₀ , Δ, Λ) is defined as follows.

  Here, the state space Q is

とする。ここで、Ｚ／ＮＺはモジュロＮでの足し算を備えたＮ元集合である。

And Here, Z / NZ is an N-ary set with addition by modulo N.

  The initial state is

である。

It is.

Transition Δ: Q × Σ _⊥ → Q is determined as follows. For any a∈Σ _⊥ ,

  However,

であり、

And

である。

It is.

  here,

である。

It is.

Finally, the output function Λ: determine Q → Σ _⊥ the in the following manner.

Describe intuition. The configuration of the Moore machine filter MA _{, N} is a combination of the following three blocks: a determinization processing unit (CPU 20 in FIG. 15 described later in detail), a counter (included in 22b in FIG. 15), This is a buffer of size N (22a in FIG. 15).

(Determinized) Pattern A is a non-deterministic finite automaton (NFA), but what we want is a deterministic Moore machine. This determinization is a part of the state space Q

に冪集合による構成Ｐが現れる理由を説明している。例えば、この部品の元｛（ｓ_１，ｎ_１），…，（ｓ_ｋ，ｎ_ｋ）｝は「非決定的有限オートマトン（ＮＦＡ）Ａにおいて、状態ｓ_１，…，ｓ_ｋはアクティブである」ということを意味している。式（４）を見ると、これは普通の決定化をしていることがわかる。例外は式（４）で（ｓ_０，０）を追加していることである。これは、入力文字列のどこからでもマッチングを始められるようにするためである。

Explains the reason why the composition P by the power set appears in FIG. For example, the element {(s ₁ , n ₁ ),..., (S _k , n _k )} of this part is “states s ₁ ,..., _Sk are active in nondeterministic finite automaton (NFA) A”. It means that. Looking at equation (4), it can be seen that this is a normal determinization. The exception is that (s ₀ , 0) is added in equation (4). This is so that matching can be started from anywhere in the input character string.

(Counter) Further, the active state of moving the automaton A has a counter (in 22b in FIG. 15) indicating how many steps have been moved from the initial state. This is the part Z / NZ of the state space Q. The maximum values of these counters are the same as the buffer size N. When the maximum value is reached, the counter starts at one. It can be seen from equation (4) that the active counter increases by one with modulo N. For example, the maximum value of the counter may be set to 2 × N, and the increment value may be set to 2 instead of 1. The increment value is not limited to 1, and may be a predetermined value such as 2 or 3 which is a natural number. .

(Buffer) A FIFO buffer of size N (22a in FIG. 15) is a second component in the state space Q.

が現れる理由を説明している。Ｎ個のセルそれぞれがΣ_⊥の文字とラベル（ｐａｓｓ又はｍａｓｋ）を保持している。式（３）と式（５）を見ると、バッファの基本的な動作は一番左の要素を取り出し、読んだ文字を右に追加することだと分かる。

Explains why appears. Each of the N cells holds a character _{} and a label (pass or mask). Equations (3) and (5) show that the basic operation of the buffer is to extract the leftmost element and add the character read to the right.

  It is the buffer label (pass or mask) that determines whether a character is masked. The prescribed label is mask (third case in equation (5)), and if it does not change for N steps, the corresponding character in the output is masked with ⊥ (second case in equation (6)). The label can change from mask to pass for two different reasons (the first two cases in equation (5)).

1. For the second expression (5) is when the plurality of characters up to the end of the buffer forms a matched against pattern A, leads to the receiving state S∈S _F pattern A. At this time, these characters are marked with "pass" to clearly indicate that they must be passed to pattern matching (FIG. 2). Number of characters to be passed ψ (S ') is calculated using the counter n that is associated with the active s∈S _F.
2. Condition for the first case of equation (5)

は、あるアクティブな状態ｓのカウンタが最大値Ｎに達したという意味である。この場合、Ａのこのアクティブ状態ｓが最終的に受理状態に到達するのかどうかがはっきりしない。安全側に倒すために、Ｎ個の文字全てをマスクせずにパターンマッチングに引き渡す。実時間制約なしの設定では、フィルタリングの完全性が失われるかもしれない箇所はここだけである。

Means that the counter in a certain active state s has reached the maximum value N. In this case, it is not clear whether this active state s of A will eventually reach the accepting state. In order to fall to the safe side, all N characters are passed on to the pattern matching without masking. This is the only place where the integrity of the filtering may be lost in a setting without real-time constraints.

  In summary, definition 3.3 constitutes a Moore machine that operates in the manner illustrated in FIG. The Moore machine state space is a combination of the following: the determinant of the pattern NFA A, a counter that counts the number of steps since the initial state, and N labeled with a pass or mask. This is a FIFO (First-In First-Out) buffer for storing characters.

(Proposition 3.4): The Moore machine M _{A, N} is a filter with a buffer size N of A in the sense of definition 3.2.

  In our implementation, we define the filter as a state space, as described in 3.2.

を持つようなムーアマシンそのままとしては実現していない。代わりに、状態空間Ｑを「バッファ部分」

It is not realized as a Moore machine as it is. Instead, state space Q is "buffer part"

と「非バッファ部分」

And the "unbuffered part"

に分割して、前半のバッファ部分を必要になり次第生成している。より正確に述べると、非バッファ部分ははじめに、決定的有限オートマトン（ＤＦＡ）として一度に構成され、このＤＦＡはサイズＮの配列として実現されたバッファ部分をどのように制御するかを支配している。実例を例３．６に示す。

And the buffer part of the first half is generated as needed. More precisely, the non-buffer part is initially configured at one time as a deterministic finite automaton (DFA), which governs how to control the buffer part implemented as an array of size N. . An example is shown in Example 3.6.

(Proposition 3.5): Let A = (Σ, S, s ₀ , S _F , E) be a nondeterministic finite automaton (NFA). For the induced Moore machine filter MA _{, N} , the size of the non-buffered part P (S × (Z / NZ)) of its state space is suppressed by O (2N · | S |).

Therefore, the memory usage of the non-buffer portion including the transition is O ( ^{2N · | S |} · | Σ |). The memory usage of the buffer portion is O (N · log | Σ |). In summary, the amount of space calculation when the Moore machine filter M _{A, N} of the present inventors is executed is O ( ^{2N · | S |} · | Σ |).

  The spatial complexity is exponential for N, but this comes from the power set construction for the unbuffered part P (S × (Z / NZ)). However, experimentally, the memory consumption does not necessarily increase exponentially for N. This is because not all states of P (S × (Z / NZ)) can be reached (see RQ2 in Chapter 5).

  FIG. 6A is a diagram illustrating an example of a pattern that is a non-deterministic finite automaton (NFA) according to the embodiment, and FIG. 6B is a diagram illustrating an example of a non-buffer portion of the Moore machine filter according to the embodiment. FIG. 7A is a diagram showing a Moore machine filter run for a predetermined character string.

(Example 3.6): Consider a pattern aa * b. This is illustrated in the non-deterministic finite automaton (NFA) A ₀ of FIG. 6A. The Moore machine filter _MA0,2 of definition 3.3 is shown in FIG. 6B, where the buffer state has been omitted. The run with the character string w = abbbaab is shown in FIG. 7A. The output character string is "ab @ aab", which indicates that the filtering result is ab @ aab.

7A shows a run of _{M A0,2} for string w = abbbaab. The table in FIG. 7A shows the state of the buffer, and character data is added to the buffer from the right. "The symbol of a, arrow and b from the top" indicates that the input character is a and b is an output.

3.3 Properties of Moore Machine Filter M _{A, N In} the remainder of this section, A is a pattern NFA (non-deterministic finite automaton) A = (Σ, S, S ₀ , E, S _F ), N is a positive integer, M _{A , N} = (Σ _⊥ , Σ _⊥ , Q, q ₀ , Δ, Λ) as the Moore machine filter of definition 3.3. The _{w = a 1 a 2 ... a} n a string on sigma, ⊥ ^N w Moore machine filter _{M A} for the input string W⊥ ^N a _', and outputs a string of _N. It is assumed that a character string w ′ = b ₁ b ₂ ... B _n . However, a _{b i ∈Σ ⊥.}

(Theorem 3.7) (Soundness): The Moore machine filter MA _{, N} is sound in the meaning of the definition 3.2. There is an upper bound on the length of matching, and completeness is established if the buffer size N is greater than or equal to the upper bound. This is essentially the same as multiple string matching.

(Theorem 3.8) (Completeness): It is assumed that max {| w ||| w {L (A)} ≦ N <∞. In this case, a nondeterministic finite automaton (NFA) A ′ in which L (A) = L (A ′) and in which the Moore machine filter M _{A ′, N} is complete can be configured. The second half means the following: If the subscript k satisfies a _k = b _k , the interval [i, j] where kｉ [i, j] and w | _{[i, j]} （L (A) Exists.

The intuition of monotonicity is that as the buffer size N 'increases, the Moore machine filter MA _{, N'} masks more characters, but also increases the state space. The exact claim is more complicated, and the larger buffer size N "must be a multiple of the smaller one.

(Theorem 3.9) (monotonicity): For any positive real number N ′, MA _{, N ′} is defined as a Moore machine filter of definition 3.3, and { ^{N ′} w ′ ^{(N ′)} is an input character string w}. the output string of ^'Moore machine filter M _{aN for'} ^N. It is assumed that w ′ ^{(N ′)} = b ₁ ^{(N ′)} b ₂ ^{(N ′)} ... b _n ^{(N ′)} . Here, b _i ^{(N ′)} ∈Σ _⊥ . For any positive real number n, any subscript k of N ′ and w, if b _k ^{(N ′)} = ⊥, then b _k ^{(nN ′)} = ⊥.

  As stated in Proposition 3.5, the state space of the Moore machine filter is exponentially larger than the state space of A. This is due to the power set construction required for deterministic branching. By sacrificing execution time, nondeterministic finite automata (NFAs) can also be determined as needed, which usually requires less memory space.

4. Moore Machine Filtering for Pattern Matching 2: With Real-Time Constraints We propose a configuration of a Moore machine filter for real-time constrained pattern matching, which is the main contribution of the present inventors. Although the basic idea is the same as the setting without a real-time constraint (Chapter 3), since a real-time-constrained automaton (Timed Automata; TA) cannot generally be determined, it is a technical problem. Here, the present inventors use one clock decision (for example, see section 5.3 of Non-Patent Document 2). The configuration overestimates reachability, so that filtering integrity can be maintained. Moreover, the local nature of the resulting TA, which has only one clock variable that resets at each transition, allows the creation of filters that are finite state Moore machines without real-time constraints.

4.1 Formulation of problem (Definition 4.1) (character string with time stamp): Let Σ be an alphabet. The character string with a time stamp on the alphabet Σ is a character string w of a pair (a _i , τ _i ) ∈Σ × R _{> 0} , and τ _i <τ for an arbitrary i∈ [1, | w | −1]. _{i + 1} is satisfied.

をタイムスタンプ付き文字列とする。アルファベットΣ上のタイムスタンプ付き文字列の集合をＴ（Σ）と書く。

Is a character string with a time stamp. A set of character strings with a time stamp on the alphabet Σ is written as T (Σ).

The partial character strings (a _i , τ _i ), (a _{i + 1} , τ _{i + 1} ),..., ( _Aj , τ _j ) are written as w (i, j). For t∈R _{≧ 0} , shift t of character string w (shift only time t)

と定める。ただし、

Is determined. However,

である。タイムスタンプ付き文字列

It is. String with time stamp

と

When

について、これらの吸収連結とは、

With regard to these absorption consolidation,

であり（ただし

And (but

と

When

はどちらも普通の連結）、これらの非吸収連結とは

Are both ordinary consolidations), and what are these non-absorbing consolidations?

である。吸収連結ｗ○ｗ'はτ_｜ｗ｜＜τ'_１のときにのみ定義されることに注意する。

It is. Absorption consolidated w ○ w 'is τ _{| <τ | w'} note to be defined only at the time of the _1.

  Character string with time stamp on alphabet Σ

と、時刻ｔ，ｔ'∈Ｒ_＞０で、時刻ｔ＜ｔ'を満足するものについて、タイムスタンプ付き文字列区間ｗ｜_{（ｔ，ｔ'）}は、拡張アルファベットΣ凵｛＄｝上のタイムスタンプ付き文字列（ｗ（ｉ，ｊ）−ｔ）○（＄，ｔ'−ｔ）で定義される。ここで、パラメータｉ，ｊはτ_ｉ−１≦ｔ＜τ_ｉとτ_ｊ＜ｔ'≦τ_ｊ＋１となるように選ばれている。ここで、タイムスタンプ付き文字列ｗ（ｉ，ｊ）−ｔはｗ（ｉ，ｊ）の（−ｔ）シフトであり、未使用の記号＄は終端文字とよばれる。

And at time t, t ′ {R _{> 0} , satisfying time t <t ′, the time-stamped character string section w | _{(t, t ′)} is the time on the extended alphabet {u} The character string with a stamp (w (i, j) -t) is defined by (○, t'-t). Here, the parameters i and j are selected so that τ _i−1 ≦ t <τ _i and τ _j <t ′ ≦ τ _{j + 1} . Here, the character string w (i, j) -t with a time stamp is a (-t) shift of w (i, j), and the unused symbol ＄ is called a terminal character.

(Definition 4.2) (Real-time constrained automaton): C represents a finite set of clock variables, and Φ (C) is an inequality

の複数の連言の集合を表わしている。

Represents a set of a plurality of conjunctions.

Here, x∈C, c∈Z _{≧ 0} , and

である。実時間制約付きオートマトンＡ＝（Σ，Ｓ，ｓ_０，Ｓ_Ｆ，Ｃ，Ｅ）は組であって、Σはアルファベット、Ｓは状態の有限集合、ｓ_０∈Ｓは初期状態、Ｓ_Ｆ⊂Ｓは受理状態の集合、Ｅ⊂Ｓ×Ｓ×Σ×Ｐ（Ｃ）×Φ（Ｃ）は遷移の集合である。遷移の複数の構成要素（ｓ，ｓ'，ａ，λ，δ）∈Ｅは、ソース、ターゲット、アクション、リセット変数、遷移のガードをそれぞれ表わしている。

It is. A real-time constrained automaton A = (Σ, S, s ₀ , S _F , C, E) is a set, Σ is an alphabet, S is a finite set of states, s ₀ ∈S is an initial state, S _F ⊂ S is a set of acceptance states, and E⊂S × S × Σ × P (C) × Φ (C) is a set of transitions. A plurality of transition components (s, s ′, a, λ, δ) ∈E represent a source, a target, an action, a reset variable, and a transition guard, respectively.

The value with clock ν is defined as a function ν: C → R _{≧ 0} . The t shift ν + t of the clocked value ν is defined as (ν + t) (x) = ν (x) + t. Here, t∈R _{≧ 0} . Real-time constrained automaton A = (Σ, S, s ₀ , _SF , C, E) and time-stamped character string

について、ｗ上のＡのランとは組（ｓ_ｉ，ｖ_ｉ）∈Ｓ×（Ｒ_≧０）^Ｃの列ｒであって、次の条件を満足するものである。

, The run of A on w is a row r of the set (s _i , v _i ) ∈S × (R _{≧ 0} ) ^C , which satisfies the following condition.

(Initial Condition) s ₀ is an initial state, and ν ₀ (x) = 0 for any x∈C.

(Continuous condition) For any i∈ [1, | w |], transitions such that ν _i−1 + τ _i −τ _i−1 | = δ and ν _i (x) = 0 (x∈λ is arbitrary) (S _i−1 , s _i , a _i , λ, δ) εE exists, and v _i (x) = v _i−1 (x) + τ _i −τ _i−1 (where x∈λ).

  A run that satisfies only the continuous condition is called a pass. run

はｓの最後の要素ｓ_{｜ｓ｜−１}がＳ_Ｆに属するとき受理するという。言語Ｌ（Ａ）はタイムスタンプ付き文字列の集合｛ｗ｜ｗ上のＡの受理するランが存在する｝と定義される。

Of _-1 is to accept when belonging to the _{S F |} is the last element _s of _{s |} s. The language L (A) is defined as a set of time-stamped character strings {there is a run accepted by A on w | w}.

  Here, the problem of our goal is described. Algorithms for solving this have been actively studied (for example, see Non-Patent Documents 4 and 5), and a filtering Moore machine as a preprocessor for these algorithms is a contribution of this embodiment.

(Definition 4.3) (Pattern matching with real-time constraint): Let A be an automaton with real-time constraint, w be a character string with a time stamp, and both be on the common alphabet Σ. The real-time constrained pattern matching problem is to find all the sections (t, t ') where the section w | _{(t, t')} is accepted by the real-time constrained automaton (TA) A. That is, the matching set

を求めるものである。

Is what you want.

4.2 Determining one clock of TA The counter and buffer of the three main blocks used in the configuration without the real-time constraint of the filter (Definition 3.3) are used for the setting with the real-time constraint. You can bring it. For overdetermination, the idea of overestimation in Definition 4.5 is used. This is based on (for example, see Section 5.3 of Non-Patent Document 2).

  Start with auxiliary symbols.

(Definition 4.4) (Limit ν | _C , ν ν ′ ′): Let ν: C ′ → R _{≧ 0 be the} value with the clock. The restriction of ν to C⊂C ′ is written as ν | _C : C → R _{≧ 0} . This is (ν | _C ) (x) = ν (x) for any xεC.

ν: C → R _{≧ 0} and ν ′: C ′ → R _{≧ 0} are clocked values. These knots ν′ν ′: C′C ′ → R _{≧ 0} are defined as clocked values on the non-exchange C′C ′ as follows.

A function that maps x _i to r _i (for any _i {1,..., N})

と書かれる。

Is written.

(Definition 4.5) (Determining one clock): A = (Σ, S, s ₀ , _SF , C, E) is a real-time constrained automaton (Timed Automaton; TA), and y is an unused clock. Variable (in other words, y∈C). The real-time constrained automaton (TA) A ′ = (Σ, S ′, s ₀ ′, S _F ′, {y}, E ′) is called one-clock decision of the automaton A when the following conditions are satisfied. .

(1) Arbitrary element of new, finite state space S '

は対（ｓ_ｉ，Ｚ_ｉ）の有限集合

Is a finite set of pairs (s _i , Z _i )

である。ここで、ｓ_ｉ∈ＳはＡの状態であり、Ｚ_ｉは

It is. Here, s _i ∈S is the state of A, and Z _i is

の部分集合でゾーンとよばれる特殊な多角形により与えられるものである。

And is given by a special polygon called a zone.

(2) Arbitrary transition of automaton A '

について、ガードδはクロック変数ｙについての複数の区間の有限和集合である。さらに、それは遷移ＥがオートマトンＡで有効かどうかを反映している。正確には、任意のｕ，ｕ'∈Ｒ_≧０でδを満たすものについて、

Is a finite union of a plurality of intervals for the clock variable y. Furthermore, it reflects whether transition E is valid in automaton A. To be more precise, for any u, u ′ R _{≧ 0} and satisfying δ,

が成立している。ただし、集合

Holds. However, the set

は

Is

で定義される。

Is defined by

(3) Any transition of automaton A 'resets only one clock variable y. In other words, all transitions

について、λ＝｛ｙ｝である。

Λ = {y}.

(4) Arbitrary transition of automaton A '

はＡの遷移を模倣する。より正確には、

Mimics the transition of A. More precisely,

と

When

とする。ｓ'∈Ｓとν'：Ｃ→Ｒ_≧０（ここで、τは経過時間）が存在して、

And s′∈S and ν ′: C → R _{≧ 0} (where τ is elapsed time)

がオートマトンＡの（長さ１の）パスであると仮定する。このとき、ゾーン

Is the path of automaton A (of length 1). At this time, the zone

であって、
１）

And
1)

２）付値

2) Price

（これはクロック集合Ｃ凵｛ｙ｝上のものである）はゾーンＺ'に属する。

(This is on the clock set C u {y}) belongs to zone Z ′.

(5) Automaton A 'is deterministic: arbitrary state

、任意のクロック付値

, Any value with clock

、ａ∈Σ、経過時間を表わすτ∈Ｒ_≧０について、

, A}, and τ∈R _{≧ 0} representing the elapsed time,

からの長さ１のａ，τでラベル付けされたパスは一意である。つまり、もし

The path labeled with a, τ of length 1 from is unique. That is, if

と

When

が両方ともオートマトンＡ'のパスならば、

Are both paths of automaton A ',

かつν'＝ν"となる。（条件３のために

And ν ′ = ν ″ (for condition 3

となっていることに注意する。）

Note that )

(6) The initial state s ₀ ′ of the automaton A ′ is

で与えられる。ここで０は全てのクロック変数を０に写す付値である。

Given by Here, “0” is a value that maps all clock variables to “0”.

(7) The state S belongs to S ′ _F when s∈S _F

が存在するとき、かつそのときに限る。

If and only if exists.

(Proposition 4.6): Let A = (Σ, S, s ₀ , S _F , C, E) be a real-time constrained automaton (TA). The automaton A ′ = (Σ, S ′, s ₀ ′, S _F ′, {y}, E ′) is defined as one clock of the automaton A. At this time, the automaton A ′ satisfies the following properties.

(Simulation) It is assumed that w∈T (Σ) is a character string with a time stamp, and a run on the character string w that reaches the state s∈S in the automaton A exists. At this time, the following is satisfied

が存在する：（１）あるゾーンＺについて

Exists: (1) For a certain zone Z

となる、（２）オートマトンＡ'で状態Ｓへの文字列ｗ上のランが存在する。

(2) There is a run on the character string w to the state S in the automaton A ′.

(Language inclusion) In particular, L (A) ⊂L (A ′).

  Note that definition 4.5 gives properties, not compositions. For the same real-time constrained automaton (TA) A, there are a plurality of one-clock determinants having different sizes and different precisions. In the implementation of the present inventors, for example, a specific configuration proposed in section 5.3.4 of Non-Patent Document 2 is used.

4.3 Configuration of our Moore machine filter MA _{, N} (Definition 4.7) (Moore machine filter MA _{, N} for real-time constrained pattern matching): A = (Σ, S, s) ₀ , S _F , C, E) are automata (TA) with real-time constraints, and N∈Z _{> 0} . The configuration of the Moore machine filter MA _{, N} is performed according to the following steps.

  In the first step, the original real-time constrained automaton (TA) A is extended by a counter. In particular,

を次のように定義する。

Is defined as follows.

、そして

And

In the second step, one clock of the automaton ^AN-ctr is determined (definition 4.5).

がその結果であるとする。

Is the result.

Finally, in the third step, the Moore machine filter MA _{, N} is defined as in the following equation.

  Here, Δ and Λ are defined as follows.

、ただし、状態Ｓ'はオートマトンＡ^{Ｎ−ｃｔｒ−ｄ}での状態Ｓの、文字ａと経過時間τのもとでの一意な後続であり（定義４．５）、

Where state S ′ is a unique succession of state S in automaton ^AN-ctr-d under letter a and elapsed time τ (definition 4.5),

は次式のように定義される。

Is defined as:

  here,

である。

It is.

と定義する。

Is defined.

  FIG. 7B is a block diagram illustrating an example of a processing circuit of the prefix information processing circuit according to the embodiment. 7B, the processing circuit includes a filter unit 11 and a masking application unit 12.

Note that the resulting Moore machine takes a time-stamped string as input. As a result, the input alphabet becomes infinite (that is, Σ _⊥ × R _{≧ 0} ). This is not a major implementation problem. Because the state space remains finite. In addition, the output alphabet of the Moore machine filter M _{A, N} (the filter unit 11 in FIG. 7B) is a binary set {pass, mask}, and the automaton of the Moore machine filter outputs only the mask information. Although the finite state Moore machine cannot certainly buffer a plurality of characters with real time constraints, the original time stamped character string is copied, and appropriate masking is performed by the masking application unit 12 later. Applicable (see FIG. 7B).

(Theorem 4.8) (Soundness): Let automaton A be a pattern TA A = (Σ, S, s ₀ , S _F , C, E), define N as a positive integer, and define MA _{, N} 4.7. Moore machine filter. w = (a ₁ , τ ₁ ) (a ₂ , τ ₂ )... (a _n , τ _n ) is a character string with a time stamp on Σ, and mask ^N w ′ is an input character string w (⊥, τ _n ). ^{It is} assumed that the output character string of the Moore machine filter M _{A, N} for _N (here, the input / output character strings are mask ^N and (⊥, τ _n ) ^N added as shown in FIG. 4). It is assumed that a character string w ′ = b ₁ b ₂ ... B _n . Here, b _k {pass, mask}.

A pair of subscripts (i, j) of an arbitrary character string w that satisfies w (i, j) −τ _i−1 ∈L (A) and a subscript k∈ [i, j] of a character string w , B _k = pass.

5. Example 1 (implementation and experiment)
The present inventors have implemented a configuration of a Moore machine filter for pattern matching with real-time constraints (Example 1). Our implementation collapses successive ⊥ with two ⊥ and keeps the timestamp of the first and last ⊥. The buffer portion of the state space Q is generated as needed ({pass, mask} ^{N in} definition 4.7), which is as described in Proposition 3.5. The present inventors conducted experiments to answer the following research questions (RQ).

RQ1: Do Our Moore Machine Filters Mask Many Events?
RQ2: Do Our Moore Machine Filters Work Online?
That is, does it work in linear time and constant space for the length of the input time-stamped string?
RQ3: Can our Moore Machines Accelerate the Real-Time Constrained Pattern Matching Task?
RQ4: Are our filters highly accurate?
In other words, do many of the unmasked events contribute to the actual matching?
RQ5: Is the response of our filter fast?
In other words, will there be a big delay?

  The implementation of the filter configuration was performed in C ++ language and compiled with clag-900.0.39.2. The input of the tool includes a pattern TA A, a buffer size N, and a character string w with a time stamp, and outputs a filtered character string. The experiment was performed with Mac OS 10.13.4 on RAM of a personal computer (MacBook Pro Early 2013 with 2.6 GHz Intel Core i5 processor and 8GB 1600 MHz DDR). The benchmark problems used are in FIGS. These are all taken from the car scenario.

  FIG. 8 is a diagram illustrating an example of a Moore machine filter for data of a vehicle torque sensor according to the first embodiment.

In FIG. 8, a set W of input character strings (having a length of 242,808 to 4,873,207) is a sledmo_enginenewc. Generated from slx. This pattern describes that high occurs four or more times within one second. With respect to the buffer size N = 10, the size of the Moore machine filter MA _{, 10} (measured by the number of reachable states of the non-buffer part of SN-ctr-d) was 16.

  FIG. 9 is a diagram illustrating an example of the Moore machine filter for the data of the gear sensor of the vehicle according to the first embodiment.

In FIG. 9, a set W of input character strings (having a length of 306 to 1,011,426) was generated from a model of the automatic transmission. This pattern taken from the model φAT5 represents an event that gearshifts occur too frequently (from first gear to second gear). When the buffer size N = 10, the size of the Moore machine filter MA _{, 10} was measured by the same method as in FIG.

  FIG. 10 is a diagram illustrating an example of the Moore machine filter for the data of the accelerator sensor of the vehicle according to the first embodiment.

In FIG. 10, a set W of input character strings (having a length of 708 to 1,739,535) was generated using the same model as the gear. The pattern is the same as φAT8: the gear shifts from 1st to 4th and the RPM is higher but the speed is lower (in other words, the event v ≧ 100 does not occur). For the buffer size N = 10, the size of the Moore machine filter MA _{, 10} was measured by the same method as in FIG.

  For the measurement of execution time and memory usage, we averaged 20 runs using GNU time. In each experiment we measured the entire workflow. RQ2 measures the time and memory usage including the configuration of the filter, and RQ3 measures the time and memory usage of the filter configuration, filtering, inter-process communication and pattern matching. The RQ3 experiment used MONAA, the latest tool for real-time constrained pattern matching.

RQ1: Filtering rate

  FIG. 11A is a graph showing a simulation result of a Moore machine filter with respect to the data of the torque sensor of the vehicle according to the first embodiment, showing a filtered character string length with a real time with respect to an input character string length with a real time. FIG. 11B is a graph showing a simulation result of the Moore machine filter with respect to the data of the gear sensor of the vehicle according to the first embodiment, and showing the filtered real-time character string length with respect to the input real-time character string length. FIG. 11C is a graph showing a simulation result of a Moore machine filter with respect to the data of the accelerator sensor of the vehicle according to the first embodiment, showing a filtered real-time character string length with respect to an input real-time character string length. 11A to 11C show the filtered time-stamped character string lengths of the real-time-constrained automaton A, the buffer size N, and the time-stamped character string w∈W, respectively.

  As is clear from FIGS. 11A to 11C, it can be seen that the larger the buffer size N, the shorter the filtered character string. This is consistent with the theoretical considerations in Theorem 3.9 (although the result was a setting without real-time constraints). Peak performance appears to be realized at a relatively small N, such as buffer size N = 10. When the buffer size N = 10, the lengths of the original character strings with time stamps in torque, gear, and accelerator are about 1/3, 1/2, and 1/100, respectively. For the accelerator, our filter filters many characters. This is because the size of the alphabet and the size of the automaton with pattern real-time constraints are relatively large. This dramatic data reduction indicates that our filtering approach can be used in embedded scenarios (see FIG. 1).

RQ2: Speed and memory usage

  FIG. 12A is a graph showing a simulation result of a Moore machine filter with respect to data of the vehicle torque sensor according to the first embodiment, and showing execution time with respect to an input character string length with real time. FIG. 12B is a graph showing a simulation result of the Moore machine filter with respect to the data of the gear sensor of the vehicle according to the first embodiment, and showing the execution time with respect to the input character string length with real time. FIG. 12C is a graph showing a simulation result of the Moore machine filter with respect to the data of the accelerator sensor of the vehicle according to the first embodiment, and showing the execution time with respect to the input character string length with real time.

  FIG. 13A is a graph showing a simulation result of the Moore machine filter with respect to the data of the torque sensor of the vehicle according to the first embodiment, and showing the memory usage with respect to the input character string length with real time. FIG. 13B is a graph showing a simulation result of the Moore machine filter with respect to the data of the gear sensor of the vehicle according to the first embodiment, and showing the memory usage with respect to the input character string length with real time. FIG. 13C is a graph showing a simulation result of a Moore machine filter with respect to the data of the accelerator sensor of the vehicle according to the first embodiment, showing a memory usage amount with respect to an input real-time character string length.

  That is, FIGS. 12 and 13 show the execution time and the memory usage of the Moore machine filter of the present inventors for the automaton A with the pattern real time constraint, the buffer size N, and the character string w∈W with the time stamp. ing.

  In FIG. 12, it can be seen that the execution time is linear with respect to the input character string. In FIG. 13, it can be seen that the memory usage is approximately a constant with respect to the length of the input character string. These two results suggest that our filtering approach is available online.

  The time required to configure the Moore machine filter is considered negligible. Here, refer to the execution time for a short input character string in FIG.

  Regarding the effect of changing the buffer size N variously, it can be seen that the execution time is relatively long for the small buffer size N. This is probably because fewer characters were masked and more characters were output, which worsened the cost of the input / output device (I / O). For memory usage, contrary to the worst case result in Proposition 3.5 (exponential for N), the increase for large buffer sizes N was modest. This is because not all states of the power set configuration can be reached.

RQ3: Acceleration of real-time constrained pattern matching

  FIG. 14A is a graph showing a simulation result of a tool according to a comparative example with respect to data of a vehicle torque sensor, and showing execution time with respect to an input character string length with real time. FIG. 14B is a graph showing simulation results of a tool according to a comparative example with respect to data of a gear sensor of an automobile, and showing execution time with respect to an input character string length with real time. FIG. 14C is a graph showing simulation results of a tool according to a comparative example with respect to data of an accelerator sensor of a vehicle, and showing execution time with respect to an input character string length with real time.

  That is, FIG. 14 shows the execution time of the workflow of FIG. Here, the filter is given by the algorithm of the present inventors, and the pattern matching is performed by the latest tool MONAA. More specifically, the standard output of the Moore machine filter is connected to the standard input of the MONAA via a Unix pipeline. In this way, the filter and the MONAA are executed in parallel on different cores.

  It has been found that if the buffer size N is sufficiently large (for example, N = 10), the overall performance of real-time constrained pattern matching is improved by filtering. The torque and gear are up 1.2 times faster, and the accelerator about 2 times faster. This acceleration suggests that our filtering approach may be useful independently of the configuration assumptions shown in FIG. If the log is huge and monitoring can take hours or even days, running it in parallel with a filter might save time.

RQ4: Accuracy

  For the three example torques, gears, accelerators, and buffer size N = 10, the ratios of those that contributed to the actual matching in the unmasked event were 0.34%, 99%, and 92%, respectively. Therefore, it can be seen that the accuracy varies dramatically depending on the pattern. Note that even in the less accurate example (torque), our filter does reduce the log size by a factor of approximately three (FIGS. 11A-11C).

  Most of the inaccuracy in this real-time constrained setting is due to the looseness of one clock determinism (definition 4.5). For example, an automaton (TA) with real-time constraints on torque (FIG. 8) requires the generation of four consecutive highs within one second using the same clock x. The best overestimation by this one-clock decision (all clocks must be reset at each transition) is a requirement that high appear in each of four consecutive sections of length 1 or less. This is much less strict than the original requirement, explaining the relatively low accuracy in the torque example.

RQ5: Reactivity

  The average delay (execution time) / | w | * N by our filter was calculated for three examples of torque, gear, accelerator and buffer size N = 10. The results were 2.2 microseconds, 3.1 microseconds, and 0.91 microsecond, respectively. Although these delays are highly dependent on the computational power of the processor, we conclude that filters with small delays operate fast enough.

6. Related research The efficiency of pattern matching has been actively studied in the fields of databases and networks. In these areas, hardware configuration issues (speed differences between L1 / L2 cache and main memory) are similar to the embedded monitor problem we have discussed so far.

  Research in these areas of application has treated strings (or strings) as patterns. Here, the main source of the idea is a classic algorithm such as Boyer-Moore, Commentz-Walter, or Aho-Corasick. Many algorithms for patterns given by regular expressions or automata instead of strings rely on these string matching techniques.

  In databases and networks, pattern matching for regular expressions has been performed mainly by application-specific heuristics that take machine configuration into account.

  Pre-filtering before actual pattern matching has been considered in the above study (see, for example, Non-Patent Document 3). The main difference between these studies and ours is that their filters explicitly include matching candidates, ie, the subscripts of what may be matched. For this reason, the second step in the workflow (pattern matching, as we call it) is called inspection in their embodiment. In contrast, our filter only masks input strings. This is because the purpose of the present inventors (in view of an embedded application) is not only to speed up the matching but also to reduce the amount of data sent from the sensor to the pattern matching apparatus. This choice allows the use of a Moore machine, and further facilitates implementation by a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuits (ASIC).

  Monitoring of real-time temporal logic and pattern matching with real-time constraints (for example, see Non-Patent Document 4) is a relatively new topic. Although such research has mainly been studied in the context of physical information systems, it has good prospects for application to databases and networks. In real-time constrained pattern matching, specifications can be described in real-time constrained automata (used in this study), real-time constrained regular expressions, and temporal Boolean expressions with distance. Algorithms for real-time constrained pattern matching of specifications in these formulations have been actively studied, for example, in Non-Patent Document 1. In addition, real-time constrained pattern matching is accelerated by combining a shift table technique such as Boyer-Moore or Frank-Jennings-Smyth with a real-time constrained automaton (for example, see Non-Patent Document 5). .

7. Conclusion In response to the growing demand for monitoring in embedded applications in recent years, the present inventors have proposed a configuration of a filtering Moore machine for pattern matching (without real-time constraints and with real-time constraints). Its configuration is automaton theoretical, and realizes a filter as a Moore machine.

  FIG. 15 is a block diagram illustrating a configuration example of the prefix information processing circuit 4 according to the second embodiment. In FIG. 15, a pre-information processing circuit 4 is a processor circuit having a function of a Moore machine filter, and includes a CPU 20, a ROM 21, a RAM 22, an operation unit 23, a display unit 24, an input interface 25, and an output interface. 26 are connected via a bus 27.

  In FIG. 15, a CPU 20 is a processor that executes while controlling the processing of the Moore machine filter. The ROM 21 stores programs and data necessary for operating the front information processing circuit 4. The RAM 22 is a memory area used when executing the processing of the Moore machine filter (filtering processing), and is provided with a buffer unit 22a and a non-buffer unit 22b which are, for example, FIFO memories. Note that the buffer unit 22a may be referred to as a “buffer 22a”, and the non-buffer unit 22b may be referred to as a “non-buffer 22b”. Various programs (the generation program 22p1, the main program 22p2, and the subprogram 22p3) executed by the CPU 20 are loaded from the ROM 21 into the RAM 22. Details of these programs will be described later. The input interface 25 receives the input sequence data, converts the data into a predetermined data format, and outputs the data to the CPU 20 or the like. The output interface 26 converts the sequence data resulting from the processing of the Moore machine filter by the CPU 20 into a predetermined data format, and outputs the data to an external circuit or an external line. The operation unit 23 includes, for example, a keyboard and a mouse, and is used for executing, stopping, and inputting necessary data.

  The operation unit 23 is also used to input a condition (referred to as a matching condition) of a pattern to be searched from the input sequence data to the pre-information processing circuit 4. The matching condition may be input in the form of a character string or a regular expression. Alternatively, it may be provided to the pre-information processing circuit 4 as an automaton. In another embodiment, the matching condition may be input via the input interface 25 (for example, from an external device) together with the sequence data. The display unit 24 is, for example, a liquid crystal display, and displays input sequence data, output sequence data, and the like.

  FIG. 16 shows a configuration example of the buffer unit 22a. The buffer unit 22a is one of the components of a finite state machine (specifically, a Moore machine) operated by the pre-information processing circuit 4. Although the details will be described later, the Moore machine operating on the pre-information processing circuit 4 defines the state space by dividing the state space into a buffer portion and a non-buffer portion, like the Moore machine described in section 3.2 of this specification. . The buffer unit 22a corresponds to a buffer part of the state space.

  The buffer unit 22a is a FIFO buffer having N memory blocks (22a-1, 22a-2,..., 22a-N). Each of the memory blocks (22a-1, 22a-2,..., 22a-N) has a data area for storing one unit of input sequence data and a flag area. In FIG. 16, a row 221a represents a data area, and a row 221b represents a flag area. Each data area is a storage area of the same size (or larger size) as one unit of sequence data. For example, when the sequence data is a character string, each character constituting the character string is a one-byte character, and when the sequence data is input one character at a time (one byte at a time) to the front information processing circuit 4, the size of the data area is One byte is sufficient.

  For example, each flag area is a 1-bit storage area in which 0 (mask) or 1 (pass) is stored. Hereinafter, data (0 or 1) stored in the flag area is referred to as “flag”. The value 0 stored in the flag area is described as “mask”, and the value 1 stored in the flag area is described as “pass”.

  In the pre-information processing circuit 4 according to the second embodiment, when the sequence data is input to the buffer unit 22a, the data is stored in the rightmost memory block (22a-1). Before the data is stored in the memory block (22a-1), the data (and the flag) of the leftmost memory block (22a-N) is output from the buffer unit 22a, and the remaining memory blocks (22a-1, .. 22a- (N-1)) are respectively moved to the memory blocks (22a-2, 22a-3,... 22a-N) on the left. In the following description, the rightmost memory block (22a-1) is referred to as "the head of the buffer unit 22a", and the leftmost memory block (22a-N) is referred to as "the end of the buffer unit 22a".

  Here, an example in which each memory block (22a-1, 22a-2,... 22a-N) has a data area and a flag area has been described, but the data area may not be provided. For example, in the Moore machine according to the definition described in section 4.3 of this specification, as described in section 4.3, data (input sequence data) is not stored in the buffer portion of the state space. Only flags are stored. Therefore, for example, if the Moore machine that operates on the pre-information processing circuit 4 is a Moore machine that conforms to the definition described in section 4.3 of this specification, the buffer area 22a does not need a data area.

  Next, an example of a Moore machine that operates on the pre-information processing circuit 4 according to the second embodiment will be described. Here, a case will be mainly described in which the front-end information processing circuit 4 receives a character string without a time stamp as input sequence data and generates a Moore machine that filters the received character string. In this case, the Moore machine operated by the prefix information processing circuit 4 is the same as that described in section 3.2 of this specification.

  The Moore machine operated by the prefix information processing circuit 4 is generated based on the matching condition of the input sequence data. Therefore, before explaining the Moore machine, an example of the matching condition will be described. In the following description, an example in which the matching condition is expressed as “a (a *) b” (when expressed in a regular expression) will be described.

The regular expression “a (a *) b” is equivalent to the automaton A = (Σ, S, s ₀ , S _F , E) that operates according to the state transition diagram shown in FIG. The meaning of each symbol of the automaton A = (Σ, S, s ₀ , S _F , E) is as follows. Σ represents the input character set, S is represents the set of states, s _0, is the initial state (which is also the element of S), S _F represents the final state (also called accepting state) (the subset of S E) is a set of transitions.

In the example described here, the automaton A has three states {s ₀ , s ₁ , s ₂ }, where s ₀ is the initial state and s ₂ is the final state (acceptance state). Σ is composed of characters a and b. In FIG. 17, each state {s ₀ , s ₁ , s ₂ } is represented by a circle, and a double circle represents an acceptance state. Further, characters (a, b) given above arrows (edges) connecting the states mean input to the automaton A. For example, in FIG. 17, the character “a” is written on the arrow connecting the state s ₀ and the state s _1. This is because “the character“ a ”is input when the automaton A is in the state s ₀ . represents a transition to "be in the automaton a Haga state s _1.

The prefix information processing circuit 4 generates a Moore machine according to the definition described in section 3.2 of this specification. Here the Moore machine _{M A} which is _{generated, N = (Σ ⊥, Σ} ⊥, Q, q 0, Δ, Λ) and denoted. In addition, the meaning of each symbol of M _{A, N} = (Σ _⊥ , Σ _，, Q, q ₀ , Δ, Λ) is as follows. The first _{} represents the input character set, and the second _{} represents the output character set. As is mentioned above sigma, an input character set of the automaton A, sigma _⊥ for the input character set of the automaton A, a character set to add a character ⊥ (although characters ⊥ is the input character of the automaton A These characters are not included in the set Σ. In this specification, ⊥ is referred to as a “block character.” Q represents the state space of the Moore machine, q ₀ represents the initial state, Δ represents a transition function, and Λ represents an output function. The suffix _A of M _{A, N} means the automaton that is the basis of the Moore machine (that is, the automaton A received by the front information processing circuit 4), and N is the buffer size (the buffer described with reference to FIG. 16). 22a).

When generating the Moore machine, the pre-information processing circuit 4 first defines an extended state based on each state that the automaton A can take. In Example 2, the automaton A can take state (provisionally denoted to as s _k), a set number of transitions required for the automaton A is shifted from the initial state (s ₀₎ to the state s _k, new Defined as (extended) state. If the number of transitions required until the transition from the initial state (s ₀₎ to the state s _k of c times, the new state is denoted as (s _{k, c).} In Example 2, sometimes that of the new state is referred to as the "counter with the state", also referred to a number of transitions required until the transition from the initial state (s ₀₎ to the state s _k a "counter" Sometimes. However, in the second embodiment, the counter is an integer equal to or greater than 0, but the upper limit is an integer equal to the buffer size N, and the counter is exactly a value obtained by calculating the following equation (7) (that is, The counter belongs to the coset related to modulus N).

((Number of transitions -1) mod N) +1 ... (7)
So although the exact value of the number of transitions and the counter does not have to be equal, the c of the embodiment 2 (s _{k, c),} to also be called counter state s _k, be referred to as the number of transitions There is also.

  The counter and the state with the counter will be described with reference to a state transition diagram (FIG. 18) of the automaton described using the state with the counter. In the following description, a case where the buffer size (N) is 2 will be described unless otherwise specified.

In the automaton A of FIG. 17, the number of transitions required until the transition from the initial state s ₀ to the state s ₁ is so once counter state s ₁ is 1 Based on Equation (7) above. Therefore, the front information processing circuit 4 defines (s ₁ , 1) as the state with the counter.

In addition, as seen from FIG. 17, in the automaton A, the state letter "a" as the sequence data when s ₁ is input, the state transitions to s ₁ again (which, for example, the state is s ₀ Sometimes the character "a" is entered twice consecutively). In this case, two transitions result, it means that a transition to the state s _1, in the number of transitions is 2, the value of the counter is also 2. Therefore, the prefix information processing circuit 4 defines (s ₁ , 2) as the state with the counter.

Further, in the automaton A, when a state letter "a" when s ₀ is entered three consecutive times, the state transitions to s ₁ again. In this case, the number of transitions is three, but since the buffer size is two, the value of the counter is 1 [((3-1) mod 2) + 1 = 1] based on the above equation (7). Therefore, the new state produced by subjected the counter state _{s 1} automaton A can take (counter with state), There are two of _(s 1, 1) and _(s 1, 2).

Similarly, there are _two new states (s ₂ , 1) and (s ₂ , 2) generated by adding a counter to the state s ₂ that can be taken by the automaton A. Therefore, when the buffer size N is 2, the pre-information processing circuit 4 performs five states with counters (s ₀ , 0), (s ₁ , 1), (s) based on the automaton A shown in FIG. ₁ , 2), (s ₂ , 1) and (s ₂ , 2) are defined. After defining the state with the counter, the pre-information processing circuit 4 defines an automaton using the state with the counter as shown in FIG. 18 (the automaton using the state with the counter defined here is denoted as A ′). Do).

The automaton A ′ shown in FIG. 18 is different from the automaton A shown in FIG. 17 in that each state is a state with a counter, but the rule of the state transition of the automaton A ′ shown in FIG. This is the same as the automaton A shown in FIG. That is, the prefix information processing circuit 4 defines the automaton A ′ based on the automaton A shown in FIG. For example, in the automaton A shown in FIG. 17, when the character “b” is input in the state s ₁ ((s ₁ , 1) or (s ₁ , 2)), the state becomes s ₂ ((s ₂ , 2) Or (s ₂ , 1)). Therefore, when the prefix information processing circuit 4 defines the automaton A ′, if the character “b” is input in the state (s ₁ , 1) or (s ₁ , 2), the state becomes (s ₂ , 2) Alternatively, the automaton A ′ is defined so as to transition to (s ₂ , 1).

  Next, the prefix information processing circuit 4 defines (generates) a Moore machine based on the automaton A ′ in FIG. First, a definition of a state (state space) that the Moore machine can take and a method of defining a transition function will be described. In the process of generating a Moore machine by the prefix information processing circuit 4, a process similar to a known subset configuration method (also referred to as a power set configuration method) is performed. Since the subset configuration method is a known method as disclosed in, for example, Japanese Patent Application Laid-Open No. 2009-58989, a detailed description is omitted. Here, only the processing related to the generation of the Moore machine executed by the front information processing circuit 4 will be described.

  The subset construction method is a process used when converting a nondeterministic finite automaton (NFA) into a deterministic finite automaton (DFA) (called determinization). Therefore, the Moore machine generated by the prefix information processing circuit 4 is a DFA. As is well known, determinization specifies all states to which a transition is made when an input character x is given to a state (or a set of states) of a nondeterministic finite state automaton (NFA). The set of specified states is made into a state of a deterministic finite state automaton. The pre-information processing circuit 4 also performs the same processing as this determination.

However, in the determinization performed by the prefix information processing circuit 4, the initial information (s ₀ , 0) added to the “set of specified states” described above is generated by the prefix information processing circuit 4. It is defined as the state of the Moore machine M _{A, N.} The input character set uses _{} instead of the input character set _{} of the automaton A '. Hereinafter, the generation processing of the moor machines M _{A and N} by the front information processing circuit 4 will be described with reference to FIG. 18 and FIG.

If the input character a is given when the automaton A ′ in FIG. 18 is in the initial state (s ₀ , 0), the state transits to the state with counter (s ₁ , 1) and does not transit to any other state. For this reason, the prefix information processing circuit 4 sets the set of transition destination states (when the input character a is given) from the initial state (s ₀ , 0) to ｛(s ₁ , 1), (s ₀ , 0)つ ま り (that is, the sum of the specified transition destination state (s ₁ , 1) and (s ₀ , 0) becomes a set of transition destination states). Hereinafter, this set of states will be referred to as q ₁ ′. The initial state _(s 0, 0) is 'expressed as (i.e. _{q 0' q 0} is the initial state of the Moore machine _{M A, N).} Also likewise pre processing circuit 4, a set of transition destination state when the initial state (s _{0, 0)} input character b automaton A 'in is given, and the initial state (s _{0, 0)} Specifies the set of transition destination states when the input character ⊥ is given to the automaton A ′ in. Referring to FIG. 18, there is no transition destination state corresponding to these cases. If the state of the transition destination does not exist, it is equivalent to the above-mentioned “set of specified states” being an empty set. In this case, the prefix information processing circuit 4 determines the set {(s ₀ , 0)} (that is, q ₀ ′) of the state formed by adding the initial state (s ₀ , 0) to the empty set as the transition destination. I do. For this reason, the prefix information processing circuit 4 sets the set of transition destination states from the initial state (s ₀ , 0) (when the input character b is given and when the input character ⊥ is given) to ｛(s ₀ , 0)｝ (= q ₀ ′).

Subsequently, the prefix information processing circuit 4 specifies a set of transition destination states from the set of states q ₁ ′ (= {(s ₁ , 1), (s ₀ , 0)}). As can be seen from the state transition diagram of FIG. 18, when the input character a is given to the automaton A ′ in the state (s ₁ , 1), the transition destination state is (s ₁ , 2) and the state (s ₀ , 0) The transition destination state when the input character a is given to the automaton A ′ in ()) is (s ₁ , 1). Therefore pre-processing circuit 4, the state _{(s 1, 1), (} s 1, 2) made by the addition of state _(s 0, 0) in the set _{{(s 1, 1),} (s 1, 2) , (S ₀ , 0)} is determined as a set of transition destination states when the input character a is given to the state set q ₁ ′. Hereinafter, this set of states {(s ₁ , 1), (s ₁ , 2), (s ₀ , 0)} is denoted as q ₂ ′. Similarly, the front information processing circuit 4. The set of transition destination states when the input character b is given to the set of states q ₁ ′ (this is q ₃ ′ shown in FIG. 19. The element of q ₃ ′ is ｛(s ₂ , 2) , (S ₀ , 0)}) and a set of transition destination states when the input character ⊥ is given (this becomes q ₀ ′).

The pre-information processing circuit 4 determines these states and state transitions of the Moore machines MA _{and N} by repeating these processes. FIG. 19 illustrates the states and state transitions of the determined Moore machines MA _{and N.} Then, the prefix information processing circuit 4 stores the determined states and state transitions in the RAM 22. FIGS. 20 and 21 show examples of the states and state transitions of the Moore machines MA and _N stored in the RAM 22. FIG. FIG. 20 shows a state transition table (equivalent to the state transition diagram of FIG. 19) of the Moore machines M _{A and N} generated by the prefix information processing circuit 4 based on the automaton A ′ of FIG. Is a state management table of the Moore machine MA _{, N.}

As shown in FIG. 21, the state management table has columns of “state”, “subset”, and “Current”. The column “state” stores a list of possible states of the Moore machine MA _{, N.} Each row of the column “subset” stores an element (specifically, one or more states (a state with a counter) of the automaton A ′) included in the state of the Moore machine MA _{, N.} The column “Current” is an area for storing the current state of the Moore machine. As will be described later in detail, the state corresponding to the row in which “1” is stored in the column “Current” is the state of the Moore machine. It is the current state.

The state transition table of FIG. 20 represents the state transition rule (transition function) of the Moore machine MA _{, N.} The state transition table has a plurality of rows, and each row (denoted as δ _{0 to} δ ₁₁ ) represents a transition specification of the Moore machine MA _{, N.} As shown in FIG. 20, each row of the state transition table has columns of “state before transition”, “state after transition”, and “input”. For example, regarding the top row of the state transition table (the row describing the specification of the transition δ ₀ ), “q ₀ ′” and “q” are respectively set in “pre-transition state”, “post-transition state”, and “input”. ₁ '"and" a "are stored. This means that if the state before the transition is q ₀ ′ and the input character string “a” is given, the state after the transition will be q ₁ ′.

The state transition table and the state management table of the Moore machine MA _{, N} are stored in the non-buffer 22b of the RAM 22. The state transition table and the state management table generated by the prefix information processing circuit 4 may include information other than the information described here. Also, the state transition tables and the state management tables shown in FIGS. 20 and 21 are examples, and the pre-information processing circuit 4 must necessarily create information in the format shown in FIGS. is not. The pre-information processing circuit 4 stores information necessary for the operation (state transition) of the Moore machines MA _{and N} in a storage area (such as the RAM 22) in a format different from the format shown in FIGS. Is also good.

The operation of the Moore machine MA _{, N} requires the definition of the output function in addition to the definition of the state and the definition of the transition function. The details of the output function will be described later. When the mooring machines M _{A and N according} to the second embodiment operate, the contents of the buffer 22a are also operated, which will also be described later.

  Subsequently, each functional block of the front information processing circuit 4 will be described. FIG. 22 is a diagram illustrating each functional block of the prefix information processing circuit 4. As shown in FIG. 22, the pre-information processing circuit 4 has processing modules (functional blocks) of a generation module 22m1, a filter module 22m2, and a Moore machine module 22m3. These functional blocks are realized by the CPU 20 executing each program of the front information processing circuit 4. Specifically, the generation module 22m1 is a functional block realized by the CPU 20 executing the generation program 22p1. The filter module 22m2 is a functional block realized by the CPU 20 executing the main program 22p2. The Moore machine module 22m3 is a functional block realized by the CPU 20 executing the subprogram 22p3.

  The filter module 22m2 and the Moore machine module 22m3 are function blocks for executing data processing (filtering), and the generation module 22m1 is a function block for generating the Moore machine module 22m3 (subprogram 22p3). The generation module 22m1 generates the Moore machine module 22m3 by receiving an instruction from the filter module 22m2. The Moore machine module 22m3 performs an operation as the above-described finite state machine (Moore machine) based on an instruction from the filter module 22m2. Specifically, it receives sequence data (character string) from the filter module 22m2 one unit at a time (one character at a time), and performs state transition and information output accordingly. Details of the processing of the generation module 22m1, the filter module 22m2, and the Moore machine module 22m3 will be described below.

  Subsequently, a flow of the filtering process performed by the prefix information processing circuit 4 will be described. Hereinafter, an example will be described in which the prefix information processing circuit 4 receives, as sequence data, a one-byte character sequence (character string) to which a time stamp is not added, one byte at a time.

  FIG. 23 and FIG. 24 are flowcharts of the data processing (filtering) performed by the front information processing circuit 4. The flowchart in FIG. 23 illustrates the entire flow of the filtering process. FIG. 24 is a flowchart detailing the processing of a part (step S103) of the flowchart of FIG.

  First, the overall flow of the filtering process will be described with reference to FIG. The filtering process is performed, for example, when the front information processing circuit 4 receives a process start instruction from the user via the operation unit 23, or when the front information processing circuit 4 starts processing from an external device via the input interface 25. Executed when an instruction is received. When the filtering process is started, the filter module 22m2 receives a matching condition via the operation unit 23 or the input interface 25, and generates a Moore machine from the received matching condition (Step S101 in FIG. 23). In step S101, the filter module 22m2 causes the generation module 22m1 to generate the Moore machine module 22m3. The generation module 22m1 defines the state of the Moore machine and the transition function as described above (that is, the generation module 22m1 includes not only the program code executed by the CPU 20 but also the state management table and the like described above). Information (information necessary for the operation of the Moore machine) is also generated).

The definition of the state of the Moore machine and the definition of the transition function are as described above with reference to FIGS. The generation module 22m1 generates a state management table as shown in FIG. 21 as a state definition result and stores it in the non-buffer 22b (immediately after generation of the state management table, the Moore machine (Moore machine module 22m3) returns to the initial state. Therefore, the generation module 22m1 determines that among the elements of the column “Current”, the value of “Current” in the row (the top row in FIG. 21) corresponding to the initial state (q ₀ ′) is 1, and the other For the row, a state management table in which the value of “Current” is set to 0 is generated). The generation module 22m1 generates a state transition table as shown in FIG. 20 as a result of the definition of the transition function, and stores the state transition table in the non-buffer 22b. The generation module 22m1 creates the buffer 22a. Specifically, the generation module 22m1 secures an area having N memory blocks as shown in FIG. 16 in the RAM 22, and initializes the data area and the flag area of the N memory blocks (all The flag "mask", that is, 0, is stored in the flag area of the memory block, and the block character $ is stored in the data area of all the memory blocks.) The definition of the output function will be described later.

  Note that the filter module 22m2 does not necessarily need to receive the matching condition in step S101. For example, a Moore machine (Moore machine module 22m3) generated based on a predetermined matching condition may be mounted in the front information processing circuit 4 in advance. In that case, when performing the filtering process, the filter module 22m2 may execute the pre-mounted Moore machine. When the Moore machine is mounted in advance, the front information processing circuit 4 does not need to execute step S101, and the front information processing circuit 4 may not have the generation module 22m1.

  Subsequently, in step S102, the filter module 22m2 receives the sequence data via the input interface 25. Each time step S102 is performed once, the prefix information processing circuit 4 receives data of one unit of sequence data (here, 1-byte character).

Subsequently, the filter module 22m2 calls the Moore machine module 22m3, and passes the data (1 byte character) received in step S102 to the Moore machine module 22m3, thereby performing the process using the Moore machine MA _{, N} (step S103). Although details of the processing of step S103 will be described later, once step S103 is executed, the Moore machine module 22m3 outputs data stored in the last memory block of the buffer 22a. The filter module 22m2 outputs the data output from the Moore machine module 22m3 to an external device via the output interface 26.

  Subsequently, the filter module 22m2 determines whether the input of the sequence data has been completed (whether the reception up to the last character of the character string has been completed) (Step S104). Whether the input of the sequence data is completed is notified from the input interface 25, for example. However, the filter module 22m2 may detect whether or not the input of the sequence data has been completed by another method. If it is determined that the input of the sequence data has not been completed (step S104: NO), the filtering process returns to step S102. If it is determined that the input of the sequence data has been completed (step S104: YES), the filter module 22m2 performs a process of passing the block character に to the Moore machine module 22m3 N times (step S105). As mentioned above, N is the buffer size. Therefore, when the buffer size (N) is 2, step S103 is substantially performed twice in step S105. After step S105, the filtering process ends.

  As described above, when step S103 is executed, the data (one-byte character) passed to the Moore machine module 22m3 is input to (the data area of) the memory block of the buffer 22a, and The data stored in the last memory block is output. Therefore, when step S105 is executed, all data stored in the N memory blocks of the buffer 22a is output. That is, step S105 is performed in order to output all data (remaining) stored in the memory block of the buffer 22a before execution of step S105.

  Next, details of the processing performed in step S103 will be described with reference to FIG. The processing in FIG. 24 is executed by the Moore machine module 22m3. The Moore machine module 22m3 changes the state of the Moore machine (Moore machine module 22m3) and updates the contents of the buffer 22a every time data is received from the filter module 22m2. In the following description, it is assumed that the buffer size N is 2 (the number of memory blocks included in the buffer 22a is 2).

  Upon receiving the data (one-byte character) from the filter module 22m2, the Moore machine module 22m3 extracts the data stored in the data area of the memory block (22a-N) at the end of the buffer 22a and extracts the data stored at the end of the buffer 22a. It is determined whether or not the flag stored in the flag area of the memory block (22a-N) is mask (step S201). If the flag of the memory block (22a-N) is not mask, that is, if the flag is pass (step S201: NO), the Moore machine module 22m3 stores the data stored in the data area of the memory block (22a-N). Is output to the filter module 22m2 (without change) (step S202). The filter module 22m2 that has received the data from the Moore machine module 22m3 outputs the data to the outside via the output interface 26. Conversely, if the flag of the memory block (22a-N) is mask (step S201: YES), the Moore machine module 22m3 changes the extracted data to the block character 、, and the changed data (block character ⊥) Is output to the filter module 22m2 (step S203). The filter module 22m2 outputs the block character ⊥ received from the Moore machine module 22m3 to the outside via the output interface 26.

  In step S204, the Moore machine module 22m3 stores the data received from the filter module 22m2 in the first data area of the buffer 22a. As described above, before the data is stored at the head of the buffer 22a, the data in each memory block (22a-1, 22a-2,... 22a- (N-1)) of the buffer 22a is stored. And the flag are moved to the memory blocks (22a-2, 22a-3,... 22a-N) on the left side, respectively. That is, the buffer 22a operates as a FIFO.

  Subsequently, the Moore machine module 22m3 executes the state transition of the Moore machine (Moore machine module 22m3) using the state transition table and the state management table stored in the non-buffer 22b (Step S205). Hereinafter, an example in which the state transition table illustrated in FIG. 20 and the state management table illustrated in FIG. 21 are stored in the non-buffer 22b will be described.

In the state management table of FIG. 21, the current state of the Moore machine module 22m3 is recorded in the column “Current”. Each element of the column “Current” stores a value of either 0 or 1. The state corresponding to the row where the value of the column “Current” is “1” is the current state. In FIG. 21, the value of the column “Current” is “1” for the row where the column “status” is q ₁ ′, so the status management table of FIG. 21 indicates that the current status is q ₁ ′. .

The Moore machine module 22m3 specifies the current state of the Moore machine module 22m3 in the manner described above, and then determines the state transition table of FIG. 20 and the data received from the filter module 22m2 (hereinafter, this is referred to as “input The state of the transition destination is determined based on the “character”. When the current state is q ₁ ′ as shown in the state management table of FIG. 21 and the input character is “b”, the state after the transition is q ₃ by referring to the state transition table of FIG. ' Therefore, the Moore machine module 22m3 changes the current state to q ₃ ′ by rewriting the column “Current” in the state management table in FIG. Specifically, the Moore machine module 22m3 changes the value of the column “Current” of the row whose “state” is q ₁ ′ to “0”, and changes the value of the column “Current” of the row whose “state” is q ₃ ′. To "1".

  In step S206, the Moore machine module 22m3 changes the flag area of the first memory block (22a-1 in FIG. 16) of the buffer 22a to “mask”.

In step S207, the Moore machine module 22m3 stores one or more states of the automaton A (or the automaton A ') included in the current state of the Moore machine module 22m3 (hereinafter, this is referred to as a "state subset"). , It is determined whether there is a state where the value of the counter is equal to N (buffer size). The “state subset” is an element (state with one or more counters of the automaton A ′) stored in the column “subset” of the state management table in FIG. For example, a case where the current state of the Moore machine module 22m3 (the state after execution of step S205) is q ₃ ′ will be described. Since the contents of the column “subset” are {(s ₀ , 0), (s ₂ , 2)} in the row where the column “status” of the state management table in FIG. 21 is q ₃ ′, the current Moore machine The state subset of state q ₃ ′ of module 22m3 is {(s ₀ , 0), (s ₂ , 2)}. Among the states (states with counters) included in this state subset, the value of the counter in state (s ₂ , 2) is 2 (that is, equal to the buffer size N). In such a case (step S207: YES), the Moore machine module 22m3 changes the flag area of all the memory blocks of the buffer 22a to "pass" (step S208). Conversely, when there is no state in which the counter value is N in the state subset (step S207: NO), step S208 is not executed. For example, if the current state of the Moore machine module 22m3 is q ₁ ′, the state subset of the state q ₁ ′ is {(s ₀ , 0), (s ₁ , 1)}. Certain states do not exist. In such a case, step S208 is not performed.

In step S209, the Moore machine module 22m3 determines that the state subset of the current state of the Moore machine module 22m3 has the reception state of the automaton (automaton A in this embodiment) as the element of the Moore machine module 22m3 as an element. (That is, s ₂ ((s ₂ , 1) or (s ₂ , 2) in the example of FIGS. 20 and 21 is the accepted state) is included in the state subset) Is determined). If the state subset of the current state of the Moore machine module 22m3 has the acceptance state (of the automaton that is the source of the Moore machine module 22m3) as an element (step S209: YES), the process proceeds to step S210. If the accepted state is not included in the state subset (step S209: NO), the Moore machine module 22m3 terminates the processing of the Moore machine module 22m3 without executing step S210.

In step S210, the Moore machine module 22m3 specifies all the counter values corresponding to the accepted states included in the state subset, and determines the maximum value of those counter values (hereinafter, this maximum value is expressed as M). Ask. Then, the Moore machine module 22m3 changes the flag area of the M memory blocks from the top of all the memory blocks of the buffer 22a to “pass”. For example, if the current state of the Moore machine module 22m3 (the state after execution of step S205) is q ₄ ′, the state subsets of q ₄ ′ include the states (s ₂ , 1), (s ₂ , 2) is included. Therefore, the maximum value M of the counter value corresponding to the reception state is determined to be 2. In this case, the Moore machine module 22m3 changes the flag area of the first two memory blocks of all the memory blocks of the buffer 22a to "pass".

  After step S210, the Moore machine module 22m3 ends the process, and the filter module 22m2 restarts the process immediately after step S103.

In the flowchart of FIG. 24, steps S201 to S203 are operations of the output function of the mooring machines MA _{and N.} In steps S201 to S203, the operation shown in the equation (6) in section 3.2 is performed. In equation (6), a ₁ and l ₁ represent the contents of the data area and the contents of the flag area of the last memory block 22a-N of the buffer unit 22a, respectively. According to equation (6), if _{l 1} is "pass" (if the determination in step S201 of FIG. 24 is NO), _{a 1} is output (step S202 in FIG. 24). If _{l 1} is "mask" the contrary (if the determination in step S201 in FIG. 24 of YES), the block character is outputted (step S203 in FIG. 24).

  In addition, in the flowchart of FIG. 24, by executing steps S206 to S210, the processing corresponding to the expression (5) in section 3.2 described above is performed.

  As described above, by executing the subprogram 22p3 of FIG. 24 (or the Moore machine module 22m3 of FIG. 22), the operation (state transition) of the Moore machine is realized, and the buffer unit is executed. The data of the content of 22a is rewritten. At the same time, it is possible to output data obtained by masking data (replaced by block characters) in the input sequence data that is apparently not compatible with the matching condition.

  In the above, an example has been described in which the prefix information processing circuit 4 receives a character string (sequence data) to which a time stamp is not added and performs filtering of the received character string. That is, the Moore machine (Moore machine module 22m3) operated by the prefix information processing circuit 4 was the same as that described in section 3.2 of this specification. However, the Moore machine operated by the front information processing circuit 4 is not limited to this. For example, a Moore machine according to the definition described in section 4.3 of this specification can also operate with the front information processing circuit 4. Specifically, when performing pattern matching on a character string (sequence data) to which a time stamp has been added, the prefix information processing circuit 4 uses a Moore machine (hereinafter, referred to as a definition) described in section 4.3 of this specification. Then, this is called a “moore machine with real-time restriction”) to perform pattern matching.

  The filtering processing by the real-time constrained Moore machine is substantially the same as the filtering processing described above. In the following, the difference between the filtering processing by the real-time constrained Moore machine and the filtering processing described above will be mainly described, and the description common to both will be omitted.

  As described in section 4.3 of this specification, in the Moore machine with the real-time constraint, only the flag is stored in the buffer portion of the state space. Therefore, when the front information processing circuit 4 operates the Moore machine with the real-time constraint, the front information processing circuit defines the buffer 22a having no data area (the row 221a is removed from the buffer 22a shown in FIG. 16). Buffer is defined).

  When the real-time-constrained Moore machine operates, since data is not stored in the buffer 22a, a process slightly different from the process of the Moore machine module 22m3 described above is executed. With reference to the flowcharts shown in FIGS. 25 and 26, the flow of processing when the pre-information processing circuit 4 operates the real-time-constrained Moore machine will be described.

  First, the flow of processing of a real-time-constrained Moore machine (hereinafter sometimes simply referred to as "Moore machine") will be described with reference to FIG. Most of the processing in FIG. 26 is common to FIG. 24, and therefore, the following description will focus on the differences between the steps in FIG. 26 and FIG.

  As shown in FIG. 26, the real-time constrained Moore machine executes step S2020 instead of steps S201 to S203 in FIG. That is, when the Moore machine receives the data (one-byte character) from the filter module 22m2, it does not perform the processing shown in FIG. 24 (for example, the processing of determining the content of the flag in S201), and The flag stored in the flag area of the memory block (22a-N) is output (step S2020). Since the processing after step S205 is the same as the processing in FIG. 24, the description is omitted.

  Since the Moore machine with the real time constraint does not have a data area in the buffer 22a, unlike the processing shown in FIG. 24, it does not convert the data contained in the data area and output the data. Data conversion and output are performed by the filter module 22m2 of the pre-information processing circuit 4.

  The processing of the filter module 22m2 when the filtering processing is performed by the real-time constrained Moore machine will be described with reference to FIG. First, the filter module 22m2 causes the generation module 22m1 to generate a Moore machine (step S1010). This process is the same as step S101 in FIG. 23, but differs from step S101 in FIG. 23 in that the generated Moore machine is a real-time-constrained Moore machine. In step S1010, the filter module 22m2 secures a storage area on the RAM 22 for temporarily storing data received via the input interface 25. The storage area secured by the filter module 22m2 is a FIFO buffer, and this FIFO buffer has (N + 1) memory blocks, and each memory block has one character data (data received via the input interface 25). ) Can be stored.

  Subsequently, the filter module 22m2 receives the sequence data via the input interface 25 (Step S1020). Step S1020 is a process similar to step S102 in FIG. However, in step S1020, the filter module 22m2 also performs processing for storing the received sequence data in the FIFO buffer secured in step S1010.

  Next, the filter module 22m2 passes the data (1 byte character) received in step S1020 to the Moore machine (Moore machine with real-time constraint). The real-time constrained Moore machine executes the processing shown in FIG. 26 accordingly (step S1030). As described above, when the real-time-constrained Moore machine executes the processing shown in FIG. 26, the flag (pass or mask) stored in the flag area of the memory block (22a-N) at the end of the buffer 22a is output. I do.

  Next, the filter module 22m2 determines whether the processing in steps S1020 and S1030 has been performed N times. As mentioned above, N is the buffer size. If the processes of steps S1020 and S1030 have not been executed N times yet (step S1040: NO), the process returns to step S1020. When the processing of steps S1020 and S1030 has been performed N times (step S1040: YES), the filter module 22m2 performs the processing of step S1050 and subsequent steps.

  In step S1050, the filter module 22m2 receives the sequence data via the input interface 25. This is a process similar to step S1020. In step S1050, the filter module 22m2 passes the data (one-byte character) received in step S1050 to the Moore machine. That is, step S1050 is the same process as step S1030.

  As described above, the execution of step S1060 causes the Moore machine to output a flag (pass or mask). In step S1070, the filter module 22m2 determines whether the output of the Moore machine is pass. If the output of the Moore machine is pass (step S1070: YES), the filter module 22m2 outputs the data for one character stored at the end of the FIFO buffer to an external device via the output interface 26 (step S1080). . In step S1080, data stored at the end of the FIFO buffer having (N + 1) elements (memory blocks) is output. For example, if step S1050 is the (N + 1) -th data reception process, step S1080 The first received data is output. On the other hand, if the output of the Moore machine is mask in step S1070 (step S1070: NO), the filter module 22m2 outputs the block character $ to the external device via the output interface 26 (step S1090).

  Subsequently, the filter module 22m2 determines whether the input of the sequence data has been completed (whether the reception up to the last character of the character string has been completed) (step S1100). The processing in step S1100 is the same as step S104 in FIG. If it is determined that the input of the sequence data has not been completed (step S1100: NO), the process returns to step S1050. If it is determined that the input of the sequence data has been completed (step S1100: YES), then step S1100 is performed.

  In step S1110, the filter module 22m2 passes the block character $ to the Moore machine. As a result, the flag is output from the buffer 22a of the Moore machine. Subsequently, in step S1120, the processes in steps S1070 to S1090 are performed based on the state of the flag (pass or mask) output from the moor machine in step S1100.

  Subsequently, the filter module 22m2 determines whether the processing of steps S1110 and S1120 has been performed N times (step S1130), and if the processing of steps S1110 and S1120 has been performed N times (step S1130: YES), performs the processing. finish. If the processes of steps S1110 and S1120 have not been performed N times yet (step S1130: NO), the filter module 22m2 executes step S1110 again.

  The processing in steps S1110 to S1130 is performed for the same purpose as in step S105 in FIG. That is, at the time immediately before the execution of step S1110, the N (non-output) flags are left in the memory block of the buffer 22a. Therefore, the filter module 22m2 executes the processing of steps S1110 to S1130 N times. The flag remaining in the memory block of the buffer 22a is output, and the filter module 22m2 determines data to be output to the external device based on the output flag.

  As described above, the pre-information processing circuit 4 according to the second embodiment may output data processed so as to remove data that does not clearly match the matching condition from the input sequence data. it can. However, in the prefix information processing circuit 4 according to the second embodiment, although a certain data string (for example, a character string) in the input sequence data does not actually match the matching condition, If it is uncertain whether they match or not, the data string is output without removing it (without any processing).

This case may occur, for example, when the determination in step S207 in FIG. 24 is YES. An example will be described with reference to FIGS. For example, a Moore machine generated based on the automaton A shown in FIG. 17 (having five states of q ₀ ′ to q ₄ ′ shown in FIG. 21 and a rule shown in FIG. 20 (or FIG. 19)) , And a buffer size of 2 is assumed. When the current state of such a Moore machine is q ₂ ′, the state subset of state q ₂ ′ is {(s ₀ , 0), (s ₁ , 1), (s ₁ , 2)}. In this case, as can be seen from FIG. 24 (especially steps S207 and S208), the data stored in the buffer 22a at this point is output as it is (without being converted to block characters). This is because in step S208, the flag areas of all the memory blocks in the buffer 22a are changed to "pass". However, since the state subset at this time does not include the reception state (s ₂ ) as an element, the data string stored in the buffer 22a has the matching condition described as the automaton A shown in FIG. , But it is not necessarily certain that the whole of the matching condition is satisfied. In such a case, the front-end information processing circuit 4 according to the second embodiment outputs the data stored in the buffer 22a as it is (without being converted into a block character), so that there is a possibility that the matching condition is met. It does not remove certain data.

  In the above, the example has been described in which the prefix information processing circuit 4 converts data that does not clearly match the matching condition into the block character ⊥ in order to remove data that does not clearly match the matching condition. The method of removing data that does not clearly match is not limited to this. For example, as a result of the prefix information processing circuit 4 converting data which clearly does not match the matching condition in the input sequence data into block characters ⊥, the converted data sequence has block characters 複数 repeated a plurality of times. If a character string that appears in the form of a character string is included, for example, the prefix information processing circuit 4 may convert this character string into a set of “block character ⊥ and the number of appearances thereof” and then output it to an external device. Good. Specifically, the prefix information processing circuit 4 converts the character string "abbbbbb" to "ab @" by performing the above-described processing (FIGS. 23 and 24), ab @ "may be converted to" ab @ 5 "and output to an external device (that is," $ 5 "indicates that five consecutive block characters $). . By performing such conversion, the data size is substantially reduced, so that the amount of data output to an external device can be reduced.

  FIG. 27 is a flowchart illustrating a real-time automaton determinizing process when configuring the pre-information processing circuit 4 according to the second embodiment.

In steps S61 to S63 of FIG. 27, the definition of the state s ₀ ^d to the state space S ₀ in the automaton, the initialization of the current state space S _curr ^d and the state space S ^d , and the initialization of the output function _{ｒ r} ^d Perform processing. In step S64～S75, current state-space _{S curr} ^d executes step S67~S74 when not empty. In steps S65 to S72, the processes in steps S67 to S69 are executed for each state s ^d S _curr ^d . Further, in steps S66 to S71, the processing of steps S67 to S69 is executed for each character a ^. Further, in steps S68 to S70, the processing of step S69 is executed for each section I′∈J (J is the least sparse division of a set of sections as shown in step S67). In step S76, the state space S _F ^d of the filtering result is defined as a subset of the state space S ^d and the intersection with the state space S _F of the filtering result is non-empty, and the determinizing process ends. I do.

  As described above, the non-deterministic real-time can be converted to a deterministic automaton by executing the determinizing process of FIG.

  FIG. 28 is a flowchart illustrating an approximation process for approximating a real-time constrained automaton to a real-time automaton when configuring the prefix information processing circuit 4 according to the second embodiment. Note that the rt real time parameter of the superscript character of the parameter is shown.

In step S81~S82 in Figure 28, the definition of the state _s ^{0 rt} in automaton, state space ^{S rt,} the initialization processing of _{S rt curr} performed. In steps S83 to S99, when the current state space S ^rt _curr is not empty, the processing in steps S84 to S98 is executed. In steps S85 to S96, the processing of steps S87 to S94 is executed for each (s, Z) ＺS ^rt _curr . Further, in steps S86 to S95, the processing of steps S87 to S94 is executed for each (s; a; δ, λ, s ′)}. Note that up (Z) in step S87 represents the passage of time. Also, reset (Z ′, λ) in step S89 represents initialization of a clock variable included in λ. Further, S ^rt _next in step S94 and the like represents the next state space to be added after the real-time state space S ^rt . Furthermore, the zone of the DBM in step S90 is a zone defined by a well-known Difference Bound Matrix. In step S100, the state space S ^rt _F of the filtering result is set to {(s, Z)} S ^rt | s {S _F }, and the approximation processing ends.

  As described above, by executing the approximation processing in FIG. 28, the automaton with the real-time constraint can be approximated to the real-time automaton.

Automatic stop mechanism when an error occurs.
FIG. 29 is a block diagram illustrating a configuration example of an automobile control system having an automatic stop mechanism at the time of abnormality according to the third embodiment.

  In FIG. 29, the vehicle control system is configured by connecting sensor devices 1A and 1B to a vehicle controller 30 via communication lines 10a and 10b, respectively.

  In the sensor device 1A, the vehicle speed detected by the vehicle speed sensor 3a and the angular speed detected by the acceleration sensor 3b are input to the front information processing circuit 4a. The prefix information processing circuit 4a has the same configuration as the prefix information processing circuit 4 according to the second embodiment. The pre-information processing circuit 4a processes the input real-time sequence data of vehicle speed and acceleration so as to remove data that can be easily recognized as not matching the above-mentioned matching condition. The data is transmitted to the post-processing circuit 5 via the communication line 10a.

  In the sensor device 1B, the gradient detected by the gradient sensor 3c, the mass detected by the mass sensor 3d, and the input data (emergency stop instruction data) input to the input data unit 3e to the actuator are pre-processed. Input to the circuit 4b. The prefix information processing circuit 4b has the same configuration as the prefix information processing circuit 4 according to the second embodiment. The pre-information processing circuit 4b processes the input gradient data, the mass, and the real-time sequence data of the input data so as to remove data that can be easily recognized as not matching the above-described matching condition, and processes the real-time data after the processing. The attached sequence data is transmitted to the downstream information processing circuit 5 via the communication line 10b.

  In the vehicle controller 30, the rear information processing circuit 5 receives the sequence data processed by the front information processing circuit 4a and the sequence data processed by the front information processing circuit 4b. Then, the post-processing circuit 5 performs a process of extracting sequence data that matches the above-described matching conditions (matching conditions used in the pre-processing circuit 4a and the pre-processing circuit 4b) for these sequence data. Then, the extracted sequence data is output to the failure detection unit 31. The failure detection unit 31 determines whether or not to match a predetermined failure condition based on the input sequence data, and outputs information to that effect to the vehicle operation control unit 32 when matching to the failure condition. For example, predetermined control processing such as emergency stop of a car is performed.

  As described above, the pre-information processing circuit 4b does not process (does not remove) data that matches a part of the matching conditions but does not necessarily determine whether the entire matching condition is satisfied. Therefore, in the data extraction processing performed by the post-processing circuit 5, the data that matches the above-described matching condition is compared with the processed sequence data received from the pre-processing circuit 4 a or the pre-processing circuit 4 b. The process of extracting all is performed. Specifically, for example, the prefix information processing circuit 4a or the prefix information processing circuit 4b converts a character string (sequence data) in which some characters (characters that clearly do not match the matching conditions) are rewritten into block characters 後. When transmitting to the post-processing information processing circuit 5, the post-processing information processing circuit 5 not only removes the block character from the character string, but also detects a character string that matches the matching condition among the character strings that have not been rewritten into the block character ⊥. It also determines whether the character string is included and extracts a character string that matches the matching condition.

  It should be noted that the processing load for the post-information processing circuit 5 to extract a character string (sequence data) that matches the matching condition is such that the front information processing circuit 4a and the front information processing circuit 4b perform vehicle control as shown in FIG. In the case where the information processing circuit is provided in the system, it is lower than in the case where the preceding information processing circuit 4a and the preceding information processing circuit 4b are not provided. The data (character string) that clearly does not match the matching condition is removed (converted into a block character) by the prefix information processing circuit 4a or the prefix information processing circuit 4b. Is significantly reduced.

  As described above, according to the third embodiment, a failure is detected by monitoring log data (vehicle speed, acceleration, gradient, mass, and the like) of a running vehicle by using the vehicle control system, and a failure is detected. If it is necessary to stop the vehicle, an appropriate input is given to the vehicle operation control unit 32 to perform an emergency stop. In particular, by attaching the front information processing circuits 4a and 4b to the sensor devices 1A and 1B, respectively, it is possible to reduce the data transfer amount in the communication lines 10a and 10b and handle more data.

Route optimization for semi-connected cars.
FIG. 30 is a block diagram illustrating a configuration example of an automobile control system having a traveling route optimization mechanism for a semi-connected car according to the fourth embodiment. The vehicle control system is configured by connecting a vehicle 40 to a server device 50 via a network including communication lines 10c and 10d. Here, the semi-connected car controls the running of the car 40 by connecting the control unit of the car 40 as necessary without connecting to the server device 50 at all times.

  In the automobile 40, the accelerator data detected by the accelerator sensor 3f and the accelerator pedal data detected by the brake pedal sensor 3g are input to the drive torque estimating unit 33. Driving torque estimating section 33 estimates the driving torque based on the input accelerator data and accelerator pedal data by a known method, and outputs the estimated driving torque to estimated vehicle speed calculating section 34. The gradient detected by the gradient sensor 3c and the mass detected by the mass sensor 3d are input to the estimated vehicle speed calculation unit 34. The estimated vehicle speed calculator 34 calculates the estimated vehicle speed by a known method based on the input three data, and outputs the calculated vehicle speed to the deviation amount calculator 35. The deviation amount calculation unit 35 compares the calculated estimated vehicle speed with the vehicle speed detected by the vehicle speed sensor 3a to calculate a deviation amount capable of estimating a road condition based on the deviation of the vehicle speed, and sends the calculated deviation amount to the front information processing circuit 4c. Output. The prefix information processing circuit 4c has the same configuration as the prefix information processing circuit 4 according to the second embodiment. The prefix information processing circuit 4c processes the input real-time sequence data of the deviation amount so as to remove data that can be easily recognized as not matching the above-mentioned matching condition. Is transmitted to the downstream information processing circuit 5 of the server device 50 via the communication line 10c.

  In the server device 50, the post information processing circuit 5 receives the sequence data processed by the front information processing circuit 4c, extracts sequence data matching the above matching condition, and converts the extracted sequence data into an abnormal road. Output to the state detection unit 51. The abnormal operation state detection unit 51 determines whether to match a predetermined “abnormal road state” condition (for example, the deviation amount is equal to or more than a predetermined threshold value and is determined to be an abnormal road state) based on the input sequence data. It is determined whether or not the condition is met, and when the condition is matched, information to that effect is output to the traveling plan control unit 52. The traveling plan control unit 52 detects an unfavorable road condition based on the input information, optimizes the traveling plan according to the road condition, and transmits the data of the optimized traveling plan via the communication line 10d. The driving of the automobile 40 is optimized by outputting to the traveling control unit 36 of the automobile 40.

  As described above, according to the fourth embodiment, the running log (accelerator data, brake pedal data, gradient, mass, vehicle speed, and predetermined calculation data based thereon) of the running semi-connected car is appropriately transmitted to the server device 50. It is transmitted via the communication line 10c. Here, an unfavorable road condition is detected by monitoring the data by the abnormal road condition detecting unit 51, and the traveling plan is optimized according to the road condition. Here, by providing the front information processing circuit 4c in the automobile 40, which is a semi-connected car, and providing the rear information processing circuit 5 in the server device 50, the data transfer amount is reduced, and for example, the situation of wireless communication is not good. It can operate properly even in an environment.

Monitoring attacks on server devices and blocking access.
FIG. 31 is a block diagram illustrating a configuration example of a communication system having a mechanism for monitoring an attack on a server device and blocking access according to the fifth embodiment. The communication system is configured by connecting a server device 60 and a router device 70 via a network including a communication line 10e.

  In the server device 60, the access log collection unit 61 collects a log (access source information, time, etc.) regarding an external access to the server device 60, and outputs the sequence data to the prefix information processing circuit 62. The prefix information processing circuit 62 has the same configuration as the prefix information processing circuit 4 according to the second embodiment. The pre-information processing circuit 62 processes the input real-time sequence data so as to remove data that is easily recognized as not matching the above matching condition, and converts the processed real-time sequence data to post-information. This is transmitted to the processing circuit 63. The post-information processing circuit 63 receives the input sequence data with real time, extracts sequence data matching the above-described matching condition, and outputs the extracted sequence data to the attack detection unit 64. The attack detection unit 64 detects aggressive access to the server device 60 with reference to predetermined threshold data based on the input sequence data, and transmits the detected access information to the router device via the communication line 10e. 70 to the access control unit 71. In response to this, the access control unit 71 performs control to block access to the server device 60 based on the detected access information input.

  As described above, according to the fifth embodiment, in the server device 60 such as WWW, an external communication log is monitored using the real-time condition extraction device including the front information processing circuit 62 and the rear information processing circuit 63. By doing so, an external attack is detected, and an appropriate input is given to the router to block access from the attacker. By using the real-time data filter unit of the real-time condition extraction device, the CPU time required for data processing can be reduced and monitoring can be performed without impairing the original operation of the server device 60.

  In the above embodiments and examples, the pre-information processing circuit 4 generates a Moore machine based on an automaton describing a predetermined matching condition regarding sequence data of an input event, and uses the generated Moore machine. And filtering the sequence data so as to substantially remove data that does not match the matching condition, and outputs the filtered sequence data. However, the present invention is not limited to this, and the model generated for filtering is not limited to a Moore machine, but may be various finite state machines such as a Mealy machine.

Difference between features of this embodiment and Patent Documents 2 and 3.

(1) Patent Document 2
In Patent Document 2, a program description (1) in which a plurality of devices are defined using a programming language capable of describing parallel operations is input, the input program description is converted into an intermediate expression (S2), and real-time constraints are set. The intermediate representation (S3) based on the hardware description language and the circuit description are synthesized (S4) based on the generated parameters for generating the parameters to be satisfied. Intermediate expressions are simultaneous control flow flags, timed automata with simultaneous parameters, and the like. Parametric model checking is performed for parameter generation. The program description uses the run method to define the device, and uses barrier synchronization to define the clock synchronization of the device. As a result, a bus system that meets real-time restrictions can be designed.

  Patent Document 2 discloses a verification process for design automation in order to efficiently design a bus system so as to satisfy real-time constraints, particularly when designing a circuit from a language capable of describing parallel operation such as JAVA (registered trademark). Is modeled as preprocessing of. As one of the steps, a concurrent control flow graph (C-CFG) is converted into a concurrent timed automaton with parameters (C-TNFA) and further into a timed automaton with parameters (TNFA). At the time of conversion from C-CFG to C-TNFA, a process for deleting a state transition that does not meet the premise in the subsequent verification process is performed, and at the time of conversion from C-TNFA to TNFA, an operation that does not need to take the bus right is performed in parallel. An upper limit of the transition time is set, and a process of deleting a state that does not satisfy the upper limit is performed.

  Patent Literature 2 discloses mask processing based on post-processing in preprocessing, but does not disclose specific techniques of the present invention, such as determinism and buffer optimization based on time constraints in an automaton.

(2) Patent Document 3
The method disclosed in Patent Document 3 is a method of converting a source code for converting software source code into an inspection code by using a computer. The method includes inputting a software source code and inputting a plurality of different conversion rules. And inputting a non-functional rule that is a constraint on process performance, and a non-functional check code written in an input language of a verification tool by using the plurality of different conversion rules and the non-functional rule. To the conversion.

  In Patent Literature 3, particularly, when converting the behavior of software into an input language (inspection code) as a process prior to software inspection, the software is converted into a time automaton in which each component (function) of the software is provided with a processing time according to an execution environment. In the case where there is a specific defect only at the time of repeated execution, a technology that removes the repeated portion and enables detection of other defects while reducing the number of states to avoid a state explosion that increases the calculation time too much is disclosed. ing.

  However, Patent Document 3 discloses mask processing in preprocessing, but does not disclose a specific method of the present invention such as determinization or buffer optimization based on time constraints in an automaton.

  As described above in detail, according to the information processing apparatus and method according to the present invention, it is possible to perform processing more efficiently than the time-series correlation extraction apparatus according to the conventional example.

1, 1A, 1B Sensor device 2 Monitoring device 3 Sensor 3a Vehicle speed sensor 3b Acceleration sensor 3c Gradient sensor 3d Mass sensor 3e Input data section to actuator 3f Accelerator sensor 3g Brake pedal sensor 4, 4a, 4b, 4c Pre-processing information processing circuit 5 Post-processing information circuit 6 Display unit 7 Filter unit 8 Pattern matching unit 10, 10a to 10e Communication line 11 Filter unit 12 Masking application unit 20 CPU
21 ROM
22 RAM
22a Buffer unit 22b Non-buffer unit 23 Operation unit 24 Display unit 25 Input interface 26 Output interface 27 Bus 30 Car controller 31 Failure detection unit 32 Car operation control unit 33 Drive torque estimation unit 34 Estimated vehicle speed calculation unit 35 Deviation amount calculation unit 36 Running Control unit 40 Automobile 50 Server device 51 Abnormal road condition detection unit 52 Driving plan control unit 60 Server device 61 Access log collection unit 62 Pre-information processing circuit 63 Post-information processing circuit 64 Attack detection unit 70 Router 71 Access control unit

Claims (16)

  A finite state machine is generated based on a predetermined matching condition regarding sequence data of an input event, and data that does not match the matching condition is substantially removed from the sequence data using the generated finite state machine. An information processing apparatus, comprising: an information processing circuit that outputs sequence data that has been processed into an image.   The information processing apparatus according to claim 1, wherein the sequence data is sequence data of a real-time time-stamped event, and the matching condition is described as a real-time restricted automaton.   The finite state machine has a FIFO buffer having N memory blocks and information describing rules of state transitions of the finite state machine. Each of the N memory blocks has a first state and a second state. 3. The information processing apparatus according to claim 2, further comprising an area for storing a flag indicating one of the states. Each time the finite state machine receives an input of one unit of data of the sequence data,
Fetch the contents of the memory block at the end of the buffer,
Based on the received data and the rules, transition the state of the finite state machine,
A second state is stored in a first memory block of the buffer as an initial value of a flag corresponding to the received data,
Update the flag stored in each memory block in the buffer according to the state of the finite state machine after the transition,
The information processing device according to claim 3. Each of the possible states of the finite state machine is a set ｓ (s) of a set (s, n) of a state s that the automaton can take and a counter n corresponding to the number of transitions required from the initial state to the state s. s ₁ , n ₁ ), (s ₂ , n ₂ ),... (s _k , n _k )} (k is an integer of 1 or more),
The information processing circuit,
(1) If there is a set whose counter value is N in the set of sets included in the state after the state transition of the finite state machine, N memories in the buffer Change all the flags of the block to the first state,
(2) the finite state the state s ₁ the machine state _includes, s 2 _,, ... if it contains an accepting state in the s _k, the maximum value of the counter associated with the state of accepting states M, and change the flags of the M memory blocks from the head of the buffer to the first state;
The information processing device according to claim 4. The sequence data is a time-stamped character string to which a time stamp is attached for each unit of data, and the characters constituting the character string are elements within a predetermined character set.
The finite state machine outputs a flag stored in a memory block at the end of the buffer each time the unit of data is received,
The information processing circuit,
When the flag output by the finite state machine is the first state, one unit of data corresponding to the flag output by the finite state machine is output to the outside,
When the flag output by the finite state machine is the second state, one unit of data corresponding to the flag output by the finite state machine is converted to a character not included in the character set and output to the outside. By substantially removing data that does not match the matching condition from the sequence data,
The information processing device according to claim 5. Accepting input of a matching condition for searching for a predetermined pattern included in sequence data composed of a plurality of symbols,
Based on the received matching condition, generate a finite state machine configured to generate information for substantially removing data that does not match the matching condition from the sequence data,
Information processing circuit.   The information processing circuit according to claim 7, wherein the matching condition is described as an automaton.   The finite state machine has a FIFO buffer having N memory blocks and information describing rules of state transitions of the finite state machine. Each of the N memory blocks has a first state and a second state. 9. The information processing circuit according to claim 8, further comprising an area for storing a flag indicating one of the states. Each time the finite state machine receives an input of one unit of data of the sequence data,
Output the contents of the memory block at the end of the buffer,
Based on the received data and the rules, transition the state of the finite state machine,
A second state is stored in a first memory block of the buffer as an initial value of a flag corresponding to the received data,
Update the flag stored in each memory block in the buffer according to the state of the finite state machine after the transition,
An information processing circuit according to claim 9. Each of the possible states of the finite state machine is a set ｓ (s) of a set (s, n) of a state s that the automaton can take and a counter n corresponding to the number of transitions required from the initial state to the state s. s ₁ , n ₁ ), (s ₂ , n ₂ ),... (s _k , n _k )} (k is an integer of 1 or more),
The information processing circuit,
(1) If there is a set whose counter value is N in the set of sets included in the state after the state transition of the finite state machine, N memories in the buffer Change all the flags of the block to the first state,
(2) the finite state the state s ₁ the machine state _includes, s 2 _,, ... if it contains an accepting state in the s _k, the maximum value of the counter associated with the state of accepting states M, and change the flags of the M memory blocks from the head of the buffer to the first state;
The information processing circuit according to claim 10, wherein: Each of the N memory blocks further has a data area for storing data of one unit of the sequence data,
The information processing circuit is configured to input the sequence data to the finite state machine one unit at a time,
When the finite state machine receives the input of the one unit of data,
In addition to storing an initial value of a flag corresponding to the received data in a head memory block of the buffer, storing the received data in a data area of the head memory block.
The information processing circuit according to claim 11. The sequence data is a character string, the characters constituting the character string are elements in a predetermined character set,
When the finite state machine receives the input of the one unit of data,
When the flag of the head memory block of the buffer is in the first state, the contents of the head memory block of the buffer are output;
When the flag of the first memory block of the buffer is in the second state, the contents of the first memory block of the buffer are changed to characters that are not included in the character set and output, so that the matching from the sequence data is performed. Substantially remove data that does not match the conditions,
The information processing circuit according to claim 12. The sequence data is a time-stamped character string to which a time stamp is attached for each unit of data, and the characters constituting the character string are elements within a predetermined character set.
The automaton is a real-time constrained automaton;
The finite state machine outputs a flag stored in a memory block at the end of the buffer each time the unit of data is received,
The information processing circuit,
When the flag output by the finite state machine is the first state, one unit of data corresponding to the flag output by the finite state machine is output to the outside,
When the flag output by the finite state machine is the second state, one unit of data corresponding to the flag output by the finite state machine is converted to a character not included in the character set and output to the outside. By substantially removing data that does not match the matching condition from the sequence data,
The information processing circuit according to claim 11. A first information processing device, which is the information processing device according to any one of claims 1 to 6,
An information processing system comprising: a second information processing device connected to the first information processing device via a predetermined communication line or a network;
The information processing circuit included in the second information processing device extracts data that matches the matching condition from the processed sequence data output by the first information processing device, and outputs the extracted data. An information processing system, comprising: An information processing method by an information processing device, which performs a predetermined process on sequence data of an input event,
The information processing circuit of the information processing device includes:
Receiving an automaton describing a predetermined matching condition for the sequence data;
Generating a finite state machine based on the automaton;
Receiving an input of the sequence data;
Using the finite state machine, processing the sequence data so as to substantially remove data that does not match the matching condition from the sequence data,
Outputting the processed sequence data;
An information processing method, comprising:

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