JP2020052677A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device having a training function for calibrating not only the timing of a signal but also the duty ratio of the signal in order to improve the accuracy of write data or read data.SOLUTION: A semiconductor device 1 comprises: a clock supply circuit 2 for supplying a clock WCK; a duty adjustment circuit 3 for adjusting the duty ratio of the clock WCK to the specified duty ratio; a driver 7 for transferring a clock of which the duty ratio has been adjusted to a memory 6 through a first path R1; a control circuit 5 for changing the specified duty ratio during the training period; and a determination circuit 4 for determining the specified duty ratio after the end of the training period on the basis of the monitoring result MA of the duty ratio transmitted from the memory 6 through a second route R2 during the training period.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, for example, to a technique for improving an opening of a data eye pattern.

  2. Description of the Related Art Conventionally, there is known an apparatus having a training function for calibrating timing of a signal necessary for performing a write operation of a memory. For example, a memory control device described in Patent Document 1 performs one or more write-read-verify operations to calibrate a clock cycle relationship between a data strobe signal and a clock signal.

JP 2015-43254 A

  However, in order to improve the accuracy of the write data or the read data, not only the timing of the signal but also a training function for calibrating the duty ratio of the signal is required.

  Other problems and novel features will be apparent from the description of this specification and the accompanying drawings.

  In the semiconductor device of one embodiment, the duty adjustment circuit adjusts the duty ratio of the clock to the designated duty ratio, the control circuit changes the designated duty ratio during the training period, and the determination circuit determines the second duty ratio during the training period. The designated duty ratio after the end of the training period is determined based on the monitoring result of the duty ratio transmitted from the memory through the path.

  According to one embodiment, the accuracy of write data or read data can be improved.

FIG. 2 is a diagram illustrating a configuration of a memory system according to the first embodiment. FIG. 9 is a diagram illustrating a configuration of a memory system according to a second embodiment. FIG. 14 is a diagram illustrating a configuration of a memory system according to a third embodiment. (A) is a figure showing the structure of a DDR memory system. FIG. 2B illustrates a configuration of the LSI 402. It is a figure showing the structure of DDR-PHY95 of a reference example. It is a figure showing the structure of DRAM200 and DDR-PHY100 of a 4th embodiment. It is a flowchart showing the procedure of the training of the memory interface of 4th Embodiment. It is a flowchart in the 4th Embodiment which shows the procedure of the 1st training of step S104 of FIG. It is a figure showing the example of a monitoring result. (A)-(i) is a figure for demonstrating the 2nd training of step S110 of FIG. The write clock WCK before executing the DCC of the fourth embodiment, the write clock WCK after executing the DCC of the fourth embodiment, and the s-th bit write data WDQs (s = 0 to 7) FIG. It is a figure showing the composition of DRAM201 and DDR-PHY101 of a 5th embodiment. It is a flowchart showing the procedure of the 1st training of step S104 of FIG. 7 in 5th Embodiment. It is a figure showing the timing chart of a 5th embodiment. It is a figure showing the structure of DRAM202 and DDR-PHY102 of a 6th embodiment. It is a flowchart showing the procedure of the training of the memory interface of the sixth embodiment. FIG. 17 is a diagram for explaining the processing in step S811 in FIG. 16. The write clock WCK and the s-th bit write data WDQs (s = 0 to 7) before the DCC of the sixth embodiment is executed, and the write clock WCK and the s-th bit after the DCC of the fifth embodiment are executed. FIG. 10 is a diagram illustrating bit write data WDQs. It is a figure showing the composition of DRAM203 and DDR-PHY103 of a 7th embodiment. It is a flow chart showing the procedure of training of the memory interface of a 7th embodiment. 21 is a flowchart illustrating a procedure of a first training in step S704 of FIG. 20 in a seventh embodiment.

Hereinafter, embodiments will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram illustrating a configuration of the memory system according to the first embodiment.

The memory system includes a semiconductor device 1 and a memory 6.
The semiconductor device 1 includes a clock supply circuit 2, a duty adjustment circuit 3, a driver 7, a determination circuit 4, and a control circuit 5.

The clock supply circuit 2 supplies a clock WCK.
The duty adjustment circuit 3 adjusts the duty ratio of the clock WCK to the designated duty ratio. In the following description, in one cycle T of the periodic signal, when the high-level period is HT and the low-level period is LT, the duty ratio is represented by HT / T.

  The driver 7 transfers the clock WCK whose duty ratio has been adjusted to the memory 6 through the first path R1.

The control circuit 5 changes the designated duty ratio during the training period.
The determination circuit 4 determines the designated duty ratio after the end of the training period based on the monitoring result of the duty ratio transmitted from the memory 6 through the second route R2 during the training period.

  As described above, according to the present embodiment, the write data can be correctly written or the read data can be correctly read by the training for calibrating the duty ratio of the clock.

[Second embodiment]
FIG. 2 is a diagram illustrating a configuration of a memory system according to the second embodiment.

The memory system includes a semiconductor device 11 and a memory 16.
The semiconductor device 11 includes a duty adjustment circuit 13, a driver 17, a determination circuit 14, and a control circuit 15.

  The duty adjustment circuit 13 adjusts the duty ratio of the write data WD to the designated duty ratio.

  The driver 17 transfers the write data WD whose duty ratio has been adjusted to the memory 16 through the first path R11.

The control circuit 15 changes the designated duty ratio during the training period.
The determination circuit 14 determines the designated duty ratio after the end of the training period based on the monitoring result of the duty ratio transmitted from the memory 16 through the first route R11 during the training period.

  The determination circuit 14 determines the designated duty ratio after the end of the training period by comparing the size of the opening of the eye pattern of the write data WD to the memory 16 for the plurality of changed designated duty ratios.

  As described above, according to the present embodiment, the write data can be correctly written by the training for calibrating the duty ratio of the write data.

[Third Embodiment]
FIG. 3 is a diagram illustrating a configuration of a memory system according to the third embodiment.

The memory system includes a semiconductor device 21 and a memory 26.
The semiconductor device 21 includes a clock supply circuit 22, a duty adjustment circuit 23, a driver 27, a determination circuit 24, and a control circuit 25. The memory 26 includes an RDQS output circuit 29.

The clock supply circuit 22 supplies a clock WCK.
The duty adjustment circuit 23 adjusts the duty ratio of the clock WCK to the designated duty ratio.

  The driver 27 transfers the clock WCK whose duty ratio has been adjusted to the memory 26 via the first path R21.

The control circuit 25 changes the designated duty ratio during the training period.
RDQS output circuit 29 outputs read data strobe signal RDQS according to clock WCK.

  The determination circuit 24 receives the read data strobe signal RDQS transmitted from the memory 26 through the second path R22 during the training period, and performs a read operation after the end of the training period based on the Duty ratio of the read data strobe signal RDQS. Is determined.

  As described above, according to the present embodiment, the read data can be correctly read by the training for calibrating the duty ratio of the clock.

[Fourth embodiment]
FIG. 4A is a diagram illustrating a configuration of a DDR (Double Data Rate) memory system.

  The DDR memory system includes a DRAM (Dynamic Random Access Memory) 200 disposed on a PCB (Printed Circuit Board), and an LSI (Large-Scale Integrated circuit) 402 for controlling the DRAM 200.

FIG. 4B is a diagram illustrating a configuration of the LSI 402.
The LSI 402 includes a DDR memory controller 500 and a DDR-PHY (DDR-PHYsical interface) 100.

The DDR memory controller 500 controls the DRAM 200.
The DDR-PHY 100 includes Logic and I / O. The DDR-PHY 100 converts parallel data from the DDR memory controller 500 into serial data and transmits the serial data to the DRAM 200. The DDR-PHY 100 converts serial data from the DRAM 200 into parallel data and transmits the parallel data to the DDR memory controller 500.

  Clocks CK and CK #, code, command or address CA, data DQ, read data strobe signals RDQS and RDQS #, and write clocks WCK and WCK # are transmitted between DDR-PHY 100 and DRAM 200. You.

Next, a DDR-PHY and a DRAM of a reference example will be described.
FIG. 5 is a diagram illustrating a configuration of the DDR-PHY 95 of the reference example.

  The clock CLK output from the PLL circuit 99 is delayed by the delay circuit DL1 and input to the clock terminal of the flip-flop FF10. The flip-flop FF10 outputs a code, a command, or an address CA based on the timing of the input clock CLK. The code, command or address CA is amplified and inverted and amplified by the driver AM2, and then output to a DRAM (not shown).

  The clock CLK output from the PLL circuit 99 is delayed by the delay circuit DL2 and input to the clock terminal of the flip-flop FF8. The flip-flop FF8 outputs a write clock WCK based on the timing of the input clock CLK. The write clock WCK is amplified and inverted and amplified by the driver AM3, and then output to a DRAM (not shown).

  Clock CLK output from PLL circuit 99 is delayed by delay circuit DL5. The clock CLK is input to a clock terminal of the flip-flop FF3. The flip-flop FF3 outputs the write data WDQ based on the timing of the input clock CLK. Further, the write data WDQ is amplified by the driver AM6 and then output to a DRAM (not shown).

  In the above-described reference example, the duty ratio of the write clock WCK inside the DRAM does not approach the ideal value of 50%. This is because the duty ratio of the write clock WCK deteriorates in the DDR-PHY 95, the path between the DDR-PHY 95 and the DRAM, and the inside of the DRAM. When the duty ratio of the write clock WCK deteriorates, the write data written based on the write clock WCK is not always written correctly. Further, the reading accuracy of the read data RDQ cannot be improved.

  FIG. 6 is a diagram illustrating a configuration of the DRAM 200 and the DDR-PHY 100 according to the fourth embodiment.

  The DDR-PHY 100 includes a PLL circuit 99, delay circuits DL1 to DL5, drivers AM1 to AM3, AM6, receivers AM4, AM5, flip-flops FF1 to FF3, FF8, and a DCA (Duty Cycle Adjuster) code control circuit 51. And a determination circuit 52.

The PLL circuit 99 supplies a clock CLK.
Driver AM1 amplifies and inverts and amplifies clock CLK output from PLL circuit 99 to generate clocks CK and CK #. The driver AM1 transfers the generated clocks CK and CK # to the DRAM 200 via the path P1.

  The delay circuit DL1 delays the clock CLK output from the PLL circuit 99 and sends it to the clock terminal of the flip-flop FF10. The flip-flop FF10 outputs a code, a command, or an address CA at the timing of the clock CLK output from the delay circuit DL1. The driver AM2 amplifies the code, command or address CA output from the flip-flop FF10. The driver AM2 transfers the amplified code, command or address CA to the DRAM 200 via the path P2.

  The delay circuit DL2 delays the clock CLK output from the PLL circuit 99 and sends it to the clock terminal of the flip-flop FF8. The flip-flop FF8 generates the write clock WCK at the timing of the clock CLK output from the delay circuit DL2. The flip-flop FF8 outputs a low-level “L” write clock WCK when the enable signal EN is in an inactive state. Flip-flop FF8 toggles write clock WCK when enable signal EN is active. The driver AM3 amplifies and inverts and amplifies the write clock WCK output from the flip-flop FF8. The driver AM3 transfers the amplified write clocks WCK and WCK # to the DRAM 200 via the path P3.

  Receiver AM4 amplifies read data strobe signals RDQS and RDQS # transmitted from DRAM 200 via path P4, and outputs an amplified read data strobe signal RDQS. Delay circuits DL4 and DL5 delay amplified read data strobe signal RDQS. The output of the delay circuit DL4 is input to the clock terminal of the flip-flop FF1. The output of the delay circuit DL3 is input to the inverted clock terminal of the flip-flop FF2.

  Receiver AM5 receives read data RDQ transmitted from DRAM 200 via path P5. The receiver AM5 uses the read reference voltage RVref as the reference voltage. The receiver AM5 outputs a high level when the read data RDQ is equal to or higher than the read reference voltage RVref, and outputs a low level when the read data RDQ is lower than the read reference voltage RVref.

  The flip-flop FF1 outputs the amplified read data RDQ at the timing of the read data strobe signal RDQS output from the delay circuit DL4. The flip-flop FF2 outputs the amplified read data RDQ at the timing of the inverted signal of the read data strobe signal RDQS output from the delay circuit DL3.

  The delay circuit DL5 delays the clock CLK output from the PLL circuit 99. The delayed clock CLK is input to the clock terminal of the flip-flop FF3. The flip-flop FF3 outputs the write data WDQ at the timing of the clock CLK output from the delay circuit DL5. Driver AM6 further amplifies write data WDQ. The driver AM6 transfers the amplified write data WDQ to the DRAM 200 via the path P5.

  The DCA code control circuit 51 adjusts the value of the DCA code sent to the DRAM 200. The DCA code control circuit 51 outputs the DCA code to the driver AM2. The driver AM2 amplifies the DCA code, and the amplified DCA code is transferred to the DRAM 200 via the path P2. The DCA code output from the DCA code control circuit 51 indicates the designated duty ratio of the DCA 53.

  The DRAM 200 includes receivers AM7 to AM9 and AM12, drivers AM10 and AM11, flip-flops FF4 to FF7, a mode register MR, a frequency divider DV, a DCA 53, and a DCM (Duty Cycle Monitor) 54.

  The receiver AM7 outputs the clock CK by receiving and amplifying the differential clocks CK and CK # transmitted from the DDR-PHY 100 via the path P1.

  The receiver AM8 receives a differential code, command, or address CA transmitted from the DDR-PHY 100 via the path P2 and amplifies the same to output CA. The code, command or address CA is set in the mode register MR.

  The receiver AM9 outputs the write clock WCK by receiving and amplifying the write clocks WCK and WCK # transmitted from the DDR-PHY 100 via the path P2.

  The DCA 53 is arranged after the receiver AM9. The DCA 53 adjusts the duty ratio of the write clocks WCK and WCK # according to the DCA code set in the mode register MR.

  The DCA 53 adjusts the duty ratio of the write clocks WCK and WCK # using a DCA code for writing at the time of writing and using a predetermined DCA code for reading at the time of reading. During training, the DCA 53 changes the duty ratio of the write clocks WCK and WCK # using the DCA codes sequentially transferred from the DDR-PHY 100. The optimal DCA code determined by the training becomes the DCA code for writing.

  The frequency divider DV divides the frequency of the write clocks WCK and WCK # output from the DCA 53. The frequency divider DV divides the input 3.2 GHz write clock WCK into a 1.6 GHz write clock WCK, for example. The divided write clocks WCK and WCK # are sent to the clock terminals of the flip-flops FF4, FF5, FF6 and the inverted clock terminal of FF7 via the WCK tree WT, and are also sent to the DCM 54.

  The flip-flop FF4 outputs the read data strobe signal RDQS at the timing of the write clock WCK. Driver AM10 amplifies and inverts and amplifies read data strobe signal RDQS output from flip-flop FF4. Driver AM10 transfers the amplified read data strobe signals RDQS and / RDQS to DDR-PHY 100 via path P4.

  The flip-flop FF5 outputs the read data RDQ at the timing of the write clock WCK. Driver AM11 amplifies read data RDQ output from flip-flop FF5. The driver AM11 transfers the amplified read data RDQ to the DDR-PHY 100 via the path P5.

  The receiver AM12 receives the write data WDQ transmitted from the DDR-PHY 100 via the path P5 and outputs the write data WDQ to the flip-flops FF6 and FF7. The receiver AM12 uses the write reference voltage WVref as the reference voltage. The receiver AM12 outputs a high level when the write data WDQ is equal to or higher than the write reference voltage WVref, and outputs a low level when the write data WDQ is lower than the write reference voltage WVref. The flip-flop FF6 outputs the write data WDQ at the timing of the write clock WCK. The flip-flop FF7 outputs the write data WDQ at the timing of the inverted signal of the write clock WCK.

  The DCM 54 monitors the duty ratio of the write clock WCK output from the frequency divider DV. Read data RDQ representing the monitoring result is sent to the determination circuit 52 through the flip-flop FF5, the driver AM1, the path P5, the receiver AM5, and the flip-flop FF.

  In the present embodiment, the deterioration of the duty ratio of the write clock WCK can be adjusted by the DCA 53. As a result, it is possible to increase the timing margin when writing the write data normally. Further, the accuracy of reading the read data RDQ can be improved.

  FIG. 7 is a flowchart illustrating a procedure for training the memory interface according to the fourth embodiment. This training is executed in the initialization sequence of the DRAM 200.

  In step S101, ZQ calibration is performed. That is, the driver of the DDR-PHY 100 and the DRAM 200 and the ODT (On Die Termination) are calibrated.

  In step S102, the delay of the code, command, or address CA is adjusted.

  In step S103, the first synchronization adjustment between the write clock WCK and the clock CLK is performed.

  In step S104, the first adjustment of the duty ratio of the write clock WCK is performed (hereinafter, referred to as first training). Let N be the adjusted DCA code.

  In step S105, the synchronization adjustment between the second write clock WCK and the clock CLK is performed.

In step S106, the delay of the read data strobe signal RDQS is adjusted.
In step S107, the delay of the read data RDQ is adjusted.

In step S108, the delay of the write data WDQ is adjusted.
In step S109, the magnitude of the read reference voltage RVref used in the receiver AM5 is adjusted.

  In step S110, adjustment of the magnitude of the write reference voltage WVref used by the driver AM12 and the second duty cycle of the write clock WCK are performed (hereinafter, referred to as second training).

  In the following description, the adjustment of the duty ratio of the first write clock WCK and the adjustment of the duty ratio of the second write clock WCK are called DCC (Duty Cycle Correction).

  FIG. 8 is a flowchart showing the procedure of the first training in step S104 of FIG. 7 in the fourth embodiment. FIG. 9 is a diagram illustrating an example of the monitoring result.

  Referring to FIG. 8, in step S200, DCA code control circuit 51 sets the DCA code to minimum value MIN.

  In step S201, the DCA code control circuit 51 transfers the DCA code to the mode register MR via the path P1. The DCA 53 adjusts the duty ratio of the write clock WCK output from the receiver AM9 according to the DCA code transferred to the mode register MR.

  In step S202, the clock CLK output from the PLL 99 is delayed by the delay circuit DL2 and sent to the clock terminal of the flip-flop FF8. The flip-flop FF8 generates the write clock WCK at the timing of the clock CLK output from the delay circuit DL2. An activated enable signal EN is input to the flip-flop FF8. The flip-flop FF8 toggles the write clock WCK. The driver AM3 amplifies and inverts and amplifies the write clock WCK output from the flip-flop FF8. The driver AM3 transfers the amplified write clocks WCK and WCK # to the DRAM 200 via the path P3. The receiver AM9 in the DRAM 200 amplifies the received differential write clocks WCK and WCK # and outputs a write clock WCK.

  In step S203, the DCM monitors the duty ratio of the write clock WCK transmitted from the DCA 53 via the frequency divider DV and the WCK tree. The DDR-PHY 100 may send a monitor start command to the DRAM 200 so that the DCM 52 monitors the duty ratio of the write clock WCK.

  If the duty ratio is smaller than 50%, the process proceeds to step S204. If the duty ratio is greater than 50%, the process proceeds to step S206.

  In step S204, the DCM 54 sets the monitoring result to L. In step S206, the DCM 54 sets the monitoring result to H. The monitoring result may be written into the mode register MR, for example.

  In step S207, the DCM 54 outputs a monitoring result. The DDR-PHY 100 may send an MRR (Mode Register Read) command to the DRAM 200 so that the DCM 54 outputs the monitoring result. The monitoring result is transmitted to the DDR-PHY 100 via the flip-flop FF5, the driver AM11, and the path P5. In the DDR-PHY 100, the monitoring result is sent to the determination circuit 52 via the receiver AM5 and the flip-flop FF2.

  When the DCA code is the maximum value MAX in step S208, the process proceeds to step S210. If the DCA code is not the maximum value MAX, the process proceeds to step S209.

  In step S209, the DCA code is incremented, and the process returns to step S202.

  In step S210, the determination circuit 52 determines a temporary optimal DCA code based on a plurality of monitoring results of the DCA code between the minimum value MIN and the maximum value MAX. That is, as shown in FIG. 9, the determination circuit 52 mixes the H and L monitor results that exist between the section where the H monitor result continues a predetermined number of times and the section where the L monitor result continues a predetermined number of times. Is specified as an indefinite section. The determination circuit 52 determines the DCA code N corresponding to the monitoring result of any one point in the indefinite section as a temporary optimal DCA code. For example, the determination circuit 52 may determine the DCA code N corresponding to the monitoring result at the center of the undefined section as a temporary optimal DCA code.

  In the above description, for example, the DCA 53 adjusts the duty ratio of the write clock WCK to 45% when the DCA code is the minimum value MIN, and adjusts the duty ratio of the write clock WCK to 55% when the DCA code is the maximum value MAX. You may do it.

  In the above description, the processing is continued until the DCA code reaches the maximum value. However, the processing may be terminated when the monitoring result of H is repeated several times.

  In the present embodiment, the deterioration of the duty ratio of the write clock WCK from the PLL 99 of the DDR-PHY 100 to the DCM 54 of the DRAM 200 can be corrected by the first training.

  FIGS. 10A to 10I are diagrams for explaining the second training in step S110 in FIG.

  The determination circuit 52 determines whether each bit of the write data WDQ has been normally written in the memory area of the DRAM 200 while changing the DCA code, the write reference voltage WVref, and the delay amount delay of the delay circuit DL5 within a certain range. By examining this, an eye pattern of each bit of the write data WDQ is created. The range in which the DCA code is changed is three ranges of N-1, N, and N + 1.

  That is, when the DCA code = X, the delay amount delay = D, and the write reference voltage WVref = V, the DDR-PHY 100 outputs the m-th bit (= “1”) of the write data WDQ, When “1” is written to the DRAM 200, the mth bit of the write data WDQ is determined to be PASS when the DCA code = X, the delay amount delay = D, and the write reference voltage Vref = V. When the DCA code = X, the delay amount delay = D, and the write reference voltage WVref = V, the DDR-PHY 100 outputs the m-th bit (= “1”) of the write data WDQ to the DRAM 200. When “0” is written, the m-th bit of the write data WDQ is determined to be FAIL when the DCA code = X, the delay amount delay = D, and the write reference voltage Vref = V. However, it is assumed that m = 0 to 7.

  When the DCA code is X, the determination circuit 52 checks the width Lm (X) of the eye opening (the area determined to be Pass) of the m-th bit eye pattern of the created write data WDQ.

  FIG. 10A shows an eye pattern of the 0th bit of the write data WDQ created by changing the delay amount delay and the write reference voltage WVref when the DCA code is (N−1). Have been. As shown in FIG. 10A, when the write reference voltage WVref is V0 (N-1), the ratio of PASS is maximum, and the width of the eye pattern opening is specified as L0 (N-1).

  FIG. 10B shows an eye pattern of the 0th bit of the write data WDQ created by changing the delay amount delay and the write reference voltage WVref when the DCA code is (N). I have. As shown in FIG. 10B, when the write reference voltage WVref is V0 (N), the ratio of PASS is maximum, and the width of the eye pattern opening is specified as L0 (N).

  FIG. 10C shows an eye pattern of the 0th bit of the write data WDQ created by changing the delay amount delay and the write reference voltage WVref when the DCA code is (N + 1). I have. As shown in FIG. 10C, when the write reference voltage WVref is V0 (N + 1), the ratio of PASS is maximum, and the width of the eye pattern opening is specified as L0 (N + 1).

  FIG. 10D shows the eye pattern of the first bit of the write data WDQ created by changing the delay amount delay and the write reference voltage WVref when the DCA code is (N-1). Have been. As shown in FIG. 10D, when the write reference voltage WVref is V1 (N-1), the ratio of PASS is maximum, and the width of the eye pattern opening is specified as L1 (N-1).

  FIG. 10E shows an eye pattern of the first bit of the write data WDQ created by changing the delay amount delay and the write reference voltage WVref when the DCA code is (N). I have. As shown in FIG. 10E, when the write reference voltage WVref is V1 (N), the ratio of PASS is maximum, and the width of the eye pattern opening is specified as L1 (N).

  FIG. 10F shows the eye pattern of the first bit of the write data WDQ created by changing the delay amount delay and the write reference voltage WVref when the DCA code is (N + 1). I have. As shown in FIG. 10 (f), when the write reference voltage WVref is V1 (N + 1), the ratio of PASS is maximum, and the width of the eye pattern opening is specified as L1 (N + 1).

  FIG. 10G shows an eye pattern of the seventh bit of the write data WDQ created by changing the delay amount delay and the write reference voltage WVref when the DCA code is (N−1). Have been. As shown in FIG. 10 (g), when the write reference voltage WVref is V7 (N-1), the ratio of PASS is maximum, and the width of the eye pattern opening is specified as L7 (N-1).

  FIG. 10H shows an eye pattern of the seventh bit of the write data WDQ created by changing the delay amount delay and the write reference voltage WVref when the DCA code is (N). I have. As shown in FIG. 10H, when the write reference voltage WVref is V7 (N), the ratio of PASS is maximum, and the width of the eye pattern opening is specified as L7 (N).

  FIG. 10I shows an eye pattern of the seventh bit of the write data WDQ created by changing the delay amount delay and the write reference voltage WVref when the DCA code is (N + 1). I have. As shown in FIG. 10 (i), when the write reference voltage WVref is V7 (N + 1), the ratio of PASS is maximum, and the width of the eye pattern opening is specified as L7 (N + 1).

  The determination circuit 52 specifies the minimum value among the eye opening widths L0 (N-1), L1 (N-1), L2 (N-1),. Let the value be L (N-1). The determination circuit 52 specifies the minimum value among the eye opening widths L0 (N), L1 (N), L2 (N),..., L7 (N) and sets the minimum value to L (N). The determination circuit 52 specifies the minimum value among the eye opening widths L0 (N + 1), L1 (N + 1), L2 (N + 1),..., L7 (N + 1) and sets the minimum value to L (N + 1). The determination circuit 52 specifies L (K) which is the largest among L (N−1), L (N), and L (N + 1), and determines K as an optimal DCA code. When the minimum value among L0 (K), L1 (K), L2 (K),..., L7 (K) is Li (K), the write reference voltage WVref is set to Vi (K). Set.

  FIG. 11 shows a write clock WCK before executing the DCC of the fourth embodiment, a write clock WCK after executing the DCC of the fourth embodiment, and write data WDQs (s = 0 to s) of the s-th bit. 7).

  By executing the DCC of the fourth embodiment, the duty ratio of the write clock WCK can be made close to 50%. This makes it possible to match the timing of the rising edge and the falling edge of the write clock WCK with the timing near the center of the eye pattern opening of the s-th bit write data WDQs (s = 0 to 7). As a result, it is possible to increase the timing margin when writing the write data to the DRAM 200 normally.

  In the present embodiment, in the first training, DCC training of a single WCK is performed, and in the second training, training of WVref and DCC training of WCK are performed simultaneously. According to the present embodiment, the execution time required for training can be reduced, and the opening of the eye pattern of the write data WDQ can be enlarged.

  When executing DCC training for a single WCK, the training execution time is short, but since the DCA code optimization is performed at the DCM points in the DRAM, whether the eye pattern opening of the write data WDQ can be expanded. Is not guaranteed.

  On the other hand, when the training of WVref and the DCC training of WCK are performed simultaneously, the training is performed based on the opening of the eye pattern of the actual write data WDQ, so that the opening of the eye pattern of the write data WDQ can be enlarged. However, since the DCA code search range is wide, the execution time required for training increases.

  In this embodiment, in the first training, the optimum value of the DCA code is narrowed down, so that the search range of the DCA code in the second training can be narrowed, so that it is possible to shorten the training execution time as a whole. Become.

[Fifth Embodiment]
FIG. 12 is a diagram illustrating a configuration of the DRAM 201 and the DDR-PHY 101 according to the fifth embodiment.

  The fifth embodiment is different from the fourth embodiment in that, in the fifth embodiment, the DCA 63 is arranged not on the DRAM 201 side but on the DDR-PHY 101 side.

  DCA 63 is arranged at the subsequent stage of delay circuit DL2. The DCA 63 adjusts the duty ratio of the write clocks WCK and WCK # according to the DCA code sent from the DCA code control circuit 61.

  The DCA code control circuit 61 has a function of switching the DCA code used by the DCA 63. The DCA 63 adjusts the duty ratio of the write clocks WCK and WCK # using the DCA code for writing at the time of writing and using the DCA code for reading at the time of reading. The DCA 63 changes the duty ratio of the write clocks WCK and WCK # using a DCA code that is sequentially switched during training. The provisional optimal DCA code N determined by the first training becomes the DCA code for reading. Alternatively, the DCA code for reading may be a predetermined one. The optimal DCA code determined by the second training is the DCA code for writing.

  FIG. 13 is a flowchart showing the procedure of the first training in step S104 of FIG. 7 in the fifth embodiment.

  Referring to FIG. 13, in step S900, DCA code control circuit 61 sets the DCA code to minimum value MIN.

  In step S901, the DCA code control circuit 61 sends the DCA code to the DCA 63. The DCA 63 adjusts the duty ratio of the write clock WCK output from the delay circuit DL2 according to the DCA code. The driver AM3 transfers the write clock WCK to the DRAM 201 via the path P3. The receiver AM9 in the DRAM 201 amplifies the received write clock WCK.

  In step S902, the clock CLK output from the PLL 99 is delayed by the delay circuit DL2 to become the write clock WCK.

  In step S903, the DCM 54 monitors the duty ratio of the write clock WCK transmitted via the frequency divider DV and the WCK tree.

  If the duty ratio is smaller than 50%, the process proceeds to step S904. If the duty ratio is greater than 50%, the process proceeds to step S906.

  In step S904, the DCM 54 sets the monitoring result to L. In step S906, the DCM 54 sets the monitoring result to H.

  In step S907, the DCM 54 outputs a monitoring result. The monitoring result is transmitted to the DDR-PHY 101 via the flip-flop FF5, the driver AM11, and the path P5. In the DDR-PHY 101, the monitoring result is sent to the determination circuit 52 via the receiver AM5 and the flip-flop FF2.

  In step S908, when the DCA code is the maximum value MAX, the process proceeds to step S910. If the DCA code is not the maximum value MAX, the process proceeds to step S909.

  In step S909, the DCA code is incremented, and the process returns to step S902.

  In step S910, the determination circuit 52 determines a tentative optimal DCA code based on a plurality of monitoring results of the DCA code between the minimum value MIN and the maximum value MAX. That is, the determination circuit 52 specifies, as an indefinite section, a section in which H and L monitor results coexist between a section in which the H monitor result continues a predetermined number of times and a section in which the L monitor result continues a predetermined number of times. I do. The determination circuit 52 determines a DCA code N corresponding to a monitoring result of any one point in the indefinite section as a temporary optimum DCA code. For example, the determination circuit 52 may determine the DCA code N corresponding to the monitoring result at the center of the indefinite section as a temporary optimal DCA code.

  In the present embodiment, the deterioration of the duty ratio of the write clock WCK from the PLL 99 of the DDR-PHY 101 to the DCM 54 of the DRAM 201 can be corrected by the first training.

FIG. 14 is a timing chart of the fifth embodiment.
The write command WR starts the process of writing the write data to the DRAM. After the issuance of the write command WR, the enable signal EN input to the flip-flop FF8 is in an inactive state, and as a result, there is a period during which the toggle operation of the write clocks WCK and WCK # is stopped. The DCA code control circuit 61 sends the write DCA code to the DCA 63 during the period in which the toggle operation of the write clocks WCK and WCK # is stopped, and converts the DCA code used for adjusting the duty ratio to the DCA 63 to the write DCA code. Switch. This is because if the duty ratio of the write clock WCK is adjusted after the start of the toggle operation of the write clocks WCK and WCK #, the waveform of the write clock WCK is distorted, and the number of pulses of the write clock WCK becomes irregular. .

  In response to the read command RD, a process of reading read data from the DRAM is started. After the issuance of the read command RD, the enable signal EN input to the flip-flop FF8 is in an inactive state, and as a result, there is a period during which the toggle operation of the write clocks WCK and WCK # is stopped. The DCA code control circuit 61 sends the read DCA code to the DCA 63 during the period in which the toggle operation of the write clocks WCK and WCK # is stopped, and converts the DCA code used by the DCA 63 to adjust the duty ratio to the read DCA code. Switch.

  In the present embodiment, the opening of the eye pattern of the read data RDQ and the opening of the eye pattern of the WDQ of the write data can be optimized. In the fourth embodiment, since the DCA is arranged on the DRAM side, it is necessary to issue a command for switching the DCA code before issuing the write command WR and before issuing the read command RD. large. In the present embodiment, the DCA code can be switched after the write command WR and the read command RD are issued, so that overhead can be eliminated.

[Sixth Embodiment]
FIG. 15 is a diagram illustrating a configuration of the DRAM 202 and the DDR-PHY 102 according to the sixth embodiment.

  The sixth embodiment is different from the fifth embodiment in that, in the sixth embodiment, the DDR-PHY 102 includes the DCA 73, and the DCA code control circuit 71 sends the DCA code to the DCA 73. is there.

  The DCA 73 is arranged after the flip-flop FF3. The DCA 73 adjusts the duty ratio for each bit of the write data WDQ according to the DCA code for each bit sent from the DCA code control circuit 71. The DCA code sent to the DCA 63 and the DCA code sent to the DCA 73 are different.

  FIG. 16 is a flowchart illustrating a procedure of training of the memory interface according to the sixth embodiment. This training is performed in the initialization sequence of the DRAM 202.

  Steps S801 to S810 are the same as steps S101 to S110 of the fourth embodiment.

In step S811, the duty ratio of the write data WDQ is adjusted.
FIG. 17 is a diagram for explaining the processing in step S811 in FIG.

  The determination circuit 72 checks whether each bit of the write data WDQ has been normally written in the memory area of the DRAM 202 while changing the DCA code and the delay amount delay of the delay circuit DL5 within a certain range. , Creates an eye pattern for each bit of the write data WDQ. The range in which the DCA code is changed is Z ranges of K, K + 1, ..., K + Z-1.

  That is, when the DCA code = X and the delay amount delay = D, the determination circuit 72 outputs the m-th bit (= “1”) of the write data WDQ by the DDR-PHY 102 and writes “1” to the DRAM 202. When the DCA code X and the delay amount delay = D, the m-th bit of the write data WDQ is determined to be PASS. When the DCA code X and the delay amount delay = D, the DDR-PHY 102 outputs the m-th bit (= “1”) of the write data WDQ and determines “0” in the DRAM 202 Determines that the m-th bit of the write data WDQ is FAIL in the DCA code X and the delay amount delay = D. However, it is assumed that m = 0 to 7.

  To write “1” to the DRAM 202, the DDR-PHY 102 may send a write command to the DRAM 202. In order to read the written data from the DRAM 202, the DDR-PHY 102 may send a read command to the DRAM 202.

  The determination circuit 72 checks the width Lm (X) of the eye opening (the area determined to be Pass) of the m-th bit eye pattern of the write data WDQ at DCA code = X.

  FIG. 17A shows an eye pattern of the 0th bit of the write data WDQ created by changing the delay amount delay when the DCA code is (K). As shown in FIG. 17A, the width of the opening of the eye pattern is specified as L0 (K).

  FIG. 17B shows the eye pattern of the 0th bit of the write data WDQ created by changing the delay amount delay when the DCA code is (K + 1). As shown in FIG. 17B, the width of the opening of the eye pattern is specified as L0 (K + 1).

  FIG. 17C shows an eye pattern of the 0th bit of the write data WDQ created by changing the delay amount delay when the DCA code is (K + Z−1). As shown in FIG. 17C, the width of the opening of the eye pattern is specified as L0 (K + Z-1).

  FIG. 17D shows the eye pattern of the first bit of the write data WDQ created by changing the delay amount delay when the DCA code is (K). As shown in FIG. 17D, the width of the opening of the eye pattern is specified as L1 (K).

  FIG. 17E shows an eye pattern of the first bit of the write data WDQ created by changing the delay amount delay when the DCA code is (K + 1). As shown in FIG. 17E, the width of the opening of the eye pattern is specified as L1 (K + 1).

  FIG. 17F shows the eye pattern of the first bit of the write data WDQ created by changing the delay amount delay when the DCA code is (K + Z−1). As shown in FIG. 17F, the width of the eye pattern opening is specified as L1 (K + Z-1).

  FIG. 17G shows the eye pattern of the seventh bit of the write data WDQ created by changing the delay amount delay when the DCA code is (K). As shown in FIG. 17G, the width of the opening of the eye pattern is specified as L7 (K).

  FIG. 17H shows the eye pattern of the seventh bit of the write data WDQ created by changing the delay amount delay when the DCA code is (K + 1). As shown in FIG. 17H, the width of the opening of the eye pattern is specified as L7 (K + 1).

  FIG. 17I shows an eye pattern of the seventh bit of the write data WDQ created by changing the delay amount delay when the DCA code is (K + Z−1). As shown in FIG. 17I, the width of the opening of the eye pattern is specified as L7 (K + Z−1).

  The determination circuit 72 specifies the maximum value L0 (T0) among the eye opening widths L0 (K), L0 (K + 1),..., L0 (K + Z−1), and determines the optimal DCA code of the 0th bit. Is T0.

  Similarly, the determination circuit 72 specifies the maximum value L1 (T1) of the eye opening widths L1 (K), L1 (K + 1),..., L1 (K + Z−1), and determines the optimal value of the first bit. The DCA code is T1.

  Similarly, the determination circuit 72 specifies the maximum value Lm (Tm) of the eye opening widths Lm (K), Lm (K + 1),..., Lm (K + Z−1), and determines the optimal value of the m-th bit. The DCA code is Tm.

  In the present embodiment, the deterioration of the duty ratio of the write data WDQ from the flip-flop where the write data is generated in the LSI to the flip-flops FF6 and FF7 where the write data WDQ is captured in the DRAM 202 is corrected. be able to.

  FIG. 18 illustrates the write clock WCK and the s-th bit write data WDQs (s = 0 to 7) before the DCC of the sixth embodiment is executed, and the write clock after the DCC of the sixth embodiment is executed. FIG. 14 is a diagram illustrating WCK and write data WDQs of the s-th bit.

  By executing the DCC of the sixth embodiment, the duty ratio of the write clock WCK can be made close to 50%. This makes it possible to match the timing of the rising edge and the falling edge of the write clock WCK with the timing near the center of the eye pattern opening of the s-th bit write data WDQs (s = 0 to 7).

  Further, by executing the DCC of the sixth embodiment, the width of the opening of the eye pattern of the write clock WCK can be maximized. As a result, the possibility that the write data can be normally written to the DRAM 202 can be made higher than in the third and fourth embodiments.

  In this embodiment, as in the fifth embodiment, the DCA code can be switched after the write command WR and the read command RD are issued, so that overhead can be eliminated.

  In the present embodiment, in addition to the configuration of the fifth embodiment, the DDR-PHY 102 includes the DCA 73, and the DCA code control circuit 71 sends the DCA code to the DCA 73. It is not something to be done. This embodiment need not have the functions of the fifth embodiment. That is, the DDR-PHY 102 may not include the DCA 63, the DRAM 202 may not include the DCM 54, and the DCA code control circuit 71 may send the DCA code only to the DCA 73. Alternatively, similarly to the fourth embodiment, a DCA 63 for adjusting the duty ratio of the write clock WCK may be provided on the DRAM 202 side.

[Seventh Embodiment]
FIG. 19 is a diagram illustrating a configuration of the DRAM 203 and the DDR-PHY 103 according to the seventh embodiment.

  The seventh embodiment is different from the fifth embodiment in that the DCM 93 is arranged not on the DRAM 203 but on the DDR-PHY 103 in the seventh embodiment.

  DCA83 is arranged at the subsequent stage of delay circuit DL2. DCA 83 adjusts the duty ratio of write clocks WCK and WCK # in accordance with the DCA code sent from DCA code control circuit 81.

  The DCA code control circuit 81 has a function of switching the DCA code used by the DCA 83. The DCA 83 adjusts the duty ratio of the write clocks WCK and WCK # using a predetermined DCA code for writing at the time of writing and using a DCA code for reading at the time of reading. During training, the DCA 83 changes the duty ratio of the write clocks WCK and WCK # using the DCA code that is sequentially switched. The optimal DCA code determined by the training becomes the DCA code for reading.

  The DCM 93 is arranged after the receiver AM4. The DCM 93 monitors the duty ratio of the read data strobe signal RDQS output from the receiver AM4.

  FIG. 20 is a flowchart illustrating a procedure of training the memory interface according to the seventh embodiment. This training is executed in the initialization sequence of the DRAM 203.

  In step S701, ZQ calibration is performed. That is, the driver of the DDR-PHY 100 and the DRAM 200 and the ODT (On Die Termination) are calibrated.

  In step S702, the delay of the code, command, or address CA is adjusted.

  In step S703, the first synchronization adjustment between the write clock WCK and the clock CLK is performed.

  In step S704, the duty ratio of the write clock WCK is adjusted. The adjusted DCA code becomes the optimal DCA code.

  In step S705, the second synchronization adjustment between the write clock WCK and the clock CLK is performed.

In step S706, the delay of the read data strobe signal RDQS is adjusted.
In step S707, the delay of the read data RDQ is adjusted.

In step S708, the delay of the write data WDQ is adjusted.
In step S709, the magnitude of the read reference voltage RVref used in the receiver AM5 is adjusted.

  In step S710, the magnitude of the write reference voltage WVref used by the driver AM12 is adjusted.

  FIG. 21 is a flowchart showing the procedure of the first training in step S704 of FIG. 20 in the seventh embodiment.

  Referring to FIG. 21, in step S300, DCA code control circuit 81 sets the DCA code to minimum value MIN.

  In step S301, the DCA code control circuit 81 sends the DCA code to the DCA 83. The DCA 83 adjusts the duty ratio of the write clock WCK output from the delay circuit DL2 according to the DCA code. The driver AM3 transfers the write clock WCK to the DRAM 203 via the path P3. The receiver AM9 in the DRAM 203 amplifies the received write clock WCK. The write clock WCK is sent to the flip-flop FF4 via the frequency divider DV and the WCK tree. Flip-flop FF4 outputs read data strobe signal RDQS based on the timing of write clock WCK. The read data strobe signal RDQS is transmitted to the DDR-PHY 103 via the driver AM11 and the path P5. The receiver AM4 of the DDR-PHY 103 amplifies the read data strobe signal RDQS and outputs it to the DCM 93.

  In step S302, the clock CLK output from the PLL 99 is delayed by the delay circuit DL2 and sent to the clock terminal of the flip-flop FF8. The flip-flop FF8 generates the write clock WCK at the timing of the clock CLK output from the delay circuit DL2. An activated enable signal EN is input to the flip-flop FF8. The flip-flop FF8 toggles the write clock WCK. The driver AM3 amplifies and inverts and amplifies the write clock WCK output from the flip-flop FF8. The driver AM3 transfers the amplified write clocks WCK and WCK # to the DRAM 203 via the path P3. The receiver AM9 in the DRAM 300 amplifies the received differential write clocks WCK and WCK # and outputs a write clock WCK.

  In step S303, the DCM 93 monitors the duty ratio of the transmitted read data strobe signal RDQS.

  If the duty ratio is smaller than 50%, the process proceeds to step S304. If the duty ratio is greater than 50%, the process proceeds to step S306.

  In step S304, the DCM 93 sets the monitoring result to L. In step S306, the DCM 93 sets the monitoring result to H.

  In step S307, the DCM 93 outputs a monitoring result. The monitoring result is sent to the judgment circuit 82.

  In step S308, when the DCA code is the maximum value MAX, the process proceeds to step S310. If the DCA code is not the maximum value MAX, the process proceeds to step S309.

  In step S309, the DCA code is incremented, and the process returns to step S302.

  In step S310, the determination circuit 82 determines a tentative optimal DCA code based on a plurality of monitoring results of the DCA code between the minimum value MIN and the maximum value MAX. In other words, the determination circuit 82 specifies, as an indefinite section, a section in which H and L monitor results coexist between a section in which the H monitor result continues a predetermined number of times and a section in which the L monitor result continues a predetermined number of times. I do. The determination circuit 82 determines the DCA code N corresponding to the monitoring result of any one point in the indefinite section as the optimal DCA code. The determination circuit 82 may determine the DCA code N corresponding to the monitoring result at the center of the indefinite section as the optimum DCA code. The optimal DCA code is used as a DCA code for reading.

  In the present embodiment, the duty ratio of the write clock WCK from the PLL 99 of the DDR-PHY 103 to the flip-flops FF4 and FF5 of the Read Path of the DRAM 203 deteriorates, and the DDR-PHY 103 generates The deterioration of the duty ratio of the read data strobe signal RDQS up to the DCM 93 can be corrected. Thereby, the opening of the eye pattern of the read data RDQ can be improved.

  Note that this embodiment can be combined with at least one of the functions of the fourth embodiment, the fifth embodiment, and the sixth embodiment.

  In the fifth embodiment, the DCA code obtained by the first training is used as the read DCA code. However, the DCA code obtained by the present embodiment can be used as the read DCA code.

  In the existing LPDDR4 / 4X memory, the maximum operating frequency is 2133 MHz (4266 Mbps), but in LPDDR5, the speed is increased to 3200 MHz (6400 Mbps). Even if the speed is increased, the duty correction training described in the above embodiment is effective in order to maintain the write / read characteristics of the DRAM.

(Note)
The present disclosure includes the following inventions.

A memory system comprising a control device and a memory,
The control device includes:
A clock supply circuit for supplying a clock,
A driver for transferring the clock to a memory through a first path;
The memory is
A receiver for receiving the clock transmitted through the first path;
A register for holding a designated duty ratio of the clock;
A duty adjustment circuit that adjusts a duty ratio of the clock output from the receiver to a specified duty ratio in the register;
A monitoring circuit that monitors a duty ratio of the clock output from the duty adjustment circuit during a training period, and transfers the monitoring result to the control device through a second path;
The control device further includes:
In the training period, a control circuit that changes the designated duty ratio and transfers the designated duty ratio to the register in the memory.
A memory for determining a designated duty ratio after the end of the training period, based on a result of monitoring the duty ratio transmitted from the memory through the second path during the training period.

  As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various changes can be made without departing from the gist of the invention. Needless to say.

  1,11,21 semiconductor device, 2,22 clock supply circuit, 3,13,23 duty adjustment circuit, 5,15,25 control circuit, 6,16,26 memory, 7,17,27 driver, 51,61, 71, 81 DCA code control circuit, 4, 14, 24, 52 determination circuit, 29 RDQS output circuit, 53, 63, 73, 83 DCA, 54, 93 DCM, 100, 101, 102, 103 DDR-PHY, 200, 201, 202, 203 DRAM, 401 PCB, 402 LSI, 500 DDR memory controller, DL1-DL5 delay circuit, FF1-FF8, FF10 flip-flop, MR mode register, WT write clock tree, R1, R2, R11, R21, R22 , P1 to P5 routes, AM1 to AM3, AM6, AM1 , AM11 driver, AM4, AM5, AM7~AM9, AM12 receiver.

Claims (15)

A clock supply circuit for supplying a clock,
A duty adjustment circuit that adjusts a duty ratio of the clock to a specified duty ratio;
A driver for transferring the clock whose duty ratio has been adjusted to a memory through a first path;
A control circuit for changing the designated duty ratio during a training period;
A semiconductor circuit comprising: a determination circuit that determines a designated duty ratio after the training period is completed, based on a result of monitoring the duty ratio transmitted from the memory through a second path during the training period. The control circuit increases or decreases the designated duty ratio a plurality of times during the training period,
The determination circuit includes a first section in which the monitoring result of the duty ratio less than the first reference value is continued for a predetermined number of times, and a second section in which the monitoring result of the duty ratio exceeding the second reference value is continuous for the predetermined number of times. 2. The semiconductor device according to claim 1, wherein a designated duty ratio after the end of the training period is determined based on a monitoring result of any one point in a third section between the second section and the third section. 3.   3. The semiconductor device according to claim 2, wherein said first reference value and said second reference value are 50%.   The semiconductor according to claim 2, wherein the determination circuit determines the designated duty ratio corresponding to a monitoring result of any one point in the third section as the designated duty ratio after the end of the training period. apparatus. The determination circuit selects the designated duty ratio corresponding to a monitoring result of any one point in the third section,
The control circuit changes the designated duty ratio in a predetermined range around the selected designated duty ratio,
The determination circuit determines the designated duty ratio after the end of the training period by comparing the size of the opening of the eye pattern of the write data to the memory for the plurality of changed designated duty ratios. The semiconductor device according to claim 2, wherein The determination circuit selects the designated duty ratio corresponding to a monitoring result of any one point in the third section, and determines the selected designated duty ratio from the memory after the end of the training period. Determined as the specified duty ratio when reading data,
The control circuit changes the designated duty ratio in a predetermined range around the selected designated duty ratio,
The determination circuit compares the size of the opening of the eye pattern of the write data to the memory with respect to the plurality of changed designated duty ratios, so that the write data to the memory after the end of the training period. 3. The semiconductor device according to claim 2, wherein the specified duty ratio is determined at the time of writing.   7. The write circuit according to claim 5, wherein the determination circuit generates an eye pattern of the write data by changing a delay amount of the write data and a reference voltage of a receiver receiving the write data in the memory. Semiconductor device.   The control circuit switches the designated duty ratio to the designated duty ratio at the time of writing after issuing a write command at the time of switching from read to write, and issues the designated duty ratio after issuing a read command at the time of switching from write to read. 7. The semiconductor device according to claim 6, wherein a ratio is switched to the designated duty ratio at the time of the read.   9. The semiconductor device according to claim 8, wherein the control circuit switches the designated duty ratio after the issuance of the write command and the read command during a period in which the toggle of the clock is stopped. A duty adjustment circuit for adjusting the duty ratio of the write data to a specified duty ratio;
A driver for transferring the write data with the adjusted duty ratio to a memory through a first path;
A control circuit for changing the designated duty ratio during a training period;
A determination circuit for determining the designated duty ratio after the end of the training period by comparing the size of the opening of the eye pattern of the write data to the memory for the plurality of changed designated duty ratios; A semiconductor device provided. The duty adjustment circuit adjusts a designated duty ratio for each bit of the write data,
The control circuit changes the designated duty ratio for each bit of the write data,
The determination circuit compares the size of the eye pattern opening for each bit of the write data with respect to the plurality of changed designated duty ratios, thereby determining each bit of the write data after the end of the training period. 11. The semiconductor device according to claim 10, wherein said specified duty ratio is determined.   12. The semiconductor device according to claim 11, wherein the determination circuit changes an amount of delay for each bit of the write data to generate an eye pattern for each bit of the write data. A clock supply circuit for supplying a clock,
A duty adjustment circuit that adjusts a duty ratio of the clock to a specified duty ratio;
A driver for transferring the clock whose duty ratio has been adjusted to a memory through a first path;
A control circuit for changing the designated duty ratio during a training period;
In the training period, a read data strobe signal output from the memory in accordance with the clock is received through a second path, and based on a duty ratio of the read data strobe signal, the read data strobe signal at the end of the training period is read. A semiconductor device comprising: a determination circuit that determines a designated duty ratio. The control circuit increases or decreases the designated duty ratio a plurality of times during the training period,
The determination circuit includes a first section in which the monitoring result of the duty ratio less than the first reference value is continued for a predetermined number of times, and a second section in which the monitoring result of the duty ratio exceeding the second reference value is continuous for the predetermined number of times. The designated duty ratio corresponding to the monitoring result of any one point in the third section between the section and the designated section is defined as the designated duty ratio at the time of reading data from the memory after the end of the training period. 14. The semiconductor device according to claim 13, which is determined.   15. The semiconductor device according to claim 14, wherein the first reference value and the second reference value are 50%.

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