JP2020047672A - Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

To provide a silicon carbide semiconductor device capable of stabilizing voltage in a low current region by relaxing a stress by a TiN film when applying voltage between a gate electrode and a source electrode, and a method for manufacturing the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device comprises a first semiconductor layer 2 of a first conductivity type provided on a front surface of a semiconductor substrate 1 of the first conductivity type, a second semiconductor layer 3 of a second conductivity type, a first semiconductor region 7 of the first conductivity type, a gate electrode 10 provided via a gate insulation film 9, and an interlayer insulation film 11 provided on the gate electrode 10. The silicon carbide semiconductor device further includes a first electrode 13 provided on surfaces of the second semiconductor layer 3 and the first semiconductor region 7, a plating film 16 selectively provided on the first electrode 13, and a solder 17 provided on the plating film 16. In a region provided with the plating film 16, a TiN film 20 covering the interlayer insulation film 11 is provided between the interlayer insulation film 11 and the first electrode 13. In a region not provided with the plating film 16, the TiN film 20 is not provided.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

  Conventionally, silicon (Si) has been used as a constituent material of a power semiconductor device for controlling a high voltage or a large current. The power semiconductor device includes a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor: an insulated gate bipolar transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: an insulated gate field effect transistor). Have been.

  For example, a bipolar transistor or an IGBT has a higher current density than a MOSFET and can increase the current, but cannot perform high-speed switching. Specifically, the use of a bipolar transistor at a switching frequency of about several kHz is a limit, and the use of an IGBT at a switching frequency of about several tens of kHz is a limit. On the other hand, the power MOSFET has a lower current density than the bipolar transistor and the IGBT, making it difficult to increase the current, but can perform a high-speed switching operation up to about several MHz.

  However, in the market, there is a strong demand for a power semiconductor device having both a large current and a high speed, and IGBTs and power MOSFETs have been focused on improvement, and the development is now progressing almost to the material limit. . A semiconductor material replacing silicon is being studied from the viewpoint of a power semiconductor device, and silicon carbide (SiC) is used as a semiconductor material capable of manufacturing (manufacturing) a next-generation power semiconductor device having excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. Is attracting attention.

  Silicon carbide is a semiconductor material that is chemically very stable, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. Further, silicon carbide is expected to be a semiconductor material capable of sufficiently reducing on-resistance because the maximum electric field strength is at least one order of magnitude higher than that of silicon. Such features of silicon carbide also apply to a wide band gap semiconductor having a wider band gap than other silicon, for example, gallium nitride (GaN). Therefore, by using a wide bandgap semiconductor, it is possible to increase the breakdown voltage of the semiconductor device.

  Such a high breakdown voltage semiconductor device using silicon carbide has a reduced carrier loss, so that when used in an inverter, the carrier frequency is applied at an order of magnitude higher than that of a conventional semiconductor device using silicon. When the semiconductor device is applied at a high frequency, the heat generation temperature of the chip increases, which affects the reliability of the semiconductor device. In particular, a bonding wire is bonded to the front surface electrode on the front surface side of the substrate as a wiring material for extracting the potential of the front surface electrode to the outside. If used, the adhesion between the front surface electrode and the bonding wire is reduced, which affects reliability.

  Since the silicon carbide semiconductor device may be used at a high temperature of 230 ° C. or higher, a pin-shaped external terminal electrode may be joined to the front surface electrode by solder instead of a bonding wire. This can prevent the adhesion between the front surface electrode and the external terminal electrode from being reduced.

FIG. 14 is a sectional view showing a structure of a conventional silicon carbide semiconductor device. As shown in FIG. 14, a MOS gate having a general trench gate structure is provided on a front surface (a surface on the p-type silicon carbide epitaxial layer 103 side) of a semiconductor substrate made of silicon carbide (hereinafter, referred to as a silicon carbide substrate). Is provided. A silicon carbide substrate (semiconductor chip) includes an n ⁺ -type support substrate (hereinafter, referred to as an n ⁺ -type silicon carbide substrate) 101 made of silicon carbide, an n-type silicon carbide epitaxial layer 102, and an n-type high concentration Region 106 and each silicon carbide layer to be p-type silicon carbide epitaxial layer 103 are sequentially grown epitaxially.

In the n-type high-concentration region 106, a first p ⁺ -type base region 104 is selectively provided between adjacent trenches 118 (mesas). In the n-type high-concentration region 106, a second p ⁺ -type base region 105 that partially covers the bottom surface of the trench 118 is selectively provided. Second p ⁺ -type base region 105 is provided at a depth that does not reach n-type silicon carbide epitaxial layer 102. The second p ⁺ -type base region 105 and the first p ⁺ -type base region 104 may be formed at the same time. First p ⁺ -type base region 104 is provided to be in contact with p-type silicon carbide epitaxial layer 103.

Reference numerals 107 to 111, 113, and 115 denote an n ⁺ -type source region, a p ^{+ +} -type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a source electrode pad (front electrode), respectively. . Here, the source electrode pad 115 is made of a material such as aluminum (Al) or aluminum-silicon alloy (Al-Si) that is difficult to bond with solder. For this reason, the plating film 116 is provided on the source electrode pad 115, and the external terminal electrode 119 is provided on the plating film 116 via the solder 117. Further, a back surface electrode 114 is provided on the back surface side of n ⁺ type silicon carbide substrate 101.

  Here, a double-sided cooling structure is employed to increase the cooling efficiency of the silicon carbide semiconductor device. With the double-sided cooling structure, a strong stress is applied to the external terminal electrodes 119 fixed by the solder 117 from the resin sealing the silicon carbide semiconductor chip. As a result, the stress on the gate electrode 110 also increases. In order to reduce this stress, a titanium nitride (TiN) film 120 is provided between the interlayer insulating film 111 and the source electrode 113.

  A metal electrode including a Ti film (or a TiN film) and an Al film is provided on the interlayer insulating film and in the source contact hole of the interlayer insulating film, and the Al film is unnecessarily diffused by the Ti film or the TiN film serving as a barrier metal. There is known a technique for suppressing the occurrence of a phenomenon and stabilizing a threshold voltage (for example, see Patent Document 1 below).

JP-A-2006-115735

  However, if TiN film 120 is provided on the entire front surface of the silicon carbide substrate, the silicon carbide semiconductor device may be deteriorated due to the stress of TiN film 120 itself. In this case, when a voltage is applied between gate electrode 110 and source electrode 113, when a voltage is applied to the silicon carbide semiconductor device, the voltage fluctuates particularly in a low current region.

FIG. 15 is a graph showing deteriorated characteristics of a conventional silicon carbide semiconductor device. In FIG. 15, the horizontal axis represents the voltage V _GS between the gate electrode and the source electrode, and the vertical axis represents the current _ID flowing through the drain electrode. As shown in FIG. 15, in the silicon carbide semiconductor device having deteriorated characteristics, there is a portion where voltage V _GS fluctuates in a region where current _ID is low (S in FIG. 15).

  The present invention can stabilize the voltage in a low current region when a voltage is applied between the gate electrode and the source electrode by relieving the stress caused by the TiN film in order to solve the above-described problem of the related art. It is an object to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

  In order to solve the problems described above and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor layer of the first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on the front surface of the semiconductor substrate of the first conductivity type. A second semiconductor layer of a second conductivity type is selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate. A first conductivity type first semiconductor region is selectively provided on a surface layer of the second semiconductor layer opposite to the semiconductor substrate side. A gate insulating film in contact with the second semiconductor layer is provided. A gate electrode is provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer. An interlayer insulating film is provided on the gate electrode. A first electrode is provided on surfaces of the second semiconductor layer and the first semiconductor region. A plating film is selectively provided on the first electrode. A solder is provided on the plating film. A second electrode is provided on a back surface of the semiconductor substrate. In a region where the plating film is provided, a TiN film covering the interlayer insulating film is provided between the interlayer insulating film and the first electrode, and in a region where the plating film is not provided, the TiN film is not provided. .

  In addition, the silicon carbide semiconductor device according to the present invention, in the above-described invention, further includes a trench penetrating the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer, and the gate electrode includes: It is provided inside the trench via the gate insulating film.

  In addition, the silicon carbide semiconductor device according to the present invention, in the above-described invention, further includes an external terminal electrode joined by the solder for extracting a potential of the first electrode to the outside, and the plating film includes the external terminal electrode. Are provided in a region where the bonding is performed.

  In order to solve the problems described above and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step of forming a first semiconductor layer of the first conductivity type having a lower impurity concentration than the semiconductor substrate is performed on the front surface of the semiconductor substrate of the first conductivity type. Next, a second step of selectively forming a second semiconductor layer of the second conductivity type on the surface of the first semiconductor layer opposite to the semiconductor substrate side is performed. Next, a third step of selectively forming a first semiconductor region of the first conductivity type on a surface layer of the second semiconductor layer opposite to the semiconductor substrate side is performed. Next, a fourth step of forming a gate insulating film in contact with the second semiconductor layer is performed. Next, a fifth step of forming a gate electrode on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer is performed. Next, a sixth step of forming an interlayer insulating film on the gate electrode is performed. Next, a seventh step of forming a TiN film is performed. Next, an eighth step of forming a first electrode on the surface of the second semiconductor layer and the first semiconductor region is performed. Next, a ninth step of selectively forming a plating film on the first electrode is performed. Next, a tenth step of forming a solder on the plating film is performed. Next, an eleventh step of forming a second electrode on the back surface of the semiconductor substrate is performed. In the seventh step, the TiN film covering the interlayer insulating film is formed between the interlayer insulating film and the first electrode in a region where the plating film is provided, and in a region where the plating film is not provided. And the TiN film is not formed.

  According to the above-described invention, since the TiN film in contact with the interlayer insulating film is not provided in the portion where the plating film is not provided, the stress from the TiN film is eliminated, and the stress applied to the gate electrode can be reduced. it can. Therefore, the quality of the gate electrode can be maintained, and when a voltage is applied between the gate electrode and the source electrode, characteristics of a current flowing through the silicon carbide semiconductor device in a low current region can be stabilized.

  According to the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device of the present invention, when a voltage is applied between the gate electrode and the source electrode by relaxing the stress caused by the TiN film, the voltage is reduced in a low current region. This has the effect of stabilizing.

FIG. 4 is a cross-sectional view showing a structure of a portion A-A ′ in FIG. 3 of the silicon carbide semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view showing a structure of a portion B-B ′ of FIG. 3 of the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a top view showing a structure of the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a diagram showing relative values of stress applied to the silicon carbide semiconductor device according to the embodiment and a conventional silicon carbide semiconductor device. 4 is a graph showing characteristics of the silicon carbide semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view schematically showing a state of the silicon carbide semiconductor device according to the embodiment in the process of being manufactured (part 1). FIG. 5 is a cross-sectional view schematically showing a state in the course of manufacturing the silicon carbide semiconductor device according to the embodiment (part 2). FIG. 4 is a cross-sectional view schematically showing a state in the course of manufacturing the silicon carbide semiconductor device according to the embodiment (part 3). FIG. 4 is a cross-sectional view schematically showing a state in the course of manufacturing the silicon carbide semiconductor device according to the embodiment (part 4). FIG. 5 is a cross-sectional view schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment (part 5). FIG. 6 is a cross-sectional view schematically showing a state in the course of manufacturing the silicon carbide semiconductor device according to the embodiment (part 6). FIG. 7 is a cross-sectional view schematically showing a state in the course of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 7). FIG. 8 is a cross-sectional view schematically showing a state in the course of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 8). FIG. 11 is a cross sectional view showing a structure of a conventional silicon carbide semiconductor device. 5 is a graph showing deteriorated characteristics of a conventional silicon carbide semiconductor device.

  Hereinafter, preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, a layer or a region entitled with n or p means that electrons or holes are majority carriers, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region to which they are not added. When the notation of n or p including + and-is the same, it indicates that the densities are close, and the densities are not necessarily equal. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant description will be omitted. Further, in the present specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after the index, and adding "-" before the index indicates a negative index.

(Embodiment)
A semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described using a MOSFET as an example. FIG. 1 is a cross-sectional view showing a structure of a portion AA ′ of FIG. 3 of the silicon carbide semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view showing a structure of a portion BB ′ of FIG. 3 of the silicon carbide semiconductor device according to the embodiment.

As shown in FIGS. 1 and 2, the silicon carbide semiconductor device according to the embodiment has a first main surface (front surface) of an n ⁺ -type silicon carbide substrate (first conductivity type semiconductor substrate) 1, for example, On the (0001) plane (Si plane), an n-type silicon carbide epitaxial layer (first semiconductor layer of first conductivity type) 2 is deposited.

N ⁺ type silicon carbide substrate 1 is a silicon carbide single crystal substrate doped with, for example, nitrogen (N). N-type silicon carbide epitaxial layer 2 is a low-concentration n-type drift layer doped with, for example, nitrogen at a lower impurity concentration than n ⁺ -type silicon carbide substrate 1. N-type high-concentration region 6 is formed on the surface of n-type silicon carbide epitaxial layer 2 opposite to n ⁺ -type silicon carbide substrate 1. N-type high-concentration region 6 is a high-concentration n-type drift layer doped with, for example, nitrogen, having an impurity concentration lower than n ⁺ -type silicon carbide substrate 1 and higher than n-type silicon carbide epitaxial layer 2. Hereinafter, n ⁺ -type silicon carbide substrate 1, n-type silicon carbide epitaxial layer 2, and p-type silicon carbide epitaxial layer (second semiconductor layer of the second conductivity type) 3 described below are combined to form a silicon carbide semiconductor substrate.

As shown in FIGS. 1 and 2, a back surface electrode 14 is provided on the second main surface (back surface, that is, the back surface of the silicon carbide semiconductor substrate) of n ⁺ type silicon carbide substrate 1. The back electrode 14 forms a drain electrode. On the surface of the back electrode 14, a drain electrode pad (not shown) is provided.

A stripe-shaped trench structure is formed on the first main surface side (p-type silicon carbide epitaxial layer 3 side) of the silicon carbide semiconductor substrate. More specifically, trench 18 is formed from the surface of p-type silicon carbide epitaxial layer 3 opposite to n ⁺ -type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate) from the p-type silicon carbide epitaxial layer 3. The n-type high-concentration region 6 is reached through the layer 3. A gate insulating film 9 is formed on the bottom and side walls of the trench 18 along the inner wall of the trench 18, and a stripe-shaped gate electrode 10 is formed inside the gate insulating film 9 in the trench 18. Gate electrode 10 is insulated from n-type high concentration region 6 and p-type silicon carbide epitaxial layer 3 by gate insulating film 9. A part of the gate electrode 10 protrudes from above the trench 18 (on the side of the source electrode pad 15) to the source electrode pad 15 side.

On the surface layer of the n-type high-concentration region 6 on the side opposite to the n ⁺ -type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate), the first p ⁺ -type base region 4 and the second p ⁺ -type A base region 5 is selectively provided. The second p ⁺ -type base region 5 is formed below the trench 18, and the width of the second p ⁺ -type base region 5 is larger than the width of the trench 18. The first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 are doped with, for example, aluminum.

A structure in which a part of the first p ⁺ -type base region 4 is connected to the second p ⁺ -type base region 5 by extending a part thereof toward the trench 18 may be employed. In this case, a portion of the first 1p ⁺ -type base region 4, and the 1p ⁺ -type base region 4 a 2p ⁺ -type base region 5 and is arranged direction (hereinafter, referred to as a first direction) direction perpendicular to the x (hereinafter , The second direction) may have a planar layout in which the n-type high-concentration regions 6 are alternately and repeatedly arranged in y. For example, a structure in which a part of the first p ⁺ -type base region 4 extends to the trench 18 on both sides in the first direction x and is connected to a part of the second p ⁺ -type base region 5 is periodically arranged in the second direction y. May be arranged. The reason is that holes generated when avalanche breakdown occurs at the junction between the second p ⁺ -type base region 5 and the n-type silicon carbide epitaxial layer 2 are efficiently evacuated to the source electrode 13 so that the gate insulating film 9 This is to reduce the burden and increase the reliability.

P-type silicon carbide epitaxial layer 3 is provided on n-type silicon carbide epitaxial layer 2 on the first main surface side of the substrate. Inside p-type silicon carbide epitaxial layer 3, n ⁺ -type source region (first semiconductor region of first conductivity type) 7 and p ⁺⁺ -type contact region 8 are selectively provided on the first main surface side of the base. ing. N ⁺ type source region 7 is in contact with trench 18. The n ⁺ type source region 7 and the p ^{+ +} type contact region 8 are in contact with each other. Further, a region between the first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 of the surface layer of the n-type silicon carbide epitaxial layer 2 on the first main surface side of the base, and the p-type silicon carbide epitaxial layer 3 An n-type high concentration region 6 is provided in a region sandwiched between the second p ⁺ -type base regions 5.

  1 and 2, only two trench MOS structures are shown, but more MOS gates (insulated gates composed of metal-oxide-semiconductor) having a trench structure may be arranged in parallel. .

Interlayer insulating film 11 is provided on the entire surface on the first main surface side of the silicon carbide semiconductor substrate so as to cover gate electrode 10 embedded in trench 18. Source electrode 13 contacts n ⁺ -type source region 7 and p ⁺⁺ -type contact region 8 through a contact hole opened in interlayer insulating film 11. The contact hole opened in the interlayer insulating film 11 has a stripe shape corresponding to the shape of the gate electrode 10. Source electrode 13 is electrically insulated from gate electrode 10 by interlayer insulating film 11. A source electrode pad 15 is provided on the source electrode 13. Between the source electrode 13 and the interlayer insulating film 11, for example, a barrier metal (not shown) for preventing diffusion of metal atoms from the source electrode 13 to the gate electrode 10 side may be provided.

  A plating film 16 is selectively provided on the source electrode pad 15, and a solder 17 is selectively provided on the surface side of the plating film 16. The solder 17 is provided with an external terminal electrode 19 which is a wiring member for extracting the potential of the source electrode 13 to the outside. The external terminal electrode 19 has a needle-like pin shape and is joined to the source electrode pad 15 in an upright state.

  FIG. 3 is a top view showing a structure of the silicon carbide semiconductor device according to the embodiment. As shown in FIG. 3, in the silicon carbide semiconductor device, an edge termination region 41 that surrounds the periphery of the active region and maintains a withstand voltage is provided on an outer peripheral portion of active region 40 through which a main current flows. The active region 40 is provided with a gate pad region 31 electrically connected to the gate electrode 10 and a source pad region 32 where the source electrode pad 15 is exposed.

  The external terminal electrode 19 is provided via the solder 17 on the plating region 33 of the source pad region 32 where the plating film 16 is provided. A portion other than the plating region 33 is a non-plated region 34 where the plating film 16 is not provided.

  As shown in FIG. 3, the structure of the portion A-A ′ in FIG. 1 is the structure of the plated region 33, and the structure of the portion B-B ′ in FIG. 2 is the structure of the non-plated region 34. 1 and 2, in the silicon carbide semiconductor device according to the embodiment, in plating region 33 provided with plating film 16, TiN film covering interlayer insulating film 11 between interlayer insulating film 11 and source electrode 13. 20 are provided (see FIG. 1). On the other hand, in the case of no plating region 34 where the plating film 16 is not provided, the TiN film 20 that covers the interlayer insulating film 11 is not provided between the interlayer insulating film 11 and the source electrode 13 (see FIG. 2). Although the TiN film 20 is not provided in the source pad region 32 other than the plating region 33, the TiN film 20 may be formed slightly larger than the plating region 33 in consideration of alignment accuracy.

  As described above, in the silicon carbide semiconductor device according to the embodiment, the portion where plating film 16 is provided, that is, external terminal electrode 19 is provided, and external stress applied from external terminal electrode 19 to gate electrode 10 is reduced. The TiN film 20 is provided between the interlayer insulating film 11 and the source electrode 13 at the higher portion. External stress can be reduced by the TiN film 20. On the other hand, in the portion where the plating film 16 is not provided, since the TiN film 20 in contact with the interlayer insulating film 11 is not provided, the stress from the TiN film 20 disappears, and the stress applied to the gate electrode 10 can be reduced. it can. Therefore, the quality of gate electrode 10 can be maintained, and when a voltage is applied between gate electrode 10 and source electrode 13, characteristics can be stabilized in a low current region of the current flowing through the silicon carbide semiconductor device.

  FIG. 4 is a diagram showing relative values of stress applied to the silicon carbide semiconductor device according to the embodiment and a conventional silicon carbide semiconductor device. FIG. 4 shows a relative value of the stress applied to gate electrode 10, and it can be seen that the stress is lessened in the silicon carbide semiconductor device according to the embodiment than in the conventional silicon carbide semiconductor device. .

FIG. 5 is a graph showing characteristics of the silicon carbide semiconductor device according to the embodiment. In FIG. 5, the horizontal axis represents the voltage V _GS between the gate electrode and the source electrode, and the vertical axis represents the current _ID flowing through the drain electrode. As shown in FIG. 5, in the silicon carbide semiconductor device according to the embodiment, there is no portion where voltage V _GS fluctuates in a region where current _ID is low, and it can be seen that characteristics are not degraded.

(Method of Manufacturing Silicon Carbide Semiconductor Device According to Embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the embodiment will be described. 6 to 13 are cross-sectional views schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment.

First, n ⁺ -type silicon carbide substrate 1 made of n-type silicon carbide is prepared. Then, a first n-type silicon carbide epitaxial layer 2a made of silicon carbide is doped on the first main surface of n ⁺ -type silicon carbide substrate 1 while doping n-type impurities, for example, nitrogen atoms, with a thickness of, for example, about 30 μm. Epitaxial growth is continued. This first n-type silicon carbide epitaxial layer 2a becomes n-type silicon carbide epitaxial layer 2. The state so far is shown in FIG.

Next, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film on the surface of first n-type silicon carbide epitaxial layer 2a by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form a lower first p ⁺ -type base region 4a having a depth of about 0.5 μm. The second p ⁺ -type base region 5 serving as the bottom of the trench 18 may be formed simultaneously with the lower first p ⁺ -type base region 4a. It is formed so that the distance between the adjacent lower first p ⁺ -type base region 4a and the second p ⁺ -type base region 5 is about 1.5 μm. The impurity concentration of the lower first p ⁺ -type base region 4a and the second p ⁺ -type base region 5 is set to, for example, about 5 × 10 ¹⁸ / cm ³ . The state up to this point is shown in FIG.

Next, a part of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening, and a part of the surface region of the first n-type silicon carbide epitaxial layer 2a having a depth of, for example, 0.1. A lower n-type high concentration region 6a of about 5 μm is provided. The impurity concentration of the lower n-type high concentration region 6a is set to, for example, about 1 × 10 ¹⁷ / cm ³ .

Next, on the surface of first n-type silicon carbide epitaxial layer 2a, a second n-type silicon carbide epitaxial layer 2b doped with an n-type impurity such as nitrogen is formed with a thickness of about 0.5 μm. The impurity concentration of second n-type silicon carbide epitaxial layer 2b is set to be about 3 × 10 ¹⁵ / cm ³ . Thereafter, the first n-type silicon carbide epitaxial layer 2a and the second n-type silicon carbide epitaxial layer 2b are combined to form n-type silicon carbide epitaxial layer 2.

Next, an ion implantation mask having a predetermined opening is formed by, for example, an oxide film on the surface of second n-type silicon carbide epitaxial layer 2b by photolithography. Then, a p-type impurity such as aluminum is injected into the opening of the oxide film, and an upper first p ⁺ -type base region 4b having a depth of about 0.5 μm is formed so as to overlap the lower first p ⁺ -type base region 4a. I do. The lower first p ⁺ -type base region 4a and the upper first p ⁺ -type base region 4b form a continuous region and become the first p ⁺ -type base region 4. The impurity concentration of the upper first p ⁺ -type base region 4b is set to, for example, about 5 × 10 ¹⁸ / cm ³ .

Next, a part of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening. The upper n-type high concentration region 6b is provided. The impurity concentration of the upper n-type high concentration region 6b is set to, for example, about 1 × 10 ¹⁷ / cm ³ . The upper n-type high-concentration region 6b and the lower n-type high-concentration region 6a are formed so as to be at least partially in contact with each other to form the n-type high-concentration region 6. However, the n-type high-concentration region 6 may or may not be formed on the entire surface of the substrate. FIG. 8 shows the state thus far.

Next, a p-type silicon carbide epitaxial layer 3 doped with a p-type impurity such as aluminum is formed on the surface of n-type silicon carbide epitaxial layer 2 to a thickness of about 1.3 μm. The impurity concentration of p-type silicon carbide epitaxial layer 3 is set to about 4 × 10 ¹⁷ / cm ³ . The state up to this point is shown in FIG.

Next, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film on the surfaces of p-type silicon carbide epitaxial layer 3 and exposed n-type silicon carbide epitaxial layer 2 by photolithography. An n-type impurity such as phosphorus (P) is ion-implanted into the opening to form an n ⁺ -type source region 7 on a part of the surface of p-type silicon carbide epitaxial layer 3. The impurity concentration of n ⁺ -type source region 7 is set to be higher than the impurity concentration of p-type silicon carbide epitaxial layer 3. Next, the ion implantation mask used for forming n ⁺ -type source region 7 is removed, and an ion implantation mask having a predetermined opening is formed in the same manner. Is ion-implanted with a p-type impurity such as aluminum to provide a p ^++- type contact region 8. The impurity concentration of p ⁺⁺ -type contact region 8 is set to be higher than the impurity concentration of p-type silicon carbide epitaxial layer 3. The state up to this point is shown in FIG.

Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700 ° C. to form the first p ⁺ -type base region 4, the second p ⁺ -type base region 5, the n ⁺ -type source region 7, and the p ⁺⁺ -type contact region 8 Perform activation processing. As described above, each ion implantation region may be activated collectively by one heat treatment, or may be activated by heat treatment every time ion implantation is performed.

Next, a trench forming mask having a predetermined opening is formed on the surface of p-type silicon carbide epitaxial layer 3 by, for example, an oxide film by photolithography. Next, a trench 18 penetrating through the p-type silicon carbide epitaxial layer 3 and reaching the n-type high concentration region 6 is formed by dry etching. The bottom of the trench 18 may reach the first p ⁺ -type base region 4 formed in the n-type high-concentration region 6. Next, the trench forming mask is removed. FIG. 11 shows the state thus far.

Next, a gate insulating film 9 is formed along the surfaces of the n ⁺ type source region 7 and the p ^{+ +} type contact region 8 and the bottom and side walls of the trench 18. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000 ° C. in an oxygen atmosphere. Further, the gate insulating film 9 may be formed by a method of depositing by a chemical reaction such as high temperature oxidation (HTO).

  Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 18. The gate electrode 10 is formed by patterning this polycrystalline silicon layer by photolithography and leaving it inside the trench 18. In this patterning, the gate electrode 10 is formed so as to extend in a direction intersecting the stripe shape in a region facing the source electrode pad 15 where the solder 17 and the plating film 16 are provided, so that the gate electrodes 10 are connected to each other. .

Next, a film of, for example, phosphorus glass is formed to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, thereby forming an interlayer insulating film 11. Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) may be formed so as to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography to form a contact hole exposing the n ⁺ type source region 7 and the p ^{+ +} type contact region 8. After that, heat treatment (reflow) is performed to flatten the interlayer insulating film 11. The state up to this point is shown in FIG.

  Next, a TiN film 20 is formed in the contact hole and on the interlayer insulating film 11 by, for example, a sputtering method. The TiN film 20 is patterned by photolithography, and the TiN film 20 is left only in the portion where the plating film 16 is provided. The state so far is shown in FIG. FIG. 13 shows the state of the structure of the portion A-A 'in FIG.

  Next, for example, a Ti film, a TiN film, and a Ti film are stacked by a sputtering method, and an Al film is further formed to have a thickness of, for example, about 5 μm. Instead of the Al film, an Al-Si film or an Al-Si-Cu film may be formed. This conductive film is patterned by photolithography, and is left in the active region 40 of the entire device to form the source electrode 13. Next, a protective film (not shown) is selectively formed on source electrode 13 on the front surface side of the silicon carbide semiconductor substrate.

Next, a back electrode 14 of nickel or the like is provided on the second main surface of n ⁺ type silicon carbide semiconductor substrate 1. Thereafter, heat treatment is performed in an inert gas atmosphere at about 1000 ° C. to form a source electrode 13 and a back surface electrode that form ohmic junctions with n ⁺ type source region 7, p ^{+ +} type contact region 8 and n ⁺ type silicon carbide semiconductor substrate 1. 14 is formed.

Next, an aluminum film having a thickness of about 5 μm is deposited on the first main surface of n ⁺ silicon carbide semiconductor substrate 1 by a sputtering method, and aluminum is applied by photolithography so as to cover source electrode 13 and interlayer insulating film 11. Then, the source electrode pad 15 is formed.

  Next, a drain electrode pad (not shown) is formed by sequentially stacking, for example, titanium (Ti), nickel, and gold (Au) on the surface of the back electrode 14. Next, a plating film 16 is selectively formed on the source electrode 15, and an external terminal electrode 19 is formed on the plating film 16 via a solder 17. As described above, the silicon carbide semiconductor device shown in FIGS. 1 and 2 is completed.

  As described above, according to the silicon carbide semiconductor device of the embodiment, since the TiN film in contact with the interlayer insulating film is not provided in the portion where the plating film is not provided, the stress from the TiN film is eliminated. The stress applied to the gate electrode can be reduced. Therefore, the quality of the gate electrode can be maintained, and when a voltage is applied between the gate electrode and the source electrode, characteristics of a current flowing through the silicon carbide semiconductor device in a low current region can be stabilized.

  Although the present invention has been described with reference to an example in which the silicon carbide substrate made of silicon carbide has a (0001) plane as the main surface and a MOS is formed on the (0001) plane, the present invention is not limited to this. The semiconductor, the plane orientation of the substrate main surface, and the like can be variously changed.

  Further, in the embodiment of the present invention, the trench type MOSFET has been described as an example, but the present invention is not limited to this, and the present invention can be applied to various types of semiconductor devices such as a planar type MOSFET and a MOS type semiconductor device such as an IGBT. Further, in each of the above-described embodiments, the case where silicon carbide is used as the wide band gap semiconductor has been described as an example, but the same applies to the case where a wide band gap semiconductor other than silicon carbide such as gallium nitride (GaN) is used. The effect is obtained. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is similarly applicable to a case where the first conductivity type is p-type and the second conductivity type is n-type. Holds.

  As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for a high breakdown voltage semiconductor device used for a power conversion device or a power supply device of various industrial machines.

1, 101 n ⁺ -type silicon carbide substrate 2, 102 n-type silicon carbide epitaxial layer 2a first n-type silicon carbide epitaxial layer 2b second n-type silicon carbide epitaxial layer 3, 103 p-type silicon carbide epitaxial layer (base layer)
4, 104 first p ⁺ -type base region 4a lower first p ⁺ -type base region 4b upper first p ⁺ -type base region 5, 105 second p ⁺ -type base region 6, 106 n-type high-concentration region 6a lower n-type high-concentration region 6b Upper n type high concentration region 7, 107 n ⁺ type source region 8, 108 p ⁺⁺ type contact region 9, 109 Gate insulating film 10, 110 Gate electrode 11, 111 Interlayer insulating film 13, 113 Source electrode 14, 114 Back surface electrode 15, 115 Source electrode pad 16, 116 Plating film 17, 117 Solder 18, 118 Trench 19, 119 External terminal electrode 20, 120 TiN film 31 Gate pad region 32 Source pad region 33 Plating region 34 No plating region 40 Active region 41 Edge Termination area

Claims (4)

A first conductivity type semiconductor substrate;
A first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on a front surface of the semiconductor substrate;
A second conductivity type second semiconductor layer selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate;
A first semiconductor region of a first conductivity type selectively provided on a surface layer of the second semiconductor layer opposite to the semiconductor substrate side;
A gate insulating film in contact with the second semiconductor layer;
A gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer;
An interlayer insulating film provided on the gate electrode,
A first electrode provided on a surface of the second semiconductor layer and the first semiconductor region;
A plating film selectively provided on the first electrode;
On the plating film, provided solder,
A second electrode provided on a back surface of the semiconductor substrate;
With
In a region where the plating film is provided, a TiN film covering the interlayer insulating film is provided between the interlayer insulating film and the first electrode, and in a region where the plating film is not provided, the TiN film is not provided. A silicon carbide semiconductor device characterized by the above-mentioned. A trench penetrating the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer;
2. The silicon carbide semiconductor device according to claim 1, wherein said gate electrode is provided inside said trench via said gate insulating film. Further comprising an external terminal electrode joined by the solder, which takes out the potential of the first electrode to the outside,
The silicon carbide semiconductor device according to claim 1, wherein the plating film is provided in a region where the external terminal electrode is joined. A first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate on the front surface of the first conductive type semiconductor substrate;
A second step of selectively forming a second conductivity type second semiconductor layer on a surface of the first semiconductor layer opposite to the semiconductor substrate side;
A third step of selectively forming a first semiconductor region of the first conductivity type on a surface layer of the second semiconductor layer opposite to the semiconductor substrate side;
A fourth step of forming a gate insulating film in contact with the second semiconductor layer;
A fifth step of forming a gate electrode on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer;
A sixth step of forming an interlayer insulating film on the gate electrode;
A seventh step of forming a TiN film;
An eighth step of forming a first electrode on the surface of the second semiconductor layer and the first semiconductor region;
A ninth step of selectively forming a plating film on the first electrode;
A tenth step of forming a solder on the plating film;
An eleventh step of forming a second electrode on the back surface of the semiconductor substrate;
Including
In the seventh step, the TiN film covering the interlayer insulating film is formed between the interlayer insulating film and the first electrode in a region where the plating film is provided, and in a region where the plating film is not provided. And a method of manufacturing a silicon carbide semiconductor device, wherein the TiN film is not formed.

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