JP2019185429A - Information processor - Google Patents

Abstract

To provide an information processor that solves a problem of a reset signal malfunctioning due to noise mixed in a reset line and increasing a cost when a reset line is connected from a master controller to each slave controller.SOLUTION: In a communication system including a master control unit, and a slave control unit that performs serial communication with the master control unit, and a watchdog timer that resets the slave control unit, when a watchdog timer cannot receive a watchdog signal normally, a reset signal is transmitted to the slave control unit. Thereby, communication between a master CPU and a slave CPU and an operation check of a slave CPU core can be performed without using a reset signal between the master CPU and the slave CPU.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an information processing apparatus having a master control unit and a slave control unit.

At present, multi-function copiers having a plurality of functions such as copying, printers, and fax machines are installed and widely used in offices and convenience stores. In such an information processing apparatus such as a copying machine, a plurality of electrical components such as a motor and a fan necessary for operating the device are arranged in a distributed manner inside the casing. Therefore, if the control board serving as a master for controlling the entire copying machine is connected to all the electrical components inside the apparatus, the wiring becomes enormous. Therefore, in general, a distributed control composed of a master control board and a plurality of slave control boards that control a part of the copier in cooperation with the master control board. It is configured as a system.
In recent years, in such a distributed control system, serial communication is used as a communication method between a control board serving as a master and a control board serving as a slave. This is because the number of signals can be reduced by using serial communication, and as a result, the cost can be reduced by reducing the wiring. However, in such a distributed system, protection in the event of an abnormality in the control board serving as a slave is essential.

  For this purpose, for example, in Patent Document 1, for protection in a distributed control system, a master control unit transmits a predetermined outgoing code to a slave control unit via a communication line, and receives the received slave control unit. Is configured to send a reply code within a predetermined time. As a result, whether or not there is a problem such as disconnection in the communication line with the slave control unit is identified depending on whether or not the reply code can be received, and abnormal operation is prevented.

JP-A-1-177645

Here, in a control system like patent document 1, the exclusive line (reset line) for resetting a slave control part is needed between a master control part and a slave control part.
However, especially in the case of a device in which the master control unit and the slave control unit are arranged far apart, noise or the like is mixed in the reset signal while the reset line is being crushed between the master control unit and the slave control unit, The slave controller may malfunction.

  Therefore, an object of the present invention is to enable a slave control unit to be reset without using a dedicated reset line between a master control unit and a slave control unit.

  The present invention inputs a master control unit, a slave control unit that communicates with the master control unit, and a watchdog signal from the slave control unit, and when there is no input of the watchdog signal within a predetermined time. Watchdog means for resetting the slave control unit, wherein the master control unit transmits an instruction to output a watchdog signal to the slave control, and the slave control unit receives the watchdog from the master control unit. When an instruction to output a signal is received, an acknowledgment is transmitted to the master controller, and the master controller detects an abnormality in communication with the slave controller based on the presence or absence of the acknowledgment, and the slave control In response to an instruction to output a watchdog signal from the master control unit. And outputting the Tchidoggu means.

  According to the present invention, the slave control unit can be reset without using a dedicated reset line between the master control unit and the slave control unit.

1 is a schematic cross-sectional view of an image forming apparatus. It is a block diagram of a control board. It is a control block diagram of a 1st embodiment. It is a control flow between a master CPU and a slave CPU. It is a control flow when communication abnormality occurs. It is a control flow when communication abnormality occurs. It is a control block diagram of a 2nd embodiment. It is a control flow between a master CPU and a slave CPU.

FIG. 1 is a schematic sectional view of an image forming apparatus as an example of an information processing apparatus according to the first embodiment of the present invention.
The configuration of the image forming apparatus of this embodiment and the image forming operation will be described with reference to FIG.

A document placed on the document placement unit 203 of the automatic document feeder 201 is separated and fed by a paper feed roller 204, and is conveyed to a reading device 202 via a conveyance guide 206. Further, it is transported at a constant speed by the transport belt 208 and is discharged out of the apparatus by the paper discharge roller 205.
During this time, the image of the document illuminated by the illumination system 209 at the reading position of the reading device 202 is converted into an image signal by the image reading unit 213 via the optical system including the reflection mirrors 210, 211, and 212. The image reading unit 213 includes a lens, a CCD that is a photoelectric conversion element, a drive circuit for the CCD, and the like.
There are a scanning mode and a fixed mode for reading a document. In the flow-reading mode, a reading position is fixed, and a document conveyed at a constant speed is read. In the fixed mode, a document placed on the document glass table 214 of the reading device 202 is read by moving the illumination system 209 and the mirrors 210, 211, and 212 at a constant speed to move the reading position.

  The image signal is modulated into an optical signal by a semiconductor laser (not shown) or the like. The modulated laser light is exposed to a photosensitive drum 309 whose surface is uniformly charged by a charger 310 via an optical scanning device 311 using a polygon mirror and mirrors 312, 313 to form an electrostatic latent image. To do. The electrostatic latent image is developed with toner from the developing device 314. The toner image is transferred onto a recording sheet by a transfer separator 315. The recording paper is stored in paper cassettes 302 and 304. The recording paper is fed from the paper cassette 302 by the paper feed roller 303, transported by the transport roller 306, adjusted to the image timing by the registration roller 308, and transported to the transfer position of the photosensitive drum 309. On the other hand, the recording paper in the paper cassette 304 is fed by the paper feed roller 305, transported by the transport rollers 307 and 306, adjusted to the image timing by the registration roller 308, and transported to the transfer position of the photosensitive drum 309. The The recording paper on which the toner image has been transferred is conveyed to the fixing device 318 by the conveying belt 317, and the toner on the recording paper is fixed.

When the single-side mode is set, the recording sheet that has passed through the fixing device 318 is discharged out of the apparatus by the fixing discharge roller 319 and the discharge roller 324.
When the duplex mode is set, the recording paper is conveyed from the fixing paper discharge roller 319 to the reverse path 325 by the reverse roller 321 via the transport roller 320. Further, the recording paper is reversed and conveyed to the double-sided path 326 by reversing the rotation of the reversing roller 321 immediately after the trailing edge of the recording paper passes the joining point with the double-sided path 326. The recording paper transported to the double-sided path is transported by rollers 322 and 323, and after passing through the transporting roller 306, the timing with the back image is adjusted by the registration roller 308, transferred, fixed, and discharged outside the apparatus. Is done.

FIG. 2 is a block diagram of the master control board and the slave control board.
The image forming apparatus according to the present exemplary embodiment includes a central control board 104 that is a control board serving as a master, an image forming unit control board 120 that is a control board serving as a slave, a fixing transport unit control board 121, and a paper transport unit control board 122. It is configured.
Here, the paper transport unit control board 122 is in charge of paper transport from the paper cassette 302 (304) to the registration roller 303 in FIG. The fixing conveyance unit 121 is in charge of paper discharge from the registration roller 303 via transfer and fixing, and paper conveyance during double-sided conveyance. The image forming unit control board 120 controls other parts.

  Next, a communication system between the master control unit 100 on the central control board 104 and the slave control unit 101 on the image forming unit control board 120 will be described. Note that the communication system between the fixing conveyance unit control board 121 and the paper conveyance unit control board 122 is also the same as that of the image forming unit control board 120, and hence the description thereof is omitted.

FIG. 3 is a control block diagram of the master control unit and the slave control unit.
The master control unit 100 includes a master CPU 107 that controls the entire device. The master CPU 107 includes a master communication control unit 111 that performs communication between a master CPU core 109 serving as a control unit and a slave CPU 108.
The slave control unit 101 has a slave CPU 108. The slave CPU 108 includes a slave CPU core 113 that is a control unit, a slave communication control unit 112 that performs communication with the master CPU 107, and a slave I / O port control unit 114 that controls input and output of signals to the outside.
The slave control unit 101 further includes a watchdog timer 105 that resets the slave CPU 108. The watchdog timer 105 has a monitoring function for resetting the slave CPU 108 when the watchdog signal from the slave CPU 108 is interrupted for a predetermined time.

FIG. 4 is a control flow between the master CPU 107 and the slave CPU 108.
The master CPU core 109 instructs the master communication control unit 111 to transmit an instruction to output a WD (WatchDog) pulse as a watchdog signal to the slave communication control unit 112 (S101). Here, the output instruction of the WD pulse is defined in advance between the master CPU core 109 and the slave CPU core 113.
Receiving the instruction to transmit the WD pulse output instruction, the master communication control unit 111 transmits the WD pulse output instruction to the slave communication control unit 112 via the communication line between the master CPU 107 and the slave CPU 108 (S102a). ).

In communication between the master communication control unit 111 and the slave communication control unit 112, a mechanism such as a parity check is included in order to identify whether the receiving side has received data without error. When the control unit on the receiving side normally receives data, ACK (ACKnowledgement, confirmation response) is transmitted to the transmitting side (S102b). The transmission side can confirm that the transmission has been completed normally by receiving the ACK.
Accordingly, the master CPU 107 can detect an abnormality in communication with the slave CPU 108 based on the presence or absence of ACK (acknowledgment response).

When the transmission of the WD pulse output instruction is completed normally, the master communication control unit 111 outputs a transmission completion interrupt to the master CPU core 109 (S103).
By receiving the transmission completion interrupt, the master CPU core 109 determines that there is no abnormality in communication with the slave CPU 108 and in the slave CPU 108.

Upon receiving the WD pulse output instruction, the slave communication control unit 112 outputs a reception completion interrupt to the slave CPU core 113 (S104), and temporarily holds the received data including the received WD pulse output instruction.
The reception completion interrupt at this time does not indicate reception of a WD pulse output instruction but indicates that the slave communication control unit 112 has received communication.

The CPU core 113 that has received the reception completion interrupt confirms the reception data held in the slave communication control unit 112, and acquires the output instruction of the WD pulse indicated therein (S105).
The slave CPU core 113 that has received the WD pulse output instruction issues a WD pulse output instruction to the slave I / O port control unit 114 (S106). The WD pulse is for outputting a Hi level for a certain period (for example, 2 ms) to a signal that is being output at a low level in a steady state.

Receiving the WD pulse output instruction, the slave I / O port control unit 114 outputs a WD pulse to the watchdog timer 105 via the external output pin of the slave CPU 108 (S107).
The watchdog timer 105 to which the WD pulse is input does nothing when the next WD pulse is received within a predetermined interval (for example, 100 ms) from the previous WD pulse reception.
Since the master CPU core 109 needs to continuously transmit the WD pulse within a predetermined interval, the master CPU core 109 transmits an output instruction of the WD pulse to the slave communication control unit at a predetermined interval of a predetermined time (for example, 50 ms) or less. The instruction is repeatedly performed (S101).

Next, a case where there is some abnormality in the control will be described with reference to FIGS.
FIG. 5 is a diagram for explaining control when an abnormality occurs in communication between the master CPU 107 and the slave CPU 108.

S101 to S102a are the same as the control in FIG.
When communication between the master CPU 107 and the slave CPU is abnormal, the control unit on the receiving side cannot receive data normally and does not transmit ACK (if the communication line is disconnected) The data itself is not transmitted to the control unit on the receiving side).
Since the master communication control unit 111 cannot receive ACK, it does not output a transmission completion interrupt. The master CPU core 109 that has not received the transmission completion interrupt recognizes that communication with the slave CPU 108 has not been performed normally.

On the other hand, the slave communication control unit 112 cannot receive the communication contents normally (or could not recognize the communication itself), and therefore does not output a reception completion interrupt to the slave CPU core 113. As a result, no WD pulse is output to the watchdog timer 105.
The watchdog timer 105 outputs a reset signal to the slave CPU 108 when no WD pulse is input within a predetermined time. By receiving the reset signal, all internal circuits including the slave communication control unit 112, the slave CPU core 113, and the slave I / O port control unit 114 in the CPU 108 are reset and stop operating (S108). .
The stopped slave CPU 108 resumes its operation after the abnormality of communication with the master CPU 107 is recovered.

FIG. 6 is a diagram illustrating control when an operation abnormality occurs in the slave CPU core 113.
Since S101 to S104 are the same as the control of FIG.

The slave communication control unit 112 outputs a reception completion interrupt to the slave CPU core 113 (S104). However, since the slave CPU core 113 is in an abnormal operation state, the slave CPU core 113 cannot issue a WD pulse output instruction to the slave I / O port control unit 114.
The watchdog timer 105 that has not received a WD pulse within a predetermined time outputs a reset signal to the slave CPU 108. By receiving the reset signal, all internal circuits including the slave communication control unit 112, the slave CPU core 113, and the slave I / O port control unit 114 in the CPU 108 are reset and stop operating (S108). .
On the other hand, since the master CPU core 109 cannot recognize the abnormality of the slave CPU 108 at this time, it instructs to output the WD pulse again after a certain interval (S101). However, since the operation of the slave CPU 108 is stopped, ACK is not returned for the transmission of the WD pulse. Thereby, the master CPU core 109 can recognize the abnormality of the slave CPU 108.

  Through the above-described control, communication between the master CPU 107 and the slave CPU 108 and normal operation of the slave CPU core 113 can be performed without using a reset signal that requires a dedicated line between the master control unit 100 and the slave control unit 101. Can be guaranteed. Even if there is any abnormality in these, the master CPU 107 can detect the abnormality and put the slave control unit 101 in a stopped state, so that protection during abnormal operation can be achieved.

Next, a second embodiment will be described.
Since the configuration of the image forming apparatus and the block configuration of the control board are the same as those in the first embodiment, description thereof is omitted.

FIG. 7 is a control block diagram according to the second embodiment.
The master control unit 100 includes a master CPU 107 that controls the entire device. The master CPU 107 includes a master communication control unit 111 that performs communication with a master CPU core 109 and a slave CPU 208 that are control units.

The slave control unit 101 has a slave CPU 208. The slave CPU 208 includes a first slave CPU core 213, a second slave CPU core 214, and a slave communication control unit 212 that communicate with the master CPU 107, and a slave I / O that controls input and output of signals to the outside. An O port control unit 215 is included.
The slave control unit 101 is provided with a watchdog timer 105 that can reset the slave CPU 208. The watchdog timer 105 has a monitoring function for resetting the slave CPU 208 when the watchdog signal from the slave CPU 208 is interrupted for a predetermined time.

FIG. 8 is a control flow between the master CPU 107 and the slave CPU 208 in the second embodiment.
Since S201 to S205 are the same as S101 to S105 of the first embodiment, description thereof will be omitted.

The first slave CPU core 213 that has received the WD pulse output instruction instructs the second slave CPU core 214 to output the WD pulse first (S206). The first output instruction of the WD pulse is a signal defined in advance between the first slave CPU core 213 and the second slave CPU core 214.
The second slave CPU core 214 that has received the first output instruction of the WD pulse issues a second output instruction of the WD pulse to the slave I / O port control unit 215 (S207).

Receiving the second output instruction of the WD pulse, the slave I / O port control unit 215 outputs the WD pulse to the watchdog timer 105 via the external output pin of the slave CPU 208 (S208).
Upon receiving the WD pulse, the watchdog timer 105 does nothing when the next WD pulse is received within a certain time (for example, 100 ms) from the previous WD pulse reception.

Since the master CPU core 109 needs to continuously transmit WD pulses at regular intervals, an instruction to transmit an output instruction of WD pulses to the slave communication control unit at intervals of a predetermined time (for example, 50 ms) or less. Repeatedly (S201).
Since the operation when there is an abnormality in the control is the same as that in the first embodiment, description thereof is omitted.

  Through the above-described control, communication between the master CPU 107 and the slave CPU 208 and normal operation of the slave CPU cores 213 and 214 can be performed without using a reset signal that requires a dedicated line between the master control unit 100 and the slave control unit 101. Operation can be guaranteed. Even if there is any abnormality in these, the master CPU 107 can recognize the abnormality and put the slave control unit 101 in a stopped state, so that safe protection during abnormal operation is possible.

  In the second embodiment, a plurality of slave CPU cores 213 and 214 are included in one slave CPU 208, but a plurality of CPUs are mounted on the slave control unit 101, and each CPU has a CPU core. The same control is possible with the shape.

(Other embodiments)
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.
Further, the present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device.
The present invention is not limited to the above-described embodiments, and various modifications (including organic combinations of the embodiments) are possible based on the spirit of the present invention, and these are excluded from the scope of the present invention. It is not a thing. That is, the present invention includes all the configurations obtained by combining the above-described embodiments and modifications thereof.

DESCRIPTION OF SYMBOLS 100 ... Master control part 101 ... Slave control part 105 ... Watchdog timer 107 ... Master CPU
108 ... Slave CPU
109 ... Master CPU core 111 ... Master communication control unit 112 ... Slave communication control unit 113 ... Slave CPU core

Claims (7)

A master control unit;
A slave controller that communicates with the master controller;
A watchdog means for inputting a watchdog signal from the slave control unit and resetting the slave control unit when the watchdog signal is not input within a predetermined time; and
The master control unit transmits an instruction to output a watchdog signal to the slave control,
When the slave control unit receives an instruction to output the watchdog signal from the master control unit, the slave control unit transmits an acknowledgment to the master control unit,
Based on the presence or absence of the confirmation response, the master control unit detects an abnormality in communication with the slave control unit,
The information processing apparatus according to claim 1, wherein the slave control unit outputs the watchdog signal to the watchdog unit in response to a watchdog signal output instruction from the master control unit.   The master control unit transmits an instruction to output a watchdog signal to the slave control within the predetermined time after transmitting an instruction to output the watchdog signal to the slave control. The information processing apparatus according to claim 1. A master control unit having a master CPU core and a master communication control unit;
A slave controller having a slave CPU core, a slave communication controller that communicates with the master communication controller, and watchdog means for monitoring the communication system;
An information processing apparatus for a communication system having
The master CPU core sends an instruction to output a watchdog signal at regular intervals to the slave CPU core,
When the slave CPU core receives an instruction to output the watchdog signal, the slave CPU core transmits a watchdog signal to the watchdog means,
The information processing apparatus according to claim 1, wherein the watchdog means resets the slave CPU core when the watchdog signal is not transmitted from the slave CPU core within a predetermined time longer than the predetermined interval. The slave CPU core includes a first slave CPU core and a second slave CPU core,
The master CPU core transmits a first instruction to output the watchdog signal at the predetermined interval to the first slave CPU core,
When the first slave CPU core receives the first instruction, the first slave CPU core transmits a second instruction to output the watchdog signal to the second slave CPU core;
When the second slave CPU core receives the second instruction, the second slave CPU core transmits a watchdog signal to the watchdog means,
If the watchdog signal is not transmitted from the second slave CPU core within a fixed time longer than the fixed interval, the watchdog means is configured to output the first slave CPU core and the second slave CPU. The information processing apparatus according to claim 3, wherein the CPU core is reset.   5. The slave CPU core according to claim 3 or 4, wherein upon receiving an instruction to output the watchdog signal transmitted by the master CPU core, the slave CPU core responds to the master CPU core with a confirmation response. Information processing device.   6. The information processing apparatus according to claim 3, wherein there are a plurality of slave control units.   The information processing apparatus according to claim 3, wherein the communication system is an internal communication system of an image forming apparatus.