JP2019180071A - Radio system, delay error detection device, and delay error detection method - Google Patents

Abstract

To provide a radio system that can compensate delay errors at an analog units of transmission units in two systems configured similarly.SOLUTION: A radio system includes a first transmission unit 500a and a second transmission unit 500b and a delay error detection unit 501. The first transmission unit 500a and the second transmission unit 500b have a similar configuration. The delay error detection unit 501 detects an analog delay amount of the first transmission unit 500a and an analog delay amount of the second transmission unit 500b, and adjusts delay amounts of digital signals after modulation at the first transmission unit 500a and/or the second transmission unit 500b so that the analog delay amount of the first transmission unit 500a is equal to the analog delay amount of the second transmission unit 500b.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a wireless system, a delay error detection device, and a delay error detection method.

  Patent Document 1 describes a wireless system having a redundant system that includes two systems of wireless devices, an active system and a standby system, and switches between the active system and the standby system without interruption during maintenance work. ing. In a wireless system having such a redundant system, there is a problem in demodulation on the receiving side if there is a difference in data transmission timing when switching between wireless devices. Therefore, in Patent Document 1, the timing of data transmission between devices is matched by aligning the frame timing, and switching between the active system and the standby system without interruption is realized.

Japanese Patent No. 5293925

  When switching between the two systems of the active system and the standby system, a delay error in the analog unit occurs along with a delay error in digital data such as frame timing. With the recent increase in data transmission speed and the increase in radio symbol rate and the increase in modulation multi-level number, the influence of delay errors in the analog section on the transmission side upon transmission switching on the reception-side demodulation section has increased. ing. However, in Patent Document 1, the delay error of the analog unit of the wireless device on the transmission side is not considered.

  In view of the above-described problems, an object of the present invention is to provide a radio system, a delay error detection apparatus, and a delay error detection method capable of compensating for a delay error in an analog unit of two transmission units configured similarly. And

  A wireless system according to an aspect of the present invention detects first and second transmission units configured in the same manner, an analog delay amount of the first transmission unit, and an analog delay amount of the second transmission unit. The modulated digital signal in the first transmitter and / or the second transmitter so that the analog delay amount of the first transmitter and the analog delay amount of the second transmitter are equal. A delay error detecting unit for adjusting the delay amount of the delay.

  A delay error detection apparatus according to an aspect of the present invention includes a first switch that selectively inputs high-frequency signals from a plurality of transmission units, and a first switch that selectively inputs local oscillation signals from the plurality of transmission units. 2 switch, a mixer that performs frequency conversion by multiplying the high-frequency signal input through the first switch and the local oscillation signal input through the second switch, and an output signal of the mixer AD converter that converts analog signals into digital signals, a third switch that selectively inputs the modulated digital signals from the plurality of transmission units, the digital signal output from the AD converter, and the third A delay detection unit that detects a delay error by comparing the modulated digital signal input through the switch.

  A delay error detection method for a radio system according to an aspect of the present invention is a delay error detection method for a radio system including a first transmission unit and a second transmission unit configured in the same manner. A step of detecting an analog delay amount of one of the second transmission units, a step of detecting an analog delay amount of the other of the first and second transmission units, and an analog of the first transmission unit Adjusting the delay so that the delay amount is equal to the analog delay amount of the second transmitter.

  According to the present invention, it is possible to adjust the delay error of the analog unit in the first and second transmission units configured similarly. As a result, even when the first transmission unit and the second transmission unit are switched without interruption, it is possible to continue sending signals at the same timing, and to avoid affecting the demodulation on the reception side.

It is a block diagram which shows the structure of the radio | wireless system which concerns on the 1st Embodiment of this invention. It is a flowchart which shows a process when switching two transmission parts in the radio | wireless system which concerns on the 1st Embodiment of this invention. It is explanatory drawing of the delay adjustment in the radio | wireless system which concerns on the 1st Embodiment of this invention. It is explanatory drawing of the delay adjustment in the radio | wireless system which concerns on the 1st Embodiment of this invention. It is explanatory drawing of the delay adjustment in the radio | wireless system which concerns on the 1st Embodiment of this invention. It is explanatory drawing of the delay adjustment in the radio | wireless system which concerns on the 1st Embodiment of this invention. It is a schematic block diagram which shows the basic composition of the radio | wireless system by this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a wireless system 1 according to the first embodiment of the present invention.

  As shown in FIG. 1, the wireless system 1 according to the first embodiment of the present invention includes two transmission units 100 a and 100 b and a delay error detection unit 200. The two transmitters 100a and 100b are configured similarly.

  The transmission units 100a and 100b include a framing unit 111a and 111b, a mapping unit 112a and 112b, a digital modulator 113a and 113b, a delay adjuster 114a and 114b, a DA converter (Digital-to-Analog Converter) 115a, 115b, buffers 116a and 116b, mixers 117a and 117b, local oscillators 118a and 118b, and power amplifiers 119a and 119b.

  Data (DATA) and a clock (CLK) are input to the framing units 111a and 111b. The framing units 111a and 111b reshape the input data into a predetermined frame format. Timing signals are exchanged between the framing unit 111a and the framing unit 111b. The mapping units 112a and 112b map the transmission data on the IQ plane upward. The digital modulators 113a and 113b digitally modulate the transmission data using the transmission data mapped on the IQ plane. The delay adjusters 114a and 114b perform delay adjustment of the analog units of the two transmission units 100a and 100b. The DA converters 115a and 115b convert transmission data from digital signals to analog signals. The mixers 117a and 117b multiply the transmission signals from the DA converters 115a and 115b and the local oscillation signals from the local oscillators 118a and 118b, and convert the frequency of the transmission signal to a desired frequency. The power amplifiers 119a and 119b amplify the transmission signal and output it as a high frequency signal. In the transmission units 100a and 100b, the stage subsequent to the DA converters 115a and 115b is an analog unit.

  Transmission signals from the transmission units 100 a and 100 b are supplied to the switch 121. The switch 121 is a switch that switches between the two transmission units 100a and 100b. When the switch 121 is set to the terminal 121a side, a transmission signal from the transmission unit 100a side is output from the antenna 122. When the switch 121 is set to the terminal 121b side, a transmission signal from the transmission unit 100b side is output from the antenna 122.

  In the present embodiment, a delay error detection unit 200 is further provided in such a redundant system having two transmission units 100a and 100b. The delay error detection unit 200 detects the analog delay amount of the transmission unit 100a and the analog delay amount of the transmission unit 100b, so that the analog delay amount of the transmission unit 100a and the analog delay amount of the transmission unit 100b are equal. The delay amount of the modulated digital signal in 100a and / or the transmission unit 100b is adjusted.

  The delay error detection unit 200 includes a switch (first switch) 211, a switch (second switch) 212, a switch (third switch) 213, a mixer 214, a buffer 215, an AD converter (Analog-to- Digital Converter) 216 and a delay detection unit 217.

  The switch 211 selectively inputs high-frequency signals from the transmission units 100a and 100b. The switch 212 selectively inputs local oscillation signals from the transmission units 100a and 100b. The switch 213 selectively inputs the modulated digital signal from the transmission units 100a and 100b.

  The mixer 214 performs frequency conversion by multiplying the high-frequency signal from the transmission unit 100a or 100b and the local oscillation signal from the transmission unit 100a or 100b. The AD converter 216 converts the output signal of the mixer 214 from an analog signal to a digital signal. The delay detection unit 217 compares the phase of the digital signal output from the AD converter 216 with the phase of the modulated digital signal from the transmission unit 100a or 100b, and detects a delay error.

  Next, processing when the two transmission units 100a and 100b are switched without interruption in the wireless system 1 according to the first embodiment of the present invention will be described. FIG. 2 is a flowchart showing a process when switching between the two transmission units 100a and 100b in the wireless system 1 according to the first embodiment of the present invention. Here, it is assumed that the transmission unit 100a is switched to the transmission unit 100b.

  (Step S1) First, each switch (switch 211, switch 212, switch 213) of the delay error detection unit 200 is set on the transmission unit 100a side, and the analog delay amount of the transmission unit 100a is detected.

  That is, the switch 211 is set on the terminal 211a side, the switch 212 is set on the terminal 212a side, and the switch 213 is set on the terminal 213a side. When the switch 211 is set on the terminal 211a side, a high frequency signal output from the power amplifier 119a via the buffer 120a is input to the mixer 214 via the switch 211. When the switch 212 is set on the terminal 212 a side, a local oscillation signal from the local oscillator 118 a is input to the mixer 214 via the switch 212. When the switch 213 is set to the terminal 213a side, a digital signal from the digital modulator 113a is input to the delay detection unit 217 via the switch 213.

  The mixer 214 multiplies the local oscillation signal of the local oscillator 118a by the high frequency signal output from the power amplifier 119a. The output signal of the mixer 214 is a signal having a frequency corresponding to the input signal of the mixer 117a in the transmission unit 100a. The output signal of the mixer 214 is sent to the AD converter 216 via the buffer 215 and converted into a digital signal by the AD converter 216. The output signal of the AD converter 216 is a signal corresponding to the output signal of the digital modulator 113a in the transmission unit 100a.

  The delay detection unit 217 detects the phase error by comparing the phase of the output signal of the AD converter 216 with the phase of the output signal of the digital modulator 113a. The phase error detected by the delay detector 217 includes an analog delay amount δ1 of the transmitter 100a (delay amount of the delay adjuster 114a, DA converter 115a, buffer 116a, mixer 117a, and power amplifier 119a) and a delay error detector. This is equivalent to the sum of 200 analog delay amounts δa (the delay amounts of the mixer 214, the buffer 215, and the AD converter 216). Although the delay adjuster 114a is a digital circuit, it is provided for adjusting the analog delay amount, and the delay amount of the delay adjuster 114a is included in the analog delay amount of the transmission unit 100a. In this way, the analog delay amount of the transmission unit 100a is detected.

  (Step S2) Next, each switch (switch 211, switch 212, switch 213) of the delay error detection unit 200 is set on the transmission unit 100b side, and the analog delay amount of the transmission unit 100b is detected.

  That is, the switch 211 is set on the terminal 211b side, the switch 212 is set on the terminal 212b side, and the switch 213 is set on the terminal 213b side. When the switch 211 is set to the terminal 211b side, a high frequency signal output from the power amplifier 119b via the buffer 120b is input to the mixer 214 via the switch 211. When the switch 212 is set to the terminal 212b side, the local oscillation signal from the local oscillator 118b is input to the mixer 214 via the switch 212. When the switch 213 is set to the terminal 213b side, the digital signal from the digital modulator 113b is input to the delay detection unit 217 via the switch 213.

  The mixer 214 multiplies the local oscillation signal of the local oscillator 118b by the high frequency signal output from the power amplifier 119b. The output signal of the mixer 214 is a signal having a frequency corresponding to the input signal of the mixer 117b in the transmission unit 100b. The output signal of the mixer 214 is sent to the AD converter 216 via the buffer 215 and converted into a digital signal by the AD converter 216. The output signal of the AD converter 216 is a signal corresponding to the output signal of the digital modulator 113b in the transmission unit 100b.

  The delay detector 217 detects the phase error by comparing the phase of the output signal of the AD converter 216 with the phase of the output signal of the digital modulator 113b. The phase error detected by the delay detection unit 217 includes an analog delay amount δ2 of the transmission unit 100b (a delay amount of the delay adjustment unit 114b, DA converter 115b, buffer 116b, mixer 117b, and power amplifier 119b) and a delay error detection unit 200. Corresponding to the analog delay amount δa (the delay amount of the mixer 214, the buffer 215, and the AD converter 216). Although the delay adjuster 114b is a digital circuit, it is provided to adjust the analog delay amount, and the delay amount of the delay adjuster 114b is included in the analog delay amount of the transmission unit 100b. In this way, the analog delay amount of the transmission unit 100b is detected.

  (Step S3) The delay error detection unit 200 performs delay adjustment so that the analog delay amount δ1 of the transmission unit 100a is equal to the analog delay amount δ2 of the transmission unit 100b.

  As described above, in step S1, the phase of the output signal of the AD converter 216 and the phase of the output signal of the digital modulator 113a are compared, and the analog delay amount δ1 of the transmission unit 100a is detected. In step S2, the phase of the output signal of the AD converter 216 and the phase of the output signal of the digital modulator 113b are compared, and the analog delay amount δ2 of the transmission unit 100b is detected. The delay detection unit 217 obtains a delay error (δ1-δ2) between the analog delay amount δ1 of the transmission unit 100a and the analog delay amount δ2 of the transmission unit 100b, and the delay error (δ1-δ2) becomes zero. The delay amount of the delay adjuster 114a of the transmitter 100a and / or the delay adjuster 114b of the transmitter 100b is adjusted. Thereby, the analog delay amount δ1 of the transmission unit 100a and the analog delay amount δ2 of the transmission unit 100b can be made equal. The phase comparison may be performed based on the correlation between the phase of the output signal of the AD converter 216 and the phase of the output signal of the digital modulator 113a (or the digital modulator 113b).

  The delay error obtained by the delay detection unit 217 in step S1 is a delay amount corresponding to the sum of the analog delay amount δ1 of the transmission unit 100a and the analog delay amount δa of the delay error detection unit 200. The delay error obtained by the delay detection unit 217 in step S2 is a delay amount corresponding to the sum of the analog delay amount δ2 of the transmission unit 100b and the analog delay amount δa of the delay error detection unit 200. When the difference between the two delay errors is obtained, the analog delay amount δa of the delay error detector 200 is canceled. Therefore, if the delay error obtained in step S1 and the delay error obtained in step S2 are subtracted, the delay error (δ1-δ2) between the analog delay amount δ1 of the transmission unit 100a and the analog delay amount δ2 of the transmission unit 100b. Will be required.

  (Step S4) The switch 121 for switching the transmission unit is switched from the terminal 121a side to the terminal 121b side.

  While the transmission unit 100a is used for operation, the switch 121 is set to the terminal 121a side. When the switch 121 is switched to the terminal 121b side, the output signal of the power amplifier 119b of the transmission unit 100b is transmitted from the antenna 122 via the switch 121. Thereby, the transmission unit used for operation is switched from the transmission unit 100a to the transmission unit 100b.

  Here, in the present embodiment, timing signals are exchanged between the framing unit 111a of the transmission unit 100a and the framing unit 111b of the transmission unit 100b. As a result, the transmission unit 100a and the transmission unit 100b adjust the delay error of the digital data before modulation. Further, as described above, by providing the delay error detection unit 200, the delay error of the analog unit is adjusted by the transmission unit 100a and the transmission unit 100b. For this reason, even if the transmission unit used for operation is switched from the transmission unit 100a to the transmission unit 100b without interruption, it is possible to continue sending signals at the same timing and to avoid affecting the demodulation on the reception side. .

  3 to 6 are explanatory diagrams of delay adjustment in the wireless system 1 according to the first embodiment of the present invention.

  In the framing units 111a and 111b of the transmission unit 100a, the input data is shaped into a predetermined frame and output. Here, as shown in FIG. 3, there is a delay between the digital data output from the transmitter 100a (FIG. 3A) and the digital data output from the transmitter 100b (FIG. 3B). It is assumed that an error τ1 has occurred. That is, as shown in FIG. 3A, frames A0, A1, A2,... Are output from framing section 111a of transmitting section 100a. On the other hand, the frames A0, A1, A2,... From the framing unit 111b of the transmission unit 100b are delayed by the delay error τ1.

  As described above, timing signals are exchanged between the framing unit 111a of the transmission unit 100a and the framing unit 111b of the transmission unit 100b. Thereby, as shown in FIG. 4, between the digital data (FIG. 4 (A)) output from the framing unit 111a and the digital data (FIG. 4 (B)) output from the framing unit 111b. The delay error τ1 is eliminated, and the timing of the digital data can be matched.

  However, as shown in FIG. 4, even if the delay error between the digital data output from the framing unit 111a and the digital data output from the framing unit 111b is eliminated, these digital data are modulated. In the case of transmission, an analog unit delay error occurs between the transmission unit 100a and the transmission unit 100b. In FIG. 5, a delay error τ <b> 2 occurs between the transmission signal of the transmission unit 100 a (FIG. 5A) and the transmission signal of the transmission unit 100 b (FIG. 5B).

  In the present embodiment, the delay adjuster 114a and the delay adjuster 114a are configured so that the delay error (δ1-δ2) between the analog delay amount δ1 of the transmission unit 100a and the analog delay amount δ2 of the transmission unit 100b becomes zero. The delay amount of 114b is adjusted. Thereby, as shown in FIG. 6, the analog part between the high frequency signal (FIG. 6 (A)) output from the transmission part 100a and the high frequency signal (FIG. 6 (B)) output from the transmission part 100b. The delay error τ2 is eliminated, and the timing of the analog portion can be matched.

  The delay error between the analog unit of the transmission unit 100a and the analog unit of the transmission unit 100b is adjusted in the following case.

(1) When switching between the transmission unit 100a and the transmission unit 100b, adjustment is performed so that the delay error between the analog delay amount of the transmission unit 100a and the analog delay amount of the transmission unit 100b becomes zero. Switching between the transmission unit 100a and the transmission unit 100b is performed without instantaneous interruption.

(2) Before shipping, delay adjustment is performed using the delay error detection unit 200 so that there is no delay error between the analog unit of the transmission unit 100a and the analog unit of the transmission unit 100b. Once the delay error is adjusted, the delay error hardly changes thereafter. For this reason, no adjustment is required after shipment.

(3) The delay error is adjusted according to a predetermined condition. That is, when the wireless system is used in an environment where there is a temperature change, the characteristics of the analog unit may change according to the temperature change. Therefore, a temperature sensor is provided in the delay error detection unit 200, and the delay error is adjusted when the temperature change becomes a certain level or more. Alternatively, when considering aged deterioration or the like, adjustment is performed so that a delay error is eliminated when it is detected that a certain time has elapsed.

  The delay error detection unit 200 may be configured as a single “delay error detection device”.

  FIG. 7 is a schematic block diagram showing a basic configuration of a radio system according to the present invention. That is, the wireless system according to the present invention includes first and second transmission units 500 a and 500 b and a delay error detection unit 501. The first and second transmission units 500a and 500b are configured similarly. The delay error detection unit 501 detects the analog delay amount of the first transmission unit 500a and the analog delay amount of the second transmission unit 500b, and the analog delay amount of the first transmission unit 500a and the second transmission unit 500b. The delay amount of the modulated digital signal in the first transmission unit 500a and / or the second transmission unit 500b is adjusted so that the analog delay amount becomes equal.

  You may make it implement | achieve all or one part of the radio | wireless systems 1 in embodiment mentioned above with a computer. In that case, a program for realizing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be read into a computer system and executed. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” dynamically holds a program for a short time like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. In this case, a volatile memory inside a computer system serving as a server or a client in that case may be included and a program held for a certain period of time. Further, the program may be a program for realizing a part of the above-described functions, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system. You may implement | achieve using programmable logic devices, such as FPGA.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

100a, 100b: transmission unit, 111a, 111b: framing unit, 113a, 113b: digital modulator, 114a, 114b: delay adjuster, 115a, 115b: DA converter, 117a, 117b: mixer, 118a, 118b: local oscillator 119a, 119b: power amplifier, 200: delay error detector, 211, 212, 213: switch, 214: mixer, 216: DA converter, 217: delay detector

Claims (4)

First and second transmitters configured similarly;
The analog delay amount of the first transmitter and the analog delay amount of the second transmitter are detected, and the analog delay amount of the first transmitter and the analog delay amount of the second transmitter are equal. As described above, a wireless system comprising: a delay error detection unit that adjusts a delay amount of a modulated digital signal in the first transmission unit and / or the second transmission unit. The delay error detector is
A first switch for selectively inputting a high-frequency signal from the first and second transmission units;
A second switch for selectively inputting a local oscillation signal from the first and second transmission units;
A mixer that multiplies the high-frequency signal input through the first switch and the local oscillation signal input through the second switch to perform frequency conversion;
An AD converter for converting the output signal of the mixer from an analog signal to a digital signal;
A third switch for selectively inputting a modulated digital signal from the first and second transmitters;
The wireless system according to claim 1, further comprising: a delay detection unit that detects a delay error by comparing a digital signal output from the AD converter and a modulated digital signal input via the third switch. . A first switch for selectively inputting high-frequency signals from a plurality of transmission units;
A second switch for selectively inputting local oscillation signals from the plurality of transmission units;
A mixer that multiplies the high-frequency signal input through the first switch and the local oscillation signal input through the second switch to perform frequency conversion;
An AD converter for converting the output signal of the mixer from an analog signal to a digital signal;
A third switch for selectively inputting modulated digital signals from the plurality of transmitters;
A delay error detection device comprising: a delay detection unit that detects a delay error by comparing a digital signal output from the AD converter and a modulated digital signal input via the third switch. A delay error detection method for a wireless system including a first transmission unit and a second transmission unit configured similarly,
Detecting an analog delay amount of one of the first and second transmission units;
Detecting the other analog delay amount of the first and second transmitters;
A delay error detection method for a wireless system, comprising: adjusting a delay so that an analog delay amount of the first transmission unit is equal to an analog delay amount of the second transmission unit.

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