JP2019161009A - Memory device - Google Patents

Abstract

To provide a memory device capable of restraining malfunction of memory cells.SOLUTION: A memory device includes multiple word lines laminated in the first direction, a first insulator film provided between the word lines adjoining in the first direction, out of the multiple word lines, selector gates juxtaposed to the multiple word lines in the first direction, a first intermediate electrode provided between the multiple word lines and the selector gate, a second insulator film provided between the first intermediate electrode and the selector gate, a semiconductor pillar extending in the first direction while penetrating the multiple word lines, the first insulator film, the first intermediate electrode, the second insulator film and the selector gate, and charge holding films located, respectively, between the multiple word lines and the semiconductor pillar. The second insulator film has a second film thickness in the first direction thicker than the first film thickness in the first direction of the first insulator film.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a storage device.

  Development of a storage device including memory cells arranged three-dimensionally is in progress. For example, in a NAND nonvolatile memory device, a plurality of word lines and select gates are stacked via an interlayer insulating film, and a semiconductor pillar is provided that penetrates them in the stacking direction. The memory cell is arranged at a portion where the semiconductor pillar intersects with the plurality of word lines. In order to increase the storage capacity of such a semiconductor device, it is effective to reduce the number of word lines by increasing the number of word lines, select gates, and interlayer insulating films. However, the thinning of the word line and the select gate increases their parasitic resistance, and the thinning of the interlayer insulating film increases the parasitic capacitance. For this reason, a malfunction of the memory cell may occur.

JP 2007-266143 A

  Embodiments provide a storage device capable of suppressing malfunction of a memory cell.

  The memory device according to the embodiment includes a plurality of word lines stacked in a first direction, a first insulating film provided between adjacent word lines in the first direction among the plurality of word lines, A selection gate arranged in a plurality of word lines in a first direction; a first intermediate electrode provided between the plurality of word lines and the selection gate; and between the first intermediate electrode and the selection gate. A second insulating film, a semiconductor pillar extending in the first direction through the plurality of word lines, the first insulating film, the first intermediate electrode, the second insulating film, and the selection gate; A charge retention film positioned between each of the plurality of word lines and the semiconductor pillar; The second insulating film has a second film thickness in the first direction that is thicker than a first film thickness in the first direction of the first insulating film.

1 is a perspective view schematically showing a storage device according to an embodiment. It is a fragmentary sectional view showing typically the memory device concerning an embodiment. It is a block diagram which shows the structure of the memory | storage device which concerns on embodiment. It is a time chart which shows operation | movement of the memory | storage device which concerns on embodiment. It is a schematic diagram which shows operation | movement of the memory | storage device which concerns on a comparative example. It is a schematic cross section showing a manufacturing process of the memory device according to the embodiment. FIG. 7 is a schematic cross-sectional view showing a manufacturing process following FIG. 6. FIG. 8 is a schematic cross-sectional view showing the manufacturing process following FIG. 7. FIG. 9 is a schematic cross-sectional view showing the manufacturing process following FIG. 8.

  Hereinafter, embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, detailed description thereof will be omitted as appropriate, and different parts will be described. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.

  Furthermore, the arrangement and configuration of each part will be described using the X-axis, Y-axis, and Z-axis shown in each drawing. The X axis, the Y axis, and the Z axis are orthogonal to each other and represent the X direction, the Y direction, and the Z direction, respectively. Further, the Z direction may be described as the upper side and the opposite direction as the lower side.

  FIG. 1 is a perspective view schematically showing a storage device 1 according to the embodiment. The storage device 1 is, for example, a NAND type nonvolatile storage device, and includes a memory cell array MCA. In FIG. 1, a part of the insulating film is omitted to show the configuration of the memory cell array MCA.

  Memory cell array MCA includes a conductive layer CL, a plurality of electrode layers, and interlayer insulating films 13, 15 and 17. The conductive layer CL is, for example, a P-type well provided on a silicon substrate (not shown) or a semiconductor layer provided on the silicon substrate via an interlayer insulating film. The plurality of electrode layers are stacked on the conductive layer CL and include, for example, a selection gate SGS, a word line WL, and a selection gate SGD.

  The plurality of electrode layers further include dummy word lines WLS and WLD. The dummy word line WLS is provided between the selection gate SGS and the word line WL adjacent thereto. The dummy word line WLD is provided between the selection gate SGD and the word line WL adjacent thereto.

  As shown in FIG. 1, the selection gate SGD is divided into a plurality of selection gates SGDA and a plurality of selection gates SGDB by the isolation trench SHL. The selection gate SGDA and the selection gate SGDB are respectively stacked on the word line WL.

  The interlayer insulating film 13 is provided between the conductive layer CL and the selection gate SGS. The interlayer insulating film 15 is provided between two electrode layers adjacent in the Z direction among the plurality of electrode layers. The interlayer insulating film 17 is provided on the selection gate SGD.

  The memory cell array MCA further includes a plurality of semiconductor pillars SP. The semiconductor pillar SP extends in the Z direction through the word line WL and the select gate SGD (see FIG. 2).

  Memory device 1 further includes a bit line BL and a source line SL provided above memory cell array MCA. The semiconductor pillar SP is electrically connected to the bit line BL via connection plugs CH and V1, respectively. For example, the source line SL is electrically connected to the conductive layer CL via the connection conductor LI. The connection conductor LI is, for example, a plate-like conductor provided on the side of the memory cell array MCA.

  FIG. 2 is a partial cross-sectional view schematically showing the storage device 1 according to the embodiment. FIG. 2 is a schematic diagram showing the configuration of the memory hole MH including the semiconductor pillar and the electrode layer.

  As shown in FIG. 2, the semiconductor pillar SP is provided inside a memory hole MH (see FIG. 6B) extending in the Z direction through the word line WL and the selection gate SGD. The semiconductor pillar SP includes a semiconductor film SF and an insulating core IC. The insulating core IC is, for example, silicon oxide, and extends in the Z direction inside the memory hole MH. The semiconductor film SF is, for example, a polysilicon film, and is provided so as to cover the insulating core.

  The semiconductor pillar SP is connected to the bit line BL via connection plugs CH and V1. Specifically, the connection plug CH is connected to the semiconductor film SF at the upper end of the semiconductor pillar SP. On the other hand, the semiconductor layer SC is provided between the lower end of the semiconductor pillar SP and the conductive layer CL. The semiconductor layer SC is provided so as to penetrate the selection gate SGS. The semiconductor layer SC is connected to the conductive layer CL at the lower end and connected to the semiconductor pillar SP at the upper end. An insulating film 25 is provided between the semiconductor layer SC and the selection gate SGS.

  Further, a memory film MF is provided inside the memory hole MH. The memory film MF is provided between the semiconductor pillar SP and the inner wall of the memory hole MH. The memory film MF includes, for example, a block insulating film FL1, a charge holding film FL2, and a tunnel insulating film FL3. The block insulating film FL1, the charge holding film FL2, and the tunnel insulating film FL3 are sequentially stacked on the inner wall of the memory hole MH.

  As shown in FIG. 2, dummy word lines WLD0 and WLD1 are arranged between the selection gate SGD and the uppermost layer of the word line WL. The dummy word line WLD0 is arranged between the selection gate SGD and the dummy word line WLD1.

In the memory device 1 according to the present embodiment, the interlayer insulating film 15M is provided between the selection gate SGD and the dummy word line WLD0. The interlayer insulating film 15M includes, for example, the same material as the interlayer insulating film 15 provided between adjacent word lines WL in the Z direction. The interlayer insulating film 15M is, for example, a silicon oxide film. Further, an interlayer insulating film 15M is formed to have a thickness T ₁ of the thick Z-direction than the Z direction thickness T ₂ of the interlayer insulating film 15.

  FIG. 3 is a block diagram illustrating the configuration of the storage device according to the embodiment. For example, each word line WL is connected to the drive circuit WD1. Dummy word lines WLD0 and WLD1 are connected to a common drive circuit WD2. Select gates SGD and SGS are connected to drive circuits GD1 and GD2, respectively. The semiconductor pillar SP is connected to the sense amplifier SA via the bit line BL.

  As shown in FIG. 3, the memory cell MC is arranged at a portion where the semiconductor pillar SP and the word line WL intersect. The memory cell MC includes a part of the memory film MF located between the semiconductor pillar SP and the word line WL as a charge holding unit.

  A selection transistor STD is provided at a portion where the semiconductor pillar SP and the selection gate SGD intersect. The selection transistor STD includes, for example, a part of the memory film MF located between the semiconductor pillar SP and the selection gate SGD as a gate insulating film. A selection transistor STS is provided at a portion where the selection gate SGS and the semiconductor layer SC intersect. The selection transistor STS includes an insulating film 25 located between the semiconductor layer SC and the selection gate SGS as a gate insulating film (see FIG. 2).

  4A and 4B are time charts showing the operation of the storage device 1 according to the embodiment. 4A and 4B show biases supplied from the drive circuits WD1, WD2, and GD1 to the respective electrode layers when data is written to the memory cell MC.

  The selection gate SGD_SEL illustrated in FIG. 4A is, for example, SGDA illustrated in FIG. 1, and the selection gate SGD_USEL illustrated in FIG. 4B is, for example, SGDB illustrated in FIG. In the following description, the selection gate SGDA will be described as a selected selection gate SGD_SEL, and the selection gate SGDB will be described as an unselected selection gate SGD_USEL.

FIGS. 4A and 4B show selection gates SGD_SEL and SGD_USEL, and biases V _SGD , V _WLD and V _WL supplied to the word lines WL and dummy word lines WLD located therebelow during data writing. The same bias V _WLD is supplied to the dummy word lines WLD0 and WLD1. In the following description, dummy word lines WLD0 and WLD1 are collectively expressed as dummy word lines WLD. Further, in FIG. 4 (a), the also shows bias _{V BL} supplied to the unselected bit lines BL_USEL.

As shown in FIGS. 4 (a) and (b), at time _t 0 ~t _1, the selection gate SGD_SEL and SGD_USEL, bias _{V PC} is supplied. As a result, the selection transistor STD is turned on. On the other hand, the bias V _DD is supplied to the bit line BL_USEL. The bias of the selected bit line BL (not shown) is 0V. At this time, the selection transistor STS on the source side is in an OFF state. As a result, the semiconductor pillar SP connected to the unselected bit line BL_USEL is charged up to the potential V _DD .

  Here, the selected bit line BL means the bit line BL connected to the semiconductor pillar SP including the memory cell MC to be written, and the unselected bit line BL_USEL does not include the memory cell MC to be written. It means the bit line BL connected to the semiconductor pillar SP. The same applies to other elements.

At time _{t 1,} the supply of the bias _{V PC} to select gate SGD_SEL and SGD_USEL is stopped. For this reason, the potential V _SGD of the selection gates SGD_SEL and SGD_USEL decreases with an attenuation factor determined by the time constant CR caused by the parasitic resistance and parasitic capacitance.

As shown in FIG. 4 (b), the potential _{V SGD} of the select gate SGD_SEL and SGD_USEL is reduced quickly in the near end NS closer to the drive circuits GD1, for example, it becomes 0V at time _{t 2.} On the other hand, at the far end FS distant from the drive circuit GD1, the time constant CR is increased, so that the decrease in the potential _VSGD is delayed. For example, there may be a case where the voltage does not drop to 0V within the data write cycle.

Subsequently, as illustrated in FIG. 4A, the bias V _SON is supplied to the selection gate SGD_SEL at time t ₂ . At this time, the potential of the selected bit line BL is 0 V, and the selection transistor STD provided in the semiconductor pillar SP including the memory cell MC to be written is turned on. On the other hand, the bias _VDD is supplied to the bit line BL_USEL. For this reason, the select transistor STD provided in the semiconductor pillar SP not including the memory cell MC to be written is turned off.

In addition, the selection gate SGD_USEL illustrated in FIG. 4B is not supplied with a bias from the driving circuit GD1, and the potential of the bit line BL_USEL is V _DD , so that the selection transistor STD including the selection gate SGD_USEL is OFF. It becomes a state. As a result, in the semiconductor pillar SP_USEL other than the semiconductor pillar SP_SEL including the write target memory cell MC, the selection transistors STS and STD are turned off, and the semiconductor pillar SP_USEL becomes a floating potential.

On the other hand, the word line WL and the dummy word line WLD, the bias _{V PASS} is applied at time _{t 2.} As a result, the channel of the memory cell MC is turned on. Further, the bias V _PG is supplied to the selected word line WL_SEL at time t ₃ . Thereby, data can be written into the memory cell MC to be written.

On the other hand, in the semiconductor pillar SP_USEL not including the write target memory cell MC, and the potential is boosted in accordance with the bias to be supplied to each word line WL, and for example, a semiconductor pillar SP_USEL, word lines supplying a bias _{V PG} The potential difference with WL_SEL is reduced. Thereby, erroneous writing to the non-selected memory cell MC can be prevented.

The write voltage _{V PG} is not supplied to the dummy word line WLD0 and WLD1. That is, the drive circuit WD1 that supplies a bias to each word line WL has a configuration capable of supplying a higher bias than the drive circuit WD2 that supplies a bias to the dummy word lines WLD0 and WLD1 (see FIG. 3). The bias V _PG exceeds, for example, 10V. On the other hand, the bias V _PASS supplied to the dummy word line WLD is, for example, several volts.

  FIGS. 5A and 5B are schematic diagrams illustrating the operation of the storage device 2 according to the comparative example. FIG. 5A is a schematic cross-sectional view showing the structure of the storage device 2. FIG. 5B is a time chart showing the operation of the storage device 2.

  As shown in FIG. 5A, in the memory device 2, an interlayer insulating film 15 is provided between the selection gate SGD and the dummy word line WLD0. That is, the thickness in the Z direction of the insulating film provided between the select gate SGD and the dummy word line WLD0 has substantially the same Z direction thickness as the interlayer insulating film 15 provided between the word lines WL.

As shown in FIG. 5B, at the time of data writing to the memory cell MC, the selection gate SGD_USEL is supplied with the bias V _{PC and} stopped at time t ₁ . Thereafter, the potential of the selection gate SGD_USEL gradually decreases.

Subsequently, at time _{t 2,} the bias _{V PASS} is applied to the word line WL and the dummy word line WLD. At this time, by coupling through the parasitic capacitance Cp between the selection gate SGD_USEL and the dummy word line WLD, is induced induced potential _{V CP} is the selection gate SGD_USEL, the potential of the selection gate SGD_USEL rises.

For example, the far-end FS away from the driving circuit GD1, the potential of the select gate SGD_USEL is not fully down from _{V PC,} induced potential VCP is to be superimposed thereon. For this reason, part of the selection transistor STD is turned on, and the potential boost in the semiconductor pillar SP may be suppressed. As a result, a malfunction may occur in which data is written in the non-selected memory cell MC.

  On the other hand, in the memory device 1 according to the present embodiment, the interlayer insulating film 15M is provided between the selection gate SGD and the dummy word line WLD0. The interlayer insulating film 15M is formed thicker in the Z direction than the interlayer insulating film 15 provided between the word lines WL. For this reason, the parasitic capacitance Cp between the selection gate SGD and the dummy word line WLD0 is reduced, and coupling is suppressed. Thereby, erroneous writing to the memory cell MC can be prevented.

  Next, with reference to FIGS. 6A to 9B, a method for manufacturing the storage device 1 according to the embodiment will be described. FIG. 6A to FIG. 9B are schematic cross-sectional views showing the manufacturing process of the storage device 1.

As shown in FIG. 6A, interlayer insulating films 13, 15, 17 and a sacrificial film 23 are stacked on the conductive layer CL. The sacrificial film 23 is provided between two interlayer insulating films adjacent to each other in the Z direction among the interlayer insulating films 13, 15, and 17. The interlayer insulating film 13 is provided between the conductive layer CL and the sacrificial film 23 located at the lowest layer among the plurality of sacrificial films 23. The interlayer insulating film 17 is provided on the sacrificial film 23 positioned at the uppermost layer among the plurality of sacrificial films 23.
The interlayer insulating films 13, 15 and 17 are, for example, silicon oxide films. The sacrificial film 23 is, for example, a silicon nitride film.

For example, the interlayer insulating film 15 includes an interlayer insulating film 15M. Interlayer insulating film 15M, the thickness T ₁ of the Z direction is formed to be thicker than the Z direction thickness T ₂ of the other interlayer insulating film 15. The thickness _{T 1} is, for example, 1.5 to 3.0 times the thickness _{T 2.}

  As shown in FIG. 6B, a memory hole MH having a depth from the upper surface of the interlayer insulating film 17 to the conductive layer CL is formed. For example, the memory hole MH is formed to have a circular, elliptical, or polygonal opening on the upper surface of the interlayer insulating film 17.

  Subsequently, the semiconductor layer SC is formed at the bottom of the memory hole MH. For example, the conductive layer CL is a silicon layer, the semiconductor layer SC is a polysilicon layer using, for example, CVD (Chemical Vapor Deposition), and the interlayer insulating films 13, 15 exposed on the sidewalls of the memory hole MH, 17 is not deposited on the sacrificial film 23 and the sacrificial film 23, but is selectively deposited on the conductive layer CL. Further, the semiconductor layer SC is formed, for example, so that the upper surface TSS is located at a level between the lowermost sacrificial film 23 and the sacrificial film 23 located thereon.

  As shown in FIG. 7A, the memory film MF and the semiconductor film SF1 are formed inside the memory hole MH. The memory film MF has, for example, a stacked structure shown in FIG. The memory film MF is formed in contact with the upper surface of the semiconductor layer SC at the bottom surface of the memory hole MH. The semiconductor film SF1 is, for example, an amorphous silicon film. The memory film MF and the semiconductor film SF1 are formed to a thickness that leaves a space in the memory hole MH.

  As shown in FIG. 7B, a semiconductor film SF2 that covers the inner surface of the memory hole MH is formed. Specifically, a part of the semiconductor film SF1 and a part of the memory film MF stacked on the bottom surface of the memory hole MH are selectively removed by, for example, anisotropic RIE (Reactive Ion Etching). In this process, the semiconductor film SF1 protects the memory film MF remaining on the inner wall of the memory hole MH.

  Subsequently, a semiconductor film SF2 that covers the inner surface of the memory hole MH is formed. The semiconductor film SF2 is an amorphous silicon film, for example, and is formed to a thickness that leaves a space inside the memory hole MH. Further, the semiconductor films SF1 and SF2 are crystallized by heat treatment to form the semiconductor film SF. The semiconductor film SF is, for example, a polysilicon film.

  As shown in FIG. 8A, an insulator is embedded in the memory hole MH to form an insulating core IC. The insulating core IC is, for example, silicon oxide formed by CVD. Subsequently, a slit ST is formed, and the interlayer insulating films 13, 15, 17 and the sacrificial film 23 are divided. The slit ST has, for example, a depth from the upper surface of the interlayer insulating film 17 to the conductive layer CL, and extends in the Y direction.

  As shown in FIG. 8B, the sacrificial film 23 is selectively removed through the slits ST. The sacrificial film 23 is removed, for example, by wet etching, leaving the interlayer insulating films 13, 15 and 17. At this time, the memory film MF, the semiconductor film SF, and the insulating core IC formed inside the memory hole MH support the interlayer insulating films 13, 15 and 17, and hold the space 23S after the sacrifice film 23 is removed. To do.

  As shown in FIG. 9A, an insulating film 25 is formed on the surface of the semiconductor layer SC through the slit ST and the space 23S. The insulating film 25 is, for example, a silicon oxide film formed by thermally oxidizing the semiconductor layer SC.

  Subsequently, a barrier metal layer BML and a core metal layer MLC are formed in the space 23S. The barrier metal layer BML includes, for example, titanium nitride (TiN). The core metal layer MLC includes, for example, tungsten (W). The barrier metal layer BML and the core metal layer MLC are deposited through the slits ST by, for example, CVD.

  As shown in FIG. 9B, the connection conductor LI and the insulating film 27 are formed inside the slit ST. Specifically, the barrier metal layer BML and the core metal layer MLC covering the inner surface of the slit ST are removed using, for example, isotropic dry etching, and then the insulating film 27 covering the inner surface of the slit ST is formed. Further, N-type impurities are ion-implanted into the conductive layer CL through the slits ST to form contact regions LCR. Subsequently, a part of the insulating film 27 covering the bottom surface of the slit ST is selectively removed, and thereafter, a barrier metal layer BML covering the inner surface of the slit ST and a core metal layer MLC filling the inside of the slit ST are formed. To do. Thereby, the connection conductor LI can be formed inside the slit ST.

  Subsequently, interlayer insulating films 19 and 21, connection plugs CH and V1, and bit lines BL are formed on the interlayer insulating film 17, thereby completing the memory cell array MCA.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1, 2 ... Memory | storage device 13, 15, 15M, 17, 19, 21 ... Interlayer insulation film, 23 ... Sacrificial film, 23S ... Space, 25, 27 ... Insulation film, BL ... Bit line, CH ... Connection plug, CL ... conductive layer, Cp ... parasitic capacitance, NS ... near end, FS ... far end, GD1, WD1, WD2 ... drive circuit, IC ... insulating core, LCR ... contact region, LI ... connection conductor, MC ... memory cell, MCA ... memory cell array, MF ... memory film, FL1 ... block insulating film, FL2 ... charge retention film, FL3 ... tunnel insulating film, MH ... memory hole, BML ... barrier metal layer, MLC ... core metal layer, SA ... sense amplifier, SC ... Semiconductor layer, SF, SF1, SF2 ... semiconductor film, SGD, SGDA, SGDB, SGS ... select gate, SHL ... isolation trench, S L ... Source line, SP ... Semiconductor pillar, ST ... Slit, STD, STS ... Selection transistor, TSS ... Top surface, WL ... Word line, WLD, WLD0, WLD1, WLS ... Dummy word line

Claims (5)

A plurality of word lines stacked in a first direction;
A first insulating film provided between adjacent word lines in the first direction of the plurality of word lines;
Selection gates arranged side by side on a plurality of word lines in the first direction;
A first intermediate electrode provided between the plurality of word lines and the selection gate;
A second insulating film provided between the first intermediate electrode and the selection gate;
A semiconductor pillar extending in the first direction through the plurality of word lines, the first insulating film, the first intermediate electrode, the second insulating film, and the select gate;
A charge retention film positioned between each of the plurality of word lines and the semiconductor pillar;
With
The storage device, wherein the second insulating film has a second film thickness in the first direction that is thicker than a first film thickness in the first direction of the first insulating film. A first drive circuit for supplying a bias to each of the plurality of word lines;
A second drive circuit for supplying a bias to the intermediate electrode;
Further comprising
The storage device according to claim 1, wherein the first drive circuit supplies a second potential that is higher than the first potential supplied from the second drive circuit.   3. The memory device according to claim 2, wherein the first drive circuit injects charges from the semiconductor pillar into the charge holding film by supplying the two potentials to one of the plurality of word lines. A second intermediate electrode provided between the first intermediate electrode and the plurality of word lines;
The storage device according to claim 2, wherein the second drive circuit supplies a common potential to the first intermediate electrode and the second intermediate electrode. A plurality of first electrodes stacked in a first direction;
A first insulating film provided between adjacent first electrodes in the first direction of the plurality of first electrodes;
A second electrode arranged side by side with a plurality of first electrodes in the first direction;
A third electrode provided between the plurality of first electrodes and the second electrode;
A second insulating film provided between the third electrode and the second electrode;
A fourth electrode provided between the plurality of first electrodes and the third electrode;
A semiconductor pillar extending in the first direction through the plurality of first electrodes, the first insulating film, the fourth electrode, the three electrodes, the second insulating film, and the second electrode;
A charge retention film positioned between each of the plurality of first electrodes and the semiconductor pillar;
A first drive circuit for supplying a potential to each of the plurality of first electrodes;
A second drive circuit for supplying a common potential to the third electrode and the fourth electrode;
With
The storage device, wherein the second insulating film has a second film thickness in the first direction that is thicker than a first film thickness in the first direction of the first insulating film.

Images