JP2019118132A - Semiconductor device and radio communication apparatus - Google Patents

Abstract

To provide a semiconductor device capable of detecting an amplitude level of a harmonic wave.SOLUTION: A semiconductor device 100 comprises: an in-phase detection circuit 103 which synthesizes an AC signal in an in-phase manner and outputs a DC and an even-ordered harmonic wave; a detection circuit 104 for obtaining an amplitude level of the ordered harmonic wave; and a control circuit 105 for controlling the AC signal in such a manner that the amplitude level becomes minimum. The detection circuit includes: a detector by which a DC signal for bringing an amplitude level of a signal of a secondary harmonic wave into a DC voltage is generated and outputted due to the even-ordered harmonic wave; an LPF for suppressing a high frequency component included in the DC signal; an amplifier circuit for amplifying a suppressed DC signal resulting from suppressing the harmonic component; and a comparator for comparing a signal of the amplitude level of the amplified secondary harmonic wave to a reference voltage and outputting a result of comparison between a voltage of a detection signal of the secondary harmonic wave and a predetermined voltage. The control circuit controls the AC signal in accordance with the comparison result.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a wireless communication device, and more particularly to a semiconductor device and a wireless communication device that perform calibration for suppressing second harmonics.

  In recent years, the demand for computer equipment using wireless such as Bluetooth (registered trademark) has been increasing, and in order to be mounted on a wearable device, a one-chip wireless circuit and the like are required. The mounting of wireless circuits on semiconductor devices such as (System on a Chip) is increasing.

  A wireless circuit mounted on a semiconductor device is connected to a chip resistor and a chip inductor provided on a substrate together with the semiconductor device to constitute a wireless device. In these radio devices, the power of the transmission signal is amplified and transmitted as a radio signal from the antenna, but in a class D amplifier used for amplification of the transmission signal, pulse width modulation or pulse density modulation is applied, and power amplification is performed by the switching circuit. When the power of the transmission signal is amplified, the harmonics are generated.

  Patent Document 1 is known as a technique for suppressing the harmonics. In Patent Document 1, harmonics having a frequency higher than that of the transmission signal are suppressed by passing the amplified transmission signal through an LPF (Low Pass Filter).

U.S. Patent No. 5,973,568

  The conventional device requires an LPF for transmitting a transmission signal with high power, and when this LPF is not provided, there is a problem that it is not possible to know how much harmonics are emitted.

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, the semiconductor device includes an in-phase detection circuit and a detection circuit, the in-phase detection circuit detects an in-phase AC signal, and the detection circuit includes even-order harmonics output from the in-phase detection circuit. Detect the amplitude level.

  According to the one embodiment, the amplitude level of the harmonic can be detected.

FIG. 1 is a configuration diagram showing a schematic configuration of a semiconductor device according to an embodiment. A diagram showing a configuration of a semiconductor device according to a first embodiment A diagram showing an example of a pulse waveform Diagram showing the relationship between the duty ratio of the amplifier and the amplitude level of the harmonics Diagram showing the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection Diagram showing the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection Diagram showing the relationship between the duty ratio of the amplifier and the DC signal after the in-phase detection Diagram showing the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection Block diagram showing the configuration of the detection circuit of the first embodiment A circuit diagram showing a configuration of a detection circuit according to a first embodiment A diagram showing a signal input to the detector 112 Diagram showing the signal after detection Diagram showing an example of signal after AC suppression Diagram showing an example of the signal after amplification A circuit diagram showing a configuration of a detection circuit of a second embodiment The figure which shows the example of the signal which is input into amplification circuit 114 The figure which shows the configuration of the semiconductor device which relates to the form 3 of execution A circuit diagram showing a configuration of a detection circuit of a third embodiment A diagram showing a configuration of a semiconductor device according to a fourth embodiment Diagram showing the relationship between the duty ratio of the amplifier and the voltage of the comparison signal The figure which shows the structure of the radio | wireless communication apparatus based on Embodiment 5. Figure showing an example of mounting board A diagram showing an example of a circuit of a conventional wireless communication apparatus The figure which shows an example of the circuit of the radio | wireless communication apparatus of this Embodiment

  The following description and drawings are omitted and simplified as appropriate for clarification of the explanation. In addition, each element described in the drawing as a functional block that performs various processing can be configured by a CPU, a memory, and other circuits in terms of hardware, and in terms of software, a program loaded into a memory And so on. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any of them. In the drawings, the same elements are denoted by the same reference numerals, and the redundant description is omitted as necessary.

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but they are not unrelated to each other unless specifically stated otherwise, one is the other And some of all the modifications, applications, detailed explanation, supplementary explanation, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number.

Further, in the following embodiments, the constituent elements (including the operation steps and the like) are not necessarily essential unless specifically stated and when it is considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above-described numbers and the like (including the number, the numerical value, the amount, the range, and the like).
(Overview of the embodiment)

  FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device according to the embodiment. As shown in FIG. 1, a semiconductor device 10 according to the embodiment includes an in-phase detection circuit 11 for detecting an in-phase AC signal, and a detection circuit 12 for detecting an amplitude level of even harmonics output from the in-phase detection circuit. Is equipped.

  The in-phase detection circuit 11 cancels the odd harmonics by combining the AC signals which are differential signals in the same phase, and obtains the direct current and the even harmonics. Then, the in-phase detection circuit outputs the obtained signal to the detection circuit 12.

  The detection circuit 12 obtains the amplitude level of even-order harmonics from the signal after in-phase detection by detection, and outputs the detected amplitude level.

As shown in FIG. 1, the amplitude level of the harmonic can be detected by detecting the AC signal in phase and detecting the signal in phase.
Embodiment 1

  The first embodiment will be described below with reference to the drawings. FIG. 2 is a diagram showing the configuration of the semiconductor device according to the first embodiment. As shown in FIG. 2, the semiconductor device 100 includes an AC output circuit 101, a balun 102, an in-phase detection circuit 103, a detection circuit 104, and a control circuit 105.

  The AC output circuit 101 amplifies the input AC signal which is a differential signal, and outputs the amplified AC signal to the balun 102 and the in-phase detection circuit 103. For example, an alternating current output circuit amplifies an alternating current signal using a class D amplifier. A class D amplifier uses pulse width modulation to perform power amplification in a switching circuit.

  The balun 102 performs balanced-unbalanced conversion on an alternating current signal which is a differential signal, and transmits it as a wireless signal via an antenna.

  The in-phase detection circuit 103 cancels the odd harmonics by combining AC signals which are differential signals in the same phase, and obtains DC and even harmonics. Then, the in-phase detection circuit 103 outputs the obtained signal to the detection circuit 104. For example, the in-phase detection circuit 103 may be configured by a circuit that combines differential signals via a resistor.

  The detection circuit 104 detects the signal after the in-phase detection to obtain the amplitude level of the even-order harmonic. Then, the detection circuit 104 outputs the detected amplitude level to the control circuit 105.

  The control circuit 105 controls the parameters of the AC output circuit, and determines the parameter to a value at which the amplitude level obtained from the detection circuit 104 is minimum. For example, the control circuit 105 changes the duty ratio in the pulse width modulation of the class D amplifier of the AC output circuit 101, and obtains the relationship between the duty ratio and the amplitude level of the even harmonics. Then, the control circuit 105 instructs the AC output circuit 101 on a duty ratio that minimizes the amplitude level of the even harmonics.

  In the class D amplifier, when the duty ratio changes, the amplitude level of the generated harmonics also changes. FIG. 3 is a diagram showing an example of a pulse waveform. In FIG. 3, the horizontal axis indicates time, and the vertical axis indicates voltage. Further, in FIG. 3, π indicates a half cycle time, and α indicates a time from the center of the pulse waveform to the voltage change.

In FIG. 3, the voltage of the pulse waveform is represented by the following equation (1).
In equation (1), ω indicates the frequency of the pulse signal, and t indicates the time. Also, k means a natural number.

Here, when the duty ratio is 0.5, α = π / 2, and the voltage of the pulse waveform is represented by the following equation (2).

On the other hand, when the duty ratio deviates from 0.5, α = β + π / 2 (beta is an arbitrary value), and the voltage of the pulse waveform is expressed by the following approximate expression (3).

In the equation (3), the direct current component is represented by 1/2 + β / 2, and the second harmonic is represented by the following equation (4).

  Here, if the value of β is small, Sinβ can be approximated by β, so the second harmonic is approximated to β / π. That is, the second harmonic increases as the duty ratio deviates from 0.5. The semiconductor device 100 according to the first embodiment detects the deviation of the duty ratio from the relationship between the duty ratio and the amplitude level of the harmonics.

Specifically, the differential signal input to the AC output circuit 101 is defined by the following equations (5) and (6).

The common-mode detection circuit 103 adds and averages the voltages of the differential signals. Therefore, the output of the common mode detection circuit 103 is expressed by the following equation (7).

Here, when α is rewritten as D (time of “H” in one period / time of one period MAX = 1), the output of the in-phase detection circuit 103 is expressed by the following equation (8). In formula (8), D is in the range of 0 <D <1.

In the output signal shown by the equation (8), the third and higher order components can be neglected by natural attenuation. Therefore, when only the first two terms of the equation (8) are described, the equation (9) is obtained.

Here, the coefficient (e1) of the first term and the coefficient (e2) of the second term are represented by equations (10) and (11), and both become coefficients of monotonous increase and monotonous decrease.

The signal of VCMDET_O is then input to the detection circuit 104. The detection circuit 104 is composed of a circuit having a function of removing a DC component and a function of mainly detecting a peak value of amplitude for the purpose of preventing a malfunction, and the coefficient in the peak detection circuit output waveform (VDET_O) is a coefficient e1. It is calculated from / e2, and becomes equations (12) and (13).

Here, the e2 component is detected by the detection circuit 104, and VLPF_O from which the high region is removed by the LPF in the detection circuit 104 can be expressed by the following equation (14).

  In equation (14), the value for which D = 0.5 is the duty ratio that can most suppress the second harmonic. FIG. 4 is a diagram showing the relationship between the duty ratio of the amplifier and the amplitude level of the harmonics. In FIG. 3, the horizontal axis indicates the duty ratio of the class D amplifier of the AC output circuit 101, and the vertical axis indicates the amplitude of the second harmonic obtained by detection in the in-phase detection circuit 103.

  As shown in FIG. 4, at the point where the duty ratio is P0, the amplitude of the second harmonic is minimized. In addition, the value of the amplitude of the second harmonic takes a symmetrical value with respect to the point where the duty ratio is P0.

  In the semiconductor device 100, even-order harmonic signals including the second harmonic are detected to search for a duty ratio that minimizes the amplitude of the second harmonic. Here, an example of the search will be described with reference to FIG. FIG. 5 is a diagram showing the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection. In FIG. 5, the horizontal axis represents the duty ratio of the class D amplifier of the AC output circuit 101, and the vertical axis represents the amplitude of the second harmonic obtained by detection in the detection circuit 104.

  As shown in FIG. 5, the voltage of the second harmonic after detection is the same as the amplitude level of the second harmonic before detection in FIG. It becomes the minimum. Further, the voltage of the signal after detection has a symmetrical value with respect to the point where the duty ratio is P0.

The control circuit 105 searches for the duty ratio at which the voltage of the signal after detection is minimized, from the relationship between the duty ratio shown in FIG. 5 and the voltage of the second harmonic after detection. The voltage of the signal after detection may simply determine the minimum point, or the voltage of the signal after detection determines the minimum point by finding the middle point of the duty ratio with the same voltage of the signal after detection. Also good. In FIG. 5, the duty ratio P1 and P2 in which the voltage of the signal after detection is equal to 0 V which is the threshold voltage are searched, and P0 which is the middle point is determined from the equation P0 = (P1 + P2) / 2. . The threshold voltage may not be 0 V, but may be any voltage. Assuming that the threshold value is VCMP_REF, duty ratios D1 and D2 of two points at which VLPF_O = VCMP_REF are expressed by Equations (15) and (16), respectively.

Here, when the middle point between D1 and D2 is Dc = 0.5 × (D1 + D2), equation (17) is obtained.

  In equation (17), Dc is a solution of Dc = 0.5 due to the constraint of 0 <{Dc, D1, D2} <1. The variable related to the duty ratio may be controlled by digital bits such as TXDUTY_P / N to search for the optimum point.

  The method of determining the optimum duty ratio by the middle point has an effect of being resistant to noise. For example, when the detection level of the second harmonic is low, the low-voltage portion of the signal after detection is buried in the noise due to the influence of the noise floor. FIG. 6 is a diagram showing the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection. Similar to FIG. 5, in FIG. 6, the horizontal axis shows the duty ratio of the class D amplifier of the AC output circuit 101, and the vertical axis shows the amplitude of the second harmonic obtained by detection in the detection circuit 104.

  In FIG. 6, the signal is buried in noise near the duty ratio P0. Therefore, in the method of searching for the point where the voltage is minimum, the minimum point is buried in noise and it is not possible to find the point where the voltage is minimum.

  On the other hand, in the method of finding the optimum duty ratio from the middle point of two points at a predetermined voltage, the duty ratio is calculated from the signal of the portion not buried in the noise, so the optimum duty ratio is not affected by the noise. It can be asked.

  In addition, the semiconductor device according to the first embodiment has an effect that the optimum duty ratio can be obtained without being influenced by the offset of the signal voltage.

  For example, a method may be considered in which an optimum duty ratio is determined from a DC component among signals amplified by the AC output circuit 101. FIG. 7 is a diagram showing the relationship between the duty ratio of the amplifier and the DC signal after the in-phase detection. As shown in FIG. 7, since the duty ratio of the amplifier and the DC signal after the in-phase detection are in a linear relationship, a point where the optimum duty ratio is equal to a predetermined threshold voltage (for example, 0 V) is searched .

  However, if the DC signal has a voltage offset due to the variation of the components that make up the device, the duty ratio at which the voltage is 0 V is P0 ', as indicated by the hatched broken line. There is a possibility that a point different from P0 may be mistaken as an optimal duty ratio.

  On the other hand, in the semiconductor device of the first embodiment, since the second harmonic has the characteristic of line symmetry centered on the optimum duty ratio, the optimum duty ratio should be determined even if the voltage offset is included in the signal. Can. FIG. 8 is a diagram showing the relationship between the duty ratio of the amplifier and the voltage of the second harmonic after detection. Similar to FIGS. 5 and 6, in FIG. 8, the horizontal axis shows the duty ratio of the class D amplifier of the AC output circuit 101, and the vertical axis shows the amplitude of the second harmonic obtained by detection in the detection circuit 104. In FIG. 8, a broken line is a signal after detection in which an offset is included in the voltage. The voltage offset shifts the point where the voltage equals 0V, which is the threshold, to P1 'and P2' respectively, but the midpoint between P1 and P2 is the same P0 as the midpoint between P1 'and P2', so it is optimal Duty ratio can be determined.

  Next, the internal configuration of the detection circuit 104 of the first embodiment will be described. FIG. 9 is a block diagram showing the configuration of the detection circuit of the first embodiment. In FIG. 9, the detection circuit 104 includes a reference voltage generation circuit 111, a detector 112, an LPF 113, an amplification circuit 114, and a comparator 115.

  The reference voltage generation circuit 111 generates a reference voltage used by the detector 112. For example, the reference voltage generation circuit 111 generates two types of reference voltages VREF1 and VREF2. The difference between the reference voltages VREF1 and VREF2 determines the amplitude level of the second harmonic to be detected. That is, the voltages corresponding to P1 and P2 in FIG. 5 are determined by the difference voltage between the voltages VREF1 and VREF2.

  The detector 112 adds the voltage of VREF2 to the signal detected in phase in the in-phase detection circuit 103 and detects it together with VREF1 to detect a DC signal whose amplitude level is the DC voltage of the second harmonic detected in phase. obtain. Then, the detector 112 outputs the obtained amplitude level to the LPF 113.

  The LPF 113 suppresses high frequency components included in the obtained DC signal of the amplitude level, and outputs the high frequency component to the amplifier circuit 114.

  The amplifier circuit 114 amplifies the DC signal and outputs the amplified signal to the comparator 115.

  The comparator 115 compares the voltages of the amplified DC signals. The difference in voltage between the two signals to be compared reflects the difference between the amplitude level of the second harmonic signal and the two reference voltages. As described above, the voltage corresponding to P1 and P2 in FIG. 5 is determined by the difference voltage between the reference voltages VREF1 and VREF2. That is, the comparator 115 outputs the result as to whether the voltage of the detection signal of the signal of the second harmonic is higher or lower than a predetermined voltage.

  The control circuit 105 changes the duty ratio in pulse width modulation of the class D amplifier of the AC output circuit 101, and detects the duty ratio at the point where the result of the comparator 115 changes as P1 or P2 in FIG. Then, the control circuit 105 reflects the middle point P0 of P1 and P2 as the optimum duty ratio on the duty ratio in the pulse width modulation of the class D amplifier of the AC output circuit 101.

  Next, an example of a specific circuit of the detection circuit 104 of the first embodiment will be described. FIG. 10 is a circuit diagram showing a configuration of the detection circuit of the first embodiment.

  The detection circuit 104 includes resistors R1-1, R1-2, R2-1, R2-2, R3, R4, R5, R6, R7, R8, R9, capacitors C1, C2, C3, C4, a field effect transistor It comprises FET1, FET2, FET3, FET4, variable resistors VR1-1, VR1-2, switch SW1, and current source CS1. The field effect transistors FET1 and FET2 are, for example, pMOS-FETs, and the field effect transistors FET3 and FET4 are, for example, nMOS-FETs. The switch SW1 enables detection by closing and does not perform detection by opening.

  In FIG. 10, a resistor R1-1, a fixed resistor of a variable resistor VR1 and a resistor R2-1 are connected in series between a power supply potential and a ground potential, and a variable resistor terminal of the variable resistor VR1 and a field effect transistor FET1. A resistor R3 is connected between the gate and the gate. Further, between the power supply potential and the ground potential, the resistor R1-2, the variable resistor VR12 fixed resistor, and the resistor R2-2 are connected in series, and the variable resistor terminal of the variable resistor VR2 and the gate of the field effect transistor FET2 It is connected. Also, a capacitor C1 is connected between the input terminal of the second harmonic and the field effect transistor FET1.

  In the circuit configuration in the detector 112, the resistor R4 and the capacitor 2 are connected in parallel between the power supply potential and the source of the field effect transistor FET1. Further, a resistor R5 is connected between the power supply potential and the field effect transistor FET2. The switch SW1 is connected between the drain of the field effect transistor FET1 and the drain of the FET2 and the ground potential.

  The LPF 113 includes resistors R6 and R7 and capacitors C3 and C4. A resistor R6 is connected between the source of the field effect transistor FET1, the source of the field effect transistor FET2, and the gate of the field effect transistor FET4. Further, a resistor R7 is connected between the gate and the gate of the field effect transistor FET3. A capacitor C3 is connected between the terminal of the resistor R6 on the amplifier circuit 114 side and the terminal of the resistor R7 on the amplifier circuit 114 side. Further, a capacitor C4 is connected between the terminal of the resistor R7 on the amplification circuit 114 side and the ground potential.

  In the circuit configuration in the amplifier circuit 114, a resistor R8 is connected between the power supply potential and the source of the field effect transistor FET3. Further, a resistor R9 is connected between the power supply potential and the source of the field effect transistor FET4. A current source is connected between the drain of the field effect transistor FET3 and the ground potential. In addition, a current source is connected between the drain of the field effect transistor FET4 and the ground potential. The source of the field effect transistor FET3 and the source of the field effect transistor FET4 are connected to the output terminal.

  Next, the signal processing of the detection circuit 104 will be described below.

  The DC component of the second harmonic HD2 input from the input terminal is suppressed by the capacitor C1. Then, a signal obtained by adding the reference voltage VREF2 to the second harmonic HD2 whose direct current component is suppressed is input to the gate of the field effect transistor FET1. Further, a signal of the reference voltage VREF1 is input to the gate of the field effect transistor FET2. FIG. 11 is a diagram showing a signal input to the detector 112. As shown in FIG. In FIG. 11, the vertical axis represents voltage, and the horizontal axis represents time. Further, in FIG. 11, a broken line indicates a signal of the reference voltage VREF2, and a solid line indicates a signal to be detected. As shown in FIG. 11, the detector 112 receives a signal obtained by adding the reference voltage VREF2 to the second harmonic HD2 and a signal of the reference voltage VREF1.

  In the detector 112, a signal obtained by adding the reference voltage VREF2 to the second harmonic HD2 is detected, and becomes a signal obtained by converting the amplitude of the second harmonic HD2 into a DC voltage. Here, assuming that the difference voltage between two reference voltages is Vrf and the voltage after detecting the amplitude level of the second harmonic is VDC1, the detection potential obtained from the source of the field effect transistor FET1 is determined by Vo2 = VDC1 + Vrf . Further, assuming that the detection potential obtained from the source of the field effect transistor FET2 is Vo1 = VDC, the amplitude level of the second harmonic of the potential difference between the field effect transistors FET1 and FET2 has a relationship of ΔVd = VDC1−VDC. FIG. 12 shows the signal after detection. In FIG. 12, the vertical axis represents voltage, and the horizontal axis represents time. Further, in FIG. 12, the broken lines indicate the signal of the reference voltage VREF2 and the signal before detection, and the solid line indicates the signal after detection. As shown in FIG. 12, in the signal after detection, some AC components remain.

  The LPF 113 suppresses the AC component of the signal after detection. FIG. 13 is a diagram showing an example of the signal after AC suppression. In FIG. 13, the vertical axis represents voltage, and the horizontal axis represents time. Further, in FIG. 13, the broken line indicates the signal and the AC component of the reference voltage VREF2, and the solid line indicates the signal after AC suppression. Then, after passing through the LPF 113, the potentials of the signals become Vo2 '= VDC1 + a × Vrf and Vo1' = VDC, respectively. Here, a is a predetermined constant.

  Then, the amplifier circuit 114 amplifies the signal after AC suppression. FIG. 14 is a diagram showing an example of the signal after amplification. In FIG. 14, the vertical axis represents voltage and the horizontal axis represents time. Also, in FIG. 14, the solid line indicates the signal after amplification. The potential difference of each signal output from the amplifier circuit 114 is V (OUT_N) −V (OUT_P) = Av × (ΔVd + a × Vrf). Here, Av is an amplification factor in the amplifier circuit 114. The potential difference between the two signals means the difference between the voltage indicating the amplitude of the second harmonic HD2 and the threshold voltage.

  Therefore, in the comparator 115, when it is determined that the voltages of the two signals are equal, it means that the voltage indicating the amplitude of the second harmonic HD2 is equal to the threshold. Based on the comparison result, the duty ratio P1 and P2 in which the voltage of the signal after detection is equal to the threshold voltage are searched, and P0 = (P1 + P2) / 2, the optimum duty P0 at the middle point It can be determined as a ratio.

  As the determination timing of the optimum duty ratio, the control circuit 105 changes so as to sweep the range of the duty ratio which can be set at a predetermined timing such as a stable timing after power on. Then, from the relationship between the output obtained from the comparator 115 and the duty ratio, the control circuit 105 searches for duty ratios P1 and P2 at which the voltage of the signal of the second harmonic after detection is equal to the threshold voltage. The duty ratio of the AC output circuit 101 is set with P0, which is the middle point between P1 and P2, as the optimum duty ratio. By the above-described operation, calibration of the AC output circuit 101 for obtaining an optimal duty ratio can be performed.

As described above, according to the first embodiment, the amplitude level of the harmonics can be obtained by detecting the AC signal output from the AC output circuit in phase and detecting even harmonics of the signal after in-phase detection. Because it can, the AC output circuit can be controlled to suppress the amplitude level of the harmonics.
Second Embodiment

  The second embodiment will be described below with reference to the drawings. In the first embodiment, the signal of the second harmonic after detection is output to the amplification circuit through the LPF, but in the present embodiment, the connection lines between the detector and the amplification circuit are connected by a capacitor. Do.

  FIG. 15 is a circuit diagram showing a configuration of a detection circuit of the second embodiment. The same components as in the first embodiment are assigned the same reference numerals, and the description thereof is omitted.

  In FIG. 15, the capacitive connection circuit 201 includes a capacitor C21. The capacitor C21 is connected between a line connecting the source of the field effect transistor FET1 and the gate of the field effect transistor FET3 and a line connecting the source of the field effect transistor FET2 and the gate of the field effect transistor FET4. ing.

  By inserting the capacitor, the connection line between the detector 112 and the amplifier circuit 114 is equivalent to shorting in an alternating current. The high frequency component that originally existed only in one of the detected harmonics is input to the amplifier circuit 114 at the same level on the signal side of the reference voltage. FIG. 16 is a diagram showing an example of a signal input to the amplifier circuit 114. As shown in FIG. In FIG. 16, the vertical axis represents voltage and the horizontal axis represents time. Further, in FIG. 16, a broken line indicates a signal before detection, and a solid line indicates a signal in which a high frequency component is reflected on both sides by the capacitive connection circuit 201.

  This high frequency component effectively uses CMRR (Common Mode Rejection Ratio) of the amplifier circuit 114, and the high frequency component of the same level of each signal is removed at the output of the amplifier circuit 114. The amount to be removed is determined by the cutoff frequency of the RC filter and the CMRR of the amplifier circuit 114, respectively.

According to the semiconductor device of the second embodiment, harmonic components are removed using CMRR of the amplifier circuit, and the LPF is not used. Therefore, the components of the LPF circuit can be reduced, and the area saving of the semiconductor device An effect can be expected.
Third Embodiment

  The second embodiment will be described below with reference to the drawings. In the first embodiment, the voltage of the second harmonic signal after detection is compared with the threshold voltage using a comparator. However, in the present embodiment, an analog-to-digital converter circuit is provided, and The potential difference between the voltage of the second harmonic signal and the threshold voltage is converted to a digital signal.

  FIG. 17 is a diagram showing the configuration of the semiconductor device according to the third embodiment. The same components as in the first embodiment are assigned the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 17, the semiconductor device 300 includes a detection circuit 301, an AD conversion circuit 302, and a control circuit 303.

  The detection circuit 301 detects the signal after the in-phase detection to obtain the amplitude level of the even-order harmonic. Then, the detection circuit 301 outputs the detected amplitude level to the control circuit 105. Further, the detection circuit 301 outputs the signal after the in-phase detection and the signal of the reference voltage to the AD conversion circuit 302.

  The AD conversion circuit 302 analog-digital converts the potential difference between the signal after the in-phase detection and the signal of the reference voltage, and outputs the converted digital signal to the control circuit 303.

  The control circuit 303 controls the parameters of the AC output circuit, and determines the parameter to a value at which the amplitude level obtained from the detection circuit 301 is minimum. For example, the control circuit 303 changes the duty ratio in pulse width modulation of the class D amplifier of the AC output circuit 101, and obtains the relationship between the duty ratio and the amplitude level of the even-order harmonics. Then, the control circuit 303 instructs the AC output circuit 101 on a duty ratio that minimizes the amplitude level of the even-order harmonics.

  The control circuit 303 also monitors the variation of the second harmonic based on the digital signal converted by the AD conversion circuit 302. Detailed operations will be described later.

  Next, the internal configuration of the detection circuit 301 will be described. FIG. 18 is a circuit diagram showing a configuration of a detection circuit of the third embodiment. The same components as in the first embodiment are assigned the same reference numerals, and the description thereof is omitted.

  In FIG. 18, the detection circuit 301 includes switches SW31, SW32, SW33, and SW34.

  As shown in FIG. 18, the switch SW31 is connected between the variable resistor terminal of the variable resistor VR1 and the resistor R6. Further, the switch SW31 is connected between the variable resistor terminal of the variable resistor VR2 and the resistor R7.

  The switch SW33 is connected between the source of the field effect transistor FET2 and the resistor R6. Further, the switch SW34 is connected between the source of the field effect transistor FET1 and the resistor R7.

  The SW 31 and the SW 32 interlock with each other to open and close, and similarly, the SW 33 and the SW 34 interlock with each other to open and close. When the switches SW31 and SW32 are in the open state, the switches SW33 and SW34 are in the closed state, and the signal after detection is input to the LPF 113.

  When SW31 and SW32 are in the closed state, SW33 and SW34 are in the open state, and bypass the detector 112 to directly input the signal of the second harmonic and the signal of the reference voltage to the LPF 113.

The operation will be described below. After calibration using the second harmonic of Embodiment 1 or 2, the signal path is switched so that the output of the amplifier circuit 114 is monitored by the AD conversion circuit. Here, the detector 112 is bypassed, and a DC voltage (e1 component described in the first embodiment) which changes monotonously according to the second harmonic is input to the AD conversion circuit. At the end of the calibration, the output of the amplifier circuit 114 is a voltage (Vopt) at which the second harmonic is minimum, and the output of the amplifier circuit 114 at this time is temporarily stored in the memory. If the second harmonic fluctuates due to some factor (for example, temperature), the output of the amplification circuit 114 also changes accordingly,
(1) Adjust the duty so that it approaches Vopt.
(2) If it does not deviate greatly from Vopt, select either calibration operation not to be selected.

  As a judgment standard not to be largely deviated from Vopt, it can be considered that it is a level of a second harmonic permitted by the Radio Law.

As described above, according to the semiconductor device of the third embodiment, either a correction is performed again even for a sudden environmental change, or a calibration operation is not selected according to the degree of the change of the second harmonic. The correction time can be shortened by judging on the basis of the output of the analog-to-digital converter.
Embodiment 4

  The fourth embodiment will be described below with reference to the drawings. In the first embodiment, the optimum duty ratio is searched using the amplitude level of the second harmonic, but in the present embodiment, the phase of the second harmonic is used.

  FIG. 19 is a diagram showing the configuration of the semiconductor device according to the fourth embodiment. The same components as in the first embodiment are assigned the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 19, the semiconductor device 400 includes an in-phase detection circuit 401, a phase comparator 402, an LPF 403, a comparator 404, and a control circuit 405.

  The in-phase detection circuit 401 cancels the odd harmonics by combining the differential signals input to the AC output circuit 101 in the same phase, and obtains the direct current and the even harmonics. Then, the in-phase detection circuit 401 outputs the obtained signal to the phase comparator 402.

  The phase comparator 402 compares the phase of the signal output from the in-phase detection circuit 103 with the phase of the signal output from the in-phase detection circuit 401, and outputs a comparison signal using the comparison result as a voltage. The LPF 403 suppresses the AC component of the comparison signal and outputs the same to the comparator 404.

  The comparator 404 compares the comparison signal with a predetermined threshold, and outputs the comparison result to the control circuit 405. The control circuit 405 controls the AC output circuit 101 based on the comparison result.

  Next, the operation of the semiconductor device of the fourth embodiment will be described. FIG. 20 is a diagram showing the relationship between the duty ratio of the amplifier and the voltage of the comparison signal. In FIG. 20, the horizontal axis represents the duty ratio of the class D amplifier of the AC output circuit 101, and the vertical axis represents the voltage of the comparison signal obtained by the phase comparator 402.

  The control circuit 405 searches for a duty ratio at which the voltage of the comparison signal and the voltage serving as the threshold shown in FIG. 20 are equal, and instructs the AC output circuit 101 on the obtained duty ratio.

As described above, according to the semiconductor device of the fourth embodiment, the optimal duty ratio can be detected by comparing the phase difference before and after amplification of the differential signal.
Fifth Embodiment

  The fifth embodiment will be described below with reference to the drawings. The fifth embodiment is an example in which the semiconductor device of the first to fourth embodiments is applied to BLE (Bluetooth (registered trademark) Low Energy).

  FIG. 21 is a diagram showing the configuration of the wireless communication apparatus according to the fifth embodiment. The same components as in the first embodiment are assigned the same reference numerals, and the description thereof is omitted.

  In FIG. 21, a wireless communication system 500 includes a wireless communication device 501 and an MCU 502. Further, in FIG. 21, the wireless communication apparatus 501 includes a modem 50, a local oscillator 51, a power amplifier 52, a matching 53, an antenna 54, a low noise amplifier 55, a frequency divider 56, and a down converter 57-1. , 57-2, LPFs 58-1 and 58-2, and AD converters 59-1 and 59-2.

  The modem 50 modulates transmission data output from the MCU 502 to obtain a transmission signal, and outputs the transmission signal to the local oscillator 51. Also, the modem 50 demodulates the reception signals output from the AD converters 59-1 and 59-2 and outputs the result to the MCU 502.

  The local oscillator 51 generates a signal of a frequency to be transmitted wirelessly, superimposes it on the modulated transmission signal, and outputs it to the power amplifier 52.

  The power amplifier 52 is a power amplifier including the semiconductor device according to any of the embodiments 1-4. The power amplifier 52 amplifies the power of the transmission signal and outputs the power to the matching 53.

  The matching 53 matches the impedances of the power amplifier 52 and the antenna 54. The matching 53 matches the impedance of the antenna 54 and the low noise amplifier 55.

  The antenna 54 transmits the transmission signal as a radio signal, and outputs the received radio signal to the matching 53 as a reception signal.

  The low noise amplifier 55 amplifies the power of the received signal and outputs it to the downconverters 57-1 and 57-2.

  The frequency divider 56 divides the signal of the frequency generated by the local oscillator 51 and outputs it to the downconverters 57-1 and 57-2.

  The downconverters 57-1 and 57-2 convert the frequency of the received signal and output the result to the LPFs 58-1 and 58-2.

  The LPFs 58-1 and 58-2 suppress high frequency components of the reception signal and output the same to the AD converters 59-1 and 59-2.

  The AD converters 59-1 and 59-2 convert the received signal from an analog signal to a digital signal and output the converted signal to the modem 50.

  As described above, according to the wireless communication apparatus of the fifth embodiment, detection of the optimum duty ratio using the second harmonic can be applied to the wireless communication apparatus, so that unnecessary harmonics can be transmitted wirelessly. Be suppressed.

  In addition, when the semiconductor device is mounted in a wireless communication device, the number of external components connected to the semiconductor device can be reduced.

  FIG. 22 is a view showing an example of the mounting board. In FIG. 22, a substrate 600 is a substrate on which a conventional wireless communication device is mounted, and the substrate 600 includes a semiconductor 601 including an integrated circuit and an LPF 602. On the other hand, the substrate 610 is a substrate on which the wireless communication device of the present embodiment is mounted, and the substrate 610 has the semiconductor 611 of the present embodiment. As shown in FIG. 22, the substrate 610 has a smaller number of parts other than the semiconductor mounted on the substrate than the substrate 600.

  Specific reduction of the number of parts will be described by taking FIGS. 23 and 23 as an example. FIG. 23 is a diagram showing an example of a circuit of a conventional wireless communication apparatus. FIG. 24 is a diagram showing an example of the circuit of the wireless communication apparatus of this embodiment. In FIG. 23, the conventional wireless communication apparatus 700 includes an amplifier circuit 701, an LPF 702, and an antenna 703. On the other hand, in FIG. 24, the wireless communication apparatus 800 of this embodiment includes an amplifier circuit 701 and an antenna 703.

When FIG. 23 is compared with FIG. 24, compared with FIG. 23, there are few parts connected to the exterior of a semiconductor device in FIG. That is, as described in the first to fifth embodiments described above, radio communication apparatus 800 according to the present embodiment obtains the amplitude level of the harmonics by detecting the even-order harmonics of the signal after the in-phase detection. Therefore, since the AC output circuit can be controlled to suppress the amplitude level of the harmonics, it becomes unnecessary to provide a configuration for suppressing the amplitude level of the harmonics with respect to the amplified high frequency signal. The LPF circuit for high frequency signals after amplification has larger sizes of capacitors and resistors than the LPF circuit for weak signals. Therefore, eliminating the need for the LPF circuit greatly contributes to the miniaturization of the wireless communication device.

  The wireless communication apparatus can be applied to a wireless communication apparatus commission using BLE and a wireless communication apparatus other than BLE.

  As a specific application example, when the wireless communication device of the present embodiment communicates a heart rate monitor, a sphygmomanometer, or a pedometer and a computer device such as a smart phone used in fitness and health care fields by a wireless signal , Can be mounted on individual devices.

  Moreover, it can apply also to the apparatus which records the travel content of a bicycle. For example, when communicating with a wireless signal between a sensor provided on the wheel and handle of a bicycle and a computer for recording provided on the handle, it can be mounted on each device.

  In addition, when the clock has an NTP server, a mail server, or a computer terminal that receives a mail, and the clock communicates with a wireless signal, the clock is mounted on each device when the clock has a mail arrival notification function on the clock or the clock. be able to.

  In addition, when communicating between devices using a wireless signal, such as a keyless entry device or iBeacon (registered trademark), the device can be mounted on each device. It can also be installed in wearable devices.

  Further, in the semiconductor device according to each of the above embodiments, the conductivity type (p-type or n-type) of the semiconductor substrate, the semiconductor layer, the diffusion layer (diffusion region) or the like may be reversed. Therefore, when one of n-type and p-type conductivity types is the first conductivity type and the other conductivity type is the second conductivity type, the first conductivity type is p-type and the second conductivity type is Alternatively, the first conductivity type may be n-type, and the second conductivity type may be p-type.

  In addition, a device or method in which the device of the above embodiment is replaced with a method or a system, a program that causes a computer to execute processing of the device or a part of the device, a wireless communication device including the device, etc. It is effective as a form.

  Also, programs for realizing control operations and control operations in the control circuit described above can be stored using various types of non-transitory computer readable media and supplied to a computer. . Non-transitory computer readable media include tangible storage media of various types. Examples of non-transitory computer readable media are magnetic recording media (eg flexible disk, magnetic tape, hard disk drive), magneto-optical recording media (eg magneto-optical disk), CD-ROM (Read Only Memory) CD-R, CD -R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)) is included. Also, the programs may be supplied to the computer by various types of transitory computer readable media. Examples of temporary computer readable media include electrical signals, light signals, and electromagnetic waves. The temporary computer readable medium can provide the program to the computer via a wired communication path such as electric wire and optical fiber, or a wireless communication path.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the embodiment mentioned already, A various change in the range which does not deviate from the gist It goes without saying that it is possible.

10, 100, 300, 400 Semiconductor device 11 In-phase detection circuit 12 Detection circuit 101 AC output circuit 102 Balun 103, 401 In-phase detection circuit 104, 301 Detection circuit 105, 405 Control circuit 111 Reference voltage generation circuit 112 Detector 113 LPF
114 amplification circuit 115, 404 comparator 201 capacitive connection circuit 302 conversion circuit 303 control circuit 402 phase comparator 500 wireless communication system 501 wireless communication devices C1 to C4 and C21 capacitor CS1 current source FET1 to FET4 field effect transistor R1 to R9 resistance SW1 , SW31 to SW34 switches VR1 and VR2 variable resistance

Claims (13)

An in-phase detection circuit that combines an alternating current signal in phase and outputs a direct current and even harmonics;
A detection circuit for obtaining the amplitude level of the even harmonics;
A control circuit for controlling the alternating current signal so as to minimize the amplitude level;
The detection circuit is
A detector that generates and outputs a DC signal whose amplitude level is a DC voltage based on the even harmonics;
An LPF circuit that suppresses high frequency components included in the DC signal;
An amplification circuit for amplifying a suppressed DC signal in which the harmonic component is suppressed;
A comparator that compares the signal of the amplitude level of the amplified second harmonic with the reference voltage, and outputs the comparison result of the voltage of the detected signal of the second harmonic and a predetermined voltage,
The control device controls the alternating current signal according to the comparison result. It further comprises a reference voltage generation circuit that generates the reference voltage,
The reference voltage generation circuit generates a first reference voltage and a second reference voltage, and an amplitude level of the second harmonic is based on a difference voltage between the first reference voltage and the second reference voltage. The semiconductor device according to claim 1, which is determined as follows.   The detector adds the second reference voltage to the in-phase detected signal, and detects the second-harmonic signal together with the first reference voltage to set the amplitude level of the second harmonic signal as the DC voltage. The semiconductor device according to claim 2, which generates The LPF circuit connects a resistor and a capacitor in parallel between a power supply potential and the first transistor,
The semiconductor device according to claim 3, wherein a resistor is connected between a power supply potential and the second transistor.   The comparator adds the second harmonic and the second reference voltage, and compares a voltage of a signal obtained by detecting an amplified signal with a voltage of a signal obtained by detecting the first reference voltage. 5. The semiconductor device according to item 4. And an AC output circuit which amplifies an AC signal by changing a duty ratio and outputs the amplified signal to the in-phase detection circuit.
The control circuit determines the duty ratio at which the amplitude of the second harmonic of the alternating current signal becomes a minimum value from the relationship between the duty ratio of the alternating current signal and the second harmonic based on the comparison result in the comparator. The semiconductor device according to claim 1, which instructs an output circuit.   The control circuit instructs the AC output circuit to set a middle point between two duty ratios at which two voltages in the comparator become equal, as a duty ratio at which the amplitude of the second harmonic becomes a minimum value. The semiconductor device according to claim 1. An AC output circuit which outputs an AC signal to the common mode detection circuit by changing a duty ratio;
The control circuit determines a duty ratio at which the amplitude of the second harmonic of the alternating current signal becomes a minimum value from the relationship between the duty ratio of the alternating current signal and the second harmonic based on the signal detected in the detection circuit. The semiconductor device according to claim 1, which instructs the alternating current output circuit. A reference voltage generation circuit that generates a first reference voltage and a second reference voltage;
The LPF circuit includes a first resistor for a signal obtained by adding the second harmonic and the second reference voltage, a second resistor for a signal of the first reference voltage, the first resistor, and the second resistor. The semiconductor device according to claim 1, further comprising: a capacitor connected between the resistors and a capacitor connected between one of the resistors and the ground potential. A reference voltage generation circuit that generates a first reference voltage and a second reference voltage;
The semiconductor according to claim 2, wherein the LPF circuit includes a capacitor forming a capacitance between a signal obtained by adding the second harmonic and the second reference voltage and a signal of the first reference voltage. apparatus.   The semiconductor device according to claim 1, further comprising an AD conversion circuit that performs analog-to-digital conversion on the potential of the second harmonic signal detected by the detection circuit. An AC output circuit which outputs an AC signal to the common mode detection circuit by changing a duty ratio.
12. The semiconductor device according to claim 11, further comprising: a control circuit that determines whether or not to search for the optimum value of the duty ratio again based on the signal analog-to-digital converted in the AD conversion circuit. A modem to modulate transmit data,
A local oscillator that generates a radio frequency signal and converts the modulated transmission data to the radio frequency to obtain a transmission signal;
An in-phase detection circuit that combines an alternating current signal in phase and outputs a direct current and even harmonics;
A detection circuit for obtaining the amplitude level of the even harmonics;
A control circuit for controlling the alternating current signal so as to minimize the amplitude level;
The detection circuit is
A detector that generates and outputs a DC signal whose amplitude level is a DC voltage based on the even harmonics;
An LPF circuit that suppresses high frequency components included in the DC signal;
An amplification circuit for amplifying a suppressed DC signal in which the harmonic component is suppressed;
A comparator that compares the signal of the amplitude level of the amplified second harmonic with the reference voltage, and outputs the comparison result of the voltage of the detected signal of the second harmonic and a predetermined voltage,
The control circuit controls the AC signal according to the comparison result.
A semiconductor device,
An antenna for wirelessly transmitting the amplified transmission signal;
Wireless communication device comprising: