JP2019102153A - Light emitting device and display device - Google Patents

Light emitting device and display device Download PDF

Info

Publication number
JP2019102153A
JP2019102153A JP2017228807A JP2017228807A JP2019102153A JP 2019102153 A JP2019102153 A JP 2019102153A JP 2017228807 A JP2017228807 A JP 2017228807A JP 2017228807 A JP2017228807 A JP 2017228807A JP 2019102153 A JP2019102153 A JP 2019102153A
Authority
JP
Japan
Prior art keywords
electrode
light emitting
light
layer
emitting element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017228807A
Other languages
Japanese (ja)
Inventor
暢人 眞名垣
Nobuhito Managaki
暢人 眞名垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Display Inc
Original Assignee
Japan Display Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Display Inc filed Critical Japan Display Inc
Priority to JP2017228807A priority Critical patent/JP2019102153A/en
Priority to US16/180,116 priority patent/US10553657B2/en
Publication of JP2019102153A publication Critical patent/JP2019102153A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/50—OLEDs integrated with light modulating elements, e.g. with electrochromic elements, photochromic elements or liquid crystal elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/856—Arrangements for extracting light from the devices comprising reflective means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/858—Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/879—Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80518—Reflective anodes, e.g. ITO combined with thick metallic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/878—Arrangements for extracting light from the devices comprising reflective means

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

To provide a light emitting device excellent in color purity and luminous efficiency, a display device including the same, and a method of manufacturing them.SOLUTION: The light emitting device includes: a first electrode; a partition wall covering an end of the first electrode; an optical confinement layer in contact with a side surface of the partition wall and the first electrode; an electroluminescent layer located on the first electrode and in contact with the first electrode and the optical confinement layer; and a second electrode on the electroluminescent layer. Refractive index of the optical confinement layer is lower than refractive index of the electroluminescent layer.SELECTED DRAWING: Figure 1

Description

本発明の実施形態の一つは、発光素子、発光素子を含む表示装置、およびこれらの製造方法に関する。   One embodiment of the present invention relates to a light emitting element, a display including the light emitting element, and a method of manufacturing them.

表示装置の一例として、有機ＥＬ（Ｅｌｅｃｔｒｏｌｕｍｉｎｅｓｃｅｎｃｅ）表示装置が挙げられる。有機ＥＬ表示装置は、基板上に形成された複数の画素の各々に有機発光素子（以下、発光素子）を有している。発光素子は一対の電極（陰極、陽極）間に有機化合物を含む層（以下、ＥＬ層と記す）を有しており、一対の電極からＥＬ層に電流を供給することで駆動される。   As an example of the display device, an organic EL (Electroluminescence) display device can be mentioned. The organic EL display device has an organic light emitting element (hereinafter, light emitting element) in each of a plurality of pixels formed on a substrate. A light-emitting element has a layer containing an organic compound (hereinafter referred to as an EL layer) between a pair of electrodes (a cathode and an anode), and is driven by supplying current to the EL layer from the pair of electrodes.

発光素子の効率や発光色は、ＥＬ層の構造やＥＬ層に含まれる発光材料によって制御される。例えば、発光材料を適宜選択することによって種々の色の発光を得ることができる。また、発光素子内部、あるいは外部における光の干渉効果を利用することで発光波長を調整し、正面方向の発光強度を増大させることも可能である。特許文献１から３では、発光素子内に共振構造を構成し、これによって発光層から出射された発光を共振させ、発光強度や発光色の調整を行うことが開示されている。   The efficiency and luminescent color of the light emitting element are controlled by the structure of the EL layer and the light emitting material contained in the EL layer. For example, light emission of various colors can be obtained by appropriately selecting a light-emitting material. In addition, it is also possible to adjust the light emission wavelength and increase the light emission intensity in the front direction by utilizing the interference effect of light inside or outside the light emitting element. Patent Documents 1 to 3 disclose that a resonant structure is formed in a light emitting element, thereby resonating light emitted from the light emitting layer, and adjusting the light emission intensity and the light emission color.

特開２０１７−１１２０１１号公報Unexamined-Japanese-Patent No. 2017-112011 特開２０１７−６２９０２号公報JP, 2017-62902, A 特開２０１７−１０７１８１号公報JP, 2017-107181, A

本発明は、色純度と発光効率に優れた発光素子、およびこれを有する表示装置、ならびにこれらの作製方法を提供することを目的の一つとする。   An object of the present invention is to provide a light-emitting element excellent in color purity and luminous efficiency, a display device including the same, and a manufacturing method thereof.

本発明の実施形態の一つは発光素子である。この発光素子は、第１の電極、第１の電極の端部を覆う隔壁、隔壁の側面と第１の電極に接する光閉じ込め層、第１の電極の上に位置し、第１の電極と光閉じ込め層に接する電界発光層、および電界発光層の上の第２の電極を有する。光閉じ込め層の屈折率は、電界発光層の屈折率よりも低い。   One of the embodiments of the present invention is a light emitting element. The light emitting element includes a first electrode, a partition covering an end portion of the first electrode, an optical confinement layer in contact with a side surface of the partition and the first electrode, a first electrode, and the first electrode An electroluminescent layer in contact with the light confinement layer, and a second electrode over the electroluminescent layer. The refractive index of the light confinement layer is lower than the refractive index of the electroluminescent layer.

本発明の実施形態の一つは表示装置である。この表示装置は、第１の発光素子、第１の発光素子に隣接する第２の発光素子、および第１の発光素子と第２の発光素子の間の隔壁を有する。第１の発光素子と第２の発光素子はそれぞれ、隔壁に端部を覆われる第１の電極、隔壁の側面と第１の電極に接する光閉じ込め層、第１の電極の上に位置し、第１の電極と光閉じ込め層に接する電界発光層、および電界発光層の上の第２の電極を有する。第１の発光素子と第２の発光素子の各々において、光閉じ込め層の屈折率は、電界発光層の屈折率よりも低い。   One of the embodiments of the present invention is a display device. This display device has a first light emitting element, a second light emitting element adjacent to the first light emitting element, and a partition between the first light emitting element and the second light emitting element. The first light emitting element and the second light emitting element are respectively located on a first electrode whose end is covered with a partition, a light confinement layer in contact with the side surface of the partition and the first electrode, and the first electrode; An electroluminescent layer in contact with the first electrode and the light confinement layer, and a second electrode over the electroluminescent layer. In each of the first light emitting element and the second light emitting element, the refractive index of the light confinement layer is lower than the refractive index of the electroluminescent layer.

本発明の実施形態の一つは、発光素子である。この発光素子は、第１の電極、第１の電極の端部を覆う隔壁、隔壁の側面の少なくとも一部を覆う第１の光閉じ込め層、第１の光閉じ込め層と隔壁の間に位置し、第１の光閉じ込め層と隔壁に接する第２の光閉じ込め層、第１の電極の上に位置し、第１の電極と第１の光閉じ込め層に接する電界発光層、および電界発光層の上の第２の電極を有する。第２の光閉じ込め層の屈折率は、電界発光層の屈折率、および第１の光閉じ込め層の屈折率よりも低い。   One of the embodiments of the present invention is a light emitting element. The light emitting element is located between the first electrode, a partition covering the end of the first electrode, a first light confinement layer covering at least a part of the side surface of the partition, and the first light confinement layer and the partition A second light confinement layer in contact with the first light confinement layer and the partition wall; an electroluminescent layer located on the first electrode and in contact with the first electrode and the first light confinement layer; It has the upper second electrode. The refractive index of the second light confinement layer is lower than the refractive index of the electroluminescent layer and the refractive index of the first light confinement layer.

本発明の実施形態の一つは、表示装置である。この表示装置は、第１の発光素子、第１の発光素子に隣接する第２の発光素子、および第１の発光素子と第２の発光素子の間の隔壁を有する。第１の発光素子と第２の発光素子はそれぞれ、隔壁に端部を覆われる第１の電極、隔壁の側面の少なくとも一部を覆う第１の光閉じ込め層、第１の光閉じ込め層と隔壁の間に位置し、第１の光閉じ込め層と隔壁に接する第２の光閉じ込め層、第１の電極の上に位置し、第１の電極と第１の光閉じ込め層に接する電界発光層、および電界発光層の上の第２の電極を有する。第２の光閉じ込め層の屈折率は、電界発光層の屈折率、および第１の光閉じ込め層の屈折率よりも低い。   One of the embodiments of the present invention is a display device. This display device has a first light emitting element, a second light emitting element adjacent to the first light emitting element, and a partition between the first light emitting element and the second light emitting element. The first light emitting element and the second light emitting element respectively have a first electrode whose end is covered with a partition, a first light confinement layer covering at least a part of a side surface of the partition, a first light confinement layer, and a partition A second light confinement layer in contact with the first light confinement layer and the partition wall, an electroluminescent layer located on the first electrode and in contact with the first electrode and the first light confinement layer, And a second electrode over the electroluminescent layer. The refractive index of the second light confinement layer is lower than the refractive index of the electroluminescent layer and the refractive index of the first light confinement layer.

本発明の実施形態の表示素子の模式的上面図と断面図。BRIEF DESCRIPTION OF THE DRAWINGS Typical top view and sectional drawing of the display element of embodiment of this invention. 本発明の実施形態の表示素子の模式的断面図。Typical sectional drawing of the display element of embodiment of this invention. 本発明の実施形態の表示素子の模式的断面図。Typical sectional drawing of the display element of embodiment of this invention. 本発明の実施形態の表示素子の模式的断面図。Typical sectional drawing of the display element of embodiment of this invention. 本発明の実施形態の表示素子の模式的断面図。Typical sectional drawing of the display element of embodiment of this invention. 本発明の実施形態の表示装置の模式的上面図。FIG. 1 is a schematic top view of a display device according to an embodiment of the present invention. 本発明の実施形態の表示装置の画素の等価回路の一例。6 illustrates an example of an equivalent circuit of a pixel of a display device according to an embodiment of the present invention. 本発明の実施形態の表示装置の模式的断面図。BRIEF DESCRIPTION OF THE DRAWINGS Typical sectional drawing of the display apparatus of embodiment of this invention. 本発明の実施形態の表示装置の製造方法を説明する断面模式図。FIG. 5 is a schematic cross sectional view for explaining the method for manufacturing a display device of the embodiment of the present invention. 本発明の実施形態の表示装置の製造方法を説明する断面模式図。FIG. 5 is a schematic cross sectional view for explaining the method for manufacturing a display device of the embodiment of the present invention. 本発明の実施形態の表示装置の製造方法を説明する断面模式図。FIG. 5 is a schematic cross sectional view for explaining the method for manufacturing a display device of the embodiment of the present invention.

以下、本発明の各実施形態について、図面等を参照しつつ説明する。但し、本発明は、その要旨を逸脱しない範囲において様々な態様で実施することができ、以下に例示する実施形態の記載内容に限定して解釈されるものではない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in various modes without departing from the scope of the present invention, and the present invention is not interpreted as being limited to the description of the embodiments exemplified below.

図面は、説明をより明確にするため、実際の態様に比べ、各部の幅、厚さ、形状等について模式的に表される場合があるが、あくまで一例であって、本発明の解釈を限定するものではない。本明細書と各図において、既出の図に関して説明したものと同様の機能を備えた要素には、同一の符号を付して、重複する説明を省略することがある。   Although the drawings may be schematically represented with respect to the width, thickness, shape, etc. of each part in comparison with the actual embodiment in order to clarify the explanation, the drawings are merely an example, and the interpretation of the present invention is limited. It is not something to do. In the present specification and the drawings, elements having the same functions as those described with reference to the drawings in the drawings may be denoted by the same reference numerals, and overlapping descriptions may be omitted.

本発明において、ある一つの膜に対してエッチングや光照射を行って複数の膜を形成した場合、これら複数の膜は異なる機能、役割を有することがある。しかしながら、これら複数の膜は同一の工程で同一層として形成された膜に由来し、同一の層構造、同一の材料を有する。したがって、これら複数の膜は同一層に存在しているものと定義する。   In the present invention, when a plurality of films are formed by performing etching or light irradiation on a certain film, the plurality of films may have different functions and roles. However, the plurality of films are derived from the film formed as the same layer in the same step, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer.

本明細書および特許請求の範囲において、ある構造体の上に他の構造体を配置する態様を表現するにあたり、単に「上に」と表記する場合、特に断りの無い限りは、ある構造体に接するように、直上に他の構造体を配置する場合と、ある構造体の上方に、さらに別の構造体を介して他の構造体を配置する場合との両方を含むものとする。   In the present specification and claims, when expressing an aspect in which another structure is disposed on a certain structure, in the case where it is simply referred to as “above”, in a certain structure, unless otherwise specified. It includes both the case where another structure is arranged immediately above and the case where another structure is arranged above another structure via another structure so as to be in contact with each other.

（第１実施形態）
［１．基本構造］
図１（Ａ）と図１（Ｂ）にそれぞれ、本発明の実施形態の一つに係る発光素子１００の模式的上面図と断面図を示す。図１（Ａ）、図１（Ｂ）には、一つの発光素子１００とそれに隣接する発光素子１００の一部が示されており、図１（Ａ）の鎖線Ａ−Ａ´に沿った断面模式図が図１（Ｂ）である。見やすさを考慮し、図１（Ａ）では後述する第２の電極１１０、電界発光層（以下、ＥＬ層）１０８、および光閉じ込め層１０６の一部が図示されていない。図１（Ｂ）に示すように、発光素子１００は、第１の電極１０２、隔壁１０４、光閉じ込め層１０６、ＥＬ層１０８、および第２の電極１１０を備える。 First Embodiment
[1. Basic structure]
FIGS. 1A and 1B respectively show a schematic top view and a cross-sectional view of a light emitting device 100 according to one embodiment of the present invention. 1A and 1B show one light emitting element 100 and a part of the light emitting element 100 adjacent to the light emitting element 100, and a cross section taken along a dashed-dotted line A-A 'in FIG. 1A. A schematic diagram is FIG. 1 (B). For the sake of easy viewing, FIG. 1A does not illustrate a second electrode 110, an electroluminescent layer (hereinafter referred to as an EL layer) 108, and a part of the light confinement layer 106 which will be described later. As shown in FIG. 1B, the light emitting element 100 includes a first electrode 102, a partition wall 104, a light confinement layer 106, an EL layer 108, and a second electrode 110.

第１の電極は１０２は、ＥＬ層１０８にキャリア（ホール、電子）を注入し、かつ、ＥＬ層１０８から得られる発光を反射する機能を有する。第１の電極１０２は陽極、あるいは陰極として機能するが、以下、第１の電極１０２が陽極として、第２の電極１１０が陰極として機能する例を用いて発光素子１００の説明を行う。第１の電極１０２の構成は任意に選択することができるが、ホールを効率よくＥＬ層１０８に注入するため、その表面の仕事関数が高いことが好ましい。また、発光を反射することを考慮し、可視光に対して高い反射率を示すことが好ましい。したがって、例えばアルミニウムや銀などの高い反射率を有する金属や合金、およびインジウム−スズ酸化物（ＩＴＯ）やインジウム−亜鉛酸化物（ＩＺＯ）などの可視光を透過する導電性酸化物の積層構造を第１の電極１０２に適用することができる。例えば図１（Ｂ）に示すように、導電性酸化物を含む第１の導電層１０２ａ、第１の導電層１０２ａ上に位置し、上述した金属や合金を含む第２の導電層１０２ｂ、および、第２の導電層１０２ｂ上に位置し、導電性酸化物を含む第３の導電層１０２ｃの積層構造を第１の電極１０２の構造として採用することができる。この構造では、第３の導電層１０２ｃに含まれる導電性酸化物の高い仕事関数がホール注入に寄与する。また、第２の導電層１０２ｂの上面が反射面として寄与し、この反射面でＥＬ層１０８で得られる発光が反射する。   The first electrode 102 has a function of injecting carriers (holes and electrons) into the EL layer 108 and reflecting light emission obtained from the EL layer 108. The first electrode 102 functions as an anode or a cathode. Hereinafter, the light-emitting element 100 will be described using an example in which the first electrode 102 functions as an anode and the second electrode 110 functions as a cathode. The configuration of the first electrode 102 can be arbitrarily selected, but in order to efficiently inject holes into the EL layer 108, it is preferable that the work function of the surface be high. In addition, in consideration of reflection of light emission, it is preferable to exhibit high reflectance to visible light. Therefore, for example, a laminated structure of a metal or alloy having high reflectance such as aluminum or silver, and a conductive oxide transmitting visible light such as indium-tin oxide (ITO) or indium-zinc oxide (IZO) It can be applied to the first electrode 102. For example, as shown in FIG. 1B, a first conductive layer 102a containing a conductive oxide, a second conductive layer 102b located on the first conductive layer 102a and containing the above-described metal or alloy, and A stacked structure of a third conductive layer 102c containing a conductive oxide, which is located on the second conductive layer 102b, can be employed as a structure of the first electrode 102. In this structure, the high work function of the conductive oxide contained in the third conductive layer 102c contributes to hole injection. Further, the upper surface of the second conductive layer 102 b contributes as a reflective surface, and light emitted from the EL layer 108 is reflected by the reflective surface.

隔壁１０４はエポキシ樹脂やアクリル樹脂、ポリシロキサン樹脂、ポリエステル樹脂などの樹脂を含む絶縁膜であり、第１の電極１０２と接し、その端部を覆う（図１（Ａ）、図１（Ｂ））。換言すると、隔壁１０４は複数の開口を有し、その開口において第１の電極１０２が露出する。隔壁１０４の側面の傾斜は比較的急峻であることが好ましい。例えば、隔壁１０４の側面と、隔壁１０４の第１の電極１０２と接する底面とのなす角θ（図１（Ｂ）参照）は、６０°以上９０°未満、７０°以上９０°未満、あるいは８０°以上９０°未満としてもよい。隔壁１０４は光学的に均一になるよう構成される。すなわち、屈折率が隔壁１０４内の全体に亘って実質的に同一であり、光を散乱する構造（微小粒子、細孔など）を含まない。   The partition wall 104 is an insulating film containing a resin such as an epoxy resin, an acrylic resin, a polysiloxane resin, or a polyester resin, and is in contact with the first electrode 102 to cover an end portion (FIGS. 1A and 1B). ). In other words, the partition wall 104 has a plurality of openings in which the first electrode 102 is exposed. The slope of the side surface of the partition wall 104 is preferably relatively steep. For example, an angle θ (see FIG. 1B) between the side surface of the partition 104 and the bottom surface of the partition 104 in contact with the first electrode 102 is 60 ° or more and less than 90 °, 70 ° or more and less than 90 °, or 80 It may be more than 90 °. The partition 104 is configured to be optically uniform. That is, the refractive index is substantially the same throughout the inside of the partition wall 104, and does not include a light scattering structure (microparticles, pores, etc.).

光閉じ込め層１０６は絶縁膜であり、隔壁１０４の側面と接し、この側面の少なくとも一部を覆う。図１（Ｂ）では、光閉じ込め層１０６は隔壁１０４の側面と上面を覆うように設けられる例が示されている。この場合、光閉じ込め層１０６は隣接する発光素子１００に共有され、一方の発光素子１００から隣接する発光素子１００へ延伸するように設けられる。光閉じ込め層１０６は、その誘電率がＥＬ層１０８の誘電率よりも小さくなるよう構成することができ、例えば光閉じ込め層１０６とＥＬ層１０８の誘電率の差が０．２Ｆ／ｍ以上、あるいは０．３Ｆ／ｍ以上となるよう、光閉じ込め層１０６が形成される。より具体的には、光閉じ込め層１０６の誘電率は３．０Ｆ／ｍ以上５．０Ｆ／ｍ以下、あるいは３．０Ｆ／ｍ以上４．０Ｆ／ｍ以下とすることができる。あるいは、物質の屈折率の二乗が誘電率に比例することを考慮すると、光閉じ込め層１０６の屈折率がＥＬ層１０８の屈折率よりも小さくなるよう光閉じ込め層１０６を構成してもよく、例えば光閉じ込め層１０６とＥＬ層１０８の屈折率の差が０．２以上、あるいは０．３Ｆ／ｍ以上となるよう、光閉じ込め層１０６が形成される。より具体的には、光閉じ込め層１０６の屈折率を１．４以上１．６以下、あるいは１．４以上１．５以下とすることができる。このような材料として、ポリイミドやアクリル樹脂などの高分子が挙げられる。光閉じ込め層１０６と隔壁１０４がともにアクリル樹脂を含む場合、前者の誘電率や屈折率が後者のそれらよりも小さくなるよう、それぞれの材料が選択される。   The light confinement layer 106 is an insulating film, is in contact with the side surface of the partition wall 104, and covers at least a part of the side surface. In FIG. 1B, an example in which the light confinement layer 106 is provided to cover the side surface and the top surface of the partition wall 104 is shown. In this case, the light confinement layer 106 is shared by the adjacent light emitting elements 100 and provided so as to extend from one light emitting element 100 to the adjacent light emitting element 100. The light confinement layer 106 can be configured such that the dielectric constant thereof is smaller than the dielectric constant of the EL layer 108. For example, the difference between the dielectric constants of the light confinement layer 106 and the EL layer 108 is 0.2 F / m or more, or The light confinement layer 106 is formed to be 0.3 F / m or more. More specifically, the dielectric constant of the light confinement layer 106 can be 3.0 F / m or more and 5.0 F / m or less, or 3.0 F / m or more and 4.0 F / m or less. Alternatively, considering that the square of the refractive index of the substance is proportional to the dielectric constant, the light confinement layer 106 may be configured such that the refractive index of the light confinement layer 106 is smaller than the refractive index of the EL layer 108, for example The light confinement layer 106 is formed such that the difference in refractive index between the light confinement layer 106 and the EL layer 108 is 0.2 or more, or 0.3 F / m or more. More specifically, the refractive index of the light confinement layer 106 can be 1.4 or more and 1.6 or less, or 1.4 or more and 1.5 or less. Such materials include polymers such as polyimide and acrylic resin. When both the light confinement layer 106 and the partition wall 104 contain an acrylic resin, the respective materials are selected such that the former dielectric constant and refractive index are smaller than those of the latter.

あるいは、光閉じ込め層１０６は、屈折率が比較的低い材料としてフッ素を含有する高分子を含有してもよい。このような高分子としては、例えばポリテトラフルオロエチレンやポリフッ化ビニリデン、これらの誘導体、主鎖あるいは側鎖にフッ素を有するポリビニルエーテルやポリイミド、ポリメタクリル酸エステル、ポリアクリル酸エステル、ポリシロキサンなどが挙げられる。これらの高分子は分子内あるいは分子間で架橋していてもよい。   Alternatively, the light confinement layer 106 may contain a fluorine-containing polymer as a material having a relatively low refractive index. As such a polymer, for example, polytetrafluoroethylene or polyvinylidene fluoride, derivatives thereof, polyvinyl ether or polyimide having fluorine in the main chain or side chain, polymethacrylic acid ester, polyacrylic acid ester, polysiloxane etc. It can be mentioned. These polymers may be crosslinked intramolecularly or intermolecularly.

あるいは、光閉じ込め層１０６は、屈折率が比較的低い材料としてフッ化リチウム、フッ化マグネシウム、フッ化カルシウムなどの金属フッ化物、酸化ホウ素や酸化リンを含有する酸化ケイ素などの無機化合物を含有してもよい。   Alternatively, the light confinement layer 106 contains an inorganic compound such as lithium fluoride, magnesium fluoride, metal fluoride such as calcium fluoride, or silicon oxide containing boron oxide or phosphorus oxide as a material having a relatively low refractive index. May be

光閉じ込め層１０６の第１の電極１０２の表面に平行な方向の厚さ、すなわち、第１の電極１０２と接する面の幅Ｗ（図１（Ａ）、図１（Ｂ））参照）は、５０ｎｍ以上、２００ｎｍ以下となるよう、光閉じ込め層１０６を構成することができる。あるいは、幅ＷがＥＬ層１０８からの発光波長λの４分の一以下、すなわち、Ｗ≦λ／４となるよう、光閉じ込め層１０６を構成することができる。換言すると、Ｗが５０ｎｍ以上、λ／４以下となるように光閉じ込め層１０６を構成することができる。ここで発光波長とは、発光素子１００から得られる発光ピーク波長、あるいは後述するＥＬ層１０８に含まれる発光材料の発光ピーク波長である。   The thickness of the optical confinement layer 106 in the direction parallel to the surface of the first electrode 102, ie, the width W of the surface in contact with the first electrode 102 (see FIGS. 1A and 1B), The light confinement layer 106 can be configured to have a thickness of 50 nm or more and 200 nm or less. Alternatively, the light confinement layer 106 can be configured such that the width W is a quarter or less of the light emission wavelength λ from the EL layer 108, that is, W ≦ λ / 4. In other words, the light confinement layer 106 can be configured such that W is 50 nm or more and λ / 4 or less. Here, the light emission wavelength is a light emission peak wavelength obtained from the light emitting element 100 or a light emission peak wavelength of a light emitting material included in the EL layer 108 described later.

ＥＬ層１０８は、第１の電極１０２上に位置し、第１の電極１０２と光閉じ込め層１０６と接するように設けられる。図１（Ｂ）に示した例では、ＥＬ層１０８は光閉じ込め層１０６上に位置し、光閉じ込め層１０６の側面と上面に接する。本明細書と請求項では、ＥＬ層１０８とは、第１の電極１０２と第２の電極１１０によって挟持される膜を指す。   The EL layer 108 is provided on the first electrode 102 and provided so as to be in contact with the first electrode 102 and the light confinement layer 106. In the example shown in FIG. 1B, the EL layer 108 is located on the light confinement layer 106 and is in contact with the side surface and the top surface of the light confinement layer 106. In the present specification and claims, the EL layer 108 refers to a film sandwiched by the first electrode 102 and the second electrode 110.

ＥＬ層１０８の構成は任意であり、ホール注入層、ホール輸送層、発光層、電子輸送層、電子注入層、ホール阻止層、電子阻止層、励起子阻止層、電荷発生層などの機能層を適宜組み合わせてＥＬ層１０８が構成される。一つの機能層が複数の機能を有していてもよい。例えば発光材料を含む発光層が電子輸送層やホール輸送層を兼ねてもよい。また、各層は単一の材料、あるいは異なる材料の積層によって形成されていてもよい。ＥＬ層１０８の構造は隣接する発光素子１００間で同一でも良く、異なってもよい。例えば隣接する発光素子１００間で発光層に含まれる材料が異なるよう、複数の発光素子１００を構成してもよい。この場合、隣接する発光素子１００間で異なる発光色を得ることが可能である。図１（Ｂ）に示した例では、代表的な機能層として、ホール輸送層１０８ａ、発光層１０８ｂ、電子輸送層１０８ｃの三つの層が示されている。ここで、ＥＬ層１０８が複数の機能層によって構成されている場合、ＥＬ層１０８の誘電率や屈折率とは、それぞれＥＬ層１０８の全体の誘電率と屈折率を指す。   The configuration of the EL layer 108 is arbitrary, and functional layers such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, a hole blocking layer, an electron blocking layer, an exciton blocking layer, and a charge generation layer The EL layer 108 is formed by combining them as appropriate. One functional layer may have a plurality of functions. For example, a light emitting layer containing a light emitting material may double as an electron transporting layer or a hole transporting layer. Also, each layer may be formed of a single material or a lamination of different materials. The structure of the EL layer 108 may be the same or different between the adjacent light emitting elements 100. For example, the plurality of light emitting elements 100 may be configured such that the materials contained in the light emitting layer are different between the adjacent light emitting elements 100. In this case, it is possible to obtain different emission colors between the adjacent light emitting elements 100. In the example shown in FIG. 1B, three layers of a hole transport layer 108a, a light emitting layer 108b, and an electron transport layer 108c are shown as representative functional layers. Here, in the case where the EL layer 108 is configured of a plurality of functional layers, the dielectric constant and the refractive index of the EL layer 108 indicate the dielectric constant and the refractive index of the entire EL layer 108, respectively.

第２の電極１１０は、ＥＬ層１０８上に、ＥＬ層１０８に接するように設けられる。第２の電極１１０は可視光を一部反射し、一部透過する半透過半反射電極として構成され、ＥＬ層１０８に効率よく電子を注入できるよう、仕事関数が比較的低いことが好ましい。例えば第２の電極１１０は、マグネシウムやリチウム、銀、あるいはこれらの合金（Ｍｇ−Ａｇなど）を含み、可視光を一部透過可能な厚さで形成することができる。具体的な厚さは、５ｎｍから１００ｎｍの範囲で選択される。上記金属を含む膜上に、ＩＴＯやＩＺＯなどの可視光を透過可能な導電性酸化物を含む層をさらに積層しても良い。   The second electrode 110 is provided over the EL layer 108 so as to be in contact with the EL layer 108. The second electrode 110 is preferably configured as a semi-transmissive semi-reflective electrode that partially reflects visible light and partially transmits the same, and preferably has a relatively low work function so that electrons can be efficiently injected into the EL layer 108. For example, the second electrode 110 can include magnesium, lithium, silver, or an alloy thereof (such as Mg—Ag) and can be formed to a thickness that can partially transmit visible light. The specific thickness is selected in the range of 5 nm to 100 nm. A layer containing a conductive oxide capable of transmitting visible light, such as ITO or IZO, may be further stacked on the film containing the metal.

第１の電極１０２と第２の電極１１０間に電位差を与えることにより、前者からはホールが、後者からは電子がＥＬ層１０８へ注入される。ホールはホール輸送層１０８ａを経由して発光層１０８ｂへ輸送される。一方、電子は電子輸送層１０８ｃを経由して発光層１０８ｂへ輸送される。発光層１０８ｂ内でホールと電子が再結合し、発光層１０８ｂ内に含まれる発光材料の励起状態が形成される。この励起状態が基底状態に緩和する際、励起状態と基底状態のエネルギー差に相当する波長の光が放出され、発光素子１００からの発光として観測することができる。   By applying a potential difference between the first electrode 102 and the second electrode 110, holes are injected from the former and electrons are injected into the EL layer 108 from the latter. The holes are transported to the light emitting layer 108b via the hole transport layer 108a. On the other hand, electrons are transported to the light emitting layer 108 b via the electron transport layer 108 c. Holes and electrons recombine in the light emitting layer 108 b to form an excited state of the light emitting material contained in the light emitting layer 108 b. When the excited state is relaxed to the ground state, light of a wavelength corresponding to the energy difference between the excited state and the ground state is emitted and can be observed as light emission from the light emitting element 100.

［２．光学調整］
発光素子１００では、以下に説明するように、縦モードの共振構造と横モードの共振構造が形成される。 [2. Optical adjustment]
In the light emitting element 100, as described below, a longitudinal mode resonant structure and a transverse mode resonant structure are formed.

２−１．縦モード共振構造
図２（Ａ）に発光素子１００の一部の断面拡大図を示す。上述したように、第１の電極１０２は可視光を反射可能なように構成され、第２の電極１１０は可視光を一部透過し、一部反射するように構成される。このため、発光層１０８ｂから出射する光は、第１の電極１０２の反射面と第２の電極１１０の底面で反射し、共振する。すなわち、第１の電極１０２の反射面と第２の電極１１０の底面によって共振構造が形成される。この共振による干渉効果は、第１の電極１０２の反射面と第２の電極１１０の底面間の光学距離、および発光層１０８ｂからの発光のスペクトルによって決まる。反射面が第１の電極１０２の上面である場合、この光学距離は、ＥＬ層１０８の各機能層の屈折率と厚さの積の和である。上述したように、図２（Ａ）に示す例では、反射面は第２の導電層１０２ｂの上面となる。この場合、光学距離Ｌは、ＥＬ層１０８の各機能層の屈折率と厚さの積の和、および第３の導電層１０２ｃの屈折率と厚さの積との和である。この光学距離Ｌが、ＥＬ層１０８から得られる発光波長の４分の１（λ／４）の奇数倍と一致するようにＥＬ層１０８の構造や材料、第３の導電層１０２ｃの材料や厚さが適宜選択、調整される。このように光学距離Ｌが調整された場合、光学距離Ｌに合致する波長をもつ光は、第１の電極１０２の反射面と第２の電極１１０の底面間で反射を繰り返すことで干渉効果によって増幅され、一方、光学距離に合致しない波長の光は減衰する。その結果、発光素子１００から得られる発光の半値幅が小さくなり、色純度が向上するとともに、発光素子１００の正面方向における輝度、すなわち発光効率を増大することができる。 2-1. Longitudinal Mode Resonant Structure FIG. 2A shows an enlarged cross-sectional view of part of the light emitting element 100. As described above, the first electrode 102 is configured to be able to reflect visible light, and the second electrode 110 is configured to partially transmit visible light and partially reflect it. Therefore, light emitted from the light emitting layer 108 b is reflected by the reflection surface of the first electrode 102 and the bottom surface of the second electrode 110 and resonates. That is, a resonant structure is formed by the reflective surface of the first electrode 102 and the bottom surface of the second electrode 110. The interference effect due to this resonance is determined by the optical distance between the reflective surface of the first electrode 102 and the bottom surface of the second electrode 110, and the spectrum of light emission from the light emitting layer 108b. When the reflective surface is the upper surface of the first electrode 102, this optical distance is the sum of the product of the refractive index and thickness of each functional layer of the EL layer 108. As described above, in the example shown in FIG. 2A, the reflective surface is the upper surface of the second conductive layer 102b. In this case, the optical distance L is the sum of the product of the refractive index and the thickness of each functional layer of the EL layer 108, and the sum of the product of the refractive index and the thickness of the third conductive layer 102c. The structure or material of the EL layer 108, the material or thickness of the third conductive layer 102c, or the like so that the optical distance L coincides with an odd multiple of one fourth (λ / 4) of the emission wavelength obtained from the EL layer 108. Is appropriately selected and adjusted. When the optical distance L is adjusted in this manner, light having a wavelength that matches the optical distance L is repeatedly reflected between the reflective surface of the first electrode 102 and the bottom surface of the second electrode 110, thereby causing an interference effect. Amplified light, on the other hand, attenuates light of wavelengths that do not match the optical distance. As a result, the half width of light emission obtained from the light emitting element 100 can be reduced, the color purity can be improved, and the luminance in the front direction of the light emitting element 100, that is, the light emission efficiency can be increased.

２−２．横モード共振構造
図２（Ｂ）に、発光素子１００の一部の断面拡大図を示す。ここでは見やすさを考慮し、ＥＬ層１０８と第２の電極１１０は省略されている。上述した縦モード共振構造では、発光層１０８ｂから出射する光のうち、縦方向（すなわち、第１の電極１０２の上面の法線方向、およびこれに近い角度の方向）に出射する光は増幅されるが、横方向（第１の電極１０２の上面に平行な方向やこれに近い角度を有する方向）に出射する光を効果的に取り出すことができない。 2-2. Transverse Mode Resonant Structure FIG. 2B shows an enlarged cross-sectional view of part of the light emitting element 100. Here, the EL layer 108 and the second electrode 110 are omitted in consideration of easy viewing. In the longitudinal mode resonance structure described above, of the light emitted from the light emitting layer 108b, the light emitted in the vertical direction (that is, the direction normal to the upper surface of the first electrode 102 and the direction of an angle close thereto) is amplified. However, light emitted in the lateral direction (direction parallel to the top surface of the first electrode 102 or a direction close to this) can not be effectively extracted.

しかしながら、上述したように、発光素子１００には光閉じ込め層１０６が設けられる。光閉じ込め層１０６とＥＬ層１０８は屈折率、あるいは誘電率が互いに異なり、前者の屈折率や誘電率が後者のそれよりも小さい。このため、発光層１０８ｂから得られる光はＥＬ層１０８と光閉じ込め層１０６間の界面において反射する。さらに上述したように、光閉じ込め層１０６の幅Ｗは５０ｎｍ以上、２００ｎｍ以下となるよう、あるいは５０ｎｍ以上、λ／４以下となるように調整される。このため、発光層１０８ｂから出射した光の隔壁１０４へのしみ出しが効果的に抑制される。その結果、ＥＬ層１０８と光閉じ込め層１０６間の界面で反射を繰り返しても、横方向に進む光の損失が少ない。ここで、隔壁１０４の側面は第１の電極１０２の上面に対して傾いており、これに起因してＥＬ層１０８と光閉じ込め層１０６間の界面も第１の電極１０２の上面に対して傾く。したがって、光はこの界面で反射を繰り返すことで、進行方向が縦方向に徐々に近づき、第２の電極１１０の臨界角を超えた時に全反射せず、発光素子１００の外部に取り出される。このようなメカニズム（反射構造）により、発光層１０８ｂから得られる光を効率よく取り出すことが可能となり、高い発光効率を示す発光素子を提供することができる。   However, as described above, the light emitting device 100 is provided with the light confinement layer 106. The light confinement layer 106 and the EL layer 108 have different refractive indices or dielectric constants from each other, and the former has a smaller refractive index or dielectric constant than the latter. Therefore, light obtained from the light emitting layer 108 b is reflected at the interface between the EL layer 108 and the light confinement layer 106. Furthermore, as described above, the width W of the light confinement layer 106 is adjusted to be 50 nm or more and 200 nm or less, or 50 nm or more and λ / 4 or less. For this reason, the penetration of the light emitted from the light emitting layer 108 b to the partition wall 104 is effectively suppressed. As a result, even if reflection is repeated at the interface between the EL layer 108 and the light confinement layer 106, the loss of light traveling in the lateral direction is small. Here, the side surface of the partition wall 104 is inclined with respect to the upper surface of the first electrode 102, and the interface between the EL layer 108 and the light confinement layer 106 is also inclined with respect to the upper surface of the first electrode 102 due to this. . Therefore, light is repeatedly reflected at this interface, and the traveling direction gradually approaches in the longitudinal direction, and when the critical angle of the second electrode 110 is exceeded, it is not totally reflected but is extracted outside the light emitting element 100. With such a mechanism (reflection structure), light obtained from the light emitting layer 108 b can be efficiently extracted, and a light emitting element exhibiting high light emission efficiency can be provided.

なお、この時、互いに対向するＥＬ層１０８と光閉じ込め層１０６間の界面間の光学距離がλ／４の奇数倍と一致するように隔壁１０４の幅や側面の角度θ、第１の電極１０２の面積を調整してもよい。これにより、横方向においても共振による干渉効果によって発光が増幅され、発光素子１００から得られる発光の半値幅が減少し、色純度が向上するとともに、正面方向における輝度、すなわち発光効率を増大することができる。   At this time, the width of the partition 104 and the angle θ of the side face of the partition 104 are set so that the optical distance between the interface between the EL layer 108 and the light confinement layer 106 which are opposite to each other is equal to an odd multiple of λ / 4. You may adjust the area of As a result, the light emission is amplified also by the interference effect due to resonance even in the lateral direction, the half width of the light emission obtained from the light emitting element 100 is reduced, the color purity is improved, and the luminance in the front direction, that is, the light emission efficiency is increased. Can.

［３．変形例］
発光素子１００の構造は上述した構造に限られない。例えば図３（Ａ）に示すように、光閉じ込め層１０６は隔壁１０４の上面の少なくとも一部と接することなく、隣接する発光素子１００の光閉じ込め層１０６から離間していてもよい。この場合において、光閉じ込め層１０６は隔壁１０４の側面の少なくとも一部を覆い、ＥＬ層１０８が隔壁１０４の上面と接する。あるいは図３（Ｂ）に示すように、ＥＬ層１０８が隣接する発光素子１００間で互いに離間してもよい。この場合、第２の電極１１０は隔壁１０４や光閉じ込め層１０６と接してもよく、さらに図３（Ｃ）に示すように、ＥＬ層１０８の上面と隔壁１０４の上面、および光閉じ込め層１０６の上面が同一平面上に位置してもよい。 [3. Modified example]
The structure of the light emitting element 100 is not limited to the structure described above. For example, as shown in FIG. 3A, the light confinement layer 106 may be separated from the light confinement layer 106 of the adjacent light emitting element 100 without being in contact with at least a part of the top surface of the partition wall 104. In this case, the light confinement layer 106 covers at least a part of the side surface of the partition 104, and the EL layer 108 is in contact with the top surface of the partition 104. Alternatively, as shown in FIG. 3B, the EL layers 108 may be separated from each other between the light emitting elements 100 adjacent to each other. In this case, the second electrode 110 may be in contact with the partition wall 104 or the light confinement layer 106, and as shown in FIG. 3C, the top surface of the EL layer 108 and the top surface of the partition wall 104, and the light confinement layer 106. The upper surfaces may be located on the same plane.

上述したように、本実施形態の発光素子１００では、発光層１０８ｂから縦方向に出射される光が縦モードで共振して増幅されるだけでなく、横方向に出射される光が減衰することなく反射を繰り返し、最終的に発光素子１００から取り出すことができる。このため、発光素子１００は高い取出し効率を示す。また、主に縦モードにおける共振構造に起因し、発光素子１００は色純度の高い光を高効率で与えることが可能である。   As described above, in the light emitting element 100 of the present embodiment, light emitted in the longitudinal direction from the light emitting layer 108 b is not only resonated and amplified in the longitudinal mode, but also light emitted in the lateral direction is attenuated. It can be repeatedly extracted from the light emitting element 100 finally. For this reason, the light emitting element 100 exhibits high extraction efficiency. In addition, mainly due to the resonant structure in the longitudinal mode, the light-emitting element 100 can give light with high color purity with high efficiency.

（第２実施形態）
本実施形態では、発光素子１００と構造が異なる発光素子１２０を説明する。第１実施形態と同様、あるいは類似する構成に関しては説明を割愛することがある。 Second Embodiment
In this embodiment, a light emitting element 120 having a structure different from that of the light emitting element 100 will be described. Description of the same or similar configuration as that of the first embodiment may be omitted.

図４（Ａ）に発光素子１２０の断面模式図を示す。この断面模式図は図１（Ｂ）の断面に対応する。図４（Ａ）に示すように、発光素子１２０は積層された二つの光閉じ込め層を有する点で発光素子１００と異なる。より具体的には、発光素子１２０は、隔壁１０４の側面の少なくとも一部を覆う第１の光閉じ込め層１２２、および、第１の光閉じ込め層１２２と隔壁１０４の間に挟まれ、これらと接する第２の光閉じ込め層１２４を有する点で発光素子１００と異なる。   FIG. 4A is a schematic cross-sectional view of the light emitting element 120. FIG. This schematic cross-sectional view corresponds to the cross-section of FIG. 1 (B). As shown in FIG. 4A, the light emitting element 120 differs from the light emitting element 100 in that the light emitting element 120 includes two stacked light confinement layers. More specifically, the light emitting element 120 is sandwiched between and in contact with the first light confinement layer 122 covering at least a part of the side surface of the partition 104 and the first light confinement layer 122 and the partition 104. It differs from the light emitting element 100 in that the second light confinement layer 124 is provided.

第１の光閉じ込め層１２２は、その誘電率がＥＬ層１０８の誘電率と同一、あるいは近くなるよう構成される。具体的には、第１の光閉じ込め層１２２とＥＬ層１０８の誘電率の差は、０．２Ｆ／ｍ未満となるよう、第１の光閉じ込め層１２２が設けられる。あるいは、第１の光閉じ込め層１２２の屈折率がＥＬ層１０８の屈折率と同一、あるいは近くなるよう、第１の光閉じ込め層１２２が構成される。具体的には、第１の光閉じ込め層１２２の屈折率は１．６よりも大きく、１．９よりも低い。   The first light confinement layer 122 is configured such that its dielectric constant is the same as or close to the dielectric constant of the EL layer 108. Specifically, the first light confinement layer 122 is provided such that the difference between the dielectric constants of the first light confinement layer 122 and the EL layer 108 is less than 0.2 F / m. Alternatively, the first light confinement layer 122 is configured such that the refractive index of the first light confinement layer 122 is the same as or close to the refractive index of the EL layer 108. Specifically, the refractive index of the first light confinement layer 122 is greater than 1.6 and less than 1.9.

一方、第２の光閉じ込め層１２４は、第１実施形態の光閉じ込め層１０６に対応し、ＥＬ層１０８や第１の光閉じ込め層１２２よりも誘電率や屈折率が低い。具体的には、第２の光閉じ込め層１２４の誘電率は、ＥＬ層１０８や第１の光閉じ込め層１２２の誘電率と比較して０．２Ｆ／ｍ以上、あるいは０．３Ｆ／ｍ以上低く、具体的には、３．０Ｆ／ｍ以上５．０Ｆ／ｍ以下、あるいは３．０Ｆ／ｍ以上４．０Ｆ／ｍ以下とすることができる。第２の光閉じ込め層１２４の屈折率は、ＥＬ層１０８や第１の光閉じ込め層１２２の屈折率と比較して０．２以上、あるいは０．３Ｆ／ｍ以上低く、具体的には１．４以上１．６以下、あるいは１．４以上１．５以下とすることができる。具体的な材料としては、第１実施形態の光閉じ込め層１０６で使用可能な材料を第２の光閉じ込め層１２４に用いることができる。また、光閉じ込め層１０６と同様、第２の光閉じ込め層１２４は、第１の電極１０２の表面に平行な方向の厚さ、すなわち、第１の電極１０２と接する面の幅Ｗ2（図４（Ａ）参照）は５０ｎｍ以上であり、かつ２００ｎｍ以下、あるいは、λ／４以下となるよう構成される。なお、第１の光閉じ込め層１２２の第１の電極１０２の表面に平行な方向の厚さ、すなわち、第１の電極１０２と接する面の幅Ｗ1（図４（Ａ）参照）は、幅Ｗ1と幅Ｗ2の和がλ／４よりも大きく、λ以下となるよう調整される。 On the other hand, the second light confinement layer 124 corresponds to the light confinement layer 106 in the first embodiment, and has a lower dielectric constant and refractive index than the EL layer 108 and the first light confinement layer 122. Specifically, the dielectric constant of the second light confinement layer 124 is lower than that of the EL layer 108 or the first light confinement layer 122 by 0.2 F / m or more, or 0.3 F / m or more. Specifically, it can be 3.0 F / m or more and 5.0 F / m or less, or 3.0 F / m or more and 4.0 F / m or less. The refractive index of the second light confinement layer 124 is 0.2 or more, or 0.3 F / m or more lower than the refractive index of the EL layer 108 or the first light confinement layer 122, and more specifically, It can be 4 or more and 1.6 or less, or 1.4 or more and 1.5 or less. As a specific material, a material that can be used in the light confinement layer 106 of the first embodiment can be used for the second light confinement layer 124. Also, like the light confinement layer 106, the second light confinement layer 124 has a thickness in a direction parallel to the surface of the first electrode 102, that is, a width W 2 of the surface in contact with the first electrode 102 (FIG. (A)) is configured to be 50 nm or more and 200 nm or less, or λ / 4 or less. Note that the thickness of the first light confinement layer 122 in the direction parallel to the surface of the first electrode 102, that is, the width W 1 of the surface in contact with the first electrode 102 (see FIG. 4A) has a width The sum of W 1 and width W 2 is adjusted to be larger than λ / 4 and smaller than λ.

図４（Ａ）に示す発光素子１２０では、第１の光閉じ込め層１２２と第２の光閉じ込め層１２４は、いずれも隣接する発光素子１００に共有され、一方の発光素子１００から隣接する発光素子１００へ延伸するように設けられる。しかしながら発光素子１２０の構造はこれに限られず、例えば図４（Ｂ）に示すように、第２の光閉じ込め層１２４は隣接する発光素子１００間で離間してもよい。この場合、第１の光閉じ込め層１２２は隔壁１０４の上面と接してもよい。あるいは図４（Ｃ）に示すように、第１の光閉じ込め層１２２も隣接する発光素子１００間で離間してもよい。この場合、ＥＬ層１０８が隔壁１０４の上面と接する。あるいは図５（Ａ）から図５（Ｃ）に示すように、ＥＬ層１０８は隣接する発光素子１００間で互いに離間してもよい。この場合、図５（Ａ）や図５（Ｂ）に示すように、第２の電極１１０は第１の光閉じ込め層１２２と接してもよく、図５（Ｃ）に示すように隔壁１０４、第１の光閉じ込め層１２２、および第２の光閉じ込め層１２４と接してもよい。さらに、ＥＬ層１０８の上面と第１の光閉じ込め層１２２の上面が同一平面上に位置してもよく（図５（Ｂ）、ＥＬ層１０８、第１の光閉じ込め層１２２、および第２の光閉じ込め層１２４の上面の全てが同一平面上に位置してもよい。   In the light emitting element 120 shown in FIG. 4A, the first light confinement layer 122 and the second light confinement layer 124 are both shared by the adjacent light emitting element 100, and one light emitting element 100 is adjacent to the light emitting element It is provided to extend to 100. However, the structure of the light emitting element 120 is not limited to this. For example, as shown in FIG. 4B, the second light confinement layers 124 may be separated between the adjacent light emitting elements 100. In this case, the first light confinement layer 122 may be in contact with the top surface of the partition wall 104. Alternatively, as shown in FIG. 4C, the first light confinement layer 122 may also be separated between the adjacent light emitting elements 100. In this case, the EL layer 108 is in contact with the top surface of the partition wall 104. Alternatively, as shown in FIGS. 5A to 5C, the EL layers 108 may be separated from each other between the light emitting elements 100 adjacent to each other. In this case, as shown in FIG. 5A and FIG. 5B, the second electrode 110 may be in contact with the first light confinement layer 122, and as shown in FIG. It may be in contact with the first light confinement layer 122 and the second light confinement layer 124. Furthermore, the top surface of the EL layer 108 and the top surface of the first light confinement layer 122 may be located on the same plane (FIG. 5B, the EL layer 108, the first light confinement layer 122, and the second light confinement layer). All of the top surfaces of the light confinement layer 124 may be coplanar.

上述した構成では、発光層１０８ｂから横方向に出射される光は、第１の光閉じ込め層１２２と第２の光閉じ込め層１２４間の界面で反射する。また、第２の光閉じ込め層１２４の厚さＷ2が小さいため、第２の光閉じ込め層１２４からの光のしみ出しが起こりにくい。したがって、発光素子１００と同様、縦モードでの共振による発光効率の増大とともに、横方向の光も効率よく発光素子１００から取り出すことができる。このため、本実施形態を適用することで、色純度と発光効率が高い発光素子を提供することが可能である。 In the configuration described above, light emitted laterally from the light emitting layer 108 b is reflected at the interface between the first light confinement layer 122 and the second light confinement layer 124. In addition, since the thickness W2 of the second light confinement layer 124 is small, the penetration of light from the second light confinement layer 124 hardly occurs. Therefore, as in the light emitting element 100, light in the lateral direction can be efficiently extracted from the light emitting element 100 as well as the light emission efficiency is increased by the resonance in the longitudinal mode. For this reason, by applying this embodiment, it is possible to provide a light emitting element with high color purity and light emission efficiency.

（第３実施形態）
本実施形態では、図１（Ａ）、図１（Ｂ）に示した発光素子１００を有する表示装置１３０とその作製方法を説明する。第１、第２実施形態と同様、あるいは類似する構成に関しては説明を割愛することがある。 Third Embodiment
In this embodiment mode, a display device 130 including the light-emitting element 100 illustrated in FIGS. 1A and 1B and a manufacturing method thereof are described. The same or similar configuration as the first and second embodiments may not be described.

［１．全体構造］
図６に表示装置１３０の上面模式図を示す。表示装置１３０は基板１３２を有し、その上にパターニングされた種々の絶縁膜、半導体膜、導電膜を有する。これらの膜を適宜組み合わせることにより、複数の画素１３４や画素１３４を駆動するための駆動回路（走査線側駆動回路１３８、信号線側駆動回路１４０）が形成される。各画素１３４は色情報を与える最小単位であり、後述するように表示素子を駆動するための画素回路を含む領域である。複数の画素１３４は周期的に配置され、表示領域１３６を定義する。 [1. Overall structure]
The upper surface schematic diagram of the display apparatus 130 is shown in FIG. The display device 130 has a substrate 132 and has various insulating films, semiconductor films, and conductive films patterned thereon. By appropriately combining these films, driver circuits (a scan line driver circuit 138 and a signal line driver circuit 140) for driving the plurality of pixels 134 and the pixels 134 are formed. Each pixel 134 is a minimum unit for giving color information, and is an area including a pixel circuit for driving a display element as described later. The plurality of pixels 134 are periodically arranged to define a display area 136.

走査線側駆動回路１３８や信号線側駆動回路１４０は、表示領域１３６の周辺に配置される。表示領域１３６や走査線側駆動回路１３８、信号線側駆動回路１４０からは配線１４２が基板１３２の一辺へ延び、配線１４２は基板１３２の端部付近で露出されて端子（図示しない）を形成する。配線１４２は端子を介してフレキシブル印刷回路基板（ＦＰＣ）などのコネクタ１４４と電気的に接続される。ここで示した例では、半導体基板上に形成された集積回路を有する駆動ＩＣ１４６がコネクタ１４４上にさらに搭載される。駆動ＩＣ１４６やコネクタ１４４介して外部回路（図示せず）から映像信号や電源が供給され、配線１４２によって、走査線側駆動回路１３８、信号線側駆動回路１４０を介して各画素１３４に伝送される。これらの映像信号や電源に基づいて画素１３４が制御、駆動され、表示領域１３６上に映像が表示される。駆動回路や駆動ＩＣ１４６の態様については図６に示す態様に限られず、例えば駆動ＩＣ１４６は基板１３２上に実装されてもよく、信号線側駆動回路１４０の機能が駆動ＩＣ１４６に統合されていても良い。   The scanning line side drive circuit 138 and the signal line side drive circuit 140 are arranged around the display area 136. Wiring 142 extends to one side of the substrate 132 from the display area 136, the scanning line drive circuit 138, and the signal line drive circuit 140, and the wiring 142 is exposed near the end of the substrate 132 to form a terminal (not shown). . The wiring 142 is electrically connected to a connector 144 such as a flexible printed circuit (FPC) via a terminal. In the example shown here, a drive IC 146 having an integrated circuit formed on a semiconductor substrate is further mounted on the connector 144. Video signals and power are supplied from an external circuit (not shown) through the drive IC 146 and the connector 144, and are transmitted to the pixels 134 through the scanning line driver circuit 138 and the signal line driver circuit 140 by the wiring 142. . The pixels 134 are controlled and driven based on these video signals and power sources, and a video is displayed on the display area 136. The mode of the drive circuit and the drive IC 146 is not limited to the mode shown in FIG. 6. For example, the drive IC 146 may be mounted on the substrate 132 and the function of the signal line side drive circuit 140 may be integrated into the drive IC 146 .

［２．画素の構造］
２−１．画素回路
上述したように、各画素１３４には、パターニングされた種々の絶縁膜や半導体膜、導電膜によって発光素子１００を含む画素回路が形成される。画素回路の構成は任意に選択することができ、その一例を等価回路として図７に示す。 [2. Pixel structure]
2-1. Pixel Circuit As described above, in each pixel 134, a pixel circuit including the light emitting element 100 is formed of various patterned insulating films, semiconductor films, and conductive films. The configuration of the pixel circuit can be arbitrarily selected, and an example thereof is shown in FIG. 7 as an equivalent circuit.

図７の等価回路で示す画素回路は、発光素子１００に加え、駆動トランジスタ１７２、発光制御トランジスタ１８０、補正トランジスタ１７８、初期化トランジスタ１７４、書込トランジスタ１７６、保持容量１８４、付加容量１８６を有している。容量１８８は独立した容量素子ではなく、発光素子１００の寄生容量である。高電位電源線１５０には高電位ＰＶＤＤが与えられ、この電位が電流供給線１５２を介して各列に接続される画素１３４に供給される。発光素子１００、駆動トランジスタ１７２、発光制御トランジスタ１８０、補正トランジスタ１７８は、高電位電源線１５０と低電位電源線１５４との間で直列に接続される。低電位電源線１５４には低電位ＰＶＳＳが与えられる。   A pixel circuit shown by the equivalent circuit in FIG. 7 includes a drive transistor 172, a light emission control transistor 180, a correction transistor 178, an initialization transistor 174, a write transistor 176, a storage capacitor 184, and an additional capacitor 186 in addition to the light emitting element 100. ing. The capacitance 188 is not an independent capacitance element but a parasitic capacitance of the light emitting element 100. The high potential power supply line 150 is supplied with the high potential PVDD, and the potential is supplied to the pixels 134 connected to each column through the current supply line 152. The light emitting element 100, the drive transistor 172, the light emission control transistor 180, and the correction transistor 178 are connected in series between the high potential power supply line 150 and the low potential power supply line 154. Low potential power supply line 154 is supplied with low potential PVSS.

駆動トランジスタ１７２の一方の端子は発光制御トランジスタ１８０と補正トランジスタ１７８を介して高電位電源線１５０と電気的に接続され、他方の端子は発光素子１００と電気的に接続される。駆動トランジスタ１７２のゲートは、初期化トランジスタ１７４を介して第１の信号線１５６と電気的に接続されるとともに、書込トランジスタ１７６を介して第２の信号線１５８と電気的に接続される。第１の信号線１５６には初期化信号Ｖｉｎｉが与えられ、第２の信号線１５８には映像信号Ｖｓｉｇが与えられる。初期化信号Ｖｉｎｉは一定レベルの初期化電位を与える信号である。書込トランジスタ１７６は、そのゲートに接続される書込制御走査線１６０に与えられる走査信号ＳＧによって動作（オン／オフ）が制御される。初期化トランジスタ１７４のゲートは、初期化制御信号ＩＧが与えられる初期化制御走査線１６２と接続され、初期化制御信号ＩＧにより動作が制御される。書込トランジスタ１７６がオン、初期化トランジスタ１７４がオフのとき、映像信号Ｖｓｉｇの電位が駆動トランジスタ１７２のゲートに与えられる。一方、書込トランジスタ１７６がオフ、初期化トランジスタ１７４がオンのとき、初期化信号Ｖｉｎｉの電位が駆動トランジスタ１７２のゲートに与えられる。   One terminal of the drive transistor 172 is electrically connected to the high potential power supply line 150 via the light emission control transistor 180 and the correction transistor 178, and the other terminal is electrically connected to the light emitting element 100. The gate of the drive transistor 172 is electrically connected to the first signal line 156 through the initialization transistor 174 and electrically connected to the second signal line 158 through the write transistor 176. The initialization signal Vini is applied to the first signal line 156, and the video signal Vsig is applied to the second signal line 158. The initialization signal Vini is a signal giving an initialization potential of a fixed level. Write transistor 176 has its operation (on / off) controlled by scan signal SG applied to write control scan line 160 connected to its gate. The gate of the initialization transistor 174 is connected to an initialization control scan line 162 to which an initialization control signal IG is applied, and the operation is controlled by the initialization control signal IG. When the write transistor 176 is on and the initialization transistor 174 is off, the potential of the video signal Vsig is applied to the gate of the drive transistor 172. On the other hand, when the write transistor 176 is off and the initialization transistor 174 is on, the potential of the initialization signal Vini is applied to the gate of the drive transistor 172.

補正トランジスタ１７８と発光制御トランジスタ１８０のゲートにはそれぞれ、補正制御信号ＣＧが印加される補正制御走査線１６４、発光制御信号ＢＧが印加される発光制御走査線１６８が接続される。駆動トランジスタ１７２の一方の端子には、補正トランジスタ１７８を介し、リセット制御線１６６が接続される。リセット制御線１６６は、走査線側駆動回路１３８に設けられるリセットトランジスタ１８２と接続される。リセットトランジスタ１８２はリセット制御信号ＲＧによって制御され、これによりリセット信号線１７０に与えられるリセット電位Ｖｒｓｔを補正トランジスタ１７８を介して駆動トランジスタ１７２の一方の端子に印加することができる。   The correction control scanning line 164 to which the correction control signal CG is applied and the light emission control scanning line 168 to which the light emission control signal BG is applied are connected to the gates of the correction transistor 178 and the light emission control transistor 180, respectively. The reset control line 166 is connected to one terminal of the drive transistor 172 via the correction transistor 178. The reset control line 166 is connected to a reset transistor 182 provided in the scan line driver circuit 138. The reset transistor 182 is controlled by the reset control signal RG, whereby the reset potential Vrst applied to the reset signal line 170 can be applied to one terminal of the drive transistor 172 via the correction transistor 178.

駆動トランジスタ１７２の他方の端子とゲートとの間には、保持容量１８４が設けられる。付加容量１８６の一方の端子は駆動トランジスタ１７２の他方の端子に接続され、他方の端子が高電位電源線１５０に接続される。付加容量１８６は、他方の端子が低電位電源線１５４に接続されるように設けてもよい。保持容量１８４と付加容量１８６は、映像信号Ｖｓｉｇを駆動トランジスタ１７２のゲートに与えるとき、映像信号Ｖｓｉｇに応じたゲート−ソース間電圧Ｖｇｓを保持するために設けられる。   A storage capacitor 184 is provided between the other terminal of the drive transistor 172 and the gate. One terminal of the additional capacitor 186 is connected to the other terminal of the drive transistor 172, and the other terminal is connected to the high potential power supply line 150. The additional capacitance 186 may be provided such that the other terminal is connected to the low potential power supply line 154. The storage capacitor 184 and the additional capacitor 186 are provided to hold the gate-source voltage Vgs according to the video signal Vsig when the video signal Vsig is applied to the gate of the drive transistor 172.

信号線側駆動回路１４０は、第１の信号線１５６と第２の信号線１５８に初期化信号Ｖｉｎｉと映像信号Ｖｓｉｇをそれぞれ出力する。一方、走査線側駆動回路１３８は書込制御走査線１６０に走査信号ＳＧを出力し、初期化制御走査線１６２に初期化制御信号ＩＧを出力し、補正制御走査線１６４に補正制御信号ＣＧを出力し、発光制御走査線１６８に発光制御信号ＢＧを出力し、リセットトランジスタ１８２のゲートにリセット制御信号ＲＧを出力する。   The signal line side drive circuit 140 outputs the initialization signal Vini and the video signal Vsig to the first signal line 156 and the second signal line 158, respectively. On the other hand, the scanning line drive circuit 138 outputs the scanning signal SG to the write control scanning line 160, outputs the initialization control signal IG to the initialization control scanning line 162, and outputs the correction control signal CG to the correction control scanning line 164. The light emission control signal BG is output to the light emission control scanning line 168, and the reset control signal RG is output to the gate of the reset transistor 182.

２−２．断面構造
図８に表示装置１３０の模式的断面図を示す。図８では、基板１３２上に形成された隣接する三つの画素１３４の画素回路のうち、駆動トランジスタ１７２、保持容量１８４、付加容量１８６、発光素子１００の断面構造が示されている。 2-2. Cross-Sectional Structure FIG. 8 shows a schematic cross-sectional view of the display device 130. As shown in FIG. In FIG. 8, among the pixel circuits of three adjacent pixels 134 formed on the substrate 132, the cross-sectional structure of the drive transistor 172, the storage capacitor 184, the additional capacitor 186, and the light emitting element 100 is shown.

画素回路に含まれる各素子はアンダーコート１９０を介し、基板１３２上に設けられる。基板１３２はガラスや石英、あるいはプラスチックを含むことができる。プラスチックを用いることで基板１３２に可撓性を付与することができる。プラスチックとしては、ポリイミドやポリアミド、ポリエステル、ポリカルボナートなどの高分子が挙げられ、中でも耐熱性の高いポリイミドが好適である。   Each element included in the pixel circuit is provided on the substrate 132 via the undercoat 190. The substrate 132 can include glass, quartz, or plastic. By using a plastic, the substrate 132 can have flexibility. Examples of the plastic include polymers such as polyimide, polyamide, polyester, polycarbonate and the like, and among them, polyimide having high heat resistance is preferable.

アンダーコート１９０は図８に示すように単層構造を有していてもよく、複数の膜から構成されていてもよい。複数の膜を用いる場合、酸化シリコンを含む膜、窒化シリコンを含む膜、および酸化シリコンを含む膜を含む膜を順次基板１３２上に形成すればよい。   The undercoat 190 may have a single layer structure as shown in FIG. 8 or may be composed of a plurality of films. In the case of using a plurality of films, a film containing silicon oxide, a film containing silicon nitride, and a film containing a film containing silicon oxide may be sequentially formed over the substrate 132.

駆動トランジスタ１７２は、半導体膜１９２、ゲート絶縁膜１９４、ゲート電極１９６、ソース／ドレイン電極２００、２０２を含む。ゲート絶縁膜１９４はゲート電極１９６と半導体膜１９２によって挟まれる。ゲート電極１９６は、ゲート絶縁膜１９４を介して半導体膜１９２の少なくとも一部と交差するように配置され、半導体膜１９２のゲート電極１９６が重なる領域にチャネル領域１９２ａが形成される。半導体膜１９２はさらに、チャネル領域１９２ａを挟持し、不純物がドープされた低濃度不純物領域１９２ｃ、およびこれらを挟持し、不純物がドープされたソース／ドレイン領域１９２ｂを有する。低濃度不純物領域１９２ｃの不純物の濃度は、ソース／ドレイン領域１９２ｂのそれよりも低い。図８に示した例では駆動トランジスタ１７２はトップゲート型のトランジスタであるが、画素回路に含まれるトランジスタの構造に制約は無く、ボトムゲート型トランジスタでも良い。また、ソース／ドレイン電極２００、２０２と半導体膜１９２との上下関係にも制約は無い。   The driving transistor 172 includes a semiconductor film 192, a gate insulating film 194, a gate electrode 196, and source / drain electrodes 200 and 202. The gate insulating film 194 is sandwiched between the gate electrode 196 and the semiconductor film 192. The gate electrode 196 is disposed to intersect at least a part of the semiconductor film 192 with the gate insulating film 194 interposed therebetween, and a channel region 192 a is formed in a region where the gate electrode 196 of the semiconductor film 192 overlaps. The semiconductor film 192 further includes a channel region 192a, a low concentration impurity region 192c doped with impurities, and a source / drain region 192b doped with impurities. The impurity concentration of the low concentration impurity region 192c is lower than that of the source / drain region 192b. In the example shown in FIG. 8, the drive transistor 172 is a top gate type transistor, but there is no limitation on the structure of the transistor included in the pixel circuit, and a bottom gate type transistor may be used. In addition, there is no restriction on the vertical relationship between the source / drain electrodes 200 and 202 and the semiconductor film 192.

ゲート絶縁膜１９４を介し、ゲート電極１９６と同一の層に存在する容量電極２０４が一方のソース／ドレイン領域１９２ｂと重なるように設けられる。ゲート電極１９６、容量電極２０４の上には層間膜１９８が設けられる。層間膜１９８とゲート絶縁膜１９４には、半導体膜１９２に達する開口が形成され、この開口を覆うようにソース／ドレイン電極２００、２０２が配置される。ソース／ドレイン電極２０２の一部は、層間膜１９８を介してソース／ドレイン領域１９２ｂの一部と容量電極２０４と重なり、ソース／ドレイン領域１９２ｂの一部、ゲート絶縁膜１９４の一部、容量電極２０４、層間膜１９８、およびソース／ドレイン電極２０２の一部によって保持容量１８４が形成される。   A capacitor electrode 204 present in the same layer as the gate electrode 196 is provided to overlap with one of the source / drain regions 192 b through the gate insulating film 194. An interlayer film 198 is provided on the gate electrode 196 and the capacitor electrode 204. An opening reaching the semiconductor film 192 is formed in the interlayer film 198 and the gate insulating film 194, and the source / drain electrodes 200 and 202 are disposed so as to cover the opening. A part of source / drain electrode 202 overlaps with a part of source / drain region 192 b and capacitance electrode 204 via interlayer film 198, a part of source / drain region 192 b, a part of gate insulating film 194, a capacitance electrode A storage capacitor 184 is formed by the portion 204, the interlayer film 198, and the source / drain electrode 202.

駆動トランジスタ１７２や保持容量１８４の上にはさらに平坦化膜２０６が設けられる。平坦化膜２０６は、ソース／ドレイン電極２０２に達する開口を有し、この開口と平坦化膜２０６の上面の一部を覆う接続電極２０８がソース／ドレイン電極２０２と接するように設けられる。平坦化膜２０６上にはさらに付加容量電極２１０が設けられる。接続電極２０８や付加容量電極２１０は同時に形成してもよく、異なる材料を有するように異なる工程で形成してもよい。前者の場合、接続電極２０８や付加容量電極２１０は同一の層に存在し、同一の組成を有する。   A planarization film 206 is further provided on the driving transistor 172 and the storage capacitor 184. The planarization film 206 has an opening reaching the source / drain electrode 202, and a connection electrode 208 covering the opening and a part of the top surface of the planarization film 206 is provided in contact with the source / drain electrode 202. An additional capacitance electrode 210 is further provided on the planarization film 206. The connection electrode 208 and the additional capacitance electrode 210 may be formed at the same time, or may be formed in different steps so as to have different materials. In the former case, the connection electrode 208 and the additional capacitance electrode 210 exist in the same layer and have the same composition.

接続電極２０８と付加容量電極２１０を覆うように付加容量絶縁膜２１２が形成される。付加容量絶縁膜２１２は、平坦化膜２０６の開口では接続電極２０８の一部を覆わず、接続電極２０８の底面を露出する。これにより、接続電極２０８を介し、その上に設けられる第１の電極１０２とソース／ドレイン電極２０２間の電気的接続が可能となる。付加容量絶縁膜２１２には、その上に設けられる隔壁１０４と平坦化膜２０６の接触を許容するための開口２１４を設けてもよい。接続電極２０８や開口２１４の形成は任意である。接続電極２０８を設けることにより、その後のプロセスにおいてソース／ドレイン電極２０２の表面の腐食を防止することができ、ソース／ドレイン電極２０２のコンタクト抵抗の増大を防止することができる。開口２１４を通して平坦化膜２０６中の不純物を除去することができ、これによって画素回路や発光素子１００の信頼性を向上させることができる。   An additional capacitance insulating film 212 is formed to cover the connection electrode 208 and the additional capacitance electrode 210. The additional capacitance insulating film 212 does not cover a part of the connection electrode 208 at the opening of the planarization film 206 and exposes the bottom surface of the connection electrode 208. This enables electrical connection between the first electrode 102 provided thereon and the source / drain electrode 202 through the connection electrode 208. The additional capacitance insulating film 212 may be provided with an opening 214 for permitting contact between the partition wall 104 provided thereon and the planarizing film 206. The formation of the connection electrode 208 and the opening 214 is optional. By providing the connection electrode 208, corrosion of the surface of the source / drain electrode 202 can be prevented in the subsequent process, and an increase in contact resistance of the source / drain electrode 202 can be prevented. Impurities in the planarization film 206 can be removed through the openings 214, which can improve the reliability of the pixel circuit and the light emitting element 100.

付加容量絶縁膜２１２上には、接続電極２０８と付加容量電極２１０を覆うように、第１の電極１０２が設けられる。付加容量絶縁膜２１２は付加容量電極２１０と第１の電極１０２によって挟持され、この構造によって付加容量１８６が形成される。第１の電極１０２は、付加容量１８６と発光素子１００によって共有される。   A first electrode 102 is provided on the additional capacitance insulating film 212 so as to cover the connection electrode 208 and the additional capacitance electrode 210. The storage capacitor insulating film 212 is sandwiched between the storage capacitor electrode 210 and the first electrode 102, and a storage capacitor 186 is formed by this structure. The first electrode 102 is shared by the additional capacitance 186 and the light emitting element 100.

第１の電極１０２の上には、第１の電極１０２の端部を覆う隔壁１０４が設けられる。隔壁１０４により、第１の電極１０２に起因する凹凸が緩和され、この上に設けられるＥＬ層１０８や第２の電極１１０の切断を防止することができる。隔壁１０４の側面の少なくとも一部を覆うように光閉じ込め層１０６が設けられ、さらに第１の電極１０２の上には、第１の電極１０２と光閉じ込め層１０６に接するＥＬ層１０８が配置される。ＥＬ層１０８の上には、ＥＬ層１０８と接する第２の電極１１０が備えられる。   On the first electrode 102, a partition wall 104 covering an end of the first electrode 102 is provided. By the partition wall 104, unevenness due to the first electrode 102 can be alleviated, and cutting of the EL layer 108 and the second electrode 110 provided thereover can be prevented. An optical confinement layer 106 is provided to cover at least a part of the side surface of the partition wall 104, and an EL layer 108 in contact with the first electrode 102 and the optical confinement layer 106 is disposed on the first electrode 102. . A second electrode 110 in contact with the EL layer 108 is provided on the EL layer 108.

任意の構成として、第２の電極１１０上にはパッシベーション膜２１６が配置される。パッシベーション膜２１６の構造も任意に決定することができ、単層構造、積層構造のいずれを採用してもよい。積層構造を有する場合、例えばケイ素含有無機化合物を含む第１の層２１６ａ、樹脂を含む第２の層２１６ｂ、ケイ素含有無機化合物を含む第３の層２１６ｃが順次積層した構造を採用することができる。ケイ素含有無機化合物としては窒化ケイ素や酸化ケイ素が挙げられる。樹脂としてはエポキシ樹脂やアクリル樹脂、ポリエステル、ポリカルボナートなどが挙げられる。   A passivation film 216 is disposed on the second electrode 110 as an optional configuration. The structure of the passivation film 216 can be arbitrarily determined, and either a single layer structure or a laminated structure may be employed. In the case of having a stacked structure, for example, a structure in which a first layer 216a containing a silicon-containing inorganic compound, a second layer 216b containing a resin, and a third layer 216c containing a silicon-containing inorganic compound can be sequentially stacked can be employed. . Examples of the silicon-containing inorganic compound include silicon nitride and silicon oxide. Examples of the resin include epoxy resin, acrylic resin, polyester, polycarbonate and the like.

２−３．作製方法
図９（Ａ）に、基板１３２上にアンダーコート１９０を介して駆動トランジスタ１７２、保持容量１８４、およびおよび第１の電極１０２を含む付加容量１８６が形成された状態を示す。これらの素子は公知の方法を適用することで形成可能であるので、詳細は割愛する。 2-3. Manufacturing Method FIG. 9A shows a state in which a storage capacitor 186 including a driving transistor 172, a storage capacitor 184, and a first electrode 102 is formed on a substrate 132 with an undercoat 190 in between. Since these elements can be formed by applying known methods, details will be omitted.

第１の電極１０２の端部や、平坦化膜２０６に設けられた開口に起因する凹凸を覆うように隔壁１０４を形成する（図９（Ｂ））。隔壁１０４は第１実施形態で述べた材料を含み、スピンコート法やインクジェット法、印刷法によってこれらの材料、あるいはその前駆体を塗布し、得られた膜に対して露光、現像、焼成を行って形成することができる。   The partition wall 104 is formed so as to cover an end portion of the first electrode 102 and an unevenness due to an opening provided in the planarization film 206 (FIG. 9B). The partition wall 104 contains the materials described in the first embodiment, and these materials or their precursors are applied by spin coating, inkjet, printing, etc., and the obtained film is exposed, developed and baked. Can be formed.

次に、隔壁１０４の側面の少なくとも一部を覆い、隔壁１０４と第１の電極１０２に接する光閉じ込め層１０６を形成する。具体的には、スピンコート法やインクジェット法、印刷法を適用して隔壁１０４や第１の電極１０２上に第１実施形態で述べた高分子、あるいはその前駆体を塗布する（図９（Ｂ））。その後、フォトマスク２２０を介して露光を行う（図１０（Ａ））。フォトマスク２２０には照射光を遮蔽する遮光部２２２が設けられており、光閉じ込め層１０６を形成する領域と遮光部２２２が重なるよう、フォトマスク２２０を基板１３２上に配置する。その後露光を行い、エッチャントを用いる現像、焼成を行うことで光閉じ込め層１０６を形成する（図１０（Ｂ））。なお、無機化合物を用いる場合には、例えば蒸着法やスパッタリング法、化学気相堆積（ＣＶＤ）法などを用いて無機化合物の膜を形成した後、エッチングによって成形することで光閉じ込め層１０６を形成してもよい。   Next, an optical confinement layer 106 which covers at least a part of the side surface of the partition wall 104 and is in contact with the partition wall 104 and the first electrode 102 is formed. Specifically, the polymer described in the first embodiment or a precursor thereof is applied on the partition wall 104 and the first electrode 102 by applying a spin coating method, an inkjet method, or a printing method (FIG. 9 (B )). Thereafter, exposure is performed through the photomask 220 (FIG. 10A). The photomask 220 is provided with a light shielding portion 222 which shields the irradiation light, and the photomask 220 is disposed on the substrate 132 so that the region where the light confinement layer 106 is to be formed and the light shielding portion 222 overlap. Thereafter, exposure is performed, development using an etchant and baking are performed to form a light confinement layer 106 (FIG. 10B). In the case of using an inorganic compound, for example, after a film of the inorganic compound is formed by using a vapor deposition method, a sputtering method, a chemical vapor deposition (CVD) method, or the like, the light confinement layer 106 is formed by forming by etching. You may

その後、蒸着法やインクジェット法、スピンコート法などを適用し、第１の電極１０２上に、第１の電極１０２と光閉じ込め層１０６に接するＥＬ層１０８を形成する。引き続き蒸着法やスパッタリング法を用い、ＥＬ層１０８上に第２の電極１１０を形成する。第２の電極１１０上にはパッシベーション膜２１６が形成される。ＥＬ層１０８や第２の電極１１０、パッシベーション膜２１６も公知の方法を適用して形成することができるため、詳細な説明は割愛する。   After that, an evaporation method, an inkjet method, a spin coating method, or the like is applied to form an EL layer 108 which is in contact with the first electrode 102 and the light confinement layer 106 over the first electrode 102. Subsequently, the second electrode 110 is formed over the EL layer 108 by evaporation or sputtering. A passivation film 216 is formed on the second electrode 110. Since the EL layer 108, the second electrode 110, and the passivation film 216 can also be formed by applying a known method, detailed description will be omitted.

以上の工程により、表示装置１３０を作製することができる。上記説明から理解されるように、表示装置１３０は通常の半導体製造プロセスを利用することで作製することができる。したがって、本実施形態を適用することにより、プロセスに大きな負担をかけることなく、表示装置１３０を提供することができる。また、発光素子１００は優れた色純度と高い発光効率を示すことができる。したがって、本実施形態により、色再現性が高く、消費電力の小さい表示装置を製造することが可能となる。   Through the above steps, the display device 130 can be manufactured. As understood from the above description, the display device 130 can be manufactured by using a normal semiconductor manufacturing process. Therefore, by applying the present embodiment, the display device 130 can be provided without placing a heavy burden on the process. In addition, the light emitting element 100 can exhibit excellent color purity and high light emission efficiency. Therefore, according to this embodiment, it is possible to manufacture a display device with high color reproducibility and low power consumption.

本発明の実施形態として上述した各実施形態は、相互に矛盾しない限りにおいて、適宜組み合わせて実施することができる。また、各実施形態の表示装置を基にして、当業者が適宜構成要素の追加、削除もしくは設計変更を行ったもの、または、工程の追加、省略もしくは条件変更を行ったものも、本発明の要旨を備えている限り、本発明の範囲に含まれる。   The embodiments described above as the embodiments of the present invention can be implemented in combination as appropriate as long as they do not contradict each other. In addition, those in which a person skilled in the art appropriately adds, deletes, or changes the design of components based on the display device of each embodiment, or adds, omits, or changes conditions of steps are also included in the present invention. As long as it comprises the gist, it is included in the scope of the present invention.

本明細書においては、開示例として主にＥＬ表示装置の場合を例示したが、他の適用例として、その他の自発光型表示装置、液晶表示装置、あるいは電気泳動素子などを有する電子ペーパ型表示装置など、あらゆるフラットパネル型の表示装置が挙げられる。また、中小型から大型まで、特に限定することなく適用が可能である。   In the present specification, although the case of an EL display device is mainly illustrated as a disclosed example, an electronic paper type display having another self-light emitting display device, a liquid crystal display device, or an electrophoretic element as another application example Devices include any flat panel type display device. Moreover, it is applicable without particular limitation from medium size to large size.

上述した各実施形態の態様によりもたらされる作用効果とは異なる他の作用効果であっても、本明細書の記載から明らかなもの、または、当業者において容易に予測し得るものについては、当然に本発明によりもたらされるものと解される。   Even if other effects or effects different from the effects brought about by the aspects of the above-described embodiments are apparent from the description of the present specification or those which can be easily predicted by those skilled in the art, it is natural. It is understood that the present invention provides.

１００：発光素子、１０２：第１の電極、１０２ａ：第１の導電層、１０２ｂ：第２の導電層、１０２ｃ：第３の導電層、１０４：隔壁、１０６：光閉じ込め層、１０８：ＥＬ層、１０８ａ：ホール輸送層、１０８ｂ：発光層、１０８ｃ：電子輸送層、１１０：第２の電極、１２０：発光素子、１２２：第１の光閉じ込め層、１２４：第２の光閉じ込め層、１３０：表示装置、１３２：基板、１３４：画素、１３６：表示領域、１３８：走査線側駆動回路、１４０：信号線側駆動回路、１４２：配線、１４４：コネクタ、１５０：高電位電源線、１５２：電流供給線、１５４：低電位電源線、１５６：第１の信号線、１５８：第２の信号線、１６０：書込制御走査線、１６２：初期化制御走査線、１６４：補正制御走査線、１６６：リセット制御線、１６８：発光制御走査線、１７０：リセット信号線、１７２：駆動トランジスタ、１７４：初期化トランジスタ、１７６：書込トランジスタ、１７８：補正トランジスタ、１８０：発光制御トランジスタ、１８２：リセットトランジスタ、１８４：保持容量、１８６：付加容量、１８８：容量、１９０：アンダーコート、１９２：半導体膜、１９２ａ：チャネル領域、１９２ｂ：ソース／ドレイン領域、１９２ｃ：低濃度不純物領域、１９４：ゲート絶縁膜、１９６：ゲート電極、１９８：層間膜、２００：ソース／ドレイン電極、２０２：ソース／ドレイン電極、２０４：容量電極、２０６：平坦化膜、２０８：接続電極、２１０：付加容量電極、２１２：付加容量絶縁膜、２１４：開口、２１６：パッシベーション膜、２１６ａ：第１の層、２１６ｂ：第２の層、２１６ｃ：第３の層、２２０：フォトマスク、２２２：遮光部   100: light emitting element 102: first electrode 102a: first conductive layer 102b: second conductive layer 102c: third conductive layer 104: partition wall 106: light confinement layer 108: EL layer 108a: hole transport layer 108b: light emitting layer 108c: electron transport layer 110: second electrode 120: light emitting element 122: first light confinement layer 124: second light confinement layer 130: Display device 132: substrate 134: pixel 136: display region 138: scanning line side drive circuit 140: signal line side drive circuit 142: wiring 144: connector 150: high potential power supply line 152: current Supply line 154: low potential power supply line 156: first signal line 158: second signal line 160: write control scan line 162: initialization control scan line 164: correction control scan line 166 :reset Control line 168: light emission control scanning line 170: reset signal line 172: drive transistor 174: initialization transistor 176: write transistor 178: correction transistor 180: light emission control transistor 182: reset transistor 184 Storage capacity: 186: additional capacity, 188: capacity, 190: undercoat, 192: semiconductor film, 192a: channel region, 192b: source / drain region, 192c: low concentration impurity region, 194: gate insulating film, 196: Gate electrode, 198: interlayer film, 200: source / drain electrode, 202: source / drain electrode, 204: capacitance electrode, 206: planarizing film, 208: connection electrode, 210: additional capacitance electrode, 212: additional capacitance insulating film , 214: Opening 216: Passivation film 216a The first layer, 216b: second layer, 216c: third layer 220: a photomask, 222: light-shielding portion

Claims (18)

第１の電極、
前記第１の電極の端部を覆う隔壁、
前記隔壁の側面と前記第１の電極に接する光閉じ込め層、
前記第１の電極の上に位置し、前記第１の電極と前記光閉じ込め層に接する電界発光層、および
前記電界発光層の上の第２の電極を有し、
前記光閉じ込め層の屈折率は、前記電界発光層の屈折率よりも低い発光素子。 First electrode,
A partition covering an end of the first electrode;
A light confinement layer in contact with the side surface of the partition wall and the first electrode;
An electroluminescent layer located on the first electrode and in contact with the first electrode and the light confinement layer; and a second electrode on the electroluminescent layer,
A light emitting device in which a refractive index of the light confinement layer is lower than a refractive index of the electroluminescent layer; 前記光閉じ込め層の誘電率は、前記電界発光層の誘電率よりも低い、請求項１に記載の発光素子。   The light emitting device according to claim 1, wherein a dielectric constant of the light confinement layer is lower than a dielectric constant of the electroluminescent layer. 前記隔壁の側面と、前記隔壁の前記第１の電極に接する面がなす角度は、８０°以上９０°未満である、請求項１に記載の発光素子。   The light emitting element according to claim 1, wherein an angle between a side surface of the partition wall and a surface of the partition wall in contact with the first electrode is 80 ° or more and less than 90 °. 前記光閉じ込め層の前記第１の電極に接する面の幅は、５０ｎｍ以上２００ｎｍ以下である、請求項１に記載の発光素子。   The light emitting element according to claim 1, wherein a width of a surface of the light confinement layer in contact with the first electrode is 50 nm or more and 200 nm or less. 前記光閉じ込め層は、前記隔壁の上面と接する、請求項１に記載の発光素子。   The light emitting device according to claim 1, wherein the light confinement layer is in contact with an upper surface of the partition wall. 前記第２の電極は、前記光閉じ込め層と接する、請求項１に記載の発光素子。   The light emitting device according to claim 1, wherein the second electrode is in contact with the light confinement layer. 前記第２の電極は、前記隔壁と接する、請求項１に記載の発光素子。   The light emitting element according to claim 1, wherein the second electrode is in contact with the partition wall. 前記第１の電極は、可視光を反射する反射面を有し、
前記反射面と前記第２の電極間の光学距離が、前記電界発光層の発光波長の４分の１の奇数倍である、請求項１に記載の発光素子。 The first electrode has a reflective surface that reflects visible light,
The light emitting device according to claim 1, wherein an optical distance between the reflective surface and the second electrode is an odd multiple of one fourth of a light emission wavelength of the electroluminescent layer. 第１の発光素子、
前記第１の発光素子に隣接する第２の発光素子、および
前記第１の発光素子と前記第２の発光素子の間の隔壁を有し、
前記第１の発光素子と前記第２の発光素子はそれぞれ、
前記隔壁に端部を覆われる第１の電極、
前記隔壁の側面と前記第１の電極に接する光閉じ込め層、
前記第１の電極の上に位置し、前記第１の電極と前記光閉じ込め層に接する電界発光層、および
前記電界発光層の上の第２の電極を有し、
前記第１の発光素子と前記第２の発光素子の各々において、前記光閉じ込め層の屈折率は、前記電界発光層の屈折率よりも低い表示装置。 A first light emitting element,
A second light emitting element adjacent to the first light emitting element, and a partition between the first light emitting element and the second light emitting element;
The first light emitting element and the second light emitting element are respectively
A first electrode whose end is covered by the partition,
A light confinement layer in contact with the side surface of the partition wall and the first electrode;
An electroluminescent layer located on the first electrode and in contact with the first electrode and the light confinement layer; and a second electrode on the electroluminescent layer,
In each of the first light emitting element and the second light emitting element, a display device in which a refractive index of the light confinement layer is lower than a refractive index of the electroluminescent layer. 前記第１の発光素子と前記第２の発光素子の各々において、前記光閉じ込め層の誘電率は、前記電界発光層の誘電率よりも低い、請求項９に記載の表示装置。   The display device according to claim 9, wherein in each of the first light emitting element and the second light emitting element, a dielectric constant of the light confinement layer is lower than a dielectric constant of the electroluminescent layer. 前記第１の発光素子と前記第２の発光素子の各々において、前記隔壁の側面と、前記隔壁の前記第１の電極に接する面がなす角度は、８０°以上９０°未満である、請求項９に記載の表示装置。   In each of the first light emitting element and the second light emitting element, an angle between a side surface of the partition wall and a surface of the partition wall in contact with the first electrode is 80 degrees or more and less than 90 degrees. The display device according to 9. 前記第１の発光素子と前記第２の発光素子の各々において、前記光閉じ込め層の前記第１の電極に接する面の幅は、５０ｎｍ以上２００ｎｍ以下である、請求項９に記載の表示装置。   The display device according to claim 9, wherein in each of the first light emitting element and the second light emitting element, a width of a surface of the light confinement layer in contact with the first electrode is 50 nm or more and 200 nm or less. 前記光閉じ込め層は、前記隔壁の上面と接し、前記第１の発光素子と前記第２の発光素子に共有される、請求項９に記載の表示装置。   10. The display device according to claim 9, wherein the light confinement layer is in contact with the upper surface of the partition wall and is shared by the first light emitting element and the second light emitting element. 前記第２の電極は、前記第１の発光素子と前記第２の発光素子に共有され、前記第１の発光素子と前記第２の発光素子の前記光閉じ込め層と接する、請求項９に記載の表示装置。   10. The device according to claim 9, wherein the second electrode is shared by the first light emitting element and the second light emitting element, and is in contact with the light confinement layer of the first light emitting element and the second light emitting element. Display device. 前記第２の電極は、前記第１の発光素子と前記第２の発光素子に共有され、前記隔壁と接する、請求項９に記載の表示装置。   The display device according to claim 9, wherein the second electrode is shared by the first light emitting element and the second light emitting element and is in contact with the partition wall. 前記第１の発光素子と前記第２の発光素子の各々において、前記第１の電極は、可視光を反射する反射面を有し、前記反射面と前記第２の電極間の光学距離が、前記電界発光層の発光波長の４分の１の奇数倍である、請求項９に記載の表示装置。   In each of the first light emitting element and the second light emitting element, the first electrode has a reflecting surface that reflects visible light, and an optical distance between the reflecting surface and the second electrode is The display device according to claim 9, wherein the light emission wavelength of the electroluminescent layer is an odd multiple of one fourth. 第１の電極、
前記第１の電極の端部を覆う隔壁、
前記隔壁の側面の少なくとも一部を覆う第１の光閉じ込め層、
前記第１の光閉じ込め層と前記隔壁の間に位置し、前記第１の光閉じ込め層と前記隔壁に接する第２の光閉じ込め層、
前記第１の電極の上に位置し、前記第１の電極と前記第１の光閉じ込め層に接する電界発光層、および
前記電界発光層の上の第２の電極を有し、
前記第２の光閉じ込め層の屈折率は、前記電界発光層の屈折率、および前記第１の光閉じ込め層の屈折率よりも低い発光素子。 First electrode,
A partition covering an end of the first electrode;
A first light confinement layer covering at least a part of the side surface of the partition wall;
A second light confinement layer located between the first light confinement layer and the partition and in contact with the first light confinement layer and the partition;
An electroluminescent layer located on the first electrode and in contact with the first electrode and the first light confinement layer; and a second electrode on the electroluminescent layer,
A light emitting device, wherein a refractive index of the second light confinement layer is lower than a refractive index of the electroluminescent layer and a refractive index of the first light confinement layer. 第１の発光素子、
前記第１の発光素子に隣接する第２の発光素子、および
前記第１の発光素子と前記第２の発光素子の間の隔壁を有し、
前記第１の発光素子と前記第２の発光素子はそれぞれ、
前記隔壁に端部を覆われる第１の電極、
前記隔壁の側面の少なくとも一部を覆う第１の光閉じ込め層、
前記第１の光閉じ込め層と前記隔壁の間に位置し、前記第１の光閉じ込め層と前記隔壁に接する第２の光閉じ込め層、
前記第１の電極の上に位置し、前記第１の電極と前記第１の光閉じ込め層に接する電界発光層、および
前記電界発光層の上の第２の電極を有し、
前記第２の光閉じ込め層の屈折率は、前記電界発光層の屈折率、および前記第１の光閉じ込め層の屈折率よりも低い表示装置。 A first light emitting element,
A second light emitting element adjacent to the first light emitting element, and a partition between the first light emitting element and the second light emitting element;
The first light emitting element and the second light emitting element are respectively
A first electrode whose end is covered by the partition,
A first light confinement layer covering at least a part of the side surface of the partition wall;
A second light confinement layer located between the first light confinement layer and the partition and in contact with the first light confinement layer and the partition;
An electroluminescent layer located on the first electrode and in contact with the first electrode and the first light confinement layer; and a second electrode on the electroluminescent layer,
A display device, wherein a refractive index of the second light confinement layer is lower than a refractive index of the electroluminescent layer and a refractive index of the first light confinement layer.
JP2017228807A 2017-11-29 2017-11-29 Light emitting device and display device Pending JP2019102153A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017228807A JP2019102153A (en) 2017-11-29 2017-11-29 Light emitting device and display device
US16/180,116 US10553657B2 (en) 2017-11-29 2018-11-05 Light-emitting element and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017228807A JP2019102153A (en) 2017-11-29 2017-11-29 Light emitting device and display device

Publications (1)

Publication Number Publication Date
JP2019102153A true JP2019102153A (en) 2019-06-24

Family

ID=66633568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017228807A Pending JP2019102153A (en) 2017-11-29 2017-11-29 Light emitting device and display device

Country Status (2)

Country Link
US (1) US10553657B2 (en)
JP (1) JP2019102153A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022153144A1 (en) * 2021-01-14 2022-07-21 株式会社半導体エネルギー研究所 Light-emitting element, display device, and electronic equipment

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7377216B2 (en) * 2018-12-21 2023-11-09 株式会社半導体エネルギー研究所 Display devices, modules and electronic equipment
KR20200119946A (en) * 2019-04-10 2020-10-21 삼성디스플레이 주식회사 Display device
CN110492016B (en) * 2019-07-30 2020-10-27 武汉华星光电半导体显示技术有限公司 Array substrate and display panel
CN113013203B (en) * 2021-02-09 2022-08-02 武汉天马微电子有限公司 Display panel and display device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605826B2 (en) * 2000-08-18 2003-08-12 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and display device
JP2011003522A (en) * 2008-10-16 2011-01-06 Semiconductor Energy Lab Co Ltd Flexible light-emitting device, electronic equipment, and method of manufacturing flexible light-emitting device
KR20120093864A (en) * 2009-10-09 2012-08-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
JP6552100B2 (en) 2015-09-24 2019-07-31 シャープ株式会社 Organic electroluminescent device
WO2017072634A1 (en) 2015-10-30 2017-05-04 Semiconductor Energy Laboratory Co., Ltd. Display device, electronic device, and method for manufacturing display device and electronic device
JP2017112011A (en) 2015-12-17 2017-06-22 コニカミノルタ株式会社 Organic electroluminescent element, and light-emitting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022153144A1 (en) * 2021-01-14 2022-07-21 株式会社半導体エネルギー研究所 Light-emitting element, display device, and electronic equipment

Also Published As

Publication number Publication date
US20190165058A1 (en) 2019-05-30
US10553657B2 (en) 2020-02-04

Similar Documents

Publication Publication Date Title
US10297794B2 (en) Organic light emitting diode display device
JP4439260B2 (en) Manufacturing method of display device
JP4475942B2 (en) Display device and manufacturing method thereof
JP2019102153A (en) Light emitting device and display device
TWI376976B (en) Display device and display unit
KR102037850B1 (en) Organic light emitting display and manufactucring method of the same
KR101354303B1 (en) Display unit
US10608207B2 (en) Organic light-emitting diode display device including a thin film encapsulation layer
JP6817807B2 (en) Display device
US8716931B2 (en) Organic light emitting diode (OLED) display
US10826021B2 (en) Organic electroluminescence device including a plurality of unit regions each including a light emitting area and a transmissive area
KR102436248B1 (en) Organic light emitting diodes display
KR102261610B1 (en) Organic light emitting display device
JP2005197009A (en) Manufacturing method and manufacturing device of display device
KR20180076857A (en) Organic Light Emitting Diode Display Device
US10439157B2 (en) Display device
CN108258132B (en) Electroluminescent display device
KR20140014682A (en) Organic light emitting diode device and manufacturing method thereof
US20150270510A1 (en) Methods of manufacturing display devices
JP2018073567A (en) Display device
EP3093899B1 (en) Organic light emitting diode display
CN112310307A (en) OLED display panel
KR101591332B1 (en) Organic electro-luminescence device
JP2018147770A (en) Display device and method of manufacturing display device
JP6994914B2 (en) Organic EL display device