JP2019050514A - Structure - Google Patents

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JP2019050514A
JP2019050514A JP2017174113A JP2017174113A JP2019050514A JP 2019050514 A JP2019050514 A JP 2019050514A JP 2017174113 A JP2017174113 A JP 2017174113A JP 2017174113 A JP2017174113 A JP 2017174113A JP 2019050514 A JP2019050514 A JP 2019050514A
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conductor
substrate
face
dielectric substrate
plates
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忠寛 佐々木
Tadahiro Sasaki
忠寛 佐々木
誠 桧垣
Makoto Higaki
誠 桧垣
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Toshiba Corp
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Abstract

To make a frequency characteristic of a structure closer to a design value according to an embodiment of the present invention.SOLUTION: A structure as one embodiment hereof comprises: a dielectric substrate; a conductor substrate; conductor plates; through-hole vias; a conductor face; and conductor pieces. The dielectric substrate has: a first face; a second face on a side opposite to the first face; and a third face crossing the first face. The conductor substrate is in contact with the dielectric substrate at the first face. The conductor plates are arranged on the second face with a gap provided thereamong. The through-hole vias are provided for the conductor plates respectively, which extend through the dielectric substrate, connecting one conductor plate to the conductor substrate. The conductor face is opposed to the third face, and connected to the conductor substrate. The conductor pieces are disposed between the conductor face and the first conductor plate of the plurality of conductor plates, which is disposed at an end on a side of the third face, and connected to the conductor face.SELECTED DRAWING: Figure 1

Description

本発明の実施形態は、構造体に関する。   Embodiments of the present invention relate to structures.

特定の周波数帯域の電磁波を遮断する電磁バンドギャップ(EBG:Electromagnetic Band Gap)構造を有する構造体を用いて、電磁波によるノイズを抑えることが知られている。EBG構造は、隙間(ギャップ)を空けて格子状に配置された複数の導体板(パッチ)などから形成される。これらのパッチのサイズ、パッチ同士間の隙間のサイズなどにより、遮断される周波数帯域、遮断量といったEBG構造体が有する周波数特性が定まる。   It is known to suppress noise due to electromagnetic waves by using a structure having an electromagnetic band gap (EBG: Electromagnetic Band Gap) structure that blocks electromagnetic waves in a specific frequency band. The EBG structure is formed of a plurality of conductor plates (patches) or the like arranged in a lattice form with gaps (gaps) therebetween. The frequency characteristics of the EBG structure, such as the cut-off frequency band and the cut-off amount, are determined by the size of the patches, the size of the gap between the patches, and the like.

しかし、実際には、計算上の遮断量を得ることは難しく、単純にパッチの配置数を増やしても、所望の周波数特性を得ることができない。   However, in practice, it is difficult to obtain the calculated amount of interruption, and simply by increasing the number of patches, the desired frequency characteristics can not be obtained.

特開2009−218966号公報JP, 2009-218966, A

本発明の一実施形態は、構造体の周波数特性を設計値に近づけることを目的とする。   An embodiment of the present invention aims to bring the frequency characteristic of a structure close to a design value.

本発明の一態様としての構造体は、誘電体基板と、導体基板と、導体板と、スルーホールビアと、導体面と、導体片と、を備える。誘電体基板は、第1面と、第1面とは反対側の第2面と、第1面と交差する第3面と、を有する。導体基板は、第1面において、誘電体基板と接する。導体板は、第2面上において、互いに隙間を設けて配置されている。スルーホールビアは、導体板それぞれごとに設けられており、誘電体基板を貫通して、導体板の1つと導体基板とを接続する。導体面は、第3面と対向し、かつ導体基板に接続されている。導体片は、複数の導体板のうちの第3面側の端に配置された第1導体板と、導体面との間に配置され、かつ導体面に接続されている。   A structure according to an aspect of the present invention includes a dielectric substrate, a conductor substrate, a conductor plate, a through hole via, a conductor surface, and a conductor piece. The dielectric substrate has a first surface, a second surface opposite to the first surface, and a third surface intersecting the first surface. The conductor substrate is in contact with the dielectric substrate at the first surface. The conductor plates are arranged with a gap on the second surface. Through-hole vias are provided for each of the conductor plates, and penetrate the dielectric substrate to connect one of the conductor plates to the conductor substrate. The conductor surface faces the third surface and is connected to the conductor substrate. The conductor piece is disposed between the first conductor plate disposed at the end on the third surface side of the plurality of conductor plates and the conductor surface, and is connected to the conductor surface.

本発明の一実施形態に係る構造体を説明する斜視図。BRIEF DESCRIPTION OF THE DRAWINGS The perspective view explaining the structure which concerns on one Embodiment of this invention. 本発明の一実施形態に係る構造体を説明する上面透視図。The top perspective view explaining the structure concerning one embodiment of the present invention. 本発明の一実施形態ではない構造体の周波数特性を示す図。The figure which shows the frequency characteristic of the structure which is not one Embodiment of this invention. 本発明の一実施形態に係る構造体のEBG構造を説明する図。The figure explaining the EBG structure of the structure which concerns on one Embodiment of this invention. 本発明の一実施形態に係る構造体の周波数特性の変化の結果を示す図。The figure which shows the result of the change of the frequency characteristic of the structure which concerns on one Embodiment of this invention.

以下、図面を参照しながら、本発明の実施形態について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(本発明の一実施形態)
図1は、本発明の一実施形態に係る構造体を説明する斜視図である。本発明の一実施形態に係る構造体は、誘電体基板1と、導体基板2と、複数の導体板(パッチ)3と、複数のスルーホールビア4と、筐体5と、導体片6と、を備える。なお、誘電体基板1は、説明の便宜上、外枠が点線の透明な直方体にて示されている。
(One embodiment of the present invention)
FIG. 1 is a perspective view for explaining a structure according to an embodiment of the present invention. A structure according to an embodiment of the present invention includes a dielectric substrate 1, a conductor substrate 2, a plurality of conductor plates (patches) 3, a plurality of through hole vias 4, a housing 5, and conductor pieces 6. And. The dielectric substrate 1 is shown in the form of a transparent rectangular solid whose outer frame is a dotted line for convenience of explanation.

誘電体基板1は、ある面にて導体基板2と接している。本説明では、導体基板2と接する面を基準面(第1面)と記載する。また、誘電体基板1は、基準面とは反対側の面にて、複数のパッチ3と接する。本説明では、パッチ3と接する面をパッチ面(第2面)と記載する。図1では、図1の座標軸のZ軸の正の方向を上とすると、誘電体基板1の上面がパッチ面であり、下面が基準面である。   The dielectric substrate 1 is in contact with the conductor substrate 2 at a certain surface. In the present description, the surface in contact with the conductor substrate 2 is referred to as a reference surface (first surface). The dielectric substrate 1 is in contact with the plurality of patches 3 on the surface opposite to the reference surface. In the present description, the surface in contact with the patch 3 is referred to as a patch surface (second surface). In FIG. 1, assuming that the positive direction of the Z axis of the coordinate axes in FIG. 1 is the upper side, the upper surface of the dielectric substrate 1 is a patch surface, and the lower surface is a reference surface.

なお、誘電体基板1が有する誘電率は、特に限られるものではなく、構造体の所望の特性などに基づいて定められればよい。   The dielectric constant of the dielectric substrate 1 is not particularly limited, and may be determined based on the desired characteristics of the structure and the like.

導体基板2は、電位の基準として用いられる。導体基板2とグランドとが接続され、導体基板2の電位がグランド電位とされてもよい。   The conductor substrate 2 is used as a reference of potential. The conductor substrate 2 and the ground may be connected, and the potential of the conductor substrate 2 may be set to the ground potential.

パッチ3は、図1に示すように、互いに隙間を設けて、パッチ面上に格子状に配置される。当該隙間にキャパシタンス成分が生じる。また、パッチ3と導体基板2との間にもキャパシタンス成分が生じる。また、パッチ3自体にはインダクタンス成分が生じる。   As shown in FIG. 1, the patches 3 are arranged in a lattice on the patch surface with a gap therebetween. A capacitance component is generated in the gap. In addition, a capacitance component is also generated between the patch 3 and the conductor substrate 2. In addition, an inductance component is generated in the patch 3 itself.

スルーホールビア4は、それぞれ1つのパッチ3と対応しており、誘電体基板1を貫通して、パッチ3と導体基板2とを接続する。これにより、スルーホールビア4には、インダクタンス成分が生じる。なお、本説明では、1つのパッチ3とそれに付随するスルーホールビア4との組み合わせをユニットと記載する。   The through hole vias 4 correspond to one patch 3 respectively, and penetrate the dielectric substrate 1 to connect the patch 3 and the conductor substrate 2. Thereby, an inductance component is generated in the through hole via 4. In the present description, a combination of one patch 3 and the through hole via 4 accompanying it is described as a unit.

上記のインダクタンス成分およびキャパシタンス成分により、特定の周波数帯域の電磁波が遮断される。つまり、図1に示された構造はEBG構造と言え、本実施形態の構造体は、EBG構造を有するEBG構造体と言える。なお、本実施形態のEBG構造は、マッシュルーム構造と称される。   The above-mentioned inductance component and capacitance component cut off electromagnetic waves in a specific frequency band. That is, the structure shown in FIG. 1 can be said to be an EBG structure, and the structure of this embodiment can be said to be an EBG structure having an EBG structure. The EBG structure of the present embodiment is referred to as a mushroom structure.

なお、図1に示された範囲の外にも誘電体基板1、導体基板2および筐体5が広がっており、パッチ3およびスルーホールビア4がさらに存在してもよい。例えば、図1の座標軸のX方向にm(mは2以上の整数)個のパッチ3が、Y方向にn(nは2以上の整数)個のパッチ3が配置され、m×nの行列状に配置されてもよい。   The dielectric substrate 1, the conductor substrate 2 and the housing 5 extend outside the range shown in FIG. 1, and the patch 3 and the through hole via 4 may be further present. For example, m (n is an integer of 2 or more) patches 3 are arranged in the X direction of the coordinate axes in FIG. 1, and n (n is an integer of 2 or more) patches 3 are arranged in the Y direction. It may be arranged in a shape.

図2は、本発明の一実施形態に係る構造体を説明する上面透視図である。なお、誘電体基板1は省略されている。図2の例では、5×4行列の場合が示されている。図1に示された構造体の一部分は、このm×n行列の3×2行列の部分にあたる。   FIG. 2 is a top perspective view illustrating a structure according to an embodiment of the present invention. The dielectric substrate 1 is omitted. In the example of FIG. 2, the case of 5 × 4 matrix is shown. A portion of the structure shown in FIG. 1 corresponds to a portion of the 3 × 2 matrix of this m × n matrix.

筐体5は、図2に示すように、中空であり、筐体5の内壁51は誘電体基板1の側面(第3面)を取り囲む。なお、誘電体基板1の側面は、基準面およびパッチ面と交差する面である。ゆえに、筐体5の内壁51は、誘電体基板1の側面に対向している。   The housing 5 is hollow as shown in FIG. 2, and the inner wall 51 of the housing 5 surrounds the side surface (third surface) of the dielectric substrate 1. The side surface of the dielectric substrate 1 is a surface intersecting the reference surface and the patch surface. Therefore, the inner wall 51 of the housing 5 is opposed to the side surface of the dielectric substrate 1.

筐体5の内壁51の少なくとも一部は、導電性を有し、導体基板2に接続されているものとする。例えば、筐体5が1つ以上の導体により構成されてもよいし、内壁51が金属に覆われていてもよい。内壁51の導電性の部分は、導体面と言える。ゆえに、筐体5は、誘電体基板1の側面と対向し、かつ導体基板2に接続された導体面を有すると言える。   At least a part of the inner wall 51 of the housing 5 has conductivity, and is connected to the conductor substrate 2. For example, the housing 5 may be configured of one or more conductors, or the inner wall 51 may be covered with metal. The conductive portion of the inner wall 51 can be said to be a conductor surface. Therefore, it can be said that the housing 5 has a conductor surface facing the side surface of the dielectric substrate 1 and connected to the conductor substrate 2.

なお、図2では、筐体5は、四角柱の形状であるが、円筒状であってもよい。つまり、導体面は湾曲していてもよい。   In addition, in FIG. 2, although the housing | casing 5 is a shape of a square pole, it may be cylindrical. That is, the conductor surface may be curved.

図2の点線で示された枠71は、複数のパッチ3のうちの端に配置されたパッチ3(第1導体板)の内壁51と対向する縁を繋ぎ合わすことにより形成される。当該枠71と内壁51との間の領域、言い換えると、当該枠71の外側かつ筐体5の内側の領域をバッファエリア72と記載する。   The frame 71 shown by the dotted line in FIG. 2 is formed by joining together an edge opposed to the inner wall 51 of the patch 3 (first conductive plate) disposed at an end of the plurality of patches 3. The area between the frame 71 and the inner wall 51, in other words, the area outside the frame 71 and the inside of the housing 5 is referred to as a buffer area 72.

なお、誘電体基板1は、枠71よりも外側に食み出していてもよい。また、誘電体基板1の端が内壁51と接触していてもよい。   The dielectric substrate 1 may protrude outside the frame 71. Also, the end of the dielectric substrate 1 may be in contact with the inner wall 51.

導体片6はバッファエリア72に配置される。また、導体片6は内壁51の導電性の部分に接続されている。これにより、導体片6は、格子状に配置された複数のパッチ3のうち端に配置されたパッチ3と容量性結合する。これにより、本実施形態の構造体の周波数特性は、導体片6がないEBG構造の周波数特性と異なる。   The conductor pieces 6 are arranged in the buffer area 72. Also, the conductor piece 6 is connected to the conductive portion of the inner wall 51. As a result, the conductor piece 6 capacitively couples with the patch 3 disposed at one end of the plurality of patches 3 disposed in a lattice. Thereby, the frequency characteristic of the structure of this embodiment differs from the frequency characteristic of the EBG structure without the conductor piece 6.

EBG構造体は、不要な周波数帯域の電磁波を遮断する用途として用いられる。例えば、パワーアンプの筐体内にEBG構造体を設置することにより、パワーアンプの回路から発振されたノイズを抑えることができる。以降、EBG構造により遮断される周波数帯域を遮断帯域と記載する。   The EBG structure is used as an application for blocking electromagnetic waves in unnecessary frequency bands. For example, by installing the EBG structure in the housing of the power amplifier, it is possible to suppress the noise oscillated from the circuit of the power amplifier. Hereinafter, the frequency band cut off by the EBG structure is referred to as a stop band.

遮断帯域などのEBG構造体の周波数特性は、パッチ3のサイズ、パッチ3同士間の隙間のサイズ、ユニットの個数などによって定まる。例えば、行列配置するユニットの数を増加させることにより、遮断量を大きくする、あるいは、ユニットの配列間隔を調整することにより、遮断帯域を変化させるといったことが考えられる。   The frequency characteristics of the EBG structure such as the stop band are determined by the size of the patch 3, the size of the gap between the patches 3, the number of units, and the like. For example, it is conceivable to increase the cutoff amount by increasing the number of units arranged in a matrix, or to change the cutoff band by adjusting the arrangement interval of the units.

しかし、理論上の設計値に基づいてEBG構造体を製造しても、実際のEBG構造体の遮断量は、設計値よりも低くなる。図3は、本発明の一実施形態ではない構造体の周波数特性を示す図である。導体片6を備えていないEBG構造体による周波数特性が示されている。設計値が点線にて、実測値が実線にて示されている。図3より分かるように、設計上の遮断帯域において、設計上の遮断量が得られていないことが分かる。   However, even if the EBG structure is manufactured based on theoretical design values, the actual blocking amount of the EBG structure is lower than the design value. FIG. 3 is a diagram showing frequency characteristics of a structure which is not an embodiment of the present invention. The frequency characteristic by the EBG structure which is not equipped with the conductor piece 6 is shown. Design values are shown by dotted lines and actual values are shown by solid lines. As can be seen from FIG. 3, it can be seen that the designed cutoff amount is not obtained in the designed cutoff zone.

通常、EBG構造体の周波数特性は、パッチ3が必ず他のパッチ3の間に介在するという仮定に基づき、計算が行われる。しかし、実際には、端に配置され、他のパッチ3の間に介在しないパッチ3が存在する。そのため、図3のように、設計上の遮断帯域において、設計上の遮断量が得られない事態となる。   Usually, the frequency characteristics of the EBG structure are calculated based on the assumption that patch 3 always intervenes between other patches 3. However, in practice there are patches 3 which are located at the end and do not intervene between the other patches 3. Therefore, as shown in FIG. 3, in the design stop band, the design cut-off amount can not be obtained.

しかし、本実施形態の構造体では、端に配置されたパッチ3も、導体片6と容量性結合を行う。そのため、設計上の遮断量に近づける事が可能となる。   However, in the structure of the present embodiment, the patch 3 disposed at the end also performs capacitive coupling with the conductor piece 6. Therefore, it is possible to approach the cutoff amount in design.

図4は、本発明の一実施形態に係る構造体のEBG構造を説明する図である。なお、符号の添え字のアルファベットは同じ符号の各個体の区別のために付されている。   FIG. 4 is a view for explaining an EBG structure of a structure according to an embodiment of the present invention. In addition, the alphabet of the subscript of a code | symbol is attached | subjected for distinction of each individual | organism | solid of the same code | symbol.

前述の通り、パッチ3およびスルーホールビア4にはインダクタンス成分が生じる。また、隣接するパッチ3同士間の隙間、および、パッチ3と導体基板2との間には、キャパシタンス成分が生じる。これらのインダクタンス成分およびキャパシタンス成分による等価回路が図4に示されている。図4に示されるように、当該等価回路は、右手系線路および左手系線路が組み合わされた右手/左手系複合線路となる。右手/左手系複合線路の分散特性により、遮断帯域が定まる。   As described above, the patch 3 and the through hole via 4 have an inductance component. In addition, capacitance components are generated in the gaps between the adjacent patches 3 and between the patches 3 and the conductor substrate 2. An equivalent circuit based on these inductance components and capacitance components is shown in FIG. As shown in FIG. 4, the equivalent circuit is a combined right / left handed line in which the right handed line and the left handed line are combined. The stopband is determined by the dispersion characteristics of the right / left handed composite line.

図4の記号Lはインダクタンス成分を示し、記号Cはキャパシタンス成分を示す。また、添え字Rは右手系線路の成分であることを、添え字Lは左手系線路の成分であることを示す。パッチ3に生じるインダクタンス成分は、右手系線路のインダクタンス成分であるため、Lと示されている。パッチ3と導体基板2との間に生じるキャパシタンス成分は、右手系線路のキャパシタンス成分であるため、Cと示されている。スルーホールビア4のインダクタンス成分は、左手系線路のインダクタンス成分であるため、Lと示されている。隣接するパッチ3同士間の隙間に生じるキャパシタンス成分は、左手系線路のキャパシタンス成分であるため、Cと示されている。パッチ3のサイズ、パッチ3間の隙間のサイズ、およびスルーホールビア4のサイズが統一されている場合、各成分の値は同じである。 Symbol L in FIG. 4 indicates an inductance component, and symbol C indicates a capacitance component. Also, the index R indicates that it is a component of a right-handed line, and the index L indicates that it is a component of a left-handed line. The inductance component generated in the patch 3 is indicated as L R because it is an inductance component of the right-handed line. Capacitance component generated between the patch 3 and the conductor substrate 2 are the capacitance component of the right-handed transmission line, shown as C R. The inductance component of the through hole via 4 is indicated as L L because it is an inductance component of the left-handed line. Capacitance component generated in a gap between adjacent patches 3 to each other, since the capacitance component of the left-handed transmission line, shown as C L. When the size of the patch 3, the size of the gap between the patches 3, and the size of the through hole via 4 are uniform, the value of each component is the same.

また、本実施形態のような導体片6が配置された場合は、導体面がある側の端に配置されたパッチ3Aと導体片6との間にキャパシタンス成分が生じる。また、導体片6自体には、インダクタンス成分が生じる。また、導体片6と導体基板2との間にキャパシタンス成分が生じる。つまり、図4の点線の枠内にて示されるような、右手系線路のインダクタンス成分L’、右手系線路のキャパシタンス成分C’、左手系線路のキャパシタンス成分C’が生じる。こうして、導体片6と、端に配置されたパッチ3Aとが容量性結合することにより、複数のパッチ3および導体片6による右手/左手系複合伝送路が形成される。これにより、端に配置されたパッチ3Aは、右手/左手系複合線路の終端ではなくなる。 When the conductor piece 6 as in this embodiment is disposed, a capacitance component is generated between the patch 3A disposed at the end on which the conductor surface is located and the conductor piece 6. In addition, an inductance component is generated in the conductor piece 6 itself. Also, a capacitance component is generated between the conductor piece 6 and the conductor substrate 2. That is, the inductance component L ' R of the right-handed line, the capacitance component C' R of the right-handed line, and the capacitance component C ' L of the left-handed line are generated as shown in the dotted frame of FIG. Thus, capacitive coupling between the conductor piece 6 and the patch 3A disposed at the end forms a combined right-hand / left-handed transmission path by the plurality of patches 3 and the conductor piece 6. As a result, the patch 3A disposed at the end is not at the end of the combined right / left handed line.

一方、導体片6がないと、図4の点線の枠で囲まれた部分の右手/左手系複合線路がないため、端に配置されたパッチ3Aは右手/左手系複合線路の終端となり、パッチ3が必ず他のパッチ3の間に介在すると仮定して算出された設計値よりも、遮断量が減少する。   On the other hand, without the conductor piece 6, there is no right-hand / left-hand composite line in the portion enclosed by the dotted frame in FIG. 4, so the patch 3A disposed at the end becomes the end of the right-hand / left-hand composite line The blocking amount is smaller than the design value calculated assuming that 3 always intervenes between the other patches 3.

導体片6の形状、位置、サイズは調整可能であるが、導体片6と、端に配置されたパッチ3Aと、に基づく右手/左手系複合伝送路のQ値が、隣接するパッチ3同士に基づく右手/左手系複合伝送路のQ値と一致することが好ましい。   The shape, position, and size of the conductor piece 6 can be adjusted, but the Q value of the combined right / left handed transmission line based on the conductor piece 6 and the patch 3A disposed at the end is the patch 3 adjacent to each other. It is preferable to match the Q value of the combined right / left handed transmission line based on the above.

図5は、本発明の一実施形態に係る構造体の周波数特性の変化の結果を示す図である。本実施形態に係る構造体における遮断量のグラフ81と、導体片6を除いた構造体の遮断量のグラフ91と、が実線で示されている。また、本実施形態に係る構造体の反射量(反射した電磁波の量)のグラフ82と、導体片6を除いた構造体の反射量のグラフ92と、が点線で示されている。   FIG. 5 is a diagram showing the results of changes in the frequency characteristics of the structure according to an embodiment of the present invention. The graph 81 of the interruption | blocking amount in the structure which concerns on this embodiment, and the graph 91 of the interruption | blocking amount of the structure except the conductor piece 6 are shown by the continuous line. Further, a graph 82 of the reflection amount (the amount of reflected electromagnetic wave) of the structure according to the present embodiment and a graph 92 of the reflection amount of the structure excluding the conductor piece 6 are shown by dotted lines.

図5によると、周波数帯域10.25付近において、両構造体の反射量はほぼ同じにも関わらず、本実施形態の構造体の遮断量が10dB程度増加していることが分かる。このように、本実施形態のような配置の導体片6を設けることにより、実測値を設計値に近づけることができる。   According to FIG. 5, it can be seen that the blocking amount of the structure of this embodiment is increased by about 10 dB in the vicinity of the frequency band 10.25 although the reflection amounts of both structures are almost the same. Thus, by providing the conductor pieces 6 arranged as in the present embodiment, it is possible to bring the actual measurement value close to the design value.

以上のように、本実施形態の構造体は、誘電体基板と、導体基板と、導体板と、スルーホールビアと、導体面と、導体片と、を備えている。そして、誘電体基板は、基準面と、基準面とは反対側のパッチ面と、基準面と交差する面と、を有している。本実施形態の構造体によれば、導体基板は基準面において誘電体基板と接しており、導体板はパッチ面上において隙間を設けて格子状に配置されている。スルーホールビアは、導体板それぞれごとに設けられており、誘電体基板を貫通して、導体板の1つと導体基板とを接続している。導体面は、基準面と交差する面と対向しており、かつ導体基板に接続されている。導体片は、複数の導体板のうち、導体面がある側の端に配置された第1導体板と、導体面との間に配置されており、かつ導体面に接続されている。このような配置により、端に配置されたパッチ3と、導体片6とが容量性結合する。これにより、構造体の周波数特性を設計値に近づけることができる。   As described above, the structure of the present embodiment includes the dielectric substrate, the conductor substrate, the conductor plate, the through hole via, the conductor surface, and the conductor piece. The dielectric substrate has a reference surface, a patch surface opposite to the reference surface, and a surface intersecting the reference surface. According to the structure of the present embodiment, the conductor substrate is in contact with the dielectric substrate at the reference surface, and the conductor plate is arranged in a lattice form with a gap on the patch surface. Through-hole vias are provided for each of the conductor plates, and penetrate through the dielectric substrate to connect one of the conductor plates to the conductor substrate. The conductor surface faces the surface intersecting with the reference surface, and is connected to the conductor substrate. The conductor piece is disposed between the conductor surface and the first conductor plate disposed at the end on the side where the conductor surface is located among the plurality of conductor plates, and is connected to the conductor surface. Such an arrangement capacitively couples the patch 3 disposed at the end with the conductor piece 6. Thereby, the frequency characteristic of the structure can be brought close to the design value.

本実施形態の構造体の設置先は特に限られるものではない。通信装置、アンテナ、回路などの電磁波を放出するまたは受け取る機器の近くに、本実施形態の構造体を設置することにより、不要な周波数帯域の電磁波を防ぐことができる。例えば、デジタル回路、アナログ回路、デジタル・アナログ混在回路、RF(Radio Frequency)回路、またはアンテナ回路などを搭載する基板を覆う筐体などに、本実施形態の構造体が設けられてもよい。あるいは、超伝導システム、SOC(Syatem on Chip)、擬似SOCを内蔵した装置内に、本実施形態の構造体が設けられてもよい。   The installation destination of the structure of the present embodiment is not particularly limited. By installing the structure of this embodiment near an apparatus that emits or receives an electromagnetic wave such as a communication device, an antenna, or a circuit, an electromagnetic wave in an unnecessary frequency band can be prevented. For example, the structure of this embodiment may be provided in a housing that covers a substrate on which a digital circuit, an analog circuit, a digital / analog mixed circuit, an RF (Radio Frequency) circuit, an antenna circuit, or the like is mounted. Alternatively, the structure of the present embodiment may be provided in a device incorporating a superconducting system, SOC (Synatem Chip), and pseudo SOC.

また、本実施形態の構造体は、いくつかの構造体を組み合わせて、構成されていてもよい。例えば、マッシュルーム構造のEBG構造体と、少なくとも一部が導電面である内壁51を有する筒状の筐体5と、導体片6が表面の縁に設置された蓋と、を組み合わせて、本実施形態の構造体を製造してもよい。当該EBG構造体の導体基板2上に、EBG構造が内壁51に囲まれるように筐体5をかぶせる。そして、導体片6が存在する面がEBG構造を向くようにして、導体片6が導電面と接するように筐体5の上に蓋をかぶせる。蓋をかぶせた状態において、導体片6の端部が、マッシュルーム構造の端に配置されたパッチ3と筐体5の内縁との間に存在していれば、導体片6の端部がバッファエリア72に存在することになり、本実施形態の構造体と同じ配置となる。   Further, the structure of the present embodiment may be configured by combining several structures. For example, this embodiment is implemented by combining an EBG structure having a mushroom structure, a cylindrical casing 5 having an inner wall 51 at least a part of which is a conductive surface, and a lid on which a conductor piece 6 is installed at the edge of the surface. Forms of construction may be manufactured. The housing 5 is placed on the conductor substrate 2 of the EBG structure so that the EBG structure is surrounded by the inner wall 51. Then, the cover is put on the housing 5 so that the conductor piece 6 is in contact with the conductive surface, with the surface on which the conductor piece 6 exists facing the EBG structure. If the end of the conductor piece 6 exists between the patch 3 disposed at the end of the mushroom structure and the inner edge of the housing 5 with the lid covered, the end of the conductor piece 6 is a buffer area As a result, the same arrangement as the structure of this embodiment is obtained.

上記に、本発明の一実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。   While one embodiment of the invention has been described above, these embodiments have been presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

1 誘電体基板
2 導体基板
3、3A、3B、3C 導体板(パッチ)
4 スルーホールビア
5 筐体
51 内壁
6 導体片
71 枠
72 バッファエリア
81、91 遮断量のグラフ
82、92 反射量のグラフ
Reference Signs List 1 dielectric substrate 2 conductor substrate 3, 3A, 3B, 3C conductor plate (patch)
4 through-hole via 5 case 51 inner wall 6 conductor piece 71 frame 72 buffer area 81 91 graph of blocking quantity 82, 92 graph of reflection quantity

Claims (4)

第1面と、前記第1面とは反対側の第2面と、前記第1面と交差する第3面と、を有する誘電体基板と、
前記第1面において、前記誘電体基板と接する導体基板と、
前記第2面上において、互いに隙間を設けて配置された複数の導体板と、
前記誘電体基板を貫通して、前記複数の導体板の1つと前記導体基板とを接続する、前記複数の導体板それぞれごとに設けられた複数のスルーホールビアと、
前記第3面と対向し、かつ前記導体基板に接続された導体面と、
前記複数の導体板のうちの前記導体面がある側の端に配置された第1導体板と、前記導体面との間に配置され、かつ前記導体面に接続された導体片と、
を備える構造体。
A dielectric substrate having a first surface, a second surface opposite to the first surface, and a third surface intersecting the first surface;
A conductor substrate in contact with the dielectric substrate on the first surface;
On the second surface, a plurality of conductor plates arranged with a gap therebetween;
A plurality of through-hole vias provided for each of the plurality of conductor plates, which penetrate the dielectric substrate and connect one of the plurality of conductor plates to the conductor substrate;
A conductor surface facing the third surface and connected to the conductor substrate;
A first conductor plate disposed at an end of the plurality of conductor plates on which the conductor surface is located, and a conductor piece disposed between the conductor surface and connected to the conductor surface;
A structure comprising
前記導体片と、前記第1導体板と、が容量性結合することにより、前記複数の導体板および前記導体片による右手/左手系複合伝送路が形成される
請求項1に記載の構造体。
2. The structure according to claim 1, wherein a capacitive coupling between the conductor piece and the first conductor plate forms a combined right / left handed transmission line by the plurality of conductor plates and the conductor pieces.
前記導体片と、前記第1導体板と、に基づく右手/左手系複合伝送路のQ値が、前記複数の導体板の隣接する導体板同士に基づく右手/左手系複合伝送路のQ値と一致する
請求項2に記載の構造体。
The Q value of the right-hand / left-handed composite transmission line based on the conductor piece and the first conductor plate is the Q value of the right-hand / left-handed composite transmission line based on adjacent conductor plates of the plurality of conductor plates A structure according to claim 2 which matches.
前記前記導体面が、前記誘電体基板を取り囲む、中空の筐体の内壁の少なくとも一部である
請求項1ないし3のいずれか一項に記載の構造体。
The structure according to any one of claims 1 to 3, wherein the conductor surface is at least a part of an inner wall of a hollow casing surrounding the dielectric substrate.
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