JP2019040631A - Circuit verification device, circuit verification method, and computer program - Google Patents

Abstract

To provide technology for performing efficient circuit verification corresponding to setting change of circuit operation.SOLUTION: A circuit verification device includes: a hardware mode storage part 11; and a circuit verification part 12 for, when no hardware mode for verification is stored in the hardware mode storage part 11 about each speed-up circuit 31, executing circuit verification of a verification target device 30 while changing the hardware mode, and for storing the hardware mode set when a speed-up circuit operation flag is turned on as the hardware mode for verification of the corresponding speed-up circuit 31 in the hardware mode storage part 11, and for, when the hardware mode for verification is stored in the hardware mode storage part 11 about each speed-up circuit 31, setting the stored hardware mode, and for executing the circuit verification of the verification target device 30.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a technique for performing circuit verification of a device equipped with a high-speed circuit.

  In general, in a computer system, in order to check whether a circuit mounted on a device operates normally, circuit verification is performed by executing a test program and checking the result. Here, in order to speed up processing, a device to be verified may incorporate a speed-up circuit such as an instruction overtaking circuit or a read data bypass circuit from a memory.

  An example of a technique for performing circuit verification of a device equipped with such a high-speed circuit is described in Patent Document 1. In the related technique described in Patent Document 1, overtaking occurs by changing the memory mapping so that the execution result when the overtaking occurs differs from the execution result when the overtaking does not occur. It is determined whether or not. And when this overtaking occurs, the expected result of the execution result is generated by rearranging and simulating the instruction sequence in the order of overtaking, and the execution result when overtaking occurs is expected. It is determined whether or not it matches the value.

JP2012-160071A

  However, the related art described above has a problem in that it cannot perform efficient circuit verification according to a change in setting of circuit operation.

  Here, as an example of circuit operation setting change, memory configuration information change, arithmetic unit configuration information change, instruction arbitration order change, register usage order change, instruction overtaking function enable / disable Change, whether or not to suppress the arithmetic circuit bypass, or a combination of these setting changes.

  Depending on the setting change of the circuit operation, even if the circuit verification is performed by the same test program, the high-speed circuit may or may not operate. However, the result of the test program is the same whether the high speed circuit operates or not. In such a case, it is conceivable to apply the technique described in Patent Document 1. However, in this related technique, it is necessary to perform overtaking determination and generation of an expected value every time the setting of the circuit operation is changed, and the high-speed circuit cannot be efficiently verified.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a technique for performing efficient circuit verification according to a change in setting of circuit operation.

  The circuit verification device according to the present invention includes a hardware mode storage unit that stores a hardware mode for verification for each high-speed circuit mounted in the device to be verified, and the verification unit stored in the hardware storage unit. And a circuit verification unit configured to perform circuit verification of the verification target device by setting the hardware mode of the verification target device, wherein the circuit verification unit is configured to verify the speed-up circuit in the hardware mode storage unit. If the hardware mode is not stored, the hardware mode is acquired one by one from the list of settable hardware modes, and the circuit verification of the device to be verified is executed while changing the hardware mode, By referring to the speed-up circuit operation flag that is turned on when the speed-up circuit operates, the speed-up circuit operation flag is set. A first verification process for storing the hardware mode set when the signal is turned on as the hardware mode for verification of the speed-up circuit in the hardware mode storage unit, and the speed-up circuit When the hardware mode for verification is stored in the hardware mode storage unit, the verification hardware mode stored is set and the circuit verification of the device to be verified is executed. A verification process is executed.

  The circuit verification method of the present invention includes a hardware mode storage unit that stores a hardware mode for verification for each high-speed circuit mounted in the device to be verified, and the hardware storage unit that stores the hardware mode storage unit. A circuit verification unit that sets a hardware mode for verification and executes circuit verification of the device to be verified, and the circuit verification unit stores the verification mode in the hardware mode storage unit for the acceleration circuit. If the hardware mode is not stored, the hardware mode is acquired one by one from the list of settable hardware modes, the circuit verification of the device to be verified is executed while changing the hardware mode, and the high speed The speed-up circuit operation flag is turned on by referring to the speed-up circuit operation flag that is turned on when the circuit is operated. The hardware mode that is sometimes set is stored in the hardware mode storage unit as a hardware mode for verification of the speed-up circuit, and the hardware mode is set for the speed-up circuit. When the verification hardware mode is stored in the storage unit, a second verification process is executed in which the verification hardware mode is stored and the circuit verification of the device to be verified is performed. .

  The computer program according to the present invention includes a hardware mode storage unit that stores a hardware mode for verification for each high-speed circuit mounted in the device to be verified, and the hardware storage unit that stores the hardware mode storage unit. A circuit verification unit configured to set a hardware mode for verification and execute circuit verification of the device to be verified; and to the circuit verification unit of the computer device, If the hardware mode is not stored, the hardware mode is acquired one by one from the list of settable hardware modes, the circuit verification of the device to be verified is executed while changing the hardware mode, By referring to the speed-up circuit operation flag that is turned on when the speed-up circuit operates, A first circuit verification step of storing the hardware mode set when the circuit operation flag is turned on in the hardware mode storage unit as a hardware mode for verification of the high-speed circuit; When the hardware mode for verification is stored in the hardware mode storage unit for the circuit, the verification hardware mode stored is set and the circuit verification of the device to be verified is executed. 2 circuit verification steps.

  The present invention can provide a technique for performing efficient circuit verification according to a change in setting of circuit operation.

It is a block diagram which shows the structure of the circuit verification system as the 1st Embodiment of this invention. It is a hardware block diagram of the circuit verification system as the 1st Embodiment of this invention. It is a flowchart explaining the outline of operation | movement of the circuit verification system as the 1st Embodiment of this invention. It is a flowchart explaining the 1st verification process of the circuit verification system as the 1st Embodiment of this invention. It is a flowchart explaining the 2nd verification process of the circuit verification system as the 1st Embodiment of this invention. It is a block diagram which shows the structure of the circuit verification system as the 2nd Embodiment of this invention. It is a flowchart explaining the 1st verification process of the circuit verification system as the 2nd Embodiment of this invention.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a configuration of a circuit verification system 1 as a first embodiment of the present invention. In FIG. 1, the circuit verification system 1 includes a circuit verification device 10 and a device to be verified 30. The circuit verification device 10 and the device under verification 30 are connected via a communication path. The circuit verification device 10 includes a hardware mode storage unit 11 and a circuit verification unit 12. Further, the verification target device 30 includes n speed-up circuits 31 (31_1 to 31_n). Note that n is an integer of 1 or more.

  Here, the circuit verification device 10 includes a processor 1001, a memory 1002, and a communication interface 1003, as shown in FIG. In this case, the hardware mode storage unit 11 is configured by the memory 1002. The circuit verification unit 12 includes a communication interface 1003 and a processor 1001 that executes a computer program stored in the memory 1002. Further, the device under verification 30 includes a processor 3001 including a speed-up circuit 31, a memory 3002, and a communication interface 3003. Note that the hardware configuration of each device and each functional block constituting the circuit verification system 1 is not limited to the above-described configuration.

  When the hardware mode is set, the device under verification 30 is configured to operate according to the set hardware mode. The hardware mode represents setting contents related to the operation of the circuit mounted on the own device. For example, the hardware mode is memory configuration information change, arithmetic unit configuration information change, instruction arbitration order change, register use order change, instruction overtaking function enable / disable change, arithmetic circuit bypass It may be a change of whether to suppress or a setting content related to a combination thereof. The hardware mode is set in a hardware mode setting unit (not shown).

  In the verification target device 30, when the processor 3001 executes a computer program while accessing the memory 3002, the acceleration circuit 31 operates as necessary. For example, the speed-up circuit 31 may be an instruction overtaking circuit, a read data bypass circuit from a memory, or the like. For example, when the speed-up circuit 31 is an overtaking circuit, the speed-up circuit 31 executes the succeeding instruction in advance when the succeeding instruction for the memory 3002 from the processor 3001 can be executed before the preceding instruction. . Each of the n speed-up circuits 31 may be the same type of speed-up circuit as at least one other, or may be a type of speed-up circuit different from any other.

  In addition, each speed-up circuit 31 sets a corresponding speed-up circuit operation flag to ON when its own circuit operates. Specifically, each speed-up circuit 31 may turn on a flag corresponding to its own circuit among speed-up circuit operation flags constituted by n flags. In the present embodiment, the high-speed circuit operation flag is configured by the memory 3002 of the device under verification 30. However, in the present invention, the high-speed circuit operation flag may be configured by the memory 1002 of the verification device 10. In that case, each speed-up circuit 31 notifies the verification apparatus 10 that the circuit has been operated via the communication path, and causes the processor 3001 of the verification apparatus 10 to turn on the corresponding speed-up circuit operation flag. Good.

  The hardware mode storage unit 11 of the circuit verification device 10 stores a hardware mode for verification for each acceleration circuit 31 mounted on the device under verification 30. That is, the hardware mode storage unit 11 is configured to be able to store n hardware modes for verification of the n speed-up circuits 31.

  The circuit verification unit 12 is configured to operate as follows when the hardware mode for verification is not stored in the hardware mode storage unit 11 for each high-speed circuit 31 mounted in the device under verification 30. . In this case, the circuit verification unit 12 executes circuit verification of the verification target device 30 while changing the hardware mode. The execution of circuit verification of the device under verification 30 is to cause the device under verification 30 to execute a test program.

  At this time, the circuit verification unit 12 may acquire hardware modes one by one from the list of hardware modes that can be set in the device under verification 30 and sequentially set the devices under verification 30 to execute the test program. . The circuit verification unit 12 refers to the speed-up circuit operation flag described above every time one hardware mode is set and the circuit verification is executed. For the speed-up circuit 31 for which the speed-up circuit operation flag is on, the hardware mode set at that time is stored in the hardware mode storage unit 11.

  When the hardware mode for verification is stored in the hardware mode storage unit 11 for each high-speed circuit 31, the circuit verification unit 12 executes circuit verification while sequentially setting the stored hardware modes. To do.

  The operation of the circuit verification system 1 configured as described above will be described with reference to the drawings.

  First, an outline of the operation of the circuit verification system 1 is shown in FIG.

  In FIG. 3, first, the circuit verification unit 12 of the circuit verification device 10 determines whether or not the hardware mode for verification is stored in the hardware mode storage unit 11 for each acceleration circuit 31 of the device under verification 30. Judgment is made (step S1).

  Here, when the hardware mode for verification is not stored in the hardware mode storage unit 11 for each speed-up circuit 31 of the device under verification 30, the circuit verification unit 12 sets the first mode for the device under verification 30. The verification process is performed (step S2). Details of the first verification process will be described later.

  On the other hand, when a hardware mode for verification is stored in the hardware mode storage unit 11 for each speed-up circuit 31 of the device under verification 30, the circuit verification unit 12 uses the second mode for the device under verification 30. A verification process is performed (step S3). Details of the second verification process will be described later.

  Thus, the circuit verification system 1 ends the operation.

  Next, the first verification process in step S2 will be described with reference to FIG.

  In FIG. 4, the circuit verification unit 12 performs the following steps S <b> 11 to S <b> 15 for the speed-up circuit 31 </ b> _i (i = 1 to n).

  Here, first, the circuit verification unit 12 selects one of the hardware modes that can be set in the device under verification 30 and sets it in the device under verification 30 (step S11).

  Next, the circuit verification unit 12 performs circuit verification of the device under verification 30. Specifically, the circuit verification unit 12 causes the verification target device 30 to execute a test program (step S12).

  Here, when the own circuit operates, each speed-up circuit 31 of the device under test 30 sets the speed-up circuit operation flag corresponding to the own circuit to ON.

  Next, the circuit verification unit 12 checks whether or not the speed-up circuit operation flag corresponding to the speed-up circuit 31_i is turned on after the execution of the test program (step S13).

  If the corresponding speed-up circuit operation flag is on (Yes in step S13), the circuit verification unit 12 sets the hardware set in step S11 as the hardware mode for verification of the speed-up circuit 31_i. The mode is stored in the hardware mode storage unit 11 (step S14).

  At this time, if there is another speed-up circuit 31 in which the corresponding speed-up circuit operation flag is on, the circuit verification unit 12 further sets the hardware mode for verification of the speed-up circuit 31 to the hardware. You may memorize | store in the mode storage part 11. FIG.

  And the circuit verification apparatus 10 complete | finishes the verification process about this speed-up circuit 31_i.

  On the other hand, when the corresponding high-speed circuit operation flag is not on (No in step S13), the circuit verification device 10 is the hardware mode that can be set in the device under verification 30 that has not been set yet. It is confirmed whether or not there is a hardware mode (step S15).

  If there is another hardware mode (Yes in step S15), the circuit verification device 10 repeats the processing from step S11 for one of the other hardware modes.

  On the other hand, if there is no other hardware mode (No in step S15), the circuit verification device 10 ends the verification process for the speed-up circuit 31_i.

  When the processing of steps S11 to S15 is completed for the high-speed circuits 31_1 to 31_n, the circuit verification device 10 ends the first verification processing.

  Next, the second verification process in step S3 will be described with reference to FIG.

  In FIG. 5, the circuit verification unit 12 executes the following steps S <b> 21 to S <b> 22 for the speed-up circuit 31 </ b> _i (i = 1 to n).

  Here, first, the circuit verification unit 12 acquires the hardware mode for verification stored in the hardware mode storage unit 11 for the high-speed circuit 31_i, and sets it in the verification target device 30 (step S21).

  Next, the circuit verification unit 12 performs circuit verification of the device under verification 30. Specifically, the circuit verification unit 12 causes the verification target device 30 to execute a test program and verify the operation of the high-speed circuit 31_i (step S22).

  At this time, the circuit verification unit 12 can also verify other speed-up circuits 31 in which the same hardware mode for verification is stored in the hardware mode storage unit 11.

  When the processing of steps S21 to S22 is completed for the high-speed circuits 31_1 to 31_n, the circuit verification device 10 ends the second verification processing.

  Next, effects of the first exemplary embodiment of the present invention will be described.

  The circuit verification system according to the first exemplary embodiment of the present invention can perform efficient circuit verification according to a change in setting of circuit operation.

  The reason is that the circuit verification unit verifies the circuit while changing the hardware mode when the hardware mode for verification for each high-speed circuit installed in the device to be verified is not stored in the hardware mode storage unit. It is because it performs. Then, the circuit verification unit refers to the speed-up circuit operation flag, and sets the hardware mode set when the speed-up circuit operation flag is turned on to the hardware for verifying the speed-up circuit corresponding to the flag. This is because the hardware mode is stored in the hardware mode storage unit. In addition, when the hardware mode for verification for each high-speed circuit mounted on the device to be verified is stored in the hardware mode storage unit, the circuit verification unit sets the stored hardware mode. This is because circuit verification is executed.

  As a result, in this embodiment, when performing circuit verification for the same type of device to be verified, the circuit verification is performed by setting a hardware mode in which the high-speed circuit is known to operate after the second time. Therefore, the efficiency of circuit verification can be improved.

(Second Embodiment)
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. Note that, in each drawing referred to in the description of the present embodiment, the same reference numerals are given to the same configuration and steps that operate in the same manner as in the first embodiment of the present invention, and the detailed description in the present embodiment. Description is omitted.

  First, FIG. 6 shows a configuration of a circuit verification system 2 as a second embodiment of the present invention. In FIG. 6, the circuit verification system 2 is different from the circuit verification system 1 according to the first exemplary embodiment of the present invention in that a circuit verification device 20 is provided instead of the circuit verification device 10. The circuit verification device 20 includes a circuit verification unit 22 instead of the circuit verification unit 12 and further includes a hardware mode table 23 with respect to the circuit verification device 10 according to the first embodiment of the present invention. The point is different. Each device and each functional block constituting the circuit verification system 2 can be configured by the hardware configuration according to the first embodiment of the present invention described with reference to FIG. However, the hardware configurations of these devices and functional blocks are not limited to the above configurations.

  The circuit verification unit 22 is configured so that the operation when the hardware mode for verification is not stored in the hardware mode storage unit 11 is different from that of the first embodiment of the present invention.

  In this case, the circuit verification unit 22 changes the hardware mode using the hardware mode table 23 prepared for each speed-up circuit 31. Specifically, if there are n speed-up circuits 31 (31_1 to 31_n), n hardware mode tables 23 (23_1 to 23_n) are prepared in the memory 1002 or the like in advance. Each hardware mode table 23 includes one or more effective setting changes for the corresponding acceleration circuit 31 among m hardware modes (m is an integer of 1 or more) that can be set for the device under verification 30. Stores a list of hardware modes.

  Specifically, the circuit verification unit 22 performs circuit verification for each high-speed circuit 31 while sequentially selecting and setting the hardware mode stored in the corresponding hardware mode table 23. Then, the circuit verification unit 22 sets the hardware mode set when the speed-up circuit operation flag is turned on as the hardware mode for verification of the speed-up circuit 31 in the hardware mode storage unit 11. Store it.

  The operation of the circuit verification system 2 configured as described above will be described with reference to the drawings. The operation of the circuit verification system 2 is different from the operation of the circuit verification system 1 as the first embodiment of the present invention in the details of the first verification process in step S2. Details of the first verification process of the circuit verification system 2 are shown in FIG.

  In FIG. 7, the circuit verification unit 22 performs the following steps S31 to S32, S12 to S14, and S35 for the speed-up circuit 31_i (i = 1 to n).

  Here, first, the circuit verification unit 22 acquires a list of hardware modes from the hardware mode table 23_i corresponding to the speed-up circuit 31_i (step S31).

  Next, the circuit verification unit 22 selects one of the hardware mode lists acquired in step S31 and sets it in the verification target device 30 (step S32).

  Next, the circuit verification unit 22 executes Steps S12 to S14 in the same manner as the first verification process in the first embodiment of the present invention. That is, the circuit verification unit 22 causes the device under verification 30 to execute the test program, and when the speed-up circuit operation flag corresponding to the speed-up circuit 31_i is turned on, the hardware mode for verification of the speed-up circuit 31_i is changed to The data is stored in the hardware mode storage unit 11. In this case, the circuit verification device 20 ends the verification process for the speed-up circuit 31_i.

  On the other hand, when the corresponding speed-up circuit operation flag is not on (No in step S13), the circuit verification unit 22 selects other hardware that has not been set from the list acquired from the hardware mode table 23_i. It is confirmed whether there is a mode (step S35).

  If there is another hardware mode (Yes in step S35), the circuit verification device 20 repeats the processing from step S32 for one of the other hardware modes.

  On the other hand, if there is no other hardware mode (No in step S35), the circuit verification device 20 ends the process for the speed-up circuit 31_i.

  When the processes of steps S31 to S32, S12 to S14, and S35 are completed for the high-speed circuits 31_1 to 31_n, the circuit verification device 20 ends the first verification process.

  Next, the effect of the second exemplary embodiment of the present invention will be described.

  The circuit verification system as the second exemplary embodiment of the present invention can perform the circuit verification according to the change in the setting of the circuit operation more efficiently.

  The reason is that the circuit verification unit executes circuit verification for each acceleration circuit while changing the hardware mode using the hardware mode table prepared for each acceleration circuit. As a result, according to the present embodiment, it is not necessary to set a hardware mode that does not affect whether the operation is performed even if the setting is changed depending on the speed-up circuit. The processing for obtaining can be performed more efficiently. In the second embodiment of the present invention, the speed-up circuit operates in the second and subsequent circuit verifications of the same type of device to be verified using the hardware mode for verification obtained as described above. Circuit verification can be performed by setting the hardware mode, and further efficiency can be achieved.

  In each embodiment of the present invention, each functional block of the verification device has been described mainly with an example realized by a processor that executes a computer program stored in a memory. However, a part of each functional block, All or a combination thereof may be realized by dedicated hardware.

  In each embodiment of the present invention, the functional block of the verification device may be realized by being distributed to a plurality of devices.

  In each embodiment of the present invention, the speed-up circuit operation flag may be provided on the verification device side.

  In each embodiment of the present invention, the speed-up circuit of the device to be verified may turn on the speed-up circuit operation flag by another function block that determines that the speed-up circuit has operated.

  In each embodiment of the present invention described above, the operation of the verification device described with reference to each flowchart may be stored in a storage device (storage medium) of a computer device as a computer program of the present invention. Good. Further, the computer program may be read and executed by the processor of the computer device. In such a case, the present invention is constituted by the code of the computer program or a storage medium.

  Moreover, each embodiment mentioned above can be implemented in combination as appropriate.

  The present invention is not limited to the above-described embodiments, and can be implemented in various modes.

DESCRIPTION OF SYMBOLS 1, 2 Circuit verification system 10, 20 Circuit verification apparatus 11 Hardware mode storage part 12, 22 Circuit verification part 23 Hardware mode table 30 Device to be verified 31 Speed-up circuit 1001, 3001 Processor 1002, 3002 Memory 1003, 3003 Communication interface

Claims (6)

For each high-speed circuit mounted in the device to be verified, a hardware mode storage unit that stores a hardware mode for verification;
A circuit verification unit that sets the verification hardware mode stored in the hardware storage unit and executes circuit verification of the device to be verified; and
In a circuit verification apparatus provided with
The circuit verification unit acquires hardware modes one by one from a list of settable hardware modes when the hardware mode for verification is not stored in the hardware mode storage unit for the acceleration circuit. , Executing circuit verification of the device under verification while changing the hardware mode, and referring to the speed-up circuit operation flag that is turned on when the speed-up circuit is operated, The first verification process for storing the hardware mode that is set when is turned on in the hardware mode storage unit as the hardware mode for verification of the high-speed circuit,
When the hardware mode for verification is stored in the hardware mode storage unit for the speed-up circuit, the stored hardware mode for verification is set and the circuit verification of the device to be verified is executed. A circuit verification apparatus that executes a second verification process.   Executing the second verification process using the hardware mode for verification stored in advance or the hardware mode for verification of the acceleration circuit stored in the first verification process; Item 4. The circuit verification device according to Item 1. For each high-speed circuit mounted on the device to be verified, a hardware mode storage unit that stores a hardware mode for verification and a hardware mode for verification stored in the hardware storage unit are set. Using a circuit verification unit that performs circuit verification of the device to be verified,
The circuit verification unit acquires hardware modes one by one from a list of settable hardware modes when the hardware mode for verification is not stored in the hardware mode storage unit for the acceleration circuit. , Executing circuit verification of the device under verification while changing the hardware mode, and referring to the speed-up circuit operation flag that is turned on when the speed-up circuit is operated, The first verification process for storing the hardware mode that is set when is turned on in the hardware mode storage unit as the hardware mode for verification of the high-speed circuit,
When the hardware mode for verification is stored in the hardware mode storage unit for the speed-up circuit, the stored hardware mode for verification is set and the circuit verification of the device to be verified is executed. A circuit verification method for executing a second verification process.   Executing the second verification process using the hardware mode for verification stored in advance or the hardware mode for verification of the acceleration circuit stored in the first verification process; Item 4. The circuit verification method according to Item 3. For each high-speed circuit mounted on the device to be verified, a hardware mode storage unit that stores a hardware mode for verification and a hardware mode for verification stored in the hardware storage unit are set. In the circuit verification unit of the computer device comprising a circuit verification unit that executes circuit verification of the device to be verified,
When the hardware mode for verification is not stored in the hardware mode storage unit for the acceleration circuit, the hardware mode is acquired one by one from a list of settable hardware modes, and the hardware mode is When the speed-up circuit operation flag is turned on by referring to the speed-up circuit operation flag that is turned on when the speed-up circuit is operated, performing circuit verification of the device under verification while changing A first circuit verification step for storing the hardware mode set in the hardware mode storage unit as a hardware mode for verification of the high-speed circuit;
When the hardware mode for verification is stored in the hardware mode storage unit for the speed-up circuit, the stored hardware mode for verification is set and the circuit verification of the device to be verified is executed. A second circuit verification step to:
A computer program that runs In the second circuit verification step,
6. The computer program according to claim 5, wherein the hardware mode for verification stored in advance or the hardware mode for verification of the high-speed circuit stored in the first circuit verification step is used.

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