JP2019040317A - Information processing apparatus, compilation method and compilation program - Google Patents

Abstract

To reduce power consumption of an information processing apparatus while preventing a decrease in performance.SOLUTION: A compilation unit 21 inserts a code for outputting power profiler information 6 into a non-branched loop of a program code 4 and compiles it, and a combining unit 22 combines a profiler library with a compilation result to create an executable code 5. A parallel computer 3 then executes the execution code 5 and outputs power profiler information 6. Then, an analysis unit 23 analyzes the power profiler information 6 to create frequency control information 7, and the compilation unit 21 inserts a frequency control code into the program code 4 on the basis of the frequency control information 7, and compiles it to create the execution code 5. The parallel computer 3 then executes the execution code 5 including the frequency control code.SELECTED DRAWING: Figure 5

Description

  The present invention relates to an information processing apparatus, a compiling method, and a compiling program.

  In fields such as HPC (High Performance Computing), it is important to reduce power consumption while maintaining processing performance. As a technique for reducing power consumption while maintaining processing performance, there is DFS (Dynamic Frequency Scaling) control. DFS control controls power consumption by controlling the operating frequency.

  FIG. 24 is a diagram for explaining power saving by DFS control. In FIG. 24, core # 0 and core # 1 are CPU (Central Processing Unit) cores, and p # 1 to p # 3 are processing units in units of loops. The vertical axis shows the passage of time from top to bottom. FIG. 24A shows an example of power saving by DFS control for the core, and FIG. 24B shows a case where DFS control for the core is not effective.

  In FIG. 24A, the processing of p # 1 is performed by the core # 0, the processing of p # 2 is performed by the core # 1, and the processing of p # 1 and p # 2 is completed. Processing of # 3 is performed. Since the process of p # 2 is completed earlier than p # 1, there is a vacancy in the operation of core # 1. Therefore, for example, if the completion time of p # 2 is not later than the completion time of p # 1 even if the operating frequency of core # 1 is halved, the power consumption of core # 1 is halved. be able to. In this way, when a plurality of cores operate in parallel, if there is a vacant operation in any of the cores, it is possible to save power by lowering the operating frequency of the vacant core.

  There is a technique for controlling a ratio of power distributed to a plurality of components so as to satisfy a preset condition based on at least one operation state of the plurality of components that are supplied with power and perform a predetermined operation.

  In addition, by comparing information regarding the memory performance of the computer with a threshold value, it is determined whether the processing device is in a constraint state that depends on the memory performance, and when the processing device is in a constraint state that depends on the memory performance, There is a technology that performs control to lower the computing capacity. According to this technique, unnecessary computing power can be reduced, and the power consumption of the processing apparatus can be reduced while suppressing a decrease in performance.

JP 2016-189109 A International Publication No. 2008/120274

  As shown in FIG. 24 (b), when there is no vacant core operation, there is a problem that the power consumption of the core cannot be reduced by DFS control. If the operating frequency of any of the cores is lowered, processing will be delayed.

  An object of one aspect of the present invention is to reduce power consumption of an information processing apparatus while preventing performance degradation.

  In one aspect, the information processing apparatus includes a compilation unit, an execution unit, and an analysis unit. The compiling unit generates a first executable code by inserting a code for collecting profiling data into a loop without a branch of the source program. The execution unit executes the first execution code generated by the compiling unit and outputs power profiler information based on the profiling data. The analysis unit analyzes the power profiler information output by the execution unit, and creates frequency control information used for frequency control of a plurality of hardware modules included in the execution unit. Then, the compiling unit inserts frequency control code for controlling the frequency of the plurality of hardware modules into the loop of the source program based on the frequency control information created by the analyzing unit, and generates the second execution code. . Then, the execution unit executes the second execution code generated by the compilation unit.

  In one aspect, the present invention can reduce power consumption of an information processing device while preventing performance degradation.

FIG. 1 is a diagram for explaining loop conditions to be subjected to DFS control. FIG. 2 is a diagram for explaining power saving by the information processing system according to the embodiment. FIG. 3 is a diagram for explaining a case where power consumption can be reduced without degrading performance. FIG. 4A is a diagram for describing a first case in which power consumption can be reduced in a loop. FIG. 4B is a diagram for describing a second case in which power consumption can be reduced in a loop. FIG. 4C is a diagram for describing a third case in which power consumption can be reduced in a loop. FIG. 5 is a diagram illustrating the configuration of the information processing system according to the embodiment. FIG. 6A is a diagram illustrating an operation (data collection) of the information processing system. FIG. 6B is a diagram illustrating an operation (data analysis) of the information processing system. FIG. 7 is a diagram illustrating an example of a command. FIG. 8 is a flowchart showing a processing flow of profiling translation. FIG. 9 is a diagram illustrating an example of translation for profiling. FIG. 10A is a diagram illustrating an example of a flow of processing for collecting profiling data and power profiler information. FIG. 10B is a diagram illustrating an example of collecting profiling data. FIG. 11 is a flowchart showing a flow of processing for analyzing the power profiler information. FIG. 12 is a flowchart illustrating a process flow for calculating the busy rate. FIG. 13 is a diagram illustrating an example of a busy rate calculation formula. FIG. 14 is a diagram illustrating an example of busy rate information. FIG. 15 is a flowchart illustrating a process flow for determining a frequency control method. FIG. 16A is a diagram illustrating an example of frequency control information. FIG. 16B is a diagram illustrating another example of the frequency control information. FIG. 17 is a diagram illustrating an analysis example of profiling data. FIG. 18 is a flowchart showing a flow of processing for embedding the frequency control code. FIG. 19 is a diagram illustrating an example of a frequency control function inserted as a frequency control code. FIG. 20 is a diagram illustrating an example of embedding the frequency control code in the program code. FIG. 21 is a flowchart showing a flow of power saving execution by the retranslation code. FIG. 22 is a diagram illustrating an example of customization by the user. FIG. 23 is a diagram illustrating a hardware configuration of a computer that executes the management program according to the embodiment. FIG. 24 is a diagram for explaining power saving by DFS control.

  Embodiments of an information processing apparatus, a compiling method, and a compiling program disclosed in the present application will be described below in detail with reference to the drawings. Note that this embodiment does not limit the disclosed technology.

  In the DFS control according to the embodiment, the DFS control is performed using a loop as a processing unit. Therefore, first, the conditions of the loop to be subjected to DFS control will be described. FIG. 1 is a diagram for explaining loop conditions to be subjected to DFS control. As shown in FIG. 1, there are loops in which the busy state of the CPU resource changes and loops in which the CPU resource does not change. Here, the CPU resource is a hardware module related to CPU processing, and includes, for example, a memory, an L2 cache, an L1 cache, and an arithmetic unit.

  As shown in FIG. 1A, the loop in which the busy state changes is a loop having a complicated control structure and a branch having a branch such as if. If there is a branch, the flow of processing due to instruction execution is interrupted, and the use of CPU resources is not uniform. That is, when a branch occurs, the instruction sequence is interrupted and the busy state of the operation changes. In addition, since continuity of data access is interrupted, the busy state of the memory and the cache system also changes.

  On the other hand, as shown in FIG. 1B, the loop in which the busy state does not change is a loop having a simple control structure and is a loop having no branch such as if. If there is no branching, the flow of processing is uniform, so the use of CPU resources is uniform and the busy state does not change. In FIG. 1B, the calculation process is performed for a plurality of lines. Basically, the process is a process of loading data, calculating the result, and saving the result. Therefore, the usage state of the CPU resources is uniform.

  For a loop in which the busy state changes, uniform DFS control cannot be performed. Therefore, the information processing system according to the embodiment performs DFS control for a loop in which the busy state does not change.

  Next, power saving by the information processing system according to the embodiment will be described. FIG. 2 is a diagram for explaining power saving by the information processing system according to the embodiment. In FIG. 2, M represents a memory, L # 2 represents an L2 cache, L # 1 represents an L1 cache, and C represents an arithmetic unit. p # 1 and p # 2 are processing units in units of loops. The vertical axis shows the passage of time from top to bottom. Further, there are a memory, an L2 cache, an L1 cache, and an arithmetic unit as hardware modules related to the processing of the core # 0. The square of the hardware module represents the time when the hardware module is busy.

  As shown in FIG. 2, in the normal state, the entire operation of the core # 0 has no vacancy, but there is a vacancy in units of hardware modules. Therefore, the information processing system according to the embodiment performs DFS control in units of hardware modules.

  For example, in the process of p # 1, since the operation of the L2 cache memory is free, the information processing system according to the embodiment sets the power of the L2 cache memory to ½. In addition, since there is a vacancy in the operation of the arithmetic unit, the information processing system according to the embodiment sets the power of the arithmetic unit to ¼.

  By setting the power of the computing unit to ¼, the operation time of the computing unit is quadrupled, but the time of p # 1 is determined by the memory time, so there is no influence on the performance. The same applies to the L2 cache, and even if the power is halved, there is no influence on the performance.

  Also, in the process of p # 2, since there is a vacant memory operation, the information processing system according to the embodiment sets the memory power to ½. Note that by setting the operating frequency to 1/2, the power of the hardware module becomes 1/2, and by setting the operating frequency to 1/4, the power of the hardware module becomes 1/4.

  FIG. 3 is a diagram for explaining a case where power consumption can be reduced without degrading performance. In FIG. 3, the value represents a time ratio, and the larger the value, the slower the processing. As shown in FIG. 3, in case (1), memory access is a bottleneck. For example, even if the operating frequency of the arithmetic unit is set to 1/4, the performance does not deteriorate. Also in case (2), memory access is a bottleneck. For example, even if the operating frequency of the L2 cache is halved, the performance does not deteriorate.

  In the case (3), the L2 cache access is a bottleneck. For example, even if the memory operating frequency is halved, the performance does not deteriorate. Case (3) differs from cases (1) and (2) in the mechanism by which the operating frequency can be reduced. In cases (1) and (2), the operating frequency of a hardware module with a high operating speed is lowered due to the difference in operating speed between hardware modules. On the other hand, Case (3) is a case where the L2 on-cache causes an L2 cache bottleneck, and if the on-cache state continues for a certain period of time, there is a problem even if the data supply to the L2 cache is delayed when viewed from the memory. This is not the case.

  4A to 4C are diagrams for describing a case in which power consumption can be reduced in a loop. 4A shows a case of reducing the frequency of arithmetic processing at the time of memory access neck, FIG. 4B shows a case of reducing the frequency of cache processing at the time of memory access neck, and FIG. 4C shows the frequency reduction of the memory access at the time of cache access neck. It is a case.

  4A to 4C, “−” represents that the hardware module is busy at the first rotation, “=” represents that the hardware module is busy at the second rotation, and “+”. Indicates that the hardware module is busy at the third rotation. One character of “−”, “=”, and “+” represents one unit time. In addition, since arithmetic processing is performed when memory access or cache access is completed, the arithmetic processing waits for completion of memory access or cache access.

  FIG. 4A (a) is a program example of the case shown in FIG. 4A. As shown in FIG. 4A (a), in the case of FIG. 4A, three iterations are performed. FIG. 4A (b) shows a case where the performance does not deteriorate. As shown in FIG. 4A (b), when memory access takes 4 unit hours and computation processing takes 2 unit hours, the cost of only the last “++” increases even if the computation processing frequency is reduced to ½. There is almost no performance degradation.

  On the other hand, as shown in FIG. 4A (c), when the memory access takes 2 unit hours and the calculation process takes 2 unit hours, if the frequency of the calculation process is reduced to 1/2, the process can be repeated three times. 8 unit time becomes 14 unit time, and performance degradation occurs.

  Further, as shown in FIG. 4A (d), when the number of repetitions is as large as 1000000, the last “++” shown in FIG. 4A (b) has a small ratio in the entire processing time and a performance degradation. Does not occur.

  Further, as shown in FIG. 4B, even if the cache access frequency is reduced to ½, there is no cost increase and no performance degradation. Furthermore, even if the frequency of the arithmetic processing is reduced to ½, only the last “+” increases the cost, and there is almost no performance decrease.

  Further, as shown in FIG. 4C (a), even if the memory access frequency is reduced to ½, only the last “+” increases in cost due to the influence of the delay of the first memory access, and the performance decreases. There is almost no. In FIG. 4C (a), since the memory access and the cache access operate in parallel, the memory access is hidden by the on-cache cache access and does not affect the performance. Further, as shown in FIG. 4C (b), when the number of rotations is increased to 1000000, the influence of the last “+” is 1 / (1 + 1000000 × 5 + 1), and there is almost no performance degradation.

  Next, the configuration of the information processing system according to the embodiment will be described. FIG. 5 is a diagram illustrating the configuration of the information processing system according to the embodiment. As illustrated in FIG. 5, the information processing system 1 according to the embodiment includes a management device 2 and a parallel computer 3. The management device 2 manages the execution of the parallel computer 3. The parallel computer 3 includes a plurality of computers, and each computer or a plurality of cores included in each computer performs processing in parallel. A plurality of computers are mesh-connected or torus-connected in two dimensions, three dimensions, six dimensions, and the like.

  The management device 2 includes a compiling unit 21, a combining unit 22, and an analyzing unit 23. The compiling unit 21 translates the program code (source program) 4. The compile unit 21 performs profiling translation when profile collection is designated. When the compile unit 21 performs profiling translation, the combining unit 22 combines the profiler library with the translation result and creates the execution code 5.

  The execution code 5 is executed by the parallel computer 3. When the compiling unit 21 performs the profiling translation, the parallel computer 3 executes the execution code 5 and outputs the power profiler information 6. The power profiler information 6 is hardware counter information related to the power of the parallel computer 3.

  The analysis unit 23 analyzes the power profiler information 6, determines the frequency control method of each hardware module for each loop, and creates the frequency control information 7. The frequency control information 7 is information that defines a frequency ratio between hardware modules for each loop.

  The compiling unit 21 inserts a frequency control code into the program code 4 based on the frequency control information 7 and creates an execution code 5. The execution code 5 is executed by the parallel computer 3. When the frequency control code is included in the execution code 5, the parallel computer 3 executes the execution code 5 while controlling the frequency of the hardware module.

  The compiling unit 21 includes a first insertion unit 21a and a second insertion unit 21b. When the compiling unit 21 performs translation for profiling, the first insertion unit 21a determines whether or not a branch is included for each loop, and inserts a code that calls the profiler library for the loop that does not include a branch. .

  The second insertion unit 21 b inserts a frequency control code into the program code 4 based on the frequency control information 7. The second insertion unit 21b performs optimization when inserting the frequency control code and deletes unnecessary frequency control codes.

  The analysis unit 23 includes a calculation unit 23a and a creation unit 23b. The calculation unit 23a calculates the busy rate of each hardware module for each loop based on the power profiler information 6, and creates busy rate information. The creation unit 23b determines the frequency control method of each hardware module for each loop based on the busy rate information, and creates the frequency control information 7.

  Here, the management device 2 includes the compile unit 21, the coupling unit 22, and the analysis unit 23, but a device different from the management device 2 may include the compile unit 21, the coupling unit 22, and the analysis unit 23. Further, a device different from the management device 2 may include any of the compiling unit 21, the combining unit 22, and the analyzing unit 23. Further, a first device different from the management device 2 may include the compiling unit 21 and the combining unit 22, and a second device different from the management device 2 and the first device may include the analysis unit 23. The compiling unit 21 may have the functions of the combining unit 22 and the analyzing unit 23.

  Next, the operation of the information processing system 1 will be described. 6A is a diagram illustrating an operation (data collection) of the information processing system 1, and FIG. 6B is a diagram illustrating an operation (data analysis) of the information processing system 1. 6A and 6B, CMP indicates a compilation process, EXE indicates execution of the execution code 5, and ANL indicates power control analysis.

  As shown in FIG. 6A, the information processing system 1 inputs the program code 4 and performs profiling translation (step S1). The information processing system 1 performs the profiling translation when the profiling translation is designated. Then, the information processing system 1 combines the profiler library with the translation result and generates an execution code 5 (step S2).

  Modification of the program code 4 is not necessary, and the information processing system 1 only performs profiling translation and combines the profiler library. The information processing system 1 inserts a collection code of hardware counter information related to power for each loop by profiling translation.

  Then, the information processing system 1 executes fapp (step S3). The information processing system 1 executes the fapp command, so that the profiler collects hardware counter information related to power for each loop (step S4), and creates power profiler information 6.

  Then, as illustrated in FIG. 6B, the information processing system 1 executes fapppx (step S5). The information processing system 1 executes power control analysis using the fapppx command. In the power control analysis, the information processing system 1 calculates the busy rate of the hardware module of the parallel computer 3, determines an optimal frequency control method from the busy rate, and outputs the frequency control information 7.

  Then, the information processing system 1 embeds the frequency control code according to the frequency control information 7 (step S6), translates it, and creates the execution code 5. Since the execution code 5 includes the frequency control code, the information processing system 1 can reduce power consumption by executing the execution code 5.

  FIG. 7 is a diagram illustrating an example of a command. In the first translation (1), fcc-eco-busy a. c is used. fcc is a command for instructing compilation of the C program. -Eco-busy specifies a translation for inserting a busy state collection code in the power saving mode. Here, the busy state collection code is a code for collecting information for specifying the busy state of the hardware module. a. c is the program name.

  In data collection (2), fapp-eco-w Vprof. dat a. out is used. “fapp” is a command for instructing collection of the power profiler information 6. -Eco specifies execution of profiling in the power saving mode. -W File specifies the file name of the output destination of the power profiler information 6. a. out is an execution code name.

  In data analysis (3), fappxx-eco-w Vprof. dat -f freq. dat is used. fapppx is a command for instructing analysis of the power profiler information 6. -Eco specifies profiling data analysis in power saving mode. -W Dir specifies the input file name of the power profiler information 6. -F freq. dat designates the output destination file name of the frequency control information 7.

  In retranslation (4), fcc-eco-ffreq. txt a. c is used. -Eco specifies translation in the power saving mode. -F File specifies the file name of the frequency control information 7.

  In the power saving execution (5), a. out [-eco | -noeco] is used. -Eco specifies execution in the power saving mode, and -noeco specifies execution not in the power saving mode. The frequency control code is ignored for executions that are not in power saving mode. -Eco is the default. a. out is an execution code name.

  Next, a processing flow and a processing example of the information processing system 1 will be described. FIG. 8 is a flowchart showing a processing flow of profiling translation. As shown in FIG. 8, the compiling unit 21 reads the program code 4 (step S11), and performs the processing of steps S12 to S13 for each loop (I).

  That is, the compiling unit 21 determines whether or not there is a branch process in the loop (step S12), and when there is a branch process in the loop, the next loop is processed. On the other hand, when there is no branch processing in the loop, the compiling unit 21 inserts profiling code before and after the loop (step S13), and processes the next loop. When all the loops are processed, the compiling unit 21 ends the profiling translation process.

  As described above, the compile unit 21 inserts the profiling code for a loop without branch processing, thereby enabling frequency control for a loop in which the use of CPU resources is uniform.

  FIG. 9 is a diagram illustrating an example of translation for profiling. FIG. 9A shows the program code 4, and FIG. 9B shows the code in which the busy state collection code is inserted. a. f indicates that the program code 4 is described in FORTRAN. As shown in FIG. 9A, the program code 4 includes three do loops. Since there is no branch processing in the first and third loops, as shown in FIG. 9B, call busy_start () and call busy_stop () are inserted as busy state collection codes. On the other hand, since there is a branch process by the if statement in the second loop, the busy state collection code is not inserted.

  FIG. 10A is a diagram illustrating an example of the flow of processing for collecting profiling data and the power profiler information 6. FIG. 10B is a diagram illustrating an example of collecting profiling data.

  As shown in FIG. 10A, the parallel computer 3 starts collecting hardware counter information at the head of the loop (step S21). Then, the parallel computer 3 collects hardware counter information necessary for obtaining the following busy rate (step S22). The busy rate includes a memory access usage rate, an L2 cache access usage rate, an L1 cache access usage rate, and an arithmetic processing usage rate.

  The hardware counter information necessary for obtaining these busy rates includes the cycle count, the number of L1 cache misses, the number of L2 cache misses, the number of instruction commits, the L1 pipe valid, and the L2 write back. The power profiler information 6 is information for associating the cycle count, the number of L1 cache misses, the number of L2 cache misses, the number of instruction commits, the information of L1 pipe valid and L2 write back together with the number of calls to the loop. Since the hardware counter information raised above depends on the CPU architecture, the necessary hardware counter information also changes according to the CPU architecture.

  For example, in FIG. 10A, the cycle count “145032”, L1 cache miss number “3985”, L2 cache miss number “7890”, instruction commit number “2298”, L1 pipe valid “4982”, L2 Write back “11208” and the number of calls “100” are associated with each other. In FIG. 10A, the power profiler information 6 includes a plurality of records, and one record includes information associated with one loop. A plurality of records may be associated with one loop.

  Then, the parallel computer 3 finishes collecting the hardware counter information at the end of the loop (step S23). Then, the parallel computer 3 outputs the collected hardware counter information and call count information as power profiler information 6 for each loop (step S24).

  Also, as shown in FIG. 10B, profiling data is collected for the first and third loops without branch processing. In FIG. 10B, “func1-1” and “func1-2” are section names. The section is associated with a loop without branch processing.

  FIG. 11 is a flowchart showing a flow of processing for analyzing the power profiler information 6. As shown in FIG. 11, the analysis unit 23 reads the power profiler information 6 (step S31), and calculates the busy rate of each loop (step S32). And the analysis part 23 determines the frequency control method of each hardware module for every loop (step S33), and produces the frequency control information 7. FIG.

  FIG. 12 is a flowchart illustrating a process flow for calculating the busy rate. In FIG. 12, one section has a plurality of collection timings, and one record includes one collection data. As shown in FIG. 12, the analysis unit 23 initializes the busy rate to 0 (step S41).

  And the analysis part 23 takes out information for every record (I) from the electric power profiler information 6, and performs the process of step S42 about all the records. In step S42, the analysis unit 23 adds the cycle count, the number of L1 cache misses, the number of L2 cache misses, the number of instruction commits, the L1 pipe valid, and the L2 write back for each section.

And the analysis part 23 calculates the busy rate for every area (step S43), and produces busy rate information. FIG. 13 is a diagram illustrating an example of a busy rate calculation formula. As shown in FIG.
Memory busy rate = memory throughput / memory throughput upper limit L2 busy rate = (L2 throughput + memory throughput × coefficient) / L2 throughput upper limit L1 busy rate = L1 pipe valid / cycle count Operation busy rate = floating point operation pipeline / cycle count is there.

here,
Memory throughput = (L2 cache miss number + L2 write back) × cache line size / cycle count / clock frequency L2 throughput = L1 cache miss number × cache line size / cycle count / clock frequency. The coefficients used for calculating the L2 busy rate are 0.3, 0.6, and the like.

  FIG. 14 is a diagram illustrating an example of busy rate information. As shown in FIG. 14, the busy rate information is information indicating a memory busy rate, an L2 busy rate, an L1 busy rate, and an operation busy rate in each section. The busy rate information also indicates the total time and number of calls for each section. For example, the memory busy rate of “loop # 1” is “80%”, the L2 busy rate is “20%”, the L1 busy rate is “30%”, and the operation busy rate is “20%”. Yes, the total time is “13 seconds”, and the number of calls is “100”.

  FIG. 15 is a flowchart illustrating a process flow for determining a frequency control method. As illustrated in FIG. 15, the analysis unit 23 performs the processes of steps S <b> 51 to S <b> 57 for each section (I) included in the busy rate information.

  That is, the analysis unit 23 stores the hardware module M and the value R that maximize the busy rate, and sets the power ratio of M to 1.00 (step S51). And the analysis part 23 performs the process of step S52-step S57 about each of the remaining three hardware modules (J).

  That is, the analysis unit 23 calculates the power ratio of J = the busy rate of J / the busy rate of M (step S52). Then, the analysis unit 23 adjusts the power ratio to 1, 0.50, or 0.25 using the two threshold values 0.4 and 0.2. Specifically, the analysis unit 23 determines whether or not the power ratio is 0.4 or more (step S53), and if it is 0.4 or more, sets the power ratio to 1.00 (step S57). ). On the other hand, when the power ratio is not 0.4 or more, the analysis unit 23 determines whether or not the power ratio is 0.2 or more (step S54). The power ratio is set to 0.25 if not 0.5 or more (step S56). Then, the analysis unit 23 creates the frequency control information 7.

  As described above, the analysis unit 23 determines the power ratio of the hardware module as the frequency control method and creates the frequency control information 7, so that the compilation unit 21 inserts the frequency control code based on the frequency control information 7. Can do.

  FIG. 16A is a diagram illustrating an example of the frequency control information 7. As shown in FIG. 16A, the frequency control information 7 associates a memory frequency ratio, an L2 frequency ratio, an L1 frequency ratio, and an operation frequency ratio with each section. Here, the frequency ratio of each hardware module is the power ratio determined by the processing shown in FIG. The frequency control information 7 associates the total time and the number of calls with each section. For example, the memory frequency ratio of the section “loop # 1” is “1.00”, the L2 frequency ratio is “0.25”, the L1 frequency ratio is “0.50”, and the calculation frequency ratio is “ 0.25 ”, the total time is“ 13 seconds ”, and the number of calls is“ 100 ”.

  FIG. 16B is a diagram showing another example of the frequency control information 7. FIG. 16B shows a case where the adjustment of the power ratio using the threshold is not performed. For example, the memory frequency ratio of the section “loop # 1” is “1.00”, the L2 frequency ratio is “0.20”, the L1 frequency ratio is “0.30”, and the calculation frequency ratio is “ 0.20 ”, the total time is“ 13 seconds ”, and the number of calls is“ 100 ”.

  FIG. 17 is a diagram illustrating an analysis example of profiling data. As shown in FIG. 17, busy rate information is created from the power profiler information 6, and frequency control information 7 is created from the busy rate information.

  FIG. 18 is a flowchart showing a flow of processing for embedding the frequency control code. As shown in FIG. 18, the compiling unit 21 reads the frequency control information 7 (step S61). Then, the compiling unit 21 performs the following processing in steps S62 to S63 for each section (I) of the frequency control information 7.

  That is, the compiling unit 21 determines whether or not the one-section average time is less than the threshold value (step S62). Here, the section average time is the total time / number of calls. Then, the compiling unit 21 processes the next section when the one-section average time is less than the threshold value, and inserts the frequency control code before and after the loop corresponding to the section when the average time is less than the threshold value. (Step S63). Then, when the processes in steps S62 to S63 are finished for all the sections, the compiling unit 21 finishes the process of embedding the frequency control instruction.

  In this way, the compiling unit 21 can prevent overhead due to frequency control for a loop with a small power saving effect by not embedding the frequency control code when the average time of one section is less than the threshold. .

  FIG. 19 is a diagram illustrating an example of a frequency control function inserted as a frequency control code. FIG. 19A shows function specifications, and FIG. 19B shows an example of compilation output. As shown in FIG. 19A, the frequency control function freqcntl has four arguments. arg # 1 is a memory frequency control value, arg # 2 is an L2 cache frequency control value, arg # 3 is an L1 cache frequency control value, and arg # 4 is an arithmetic unit frequency control value. .

  Further, as shown in FIG. 19B, frequency control functions are inserted before and after the four loops represented by loop # 1 to loop # 4. In FIG. 19B, the L2 frequency is the frequency of the L2 cache, the L1 frequency is the frequency of the L1 cache, and the calculation frequency is the frequency of the calculator.

  The frequency control function deleted by the strikethrough is a frequency control function deleted by optimization by the compiling unit 21. When the frequency control function is continuous, the previous frequency control function is deleted. Also, duplicate frequency control functions with the same values for all arguments as before are deleted.

  In this way, the compiling unit 21 can eliminate unnecessary frequency control overhead by performing optimization.

  FIG. 20 is a diagram illustrating an example of embedding the frequency control code in the program code 4. As shown in FIG. 20, a frequency control code for increasing the efficiency of the arithmetic unit by 0.5 is embedded in the first loop. There is no frequency control code for the second loop. Since the efficiency remains 1.0 times for the third loop, the frequency control code is not embedded.

  FIG. 21 is a flowchart showing a flow of power saving execution by the retranslation code. As shown in FIG. 21, the parallel computer 3 determines whether or not it is the -noeco option (step S71). If it is not the -noeco option, the frequency is set for each hardware module according to the argument in the freqcntl function. Change (step S72). On the other hand, if it is the -noeco option, the parallel computer 3 does not perform the process of step S72.

  As described above, the parallel computer 3 executes the execution code 5 with the -noco option, so that the user can compare with the power saving execution.

  FIG. 22 is a diagram illustrating an example of customization by the user. In FIG. 22, the user has customized the frequency control information 7. As shown in FIG. 22, if the performance is not affected even if the program is executed with the calculation frequency ratio set to 0.50, the user executes the program with the calculation frequency ratio set to 0.25. With such customization, the user can save power while suppressing a decrease in performance.

  As described above, in the embodiment, the compiling unit 21 inserts and compiles the code that outputs the power profiler information 6 into the loop without the branch of the program code 4, and the combining unit 22 adds the profiler library to the compilation result. The execution code 5 is generated by combining them. Then, the parallel computer 3 executes the execution code 5 and outputs the power profiler information 6. Then, the analysis unit 23 analyzes the power profiler information 6 to create frequency control information 7, and the compiling unit 21 inserts and compiles the frequency control code into the program code 4 based on the frequency control information 7, and executes the execution code 5. Is generated. Then, the parallel computer 3 executes the execution code 5 including the frequency control code.

  Therefore, the information processing system 1 can reduce the power consumption of the parallel computer 3 while preventing performance degradation. Further, by performing the frequency control only once for the loop, it is possible to reduce the overhead of the frequency control as compared with the case where the frequency control is performed in stages.

  In the embodiment, the analysis unit 23 creates busy rate information based on the power profiler information 6, determines a frequency control method based on the busy rate information, and creates the frequency control information 7. Therefore, the analysis unit 23 can create accurate frequency control information 7.

  In the embodiment, the power profiler information 6 includes a cycle count, the number of L1 cache misses, the number of L2 cache misses, a floating point arithmetic pipeline, an L1 pipe valid, and an L2 write back. The hardware module includes a memory, an L2 cache, an L1 cache, and an arithmetic unit. Then, the analysis unit 23 determines the busy rate of the memory, the L2 cache, the L1 cache, and the arithmetic unit based on the cycle count, the number of L1 cache misses, the number of L2 cache misses, the floating point arithmetic pipeline, the L1 pipe valid, and the L2 write back. calculate. Therefore, the analysis unit 23 can accurately calculate the busy rate of the memory, the L2 cache, the L1 cache, and the arithmetic unit. Further, the analysis unit 23 can acquire hardware counter information necessary for calculating the busy rate with one collection.

  In the embodiment, the compiling unit 21 determines whether or not the average time of one section is less than the threshold when inserting the frequency control code into the program code 4 based on the frequency control information 7. If it is less, the frequency control code is not inserted. Therefore, the compiling unit 21 can prevent the occurrence of overhead due to frequency control for a loop with a small power saving effect.

  In the embodiment, the compiling unit 21 inserts a frequency control function for changing the frequency before each loop, and inserts a frequency control function for returning the frequency after each loop. When there is a frequency control function that changes the frequency immediately after the frequency control function that restores the frequency, the compiling unit 21 deletes the frequency control function that restores the frequency. Therefore, the compiling unit 21 can eliminate unnecessary frequency control overhead.

  In addition, although the management apparatus 2 was demonstrated in the Example, the management program which has the same function can be obtained by implement | achieving the structure which the management apparatus 2 has with software. Therefore, a computer that executes the management program will be described.

  FIG. 23 is a diagram illustrating a hardware configuration of a computer that executes the management program according to the embodiment. As shown in FIG. 23, the computer 50 includes a main memory 51, a CPU 52, a LAN (Local Area Network) interface 53, and an HDD (Hard Disk Drive) 54. The computer 50 includes a super IO (Input Output) 55, a DVI (Digital Visual Interface) 56, and an ODD (Optical Disk Drive) 57.

  The main memory 51 is a memory for storing a program and a program execution result. The CPU 52 is a central processing unit that reads a program from the main memory 51 and executes it. The CPU 52 includes a chip set having a memory controller.

  The LAN interface 53 is an interface for connecting the computer 50 to another computer via a LAN. The HDD 54 is a disk device that stores programs and data, and the super IO 55 is an interface for connecting an input device such as a mouse or a keyboard. The DVI 56 is an interface for connecting a liquid crystal display device, and the ODD 57 is a device for reading / writing a DVD.

  The LAN interface 53 is connected to the CPU 52 by PCI Express (PCIe), and the HDD 54 and ODD 57 are connected to the CPU 52 by SATA (Serial Advanced Technology Attachment). The super IO 55 is connected to the CPU 52 by LPC (Low Pin Count).

  A management program executed in the computer 50 is stored in a DVD that is an example of a recording medium readable by the computer 50, read from the DVD by the ODD 57, and installed in the computer 50. Alternatively, the management program is stored in a database or the like of another computer system connected via the LAN interface 53, read from these databases, and installed in the computer 50. The installed management program is stored in the HDD 54, read into the main memory 51, and executed by the CPU 52.

  In the embodiment, the case where the parallel computer 3 executes the execution code 5 has been described. However, an information processing apparatus capable of controlling the frequency of the hardware module may execute the execution code 5.

  In the embodiment, the case where the operating frequencies of the memory, the L2 cache, the L1 cache, and the arithmetic unit are controlled has been described. However, the operating frequencies of other hardware modules may be controlled. Further, as hardware counter information, information other than the cycle count, the number of L1 cache misses, the number of L2 cache misses, the floating point arithmetic pipeline, the L1 pipe valid, and the L2 write back may be used.

  In the embodiment, the case where the analysis unit 23 creates the frequency control information 7 has been described. However, the analysis unit 23 may display the analysis result on the display device in addition to the power profiler information 6.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Supplementary Note 1) A compiling unit that inserts a code for collecting profiling data into a loop without a branch of a source program to generate a first execution code;
An execution unit that executes the first execution code generated by the compiling unit and outputs power profiler information based on the profiling data;
An analysis unit that analyzes the power profiler information output by the execution unit and creates frequency control information used for frequency control of a plurality of hardware modules included in the execution unit;
The compiling unit inserts a frequency control code for controlling the frequencies of the plurality of hardware modules into the loop of the source program based on the frequency control information created by the analyzing unit, and executes a second execution code. Produces
The information processing apparatus, wherein the execution unit executes the second execution code generated by the compiling unit.

(Appendix 2) The analysis unit
A calculation unit that calculates a busy rate of the plurality of hardware modules in each loop based on the power profiler information;
The information processing apparatus according to claim 1, further comprising: a generation unit that determines a frequency control method for each loop based on a plurality of busy rates calculated by the calculation unit and generates the frequency control information.

(Supplementary Note 3) The power profiler information includes a cycle count, the number of L1 cache misses, the number of L2 cache misses, a floating point arithmetic pipeline, an L1 pipe valid, and an L2 writeback.
The plurality of hardware modules of the execution unit include a memory, an L2 cache, an L1 cache, and an arithmetic device.
The calculation unit calculates the busy rate of the memory, the L2 cache, the L1 cache, and the arithmetic unit based on the cycle count, the number of L1 cache misses, the number of L2 cache misses, the floating point arithmetic pipeline, the L1 pipe valid, and the L2 write back. The information processing apparatus according to Supplementary Note 2, wherein

(Supplementary Note 4) The frequency control information includes an execution time of a section corresponding to the loop,
The compiling unit generates a second execution code by inserting a frequency control code for controlling the frequency of the plurality of hardware modules into the loop when the average execution time of the section is equal to or greater than a predetermined threshold. The information processing apparatus according to appendix 1, 2, or 3, wherein:

(Supplementary Note 5) The compiling unit inserts a frequency control code for changing the frequency before each loop for the plurality of loops, inserts a frequency control code for returning the frequency after each loop, and based on the frequency The information processing according to any one of appendices 1 to 4, wherein when there is a frequency control code for changing the frequency immediately after the frequency control code to be returned, the frequency control code for returning the frequency is deleted. apparatus.

(Appendix 6)
Insert the code that collects the profiling data into the loop without the branch of the source program to generate the first execution code,
Frequency control created for frequency control of a plurality of hardware modules included in the processing device based on power profiler information created using profiling data collected by executing the first execution code by the processing device Compiled by executing a process of generating a second executable code by inserting a frequency control code for controlling a frequency of the plurality of hardware modules into the loop of the source program based on information Method.

(Appendix 7)
Insert the code that collects the profiling data into the loop without the branch of the source program to generate the first execution code,
Frequency control created for frequency control of a plurality of hardware modules included in the processing device based on power profiler information created using profiling data collected by executing the first execution code by the processing device Compile characterized in that, based on the information, a process for generating a second executable code by inserting a frequency control code for controlling the frequency of the plurality of hardware modules into the loop of the source program is executed. program.

(Appendix 8)
Read the power profiler information created by using the profiling data collected when the execution code inserted into the loop without the branch of the source program is the code that collects the profiling data,
An analysis program for executing a process of analyzing read power profiler information and generating frequency control information used for frequency control of a plurality of hardware modules included in the processing device.

(Appendix 9) The process to create is
Calculating a busy rate of the plurality of hardware modules in each loop based on the power profiler information;
The analysis program according to appendix 8, wherein a frequency control method for each loop is determined based on the calculated plurality of busy rates, and the frequency control information is created.

DESCRIPTION OF SYMBOLS 1 Information processing system 2 Management apparatus 3 Parallel computer 4 Program code 5 Execution code 6 Power profiler information 7 Frequency control information 21 Compile part 21a 1st insertion part 21b 2nd insertion part 22 Connection part 23 Analysis part 23a Calculation part 23b Creation part 50 Computer 51 Main memory 52 CPU
53 LAN interface 54 HDD
55 Super IO
56 DVI
57 ODD

Claims (7)

A compiling unit that inserts a code for collecting profiling data into a loop without a branch of the source program to generate a first executable code;
An execution unit that executes the first execution code generated by the compiling unit and outputs power profiler information based on the profiling data;
An analysis unit that analyzes the power profiler information output by the execution unit and creates frequency control information used for frequency control of a plurality of hardware modules included in the execution unit;
The compiling unit inserts a frequency control code for controlling the frequencies of the plurality of hardware modules into the loop of the source program based on the frequency control information created by the analyzing unit, and executes a second execution code. Produces
The information processing apparatus, wherein the execution unit executes the second execution code generated by the compiling unit. The analysis unit
A calculation unit that calculates a busy rate of the plurality of hardware modules in each loop based on the power profiler information;
The information processing apparatus according to claim 1, further comprising: a generation unit that determines a frequency control method for each loop based on a plurality of busy rates calculated by the calculation unit and generates the frequency control information. The power profiler information includes a cycle count, L1 cache miss count, L2 cache miss count, floating point arithmetic pipeline, L1 pipe valid and L2 writeback,
The plurality of hardware modules of the execution unit include a memory, an L2 cache, an L1 cache, and an arithmetic device.
The calculation unit calculates the busy rate of the memory, the L2 cache, the L1 cache, and the arithmetic unit based on the cycle count, the number of L1 cache misses, the number of L2 cache misses, the floating point arithmetic pipeline, the L1 pipe valid, and the L2 write back. The information processing apparatus according to claim 2. The frequency control information includes an execution time of a section corresponding to the loop,
The compiling unit generates a second execution code by inserting a frequency control code for controlling the frequency of the plurality of hardware modules into the loop when the average execution time of the section is equal to or greater than a predetermined threshold. The information processing apparatus according to claim 1, 2, or 3.   The compiling unit inserts a frequency control code for changing the frequency before each loop for the plurality of loops, inserts a frequency control code for returning the frequency after each loop, and a frequency control code for returning the frequency to the original. 5. The information processing apparatus according to claim 1, wherein when there is a frequency control code for changing the frequency immediately after the frequency control code, the frequency control code for restoring the frequency is deleted. Computer
Insert the code that collects the profiling data into the loop without the branch of the source program to generate the first execution code,
Frequency control created for frequency control of a plurality of hardware modules included in the processing device based on power profiler information created using profiling data collected by executing the first execution code by the processing device Compiled by executing a process of generating a second executable code by inserting a frequency control code for controlling a frequency of the plurality of hardware modules into the loop of the source program based on information Method. On the computer,
Insert the code that collects the profiling data into the loop without the branch of the source program to generate the first execution code,
Frequency control created for frequency control of a plurality of hardware modules included in the processing device based on power profiler information created using profiling data collected by executing the first execution code by the processing device Compile characterized in that, based on the information, a process for generating a second executable code by inserting a frequency control code for controlling the frequency of the plurality of hardware modules into the loop of the source program is executed. program.

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