JP2019035986A - Method of manufacturing electronic apparatus - Google Patents

Abstract

To provide a technique for manufacturing a flexible display device using a flexible substrate such as a resin substrate.SOLUTION: A flexible display device using a resin substrate is manufactured by the steps of: forming the resin substrate on a fixed substrate via an amorphous silicon film to be a release layer; forming at least a TFT element on the resin substrate; and peeling the resin substrate from the fixed substrate at the amorphous silicon film by irradiating the amorphous silicon film with laser light.SELECTED DRAWING: Figure 3

Description

The present invention relates to a method for manufacturing a device (hereinafter referred to as a light emitting device) having an element (hereinafter referred to as a light emitting element) in which a light emitting material is sandwiched between electrodes. In particular, a light-emitting device using a light-emitting material (hereinafter referred to as EL material) from which EL (Electro Luminescence) is obtained, that is, an electro-optical device typified by an EL display panel, and an electron mounted with such an electro-optical device as a component Regarding equipment.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

In recent years, a light emitting device (hereinafter referred to as an EL display device) using a light emitting element (hereinafter referred to as an EL element) using an EL phenomenon of a light emitting material has been developed. The EL display device has a structure having an EL element having an EL material sandwiched between an anode and a cathode. By applying a voltage between the anode and the cathode and passing a current through the EL material, carriers are recombined to emit light.
That is, since the EL display device has a light emission capability, the backlight used in the liquid crystal display device is unnecessary. Furthermore, it has the advantages of a wide viewing angle, light weight, and low power consumption.

Various applications using such an EL display device are expected. However, the use of the EL display device in a portable device is attracting attention because the thickness of the EL display device is thin, and thus the weight can be reduced. . Therefore, it has been attempted to form a light emitting element on a flexible plastic film.

However, since the heat resistance of the plastic film is low, the maximum temperature of the process has to be lowered, and as a result, TFTs having better electrical characteristics cannot be formed than when formed on a glass substrate. For this reason, a high-performance light emitting device using a plastic film has not been realized.

Japanese Patent Application Laid-Open No. 8-288522 describes a technique in which a thin film transistor is formed on a glass substrate, a resin substrate is bonded via a sealing layer, and then the glass substrate is peeled off.
When this technology is used, the active layer of the TFT is only protected by the base insulating film.
There has been a problem that FT tends to deteriorate.

In JP-A-11-243209, a separation layer is provided, and after the separation layer is peeled off by laser light, it is bonded to the primary transfer body via the adhesive layer, and further transferred to the secondary transfer via the adhesive layer. A technique for removing the primary transfer body after joining the bodies is described. Even when this technique is used, there is a problem that the active layer of the TFT is protected only by the base insulating film during the manufacturing process, so that the TFT is easily damaged and the TFT is easily deteriorated.

It is an object of the present invention to provide a technique for manufacturing a high-performance electro-optical device using a plastic support (including a flexible plastic film or a plastic substrate).

In the present invention, after an element forming substrate made of a plastic support is bonded to a first fixed substrate having heat resistance compared to plastic with a first adhesive layer, necessary elements are formed on the element forming substrate. The first fixed substrate is separated.

In addition, after the element formation substrate is bonded to the first fixed substrate with the first adhesive layer, necessary elements are formed on the element formation substrate, and the second fixed substrate is formed on the element with the second adhesive layer. You may isolate | separate a 1st fixed board | substrate after bonding. By providing the second fixed substrate and the second adhesive layer, necessary elements can be protected and intrusion of substances that promote deterioration due to oxidation of the EL layer such as moisture and oxygen from the outside can be prevented.

Note that the necessary elements refer to semiconductor elements (typically TFTs) or MIM elements and light-emitting elements used as pixel switching elements in an active matrix electro-optical device. A passive electro-optical device refers to a light emitting element.

Further, the method for bonding the first fixed substrate and the element formation substrate is not particularly limited.
As shown in the above, a method of bonding the element forming substrate after forming the first adhesive layer on the first fixed substrate, or a method of bonding the first fixed substrate after forming the first adhesive layer on the element forming substrate May be used.

Further, the element forming substrate made of a plastic support and the second fixed substrate have a thickness of 10 μm.
m or more resin substrates, for example, PES (polyethylene sulfide), PC (polycarbonate), PET (polyethylene terephthalate) or PEN (polyethylene naphthalate) can be used. In addition, after forming an adhesive layer on the first fixed substrate, an organic resin layer (polyimide layer, polyamide layer, polyimideamide layer BCB (benzocyclobutene) layer, etc.) formed thereon is used as an element formation substrate. You may call it.

Further, as the element formation substrate, a metal substrate such as a stainless steel substrate can be used. In that case, a necessary element may be formed by forming a base insulating film on a metal substrate. By using a thin metal substrate (thickness of 10 to 200 μm), it is possible to reduce the weight and thickness, and to obtain a flexible light-emitting device.

The first fixed substrate is separated after the necessary elements are formed on the element formation substrate. As a typical means, the entire first adhesive layer is vaporized by laser irradiation. Use the method. Further, instead of laser light irradiation, for example, JP-A-8-28852
The method of separating the first fixed substrate by etching described in No. 2 and a fluid (liquid or gas under pressure) to the first adhesive layer
For separating the first fixed substrate by spraying water (typically water jet method)
May be used, or these may be used in combination.

As the laser light, a pulse oscillation type or continuous light emission type excimer laser, YAG laser, or YVO ₄ laser can be used. As shown in FIG. 3D, laser light is passed through the first fixed substrate from the back side, and the first adhesive layer is irradiated to vaporize only the first adhesive layer to separate or peel off the first fixed substrate. Therefore, as the first fixed substrate, a substrate through which at least the laser beam to be irradiated passes, typically a light-transmitting substrate, such as a glass substrate or a quartz substrate, is used, which is thicker than the element formation substrate. Is preferred.

In the present invention, since the laser light passes through the first fixed substrate, it is necessary to appropriately select the type of the laser light and the first fixed substrate. For example, if a quartz substrate is used as the first fixed substrate, a YAG laser (fundamental wave (1064 nm), second harmonic (532 nm), third harmonic (355 nm), fourth harmonic (266 nm)
Alternatively, an excimer laser (wavelength 308 nm) may be used to form a linear beam and pass through a quartz substrate. The excimer laser does not pass through the glass substrate. Therefore, if a glass substrate is used as the first fixed substrate, the fundamental wave, the second harmonic, or the third harmonic of the YAG laser is used, and preferably the second harmonic (wavelength 532 nm) is used to generate the linear beam. What is necessary is just to form and let a glass substrate pass.

In addition, an organic material is used as the first adhesive layer, and preferably, the first adhesive layer is vaporized in whole or in part by the irradiated laser beam. Further, in order to efficiently absorb the laser beam only in the first adhesive layer, the first adhesive layer has a characteristic of absorbing the laser beam, for example, when using the second harmonic of the YAG laser, colored or black (For example, a resin material containing a black colorant)
It is desirable to use those. However, the first adhesive layer is a layer that is not vaporized by heat treatment in the element formation step. The first adhesive layer may be a single layer or a laminate,
As shown in FIG. 2, an amorphous silicon film or DL is formed between the first adhesive layer and the element formation substrate.
A C film may be provided.

By adopting such a configuration, the thickness of the element formation substrate is very thin, specifically 5
Even when a substrate having a thickness of 0 μm to 300 μm, preferably 150 μm to 200 μm is used, a highly reliable light-emitting device can be obtained. In addition, it has been difficult to form elements on such a thin substrate using a known manufacturing apparatus, but the present invention performs element formation by bonding to a first fixed substrate. A manufacturing apparatus using a thick substrate can be used without modifying the apparatus. In addition, the heat resistance of the element formation substrate can be improved by placing the element formation substrate between the insulating film formed on the element formation substrate and the first fixed substrate during the element formation step. .

According to the configuration of the invention disclosed in this specification, the first fixed substrate and the element formation substrate are bonded together by the first adhesive layer provided on the element formation substrate, and the insulating film is formed after the element formation substrate is bonded. A light emitting element is formed on the insulating film, a second fixing substrate is bonded to the light emitting element with a second adhesive layer, and then the first adhesive layer is removed by irradiation with laser light. A method for manufacturing a semiconductor device, wherein the first fixed substrate is separated.

According to another aspect of the invention, the first fixed substrate and the element forming substrate are bonded together by a first adhesive layer provided on the fixed substrate, and the insulating film is formed after the element forming substrate is bonded, A light emitting element is formed on the insulating film, a second fixing substrate is bonded on the light emitting element with a second adhesive layer, and then the first adhesive layer is removed by irradiation with a laser beam, thereby the first fixing. A method for manufacturing a semiconductor device is characterized in that a substrate is separated.

In each of the above configurations, the element formation substrate and the second fixed substrate are organic resin supports (including flexible plastic films or plastic substrates).
It is characterized by being. In addition, as the element formation substrate and the second fixed substrate,
A substrate having a thickness smaller than that of the first fixed substrate is used.

In each of the above structures, an amorphous silicon thin film may be formed between the element formation substrate and the first adhesive layer. A diamond-like carbon thin film may be formed between the element formation substrate and the first adhesive layer.

In each of the above configurations, the first adhesive layer may be colored or black using a pigment or dye to absorb laser light.

Further, in each of the above structures, the laser light is irradiated by forming a linear beam to be scanned, and the laser light is emitted by a pulse oscillation type or continuous light emission type excimer laser, YAG A laser or a YVO ₄ laser can be used.

Further, in each of the above-described configurations, the first adhesive layer provided on the front surface side of the first fixed substrate through the first fixed substrate passing through the first fixed substrate from the back surface side of the first fixed substrate. It is characterized by irradiating the laser beam. Therefore, it is preferable that the first fixed substrate transmits the laser beam to be used.

According to the present invention, a light emitting device in which an element forming layer (including an EL element) is sandwiched between an element forming substrate that is a resin substrate and a second fixed substrate that is a resin substrate is flexible (flexible) even if some stress occurs. Ability).

In addition, a highly reliable light-emitting device can be obtained even when a substrate with a thickness of the element formation substrate is extremely thin, specifically, a substrate with a thickness of 50 μm to 300 μm, preferably 150 μm to 200 μm.

The figure which shows a board | substrate bonding process. The figure which shows the state of the board | substrate bonded together. The figure which shows a manufacturing process. 10A and 10B illustrate a manufacturing process of a p-channel TFT. 10A and 10B illustrate a manufacturing process of an n-channel TFT. 8A and 8B illustrate a process for manufacturing a CMOS circuit. 8A and 8B illustrate a process for manufacturing a CMOS circuit. The figure which shows the structure of an NMOS circuit. FIG. 6 illustrates a structure of a shift register. FIG. 11 is a cross-sectional structure diagram of a driving circuit and a pixel portion of an EL display device. 2A and 2B are a top view and a cross-sectional view of an EL display device. FIG. 6 is a top view and a circuit diagram of a pixel of an EL display device. 1 is a circuit block diagram of a digital drive EL display device. FIG. 11 is a cross-sectional structure diagram of a driving circuit and a pixel portion of an EL display device. FIG. 11 is a cross-sectional structure diagram of a driving circuit and a pixel portion of an EL display device. FIG. 11 is a cross-sectional structure diagram of a driving circuit and a pixel portion of an EL display device. The figure which shows the structure of a gate side drive circuit. The figure explaining the timing chart of a decoder input signal. The figure which shows the structure of a source side drive circuit. The figure which shows the structure of a gate side drive circuit. The figure explaining the timing chart of a decoder input signal. The figure which shows the structure of a source side drive circuit. The figure which shows the state which gave the curvature. FIG. 14 illustrates an example of an electronic device. FIG. 14 illustrates an example of an electronic device.

  Embodiments of the present invention will be described below.

First, the first fixed substrate 101 and the element formation substrate 103 are bonded together, and there are two bonding methods as shown in FIG.

The first method is a method of bonding the first fixed substrate 101 and the element formation substrate 103 after providing the first adhesive layer 102 on the first fixed substrate 101. (FIG. 1 (A1)) The state after bonding is shown in FIG. 1 (B1).

The second method is a method in which after the first adhesive layer 102 is provided on the element formation substrate 103, the first fixed substrate 101 and the element formation substrate 103 are bonded together. (Fig. 1 (A2))
The state after bonding is shown in FIG.

Although not shown here, an element-forming substrate is formed by forming a first adhesive layer on a first fixed substrate and then forming an organic resin layer (polyimide layer, polyamide layer, polyimide amide layer, etc.) thereon. It may be equivalent to

Further, as shown in FIG. 2A, a between the first adhesive layer 202B and the element formation substrate 203
A structure may be provided in which a Si (amorphous silicon) layer 202A is provided. In a later step, the first fixed substrate 201 may be peeled off by irradiating the a-Si layer with laser light. A-Si containing a large amount of hydrogen so that the first fixed substrate 201 can be easily separated or separated.
It is preferable to use a layer. By irradiating laser light, hydrogen contained in the a-Si layer is vaporized to separate or peel off the first fixed substrate.

Further, as shown in FIG. 2B, between the first adhesive layer 205B and the element formation substrate 206,
A DLC film (specifically, a diamond-like carbon film) for protecting the element formation substrate 206 may be provided. The first fixed substrate 204 is the first fixed substrate 101 shown in FIG.
Is the same.

In this case, a DLC film having a thickness of 2 to 50 n as a protective film on one side or both sides of the element formation substrate.
You may use what was coated with m. Note that the DLC film may be formed by sputtering or ECR plasma CVD. The characteristics of the DLC film has a peak of asymmetric about 1550 cm ^-1, a Raman spectrum distribution with a shoulder around 1300 cm ^-1. Moreover, it has the characteristic of showing a hardness of 15 to 25 GPa when measured with a micro hardness meter. Such a carbon film has a role of preventing the entry of oxygen and water and protecting the surface of the resin substrate. In this manner, it is possible to prevent the entry of substances that promote deterioration due to oxidation of the EL layer, such as moisture and oxygen, from the outside. Therefore, a highly reliable EL light emitting device can be obtained.

Further, as shown in FIG. 2C, between the first adhesive layer 208C and the element formation substrate 209,
A first DLC film 208A for protecting the element formation substrate and a second DLC film 208B for facilitating separation or separation of the first fixed substrate 207 may be provided. Such first
What is necessary is just to use what was formed on the film-forming conditions which do not contain hydrogen as the DLC film 208A, and what was formed on the film-forming conditions containing hydrogen as the 2nd DLC film 208B. Second DLC
The first fixed substrate 207 may be separated or peeled off by irradiating the film 208B with laser light to vaporize hydrogen contained in the film.

The state after bonding obtained by the above methods is shown in FIG. Here, the same thing as FIG. 1 (B1) and FIG. 1 (B2) is illustrated. Note that the same reference numerals as those in FIGS. 1B1 and 1B2 are used.

Next, after forming a base insulating film over the element formation substrate 103, necessary elements are formed over the base insulating film. Here, an example in which the pixel portion 105 including the driver circuit 104 and the EL element is formed is shown. (Fig. 3 (B))

Next, the second fixed substrate 106 is bonded with the second adhesive layer 107. Here, in order to protect the EL element from the intrusion of moisture, oxygen, etc. from the outside, the second fixed substrate 1 is used here.
06 was used, but it is not necessary to use it if it is not particularly necessary. As the second fixed substrate 106,
A resin substrate may be used, and one having a DLC film as a protective film on one side or both sides may be used.

Next, the first fixed substrate 101 is separated by irradiating a laser beam from the back side to vaporize all or part of the first adhesive layer 102. Accordingly, the first adhesive layer 102 is made of a substance that causes a peeling phenomenon in the layer or at the interface by the laser light. Further, a laser beam that passes through the first fixed substrate 101 and is absorbed by the first adhesive layer is appropriately selected. For example, if a quartz substrate is used as the first fixed substrate, a YAG laser (fundamental wave (1064 nm
), Second harmonic (532 nm), third harmonic (355 nm), fourth harmonic (266 nm)
Alternatively, an excimer laser (wavelength 308 nm) may be used to form a linear beam and pass through a quartz substrate. The excimer laser does not pass through the glass substrate. Therefore, if a glass substrate is used as the first fixed substrate, the fundamental wave, the second harmonic, and the third of the YAG laser.
Harmonics can be used. Preferably, a linear beam is formed using the second harmonic (wavelength of 532 nm) and passed through the glass substrate.

Finally, a light emitting device sandwiched between an element formation substrate that is a resin substrate and a second fixed substrate that is a resin substrate is completed.

Further, as shown in FIG. 23, the light emitting device in which the element formation layer (including the EL element) is sandwiched between the element formation substrate 103 which is a resin substrate and the second fixed substrate 106 which is a resin substrate generates some stress. Even if it has the flexibility (flexibility) which is not damaged. FIG. 23A shows a state when no curvature is given, and FIG. 23B shows a state when a curvature is given. FIG.
In B), compressive stress acts on the element forming substrate, and tensile stress acts on the second fixed substrate.
In the element formation layer, almost no stress acts, and the expansion / contraction at the central portion can be ± 1 μm or less. It should be noted that there is no problem even if a curvature with a curvature radius of up to 10 cm is given.

The present invention having the above-described configuration will be described in more detail with the following examples.

In this embodiment, an example of a method for manufacturing a light-emitting device sandwiched between an element formation substrate which is a resin substrate and a second fixed substrate which is a resin substrate is shown with reference to FIGS. Here, all processes are performed at 350 ° C.
Hereinafter, it is preferably performed at 200 ° C. or lower. However, it goes without saying that the present invention is not limited to this embodiment.

First, a glass substrate is used as the first fixed substrate 101. Then, the first fixed substrate 101 and the element formation substrate 103 which is a resin substrate were bonded to each other with the first adhesive layer 102 using any of the methods described in the embodiment. (Fig. 3 (A))

Next, after forming a base insulating film over the element formation substrate 103, necessary elements are formed over the base insulating film. Here, an example in which the pixel portion 105 including the driver circuit 104 and the EL element is formed is shown. (Fig. 3 (B))

As the base insulating film, a silicon oxynitride film containing more nitrogen elements than oxygen elements in the film composition and silicon oxynitride containing oxygen elements more than nitrogen elements in the film composition by using a sputtering method that can be formed at a low temperature A film was laminated.

Next, a semiconductor layer is formed over the base insulating film. The material of the semiconductor layer is not limited, but it is preferably formed of silicon or silicon germanium (Si _x Ge _1-x (0 <X <1)) alloy. In this embodiment, an amorphous silicon film is formed by a sputtering method that can be formed at a low temperature, and a crystalline silicon film is formed by a laser crystallization method. When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser can be used.

Next, a gate insulating film covering the semiconductor layer is formed. In this embodiment, the silicon oxide film is formed by a sputtering method that can be formed at a low temperature.

Next, a conductive layer is formed over the gate insulating film. For the conductive layer, a conductive film is formed by a known means (thermal CVD.
Film forming method, plasma CVD method, low pressure thermal CVD method, vapor deposition method, sputtering method, or the like), and then patterning to a desired shape using a mask.

Next, an impurity region for forming an LDD region, a source region, or a drain region is formed by appropriately adding an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity to the semiconductor layer by an ion implantation method or an ion doping method. Form.

After that, an interlayer insulating film is formed using a silicon nitride film, a silicon nitride oxide film, or a silicon oxide film manufactured by a sputtering method. The added impurity element is activated. Here, laser light irradiation was performed. Instead of laser light irradiation, activation may be performed by heat treatment at 350 ° C. or lower.

Next, a contact hole reaching the source region or the drain region is formed using a known technique, and then a source electrode or a drain electrode is formed to obtain a TFT.

Next, hydrogenation is performed using a known technique, and the whole is hydrogenated to form an n-channel TFT.
Alternatively, a p-channel TFT is completed. In this embodiment, the hydrogenation treatment was performed using hydrogen plasma that can be performed at a relatively low temperature.

Next, an interlayer insulating film is formed using a silicon nitride film, a silicon nitride oxide film, or a silicon oxide film manufactured by a sputtering method. Next, a contact hole reaching the drain electrode of the pixel portion is formed using a known technique, and then the pixel electrode is formed. Next, banks are formed at both ends of the pixel electrode, and an EL layer and an anode (or cathode) of the EL element are formed on the pixel electrode.

  Next, all elements included in the pixel portion and the driver circuit are covered with an insulating film.

Next, an insulating film that covers all the elements formed on the element formation substrate and the second fixed substrate 106 are bonded together by the second adhesive layer 107. Note that although the second fixed substrate 106 is used here to protect the EL element from intrusion of moisture, oxygen, and the like from the outside here, it may not be used unless particularly necessary. As the second fixed substrate 106, a resin substrate may be used, and a substrate provided with a DLC film as a protective film on one side or both sides may be used.

Next, the first fixed substrate 101 is separated by irradiating a laser beam from the back side to vaporize all or part of the first adhesive layer 102. (FIG. 3D) In this embodiment, since a glass substrate is used as the first fixed substrate, the fundamental wave, the second harmonic wave, and the third harmonic wave of the YAG laser are used.
Here, a linear beam is formed using the second harmonic (wavelength 532 nm), and the first fixed substrate 10 is formed.
The first adhesive layer was irradiated through a glass substrate 1.

Finally, a light emitting device sandwiched between an element formation substrate that is a resin substrate and a second fixed substrate that is a resin substrate is completed. Each film (insulating film, semiconductor film, conductive film, etc.) using sputtering method
All processes can be performed at 350 ° C. or lower, preferably 200 ° C. or lower.

  This embodiment is an example of manufacturing a p-channel TFT and will be described with reference to FIGS.

First, the element formation substrate 4 bonded with the first fixed substrate 401 and the first adhesive layer 402 (separation layer).
A base insulating film 404 is formed on 03. As the base insulating film 404, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiOx Ny), or a stacked film of these is used.
It can be used in a film thickness range of ˜500 nm, and the formation means is a thermal CVD method, plasma C
A forming method such as a VD method, a vapor deposition method, a sputtering method, or a low pressure thermal CVD method can be used.

In this embodiment, a silicon oxynitride film containing a nitrogen element more than an oxygen element in a film composition and a silicon oxynitride film containing an oxygen element more than a nitrogen element in a film composition by using a sputtering method capable of film formation at a low temperature Were laminated.

The element forming substrate 4 bonded with the first fixed substrate 401 and the first adhesive layer 402 (separation layer).
Any of 03 manufactured by the method shown in the above embodiment can be applied.

Next, a semiconductor layer 405 is formed over the base insulating film. The semiconductor layer 405 is formed by forming a semiconductor film having an amorphous structure by a known means (thermal CVD method, plasma CVD method, reduced pressure thermal CVD method, vapor deposition method, sputtering method, or the like), and then known crystallization treatment. A crystalline semiconductor film obtained by performing (a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a catalyst such as nickel) is formed by patterning into a desired shape. The thickness of the semiconductor layer 405 is 20-10.
It is formed with a thickness of 0 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon or silicon germanium (Si _X Ge _1-X (0 <X <1)
) It is good to form with an alloy. In this embodiment, an amorphous silicon film is formed by a sputtering method that can be formed at a low temperature, and a crystalline silicon film is formed by a laser crystallization method. When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser can be used.

Further, after the semiconductor layer 405 is formed, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

Next, a gate insulating film 406 that covers the semiconductor layer 405 is formed. The gate insulating film 406 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, the silicon oxide film is formed by a sputtering method that can be formed at a low temperature. (Fig. 4 (A))

Next, a conductive layer 408 is formed over the gate insulating film 406. The conductive layer 408 is formed by forming a conductive film by a known means (thermal CVD method, plasma CVD method, reduced pressure thermal CVD method, vapor deposition method, sputtering method, or the like), and then patterning the conductive film into a desired shape using a mask 407. Form.
As a material of the conductive layer 408, an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. In this embodiment, a W film is formed by patterning using a sputtering method that can be formed at a low temperature and patterned. The end portion of the conductive layer 408 is formed in a tapered shape. Etching conditions may be determined appropriately. For example, in the case of W, CF ₄
Etching can be carried out satisfactorily by using a mixed gas of Al ₂ and Cl ₂ and biasing the substrate negatively.

Next, as shown in FIG. 4B, impurity regions (p + regions) 409 that form source and drain regions in a self-aligning manner are formed. This impurity region (p + region)
409 is formed by ion doping and is doped with an element belonging to Group 13 of the periodic table represented by boron. The impurity concentration of the impurity region (p + region) 409 is 1 × 10 ²⁰ to 2 × 10 ^21.
/ Cm ³ range.

Next, as illustrated in FIG. 4C, the conductive layer 410 is formed by etching so that the end portion of the conductive layer 408 recedes. In the structure of this embodiment, this is used as a gate electrode.
The formation of the gate electrode uses two etching steps, and the etching conditions are appropriately determined. For example, in the case of W, a mixed gas of CF ₄ and Cl ₂ is used, and the end can be satisfactorily processed into a tapered shape by negatively biasing the substrate. CF ₄
By mixing oxygen with Cl ₂ , anisotropic etching of W can be performed with good selectivity with respect to the base.

Thereafter, as shown in FIG. 4D, a p-type impurity (acceptor) is doped using the conductive layer 410 as a mask to form an impurity region (p− region) 411 in a self-aligning manner. The impurity concentration of the impurity region (p− region) 411 is set to be in the range of 1 × 10 ¹⁷ to 2 × 10 ¹⁹ / cm ³ .

After that, an interlayer insulating film 413 is formed using a silicon nitride film or a silicon nitride oxide film manufactured by a sputtering method or a plasma CVD method. The added impurity element is subjected to heat treatment at 350 to 500 ° C. or laser light irradiation for activation. Further, after forming a contact hole reaching the impurity region (p + region) using a known technique, a source electrode or a drain electrode 414 is formed to obtain a TFT.

Finally, hydrogenation is performed using a known technique, and the whole is hydrogenated to complete a p-channel TFT. (Fig. 4 (E))

The semiconductor layer includes a channel formation region 412 and an LDD (impurity region (p− region)) formed by LDD (
A lightly doped drain) region 411 and a source or drain region 409 formed of an impurity region (p + region) are formed. Here, the p-channel TFT is shown with the LDD structure, but it is of course possible to manufacture it with a single drain or a structure in which the LDD overlaps with the gate electrode. A basic logic circuit is configured by using the p-channel TFT shown in this embodiment, or a more complicated logic circuit (signal division circuit, D / A converter, operational amplifier,
(gamma correction circuit etc.) can also be constructed, and further, a memory and a microprocessor can be formed. For example, the driving circuit of the EL display device can be entirely composed of p-channel TFTs.

  This embodiment can be combined with the first embodiment.

This embodiment is an example of manufacturing an n-channel TFT and will be described with reference to FIGS. In addition,
Since FIGS. 4A and 5A are the same, the same reference numerals are used and description of the manufacturing steps is omitted here.

After obtaining the state of FIG. 5A according to Embodiment 2, a resist mask 415 is formed by a light exposure process, and the semiconductor film 405 is doped with an n-type impurity (donor) by ion implantation or ion doping. (FIG. 5B) Impurity region (n-region) 4 to be produced
16, the doping concentration is in the range of 1 × 10 ¹⁷ to 2 × 10 ¹⁹ / cm ³ .

Next, the gate electrode 417 is formed using a conductive material containing one or more elements selected from tantalum, tungsten, titanium, aluminum, and molybdenum over the insulating film 406.
Form. (FIG. 5C) A part of the gate electrode 417 is formed so as to partially overlap with the impurity region (n− region) 416 with the gate insulating film interposed therebetween.

After that, as shown in FIG. 5D, an n-type impurity (donor) is doped using the gate electrode 417 as a mask to form an impurity region (n + region) 418 in a self-aligning manner. The impurity concentration of the impurity region (n + region) 418 is set to be in the range of 1 × 10 ¹⁷ to 2 × 10 ¹⁹ / cm ³ .

After that, an interlayer insulating film 419 is formed using a silicon nitride film or a silicon nitride oxide film manufactured by a plasma CVD method. In addition, the added impurity element is 350 ~
Heat treatment at 500 ° C. or laser light irradiation is performed. Further, a contact hole reaching the impurity region (n + region) is formed using a known technique, and then a source or drain electrode 420 is formed to obtain a TFT.

Finally, hydrogenation is performed using a known technique, and the whole is hydrogenated to complete an n-channel TFT. (Fig. 5 (E))

In the semiconductor layer, a channel formation region 419 and an LDD (n-region) formed by an impurity region (n−region)
A lightly doped drain) region 416 and a source or drain region 418 formed of an impurity region (n + region) are formed. Further, the LDD region 416 is formed so as to overlap with the gate electrode 417, and the concentration of the electric field at the drain end is relaxed to prevent deterioration due to hot carriers. Of course, an n-channel TFT with a single drain or LDD structure can also be manufactured. A basic logic circuit is configured by using the n-channel TFT shown in this embodiment, or a more complicated logic circuit (signal dividing circuit, D / A converter, operational amplifier, γ
Correction circuit, etc.) can also be configured, and a memory and a microprocessor can also be formed.
For example, the driving circuit of the EL display device can all be composed of n-channel TFTs.

  This embodiment can be combined with the first embodiment.

This embodiment is a CM in which an n-channel TFT and a p-channel TFT are combined in a complementary manner.
This is an example of manufacturing an OS circuit, which will be described with reference to FIGS.

In accordance with the second embodiment, a base insulating film is formed on the element formation substrate bonded with the first fixed substrate and the first adhesive layer (separation layer), and then the semiconductor layers 501 and 502 are formed. (Fig. 6 (A))

Next, the gate insulating film 503, the first conductive film 504, and the second conductive film 505 are formed by sputtering.
Form. (FIG. 6B) In this embodiment, the first conductive film 504 is formed of tantalum nitride or titanium to a thickness of 50 to 100 nm, and the second conductive film 505 is formed of tungsten of 100 to 30.
It is formed to a thickness of 0 nm.

Next, as shown in FIG. 6C, a resist mask 506 is formed, and a first etching process for forming a gate electrode is performed. The etching method is not limited, but preferably I
A CP (Inductively Coupled Plasma) etching method is used. CF ₄ and Cl ₂ are mixed in an etching gas, and 500 W of RF (13.56 MHz) power is applied to a coil-type electrode at a pressure of 0.5 to ₂ Pa, preferably 1 Pa, to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, etching can be performed at a similar rate even in the case of a tungsten film, a tantalum nitride film, and a titanium film.

Under the above etching conditions, the end portion can be tapered by the shape of the resist mask and the effect of the bias voltage applied to the substrate side. The angle of the taper part is 15 to 45
To be °. In order to etch without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layer 50 composed of the first conductive film and the second conductive film is formed by the first etching process.
7, 508 (first conductive layers 507a and 508a and second conductive layers 507b and 508b) are formed. Reference numeral 509 denotes a gate insulating film, and a region not covered with the first shape conductive layer is 20 to 50.
It is etched and thinned by about nm.

Then, a first doping process is performed to dope n-type impurities (donors). (Fig. 6
(D)) The method is performed by ion doping or ion implantation. The ion doping method is performed at a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ / cm ² . As the impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In this case, the first shape conductive layers 507 and 508 serve as a mask for the element to be doped, and the acceleration voltage is appropriately adjusted (for example, 20 to 60 keV), and the impurity region is formed by the impurity element that has passed through the gate insulating film 509. (N + regions) 520 and 521 are formed. For example, the impurity region (n
The phosphorus (P) concentration in the (+ region) is in the range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

Further, a second etching process is performed as shown in FIG. The etching uses an ICP etching method, and CF ₄ , Cl _2, and O ₂ are mixed in an etching gas, and plasma is generated by supplying 500 W of RF power (13.56 MHz) to a coil-type electrode at a pressure of 1 Pa. . 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the tungsten film is anisotropically etched to leave the tantalum nitride film or titanium film as the first conductive layer. Thus, the second shape conductive layers 512 and 513 (first conductive films 512a and 51
3a and second conductive films 512b and 513b). Reference numeral 516 denotes a gate insulating film, and a region not covered with the second shape conductive layers 512 and 513 is further etched by about 20 to 50 nm to be thinned.

Then, a second doping process is performed as shown in FIG. The n-type impurity (donor) is doped under a condition of a high acceleration voltage with a lower dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 keV, and the dose is 1 × 10 ¹³ / cm ² .
In (D), an impurity region is formed inside the first impurity region formed in the island-shaped semiconductor film. Doping is performed using the second conductive films 512b and 513b as masks against the impurity elements.
Doping is performed so that an impurity element is added to a lower region of the first conductive films 512a and 512a. Thus, the impurity region (n− region) 5 overlapping with the first conductive films 512a and 513a.
14, 515 are formed. In this impurity region, since the second conductive layers 512a and 513a remain with substantially the same film thickness, the concentration difference in the direction along the second conductive layer is small.
It forms with the density | concentration of 1 * 10 < ¹⁷ > -1 * 10 < ¹⁹ > / cm < ³ >.

Then, as shown in FIG. 7B, a third etching process is performed to form the gate insulating film 346.
Etching process is performed. As a result, the second conductive film is also etched, and the end portions recede and become small, and third shape conductive layers 517 and 518 are formed. In the figure, reference numeral 519 denotes a remaining gate insulating film.

Then, as shown in FIG. 7C, a resist mask 520 is formed, and a p-type impurity (acceptor) is formed in the island-shaped semiconductor layer 501 forming the p-channel TFT.
Doping. Typically, boron (B) is used. Impurity region (p + region)
The impurity concentrations of 521 and 522 are set to 2 × 10 ²⁰ to 2 × 10 ²¹ / cm ^3, and boron is added 1.5 to 3 times the concentration of phosphorus contained to invert the conductivity type.

Through the above steps, impurity regions are formed in each island-like semiconductor layer. The third shape conductive layers 517 and 518 serve as gate electrodes. After that, as illustrated in FIG. 7D, a protective insulating film 523 including a silicon nitride film or a silicon oxynitride film is formed by a plasma CVD method. Then, a process of activating the impurity element added to each island-like semiconductor layer is performed for the purpose of controlling the conductivity type.

Further, a silicon nitride film 524 is formed and hydrogenation is performed. As a result, hydrogenation can be achieved by diffusing hydrogen in the silicon nitride film 524 into the island-like semiconductor layer.

The interlayer insulating film 525 is formed using an organic insulating material such as polyimide or acrylic. Of course,
Although a silicon oxide film formed using TEOS (Tetraethyl Ortho silicate) by plasma CVD may be applied, it is preferable to use the organic material from the viewpoint of improving flatness.

Next, contact holes are formed, aluminum (Al), titanium (Ti)
Source wiring or drain wiring 526 to 528 is formed using tantalum (Ta) or the like.

Through the above process, C is a complementary combination of an n-channel TFT and a p-channel TFT.
A MOS circuit can be obtained.

The p-channel TFT includes a channel formation region 530 and impurity regions 521 and 522 functioning as a source region or a drain region.

The n-channel TFT includes a channel formation region 531, an impurity region 515 a (Gate Overlapped Drain: GOLD region) overlapping the gate electrode 518 made of a third shape conductive layer, and an impurity region 515 b (LDD region) formed outside the gate electrode. )
And an impurity region 516 functioning as a source region or a drain region.

Such a CMOS circuit makes it possible to form a drive circuit for an active matrix EL display device. In addition, such an n-channel TFT or a p-channel TFT can be applied to a transistor forming the pixel portion.

By combining such CMOS circuits, basic logic circuits can be configured, and more complex logic circuits (signal division circuits, D / A converters, operational amplifiers, γ correction circuits, etc.) can be configured, and memory It is also possible to form a microprocessor.

  This embodiment can be combined with the first embodiment.

The n-channel TFT shown in Example 3 has a periodic table of 15 in a semiconductor to be a channel formation region.
By adding an element belonging to the group (preferably phosphorus) or an element belonging to the group 13 of the periodic table (preferably boron), the enhancement type and the depletion type can be separately formed.

When an NMOS circuit is formed by combining n-channel TFTs, an enhancement type TFT is formed (hereinafter referred to as an EEMOS circuit), or an enhancement type and a depression type are combined (hereinafter referred to as an EDMOS circuit). Called).

Here, FIG. 8A shows an example of an EEMOS circuit, and FIG. 8B shows an example of an EDMOS circuit. In FIG. 8A, reference numerals 31 and 32 denote enhancement-type n-channel TFTs (hereinafter referred to as E-type NTFTs). In FIG. 8B, 33 is an E-type NTFT, 3
Reference numeral 4 denotes a depletion type n-channel TFT (hereinafter referred to as a D-type NTFT).

8A and 8B, VDH is a power supply line to which a positive voltage is applied (positive power supply line).
VDL is a power supply line (negative power supply line) to which a negative voltage is applied. The negative power source line may be a ground potential power source line (ground power source line).

Further, FIG. 9 shows an example in which a shift register is manufactured using the EEMOS circuit shown in FIG. 8A or the EDMOS circuit shown in FIG. In FIG. 9, reference numerals 40 and 41 denote flip-flop circuits. Reference numerals 42 and 43 denote E-type NTFTs. A clock signal (CL) is input to the gate of the E-type NTFT 42, and a clock signal (CL bar) having an inverted polarity is input to the gate of the E-type NTFT 43. Reference numeral 44 denotes an inverter circuit. As shown in FIG. 9B, the EEMOS circuit shown in FIG.
The EDMOS circuit shown in B) is used. Therefore, it is possible to configure all the drive circuits of the EL display device with n-channel TFTs.

  In addition, this embodiment can be combined with Embodiment 1 or Embodiment 3.

Here, an example in which an EL (electroluminescence) display device is manufactured using the TFTs obtained in Examples 2 to 5 will be described with reference to FIGS.

FIG. 10 shows an example of a light-emitting device having a pixel portion and a driving circuit for driving the pixel portion on the same insulator (but a state before sealing). Note that a CMOS circuit serving as a basic unit is shown in the driver circuit, and one pixel is shown in the pixel portion. This CMOS circuit can be obtained according to the fourth embodiment.

In FIG. 10, 601 is a first fixed substrate, 602 is a first adhesive layer, 603 is an element formation substrate, on which a drive circuit 604 composed of an n-channel TFT and a p-channel TFT,
A switching TFT made of a p-channel TFT and a current control TFT made of an n-channel TFT are formed. In this embodiment, all TFTs are top gate type Ts.
It is formed of FT.

Description of the n-channel TFT and the p-channel TFT will be omitted because it can be referred to the fourth embodiment. The switching TFT has a structure (double gate structure) having two channel formation regions between the source region and the drain region. See the description of the structure of the p-channel TFT in Example 2. Since it can be easily understood, the description is omitted. Note that this embodiment is not limited to the double gate structure, and may be a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed.

In addition, a contact hole is provided in the first interlayer insulating film 607 before the second interlayer insulating film 608 is provided on the drain region 606 of the current control TFT. This is to simplify the etching process when a contact hole is formed in the second interlayer insulating film 608.
A contact hole is formed in the second interlayer insulating film 608 so as to reach the drain region 606, and a pixel electrode 609 connected to the drain region 606 is provided. Pixel electrode 60
An electrode 9 functions as a cathode of the EL element, and is formed using a conductive film containing an element belonging to Group 1 or Group 2 of the periodic table. In this embodiment, a conductive film made of a compound of lithium and aluminum is used.

Next, reference numeral 613 denotes an insulating film provided so as to cover the end portion of the pixel electrode 609 and is referred to as a bank in this specification. The bank 613 may be formed using an insulating film containing silicon or a resin film. When a resin film is used, the specific resistance of the resin film is 1 × 10 ⁶ to 1 × 10 ¹² Ωm (preferably 1 ×
When carbon particles or metal particles are added so as to be 10 ⁸ to 1 × 10 ¹⁰ Ωm), dielectric breakdown during film formation can be suppressed.

The EL element 610 includes a pixel electrode (cathode) 609, an EL layer 611, and an anode 612. As the anode 612, a conductive film having a high work function, typically an oxide conductive film, is used.
As the oxide conductive film, indium oxide, tin oxide, zinc oxide, or a compound thereof may be used.

Note that in this specification, a stacked body in which a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, or an electron blocking layer is combined with the light-emitting layer is defined as an EL layer.

Although not shown here, it is effective to provide a passivation film so as to completely cover the EL element 610 after the anode 612 is formed. As the passivation film, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a laminated layer.

Next, after performing the sealing (or sealing) process for protecting the EL element, the first fixed substrate 601 was separated by laser irradiation as shown in the embodiment and Example 1. The subsequent EL display device will be described with reference to FIGS.

FIG. 11A is a top view showing a state in which the EL element is sealed, and FIG.
It is sectional drawing which cut | disconnected 1 (A) by AA '. 701 indicated by a dotted line is a pixel portion, 702 is a source side driver circuit, and 703 is a gate side driver circuit. Reference numeral 704 denotes a cover material, and 705.
Is a first sealing material, and 706 is a second sealing material.

Reference numeral 708 denotes a wiring for transmitting signals input to the source side driver circuit 702 and the gate side driver circuit 703, and receives video signals and clock signals from an FPC (flexible printed circuit) 708 serving as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC.

Next, a cross-sectional structure is described with reference to FIG. Insulator 700 (element forming substrate 6
A pixel portion and a source side driver circuit 709 are formed above (corresponding to 03), and the pixel portion is formed by a plurality of pixels including a current control TFT 710 and a pixel electrode 711 electrically connected to its drain. . The source side driver circuit 709 is formed using a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined. Note that a polarizing plate (typically, a circular polarizing plate) may be attached to the insulator 700.

A bank 712 is formed at both ends of the pixel electrode 711, and an EL layer 713 and an anode 714 of the EL element are formed on the pixel electrode 711. The anode 714 also functions as a wiring common to all pixels, and is electrically connected to the FPC 716 through the connection wiring 715. Further, all elements included in the pixel portion and the source side driver circuit 709 are covered with a passivation film (not shown).

Further, a cover material 704 is bonded to the first seal material 705. Note that a spacer may be provided in order to ensure a space between the cover material 704 and the EL element.
A gap 717 is formed inside the first sealing material 705. Note that the first sealing material 705 is desirably a material that does not transmit moisture or oxygen. Furthermore, it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside the gap 717.

Note that a carbon film (specifically, a diamond-like carbon film) is preferably provided as a protective film on the front and back surfaces of the cover material 704 in a thickness of 2 to 30 nm. Such a carbon film (not shown here) has a role of preventing oxygen and water from entering and mechanically protecting the surface of the cover material 704.

Further, after the cover material 704 is bonded, the second seal material 706 is provided so as to cover the exposed surface of the first seal material 705. The second sealant 706 can be made of the same material as the first sealant 705.

By encapsulating the EL element with the structure as described above, the EL element can be completely shut off from the outside, and a substance that promotes deterioration due to oxidation of the EL layer such as moisture and oxygen can be prevented from entering from the outside. Can do. Therefore, an EL display device with high reliability can be obtained.

  This embodiment can be combined with the first embodiment.

In this example, in the EL display device obtained in Example 6, FIG. 12A shows a more detailed top surface structure of the pixel portion, and FIG. 12B shows a circuit diagram. In FIG. 12A and FIG. 12B, common reference numerals are used so that they may be referred to each other.

The source of the switching TFT 802 is connected to the source wiring 815, and the drain is connected to the drain wiring 805. The drain wiring 805 is electrically connected to the gate electrode 807 of the current control TFT 806. The source of the current control TFT 806 is electrically connected to the current supply line 816, and the drain is electrically connected to the drain wiring 817. Further, the drain wiring 817 is electrically connected to a pixel electrode (cathode) 818 indicated by a dotted line.

At this time, a storage capacitor is formed in the region indicated by 819. The storage capacitor 819 is formed between the semiconductor film 820 electrically connected to the current supply line 816, the insulating film (not shown) in the same layer as the gate insulating film, and the gate electrode 807. A capacitor formed by the gate electrode 807, the same layer (not shown) as the first interlayer insulating film, and the current supply line 816 can also be used as the storage capacitor.

  Further, this embodiment can be combined with Embodiment 1 or Embodiment 6.

In this embodiment, FIG. 13 shows a circuit configuration example of the EL display device shown in Embodiment 6 or Embodiment 7. In this embodiment, a circuit configuration for performing digital driving is shown. In this embodiment, a source side driver circuit 901, a pixel portion 906, and a gate side driver circuit 907 are provided. Note that in this specification, the drive circuit is a generic name including a source side processing circuit and a gate side drive circuit.

The source side driver circuit 901 includes a shift register 902, a latch (A) 903, and a latch (B).
904 and a buffer 905 are provided. In the case of analog driving, latches (A) and (B
) May be provided instead of a sampling circuit (transfer gate). The gate side driver circuit 907 includes a shift register 908 and a buffer 909.

In this embodiment, the pixel portion 906 includes a plurality of pixels, and EL elements are provided in the plurality of pixels. At this time, it is preferable that the cathode of the EL element is electrically connected to the drain of the current control TFT.

The source side driver circuit 901 and the gate side driver circuit 907 are formed of n-channel TFTs or p-channel TFTs obtained in Embodiments 2 to 4.

Although not illustrated, a gate side driver circuit may be further provided on the opposite side of the gate side driver circuit 907 with the pixel portion 906 interposed therebetween. In this case, both have the same structure and share the gate wiring, and even if one of them breaks, the gate signal is sent from the remaining one so that the pixel portion operates normally.

In addition, this embodiment can be combined with Embodiment 1, Embodiment 6, or Embodiment 7.

In this embodiment, FIG. 14 shows an example of an EL display device in which all TFTs used in the pixel portion and the drive circuit are composed of inverted staggered TFTs.

In FIG. 14, reference numeral 1001 denotes a first fixed substrate, 1002 denotes a first adhesive layer, and 1003 denotes an element formation substrate. First, according to the embodiment, the first fixed substrate 1001 and the first adhesive layer 1002 (
An element formation substrate 1003 attached with a separation layer is prepared. Note that a base insulating film may be formed over the element formation substrate if necessary.

Next, a gate wiring (including a gate electrode) 1004 having a single layer structure or a stacked structure is formed over the element formation substrate 1003. After forming a conductive film having a film thickness range of 10 to 1000 nm, preferably 30 to 300 nm using a thermal CVD method, a plasma CVD method, a low pressure thermal CVD method, a vapor deposition method, a sputtering method, or the like as a means for forming the gate wiring 12. Then, it is formed by a known patterning technique. The material of the gate wiring 12 is a material mainly composed of a conductive material or a semiconductor material, such as Ta (tantalum), Mo (molybdenum), Ti (titanium), W (tungsten), chromium (Cr), or the like. Main components are refractory metal materials, silicides, which are compounds of these metal materials and silicon, polysilicon having N-type or P-type conductivity, low-resistance metal materials Cu (copper), Al (aluminum), etc. Any structure having at least one material layer can be used without particular limitation.

  Next, a gate insulating film 1005 is formed.

Next, an amorphous semiconductor film is formed. Next, laser crystallization treatment of the amorphous semiconductor film is performed to form a crystalline semiconductor film, and then the obtained crystalline semiconductor film is patterned into a desired shape to form a semiconductor layer. Next, an insulating layer 1006 is formed over the semiconductor layer. This insulating layer 1006 protects the channel formation region during the impurity element addition step.

Next, an impurity region for forming an LDD region, a source region, or a drain region is formed by appropriately adding an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity to the semiconductor layer by an ion implantation method or an ion doping method. Form.

After that, an interlayer insulating film is formed using a silicon nitride film, a silicon nitride oxide film, or a silicon oxide film manufactured by a sputtering method. The added impurity element is activated. Here, laser light irradiation was performed. Instead of laser light irradiation, activation may be performed by heat treatment at 350 ° C. or lower.

Next, a contact hole reaching the source region or the drain region is formed using a known technique, and then a source electrode or a drain electrode is formed to obtain an inverted staggered TFT.

Next, hydrogenation is performed using a known technique, and the whole is hydrogenated to form an n-channel TFT.
And a p-channel TFT is completed. In this embodiment, the hydrogenation treatment was performed using hydrogen plasma that can be performed at a relatively low temperature.

Next, a first interlayer insulating film 1007 is formed using a silicon nitride film, a silicon nitride oxide film, or a silicon oxide film manufactured by a sputtering method. Next, after forming a contact hole reaching the drain region 1000 of the pixel portion using a known technique, the second interlayer insulating film 1
008 is formed. Next, a contact hole reaching the drain region 1000 of the pixel portion is formed using a known technique, and then a pixel electrode 1009 is formed. Next, banks 1010 are formed at both ends of the pixel electrode, and an EL layer 1011 and an anode 1013 of the EL element 1012 are formed over the pixel electrode.

In FIG. 14, an N-channel TFT 1014 and a P-channel TF are formed on the element formation substrate.
Driving circuit made of T1015, switching TFT 1016 made of P-channel TFT
In addition, a current control TFT 1017 made of an N-channel TFT is formed. In this embodiment, all TFTs are formed of inverted staggered TFTs.

The switching TFT 1016 has a structure (double gate structure) having two channel formation regions between the source region and the drain region. Refer to the description of the structure of the P-channel TFT in Example 2. Since it can be easily understood, the description is omitted. Note that this embodiment is not limited to the double gate structure, and may be a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed.

Further, all elements included in the pixel portion and the drive circuit are passivation films (not shown).
It is preferable to cover with.

In the subsequent steps, the second fixed substrate is bonded to the second adhesive layer in accordance with the steps of Example 6, and then the first fixed substrate 1001 is separated by irradiating the first adhesive layer 1002 with a laser. Is completed.

Note that this embodiment can be freely combined with Embodiment 1, Embodiment 7, or Embodiment 8.

In this embodiment, FIG. 15 shows an example of an EL display device in which all TFTs used in the pixel portion and the driver circuit are N-channel TFTs.

In FIG. 15, reference numeral 1101 denotes a first fixed substrate, 1102 denotes a first adhesive layer, and 1103 denotes an element formation substrate. First, according to the embodiment, the first fixed substrate 1101 and the first adhesive layer 1102 (
A base insulating film is formed over the element formation substrate 1103 attached with the separation layer.

On the base insulating film, an N-channel TFT 1104, a drive circuit composed of an N-channel TFT 1105, a switching TFT 1106 composed of an N-channel TFT, and a current control TFT 1107 composed of an N-channel TFT are formed. Note that description of the N-channel TFT is omitted because it is sufficient to refer to the third embodiment. The description of the EL element 1108 is omitted because it is sufficient to refer to the sixth embodiment.

Further, all elements included in the pixel portion and the drive circuit are passivation films (not shown).
It is preferable to cover with.

In addition, after obtaining the state of FIG. 15, the second fixed substrate is bonded with the second adhesive layer according to the process of Example 6, and then the first fixed substrate 1101 is attached to the first adhesive layer 1102 by laser irradiation. The light emitting device may be completed by separation.

By forming the gate side driver circuit and the source side driver circuit with only the N-channel TFT, the pixel portion and the driver circuit can all be formed with the N-channel TFT. Accordingly, the yield and throughput of the TFT process can be significantly improved in manufacturing an active matrix electro-optical device, and the manufacturing cost can be reduced.

Note that this embodiment can also be implemented when one of the source side driver circuit and the gate side driver circuit is an external IC chip.

In this embodiment, the drive circuit is configured using only the E-type NTFT, but it may be formed by combining the E-type NTFT and the D-type NTFT.

Note that this embodiment can be freely combined with Embodiment 1, Embodiment 3, Embodiment 5, Embodiment 7, or Embodiment 8. In this embodiment, a top gate type TFT is used, but there is no particular limitation, and an inverted stagger type TFT as shown in Embodiment 9 can also be used.

In this embodiment, FIG. 16 shows an example of an EL display device in which all TFTs used for the pixel portion and the driver circuit are P-channel TFTs.

In FIG. 16, reference numeral 1201 denotes a first fixed substrate, 1202 denotes a first adhesive layer, and 1203 denotes an element formation substrate. First, the first fixed substrate 1201 and the first adhesive layer 1202 (separation layer) are attached according to the embodiment. A base insulating film is formed over the attached element formation substrate 1203.

On top of that, a driving circuit composed of an N-channel TFT 1204, an N-channel TFT 1205, a switching TFT 1206 composed of an N-channel TFT, and an N-channel TFT
A current control TFT 1207 is formed. Note that description of the N-channel TFT is omitted because it is only necessary to refer to the second embodiment.

In this embodiment, interlayer insulating films 1208 and 1209 are formed on the current control TFT 1207, and a pixel electrode 1210 electrically connected to the drain of the current control TFT 1207 is formed thereon.
Is formed. In this embodiment, the pixel electrode 1210 made of a transparent conductive film having a large work function functions as the anode of the EL element.

  Similarly to the sixth embodiment, a bank 1211 is formed on the pixel electrode 1210.

Next, an EL layer 1212 is formed on the pixel electrode 1210. The EL layer 1212
A cathode 1213 made of a conductive film containing an element belonging to Group 1 or Group 2 of the periodic table is provided on. Thus, an EL element 1214 including the pixel electrode (anode) 1210, the EL layer 1212, and the cathode 1213 is formed.

Further, all elements included in the pixel portion and the drive circuit are passivation films (not shown).
It is preferable to cover with.

However, this embodiment differs from the sixth, ninth, and tenth embodiments in the direction of light emission from the EL element, and the element formation substrate must be transparent.

In the subsequent steps, the second fixed substrate is bonded to the second adhesive layer in accordance with the steps of Example 6, and then the first fixed substrate 1201 is separated by irradiating the first adhesive layer 1202 with a laser. Is completed.

Note that this embodiment can be freely combined with Embodiment 1, Embodiment 2, Embodiment 6, Embodiment 7, or Embodiment 8. In this embodiment, a top gate type TFT is used, but there is no particular limitation, and an inverted stagger type TFT as shown in Embodiment 9 can also be used.

In this embodiment, a P-channel type TF as shown in FIG. 4 is used instead of a general shift register.
An example in which a drive circuit is formed using a decoder using T will be described. FIG. 17 shows an example of a gate side driving circuit.

In FIG. 17, 1300 is a decoder of the gate side driving circuit, and 1301 is a buffer section of the gate side driving circuit.

First, the gate side decoder 1300 will be described. First, reference numeral 1302 denotes an input signal line (hereinafter referred to as a selection line) of the decoder 1300. Here, A1, A1 bar (a signal in which the polarity of A1 is inverted), A2, A2 bar (a signal in which the polarity of A2 is inverted),. An and An bars (signals in which the polarity of An is inverted) are shown.

The selection line 1302 transmits a signal shown in the timing chart of FIG. As shown in FIG. 18, when the frequency of A1 is 1, the frequency of A2 is 2 ⁻¹ times, the frequency of A3 is 2 ⁻² times, An
The frequency of is 2 ^{− (n−1)} times.

1303a is a first-stage NAND circuit (also referred to as a NAND cell), and 1303b is a second NAND circuit.
The NAND circuit 1303c is an nth NAND.

The NAND circuits 1303a to 1303c include P-channel TFTs 1304 to 1309.
Are combined to form a NAND circuit.

In the NAND circuit 1303a, P-channel TFTs 1304 to 1306 having gates connected to any one of A1, A2,... An (referred to as positive selection lines)
They are connected in parallel to each other, connected to a positive power supply line (V _DH ) 1310 as a common source, and connected to an output line 1311 as a common drain.

Next, the buffer 1301 is formed by a plurality of buffers 1313a to 1313c corresponding to each of the NAND circuits 1303a to 1303c. However, buffers 1313a to 131
All 3c may have the same structure. The buffers 1313a to 1313c are one conductivity type TFTs.
Are formed using P-channel TFTs 1314-1316.

The P-channel TFT 1316 has a reset signal line (Reset) as a gate, a positive power supply line 1319 as a source, and a gate wiring 1318 as a drain. The ground power line 13
Reference numeral 17 may be a negative power supply line (however, a power supply line for applying a voltage that turns on a P-channel TFT used as a pixel switching element).

Next, FIG. 19 shows the configuration of the source side driver circuit. The source side driver circuit shown in FIG. 19 includes a decoder 1401, a latch 1402, and a buffer 1403. The decoder 1401
Since the configuration of the buffer 1403 is the same as that of the gate side driving circuit, description thereof is omitted here.

In the case of the source side driver circuit shown in FIG. 19, the latch 1402 includes a first-stage latch 1404 and a second-stage latch 1405. The first-stage latch 1404 and the second-stage latch 1405 each include a plurality of unit units 1407 formed by m P-channel TFTs 1406a to 1406c.

The sources of the P-channel TFTs 1406a to 1406c are video signal lines (V1), respectively.
, V2... Vk) 1409. When a negative voltage is applied to the output line 1408, P
The channel TFTs 1406a to 1406c are turned on, and video signals corresponding to the channel TFTs 1406a to 1406c are captured. In addition, the video signal thus captured is a P-channel TFT 1406.
It hold | maintains at the capacitor | condenser 1410a-1410c connected to each of a-1406c.

The second-stage latch 1405 also includes a plurality of unit units 1407b, and the unit unit 1407b is formed of m P-channel TFTs 1411a to 1411c. The gates of the P-channel TFTs 1411a to 1411c are all connected to the latch signal line 1412. When a negative voltage is applied to the latch signal line 1412, the P-channel TFTs 1411a to 1411c are all at once.
11c is turned on.

As a result, the signals held in the capacitors 1410a to 1410c are converted into P channel type T
It is held in capacitors 1413a to 1413c connected to each of FTs 1411a to 1411c and simultaneously outputted to the buffer 303. Then, the source wiring 14 is passed through the buffer.
14 is output. The source lines are selected in order by the source side driving circuit operating as described above.

As described above, by forming the gate side driver circuit and the source side driver circuit with only the P-channel TFT, the pixel portion and the driver circuit can be all formed with the P-channel TFT. Accordingly, the yield and throughput of the TFT process can be significantly improved in manufacturing an active matrix electro-optical device, and the manufacturing cost can be reduced.

Note that this embodiment can be freely combined with Embodiment 1, Embodiment 2, Embodiment 6, Embodiment 7, or Embodiment 8 and Embodiment 11. In this embodiment, the top gate type TF is used.
Although T is used, there is no particular limitation, and an inverted staggered TFT as shown in Embodiment 9 can also be used.

In this embodiment, instead of a general shift register, an N channel type TF as shown in FIG.
An example in which a drive circuit is formed using a decoder using T will be described. FIG. 20 shows an example of a gate side driving circuit.

In FIG. 20, reference numeral 1500 denotes a decoder of the gate side drive circuit, and 1501 denotes a buffer unit of the gate side drive circuit. The buffer unit refers to a part where a plurality of buffers (buffer amplifiers) are integrated. In addition, the buffer refers to a circuit that performs driving without affecting the preceding stage.

First, the gate side decoder 1500 will be described. First, reference numeral 1502 denotes an input signal line (hereinafter referred to as a selection line) of the decoder 1500. Here, A1, A1 bar (a signal in which the polarity of A1 is inverted), A2, A2 bar (a signal in which the polarity of A2 is inverted),. An and An bars (signals in which the polarity of An is inverted) are shown. That is, it can be considered that 2n selection lines are arranged.

The selection line 1502 transmits a signal shown in the timing chart of FIG. As shown in FIG. 21, when the frequency of A1 is 1, the frequency of A2 is 2 ⁻¹ times, the frequency of A3 is 2 ⁻² times, An
The frequency of is 2 ^{− (n−1)} times.

1503a is a first-stage NAND circuit (also called a NAND cell), and 1503b is a second-stage NAND circuit.
The NAND circuit 1503c is an nth NAND. The NAND circuit requires the number of gate wirings, and n pieces are required here. That is, in this embodiment, the decoder 1500
Consists of a plurality of NAND circuits.

The NAND circuits 1503a to 1503c are N-channel TFTs 1504 to 1509, respectively.
Are combined to form a NAND circuit. N-channel TFTs 1504-1
Each gate of 509 has a select line 1502 (A1, A1 bar, A2, A2 bar ... An, An
Connected to one of the bars).

In the NAND circuit 1503a, N-channel TFTs 1504 to 1506 having gates connected to any one of A1, A2,... An (referred to as positive selection lines)
They are connected in parallel to each other, connected to a negative power supply line (V _DL ) 1510 as a common source, and connected to an output line 1511 as a common drain.

In this embodiment, the NAND circuit includes n N-channel TFTs connected in series and n N-channel TFTs connected in parallel.

Next, the buffer unit 1501 is formed by a plurality of buffers 1513a to 1513c corresponding to each of the NAND circuits 1503a to 1503c. However, buffers 1513a-15
13c may have the same structure.

The buffers 1513a to 1513c are formed using N-channel TFTs 1514 to 1516.

In this embodiment, the buffers 1513a to 1513c are connected in series to the first N-channel TFT (N-channel TFT 1514) and the first N-channel TFT, and the drain of the first N-channel TFT is gated. The second N-channel TFT (N-channel TFT 1515) is included.

The N-channel TFT 1516 (third N-channel TFT) is connected to a reset signal line (
Reset) is a gate, a negative power supply line (V _DL ) 1519 is a source, and a gate wiring 1518 is a drain. Note that the negative power supply line (V _DL ) 1519 may be a ground power supply line (GND).

Note that the N-channel TFT 1516 is used as a reset switch for forcibly pulling down the gate wiring 1518 to which a positive voltage is applied to a negative voltage. That is, when the selection period of the gate wiring 1518 is completed. A reset signal is input and a negative voltage is applied to the gate wiring 1518.
However, the N-channel TFT 1516 can be omitted.

Next, FIG. 22 shows a configuration of the source side driver circuit. The source side driver circuit shown in FIG. 22 includes a decoder 1521, a latch 1522, and a buffer unit 1523.

In the case of the source side driver circuit shown in FIG. 22, the latch 1522 includes a first-stage latch 1524 and a second-stage latch 1525. The first-stage latch 1524 and the second-stage latch 1525 each include a plurality of unit units 1527 each formed of m N-channel TFTs 1526a to 1526c. An output line 1528 from the decoder 1521 is input to gates of m N-channel TFTs 1526a to 1526c forming the unit unit 1527. Note that m is an arbitrary integer.

The sources of the N-channel TFTs 1526a to 1526c are video signal lines (V1), respectively.
, V2... Vk) 1529. That is, when a positive voltage is applied to the output line 1528, the N-channel TFTs 1526a to 1526c are turned on at the same time, and video signals corresponding to the TFTs are taken in. Further, the video signal thus captured is an N-channel TFT 1
The capacitors 1530a to 1530c are connected to the respective capacitors 526a to 1526c.

The second-stage latch 1525 also includes a plurality of unit units 1527b, and the unit unit 1527b is formed of m N-channel TFTs 1531a to 1531c. The gates of the N-channel TFTs 1531a to 1531c are all connected to the latch signal line 1532, and when a negative voltage is applied to the latch signal line 1532, the N-channel TFTs 1531a to 1531-15 all at once.
31c is turned on.

As a result, the signals held in the capacitors 1530a to 1530c are converted into N channel type T
It is held in capacitors 1533a to 1533c connected to each of FTs 1531a to 1531c and simultaneously outputted to the buffer 1523. Then, the source wiring 1 is passed through the buffer.
It is output to 534. The source lines are selected in order by the source side driving circuit operating as described above.

As described above, by forming the gate side driver circuit and the source side driver circuit with only the N-channel TFT, the pixel portion and the driver circuit can be all formed with the N-channel TFT. Accordingly, the yield and throughput of the TFT process can be significantly improved in manufacturing an active matrix electro-optical device, and the manufacturing cost can be reduced.

Note that this embodiment can also be implemented when one of the source side driver circuit and the gate side driver circuit is an external IC chip.

In this embodiment, the drive circuit is configured using only the E-type NTFT, but it may be formed by combining the E-type NTFT and the D-type NTFT.

Note that this embodiment can be freely combined with Embodiment 1, Embodiment 3, Embodiment 5, Embodiment 7, or Embodiment 8. In this embodiment, a top gate type TFT is used, but there is no particular limitation, and an inverted stagger type TFT as shown in Embodiment 9 can also be used.

As the element formation substrate, a metal substrate, for example, a stainless steel substrate can also be used. In this embodiment, an example in that case is shown below.

In this example, as the element formation substrate of Example 1, a stainless steel substrate (thickness 10 to 200 μm) was used.
m). First, according to the embodiment, the first fixed substrate and the stainless steel substrate are bonded together with the first adhesive layer.

Thereafter, according to the first embodiment, a necessary element may be formed by forming a base insulating film on an element formation substrate made of a stainless steel substrate. Note that unlike the first embodiment, a stainless steel substrate having high heat resistance is used, so that a TFT can be manufactured using a process at a higher temperature (about 500 ° C. or lower) than that of the first embodiment.

Since the stainless steel substrate is used when separating the first fixed substrate, the first fixed substrate can be separated without affecting the elements formed on the element forming substrate even if the laser beam is irradiated. it can.

Further, since the stainless steel substrate has a light shielding property, the light emitting device of this embodiment is an upward emitting light emitting device.

By using a thin metal substrate (thickness of 10 to 200 μm), it is possible to obtain a light-emitting device that can be reduced in weight and thickness and has flexibility. Moreover, since the metal substrate is used, the heat radiation effect of the TFT element formed on the element substrate can be obtained.

In addition, this embodiment can be freely combined with any one of Embodiments 1 to 13.

The driving circuit and the pixel portion formed by implementing the present invention can be used in various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated in the display unit.

Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) and the like. . Examples of these are shown in FIGS.

FIG. 24A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention is applied to an image input unit 2002 and a display unit 20.
03 and other driving circuits.

FIG. 24B illustrates a video camera, which includes a main body 2101, a display portion 2102, and an audio input portion 210.
3, an operation switch 2104, a battery 2105, an image receiving unit 2106, and the like. The present invention can be applied to the display portion 2102 and other driver circuits.

FIG. 24C illustrates a mobile computer, which is a main body 2201.
A camera unit 2202, an image receiving unit 2203, an operation switch 2204, a display unit 2205, and the like are included.
The present invention can be applied to the display portion 2205 and other driving circuits.

FIG. 24D illustrates a goggle type display including a main body 2301, a display portion 2302, an arm portion 2303, and the like. The present invention can be applied to the display portion 2302 and other driving circuits.

FIG. 24E shows a player that uses a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404,
Operation switch 2405 and the like are included. This player uses DVD (Dig as a recording medium).
(tial Versatile Disc), CD, etc. can be used for music appreciation, movie appreciation, games and the Internet. The present invention can be applied to the display portion 2402 and other driving circuits.

FIG. 24F illustrates a digital camera, which includes a main body 2501, a display portion 2502, and an eyepiece portion 2503.
, An operation switch 2504, an image receiving unit (not shown), and the like. The present invention can be applied to the display portion 2502 and other driving circuits.

FIG. 25A shows a mobile phone, which includes a main body 2901, an audio output unit 2902, and an audio input unit 29.
03, a display portion 2904, an operation switch 2905, an antenna 2906, and the like. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other driving circuits.

FIG. 25B illustrates a portable book (electronic book), which includes a main body 3001 and display portions 3002 and 300.
3, a storage medium 3004, an operation switch 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003 and other driving circuits.

FIG. 25C illustrates a display, which includes a main body 3101, a support base 3102, and a display portion 3103.
Etc. The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic device of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-14.

Claims (1)

Forming a second substrate on the first substrate;
Forming a transistor on the second substrate;
And a step of separating the first substrate and the second substrate by laser light irradiation.

Images