JP2018152437A - Circuit board, electronic device, and manufacturing method of circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress peeling of a pad from an insulating film.SOLUTION: A circuit board includes an insulating film 14 provided on a board 10, a wiring layer 16 provided inside the insulating film 14, and a pad 18 that is electrically coupled to the wiring layer 16, in which a first surface 26 is in contact with the insulating film 14, and that a through hole 22 that penetrates from a second surface 28 opposite to the first surface 26 to the first surface 26 and in which the second surface 28 side is narrower than the first surface 26 side.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a circuit board, an electronic device, and a circuit board manufacturing method.

  It has been proposed to improve the bonding strength between the pad and the bump by using the anchor effect by embedding the bump in the groove or hole provided in the pad (for example, Patent Documents 1 and 2). In addition, it has been proposed to improve the adhesion between the pad and the insulating film by using an anchor effect by providing a wedge protruding from the insulating film on the lower surface of the pad (for example, Patent Document 3). In addition, in a configuration in which bumps are formed in the openings of the resin layer provided on the rewiring, the resin layer is embedded in the slit provided in the rewiring, thereby improving the adhesion between the rewiring and the resin layer. (For example, patent document 4).

Japanese Patent Laid-Open No. 11-40940 JP 2008-60142 A JP 2004-207324 A Japanese Patent Laid-Open No. 2006-92339

  When a circuit board having a pad provided in contact with an insulating film is bonded to another member by a solder bump, the pad to which the solder bump is bonded may be separated from the insulating film.

  An object of one aspect is to suppress the peeling of the pad from the insulating film.

  In one aspect, the insulating film provided on the substrate, the wiring layer provided in the insulating film, and electrically connected to the wiring layer, the first surface is in contact with the insulating film, And a pad having a through hole penetrating from the second surface opposite to the first surface to the first surface and having a through hole narrower on the second surface side than the first surface side.

  In one aspect, a substrate, an electronic component mounted on the substrate, an insulating film provided on the substrate, and a wiring layer provided inside the insulating film and electrically connected to the electronic component Electrically connected to the wiring layer, the first surface is in contact with the insulating film, penetrates from the second surface opposite to the first surface to the first surface, and the second surface side is the first surface A circuit board comprising a pad having a through-hole narrower than the one surface side, a solder bump mounted on the second surface of the pad, and a package substrate on which the circuit board is mounted by the solder bump. An electronic device is provided.

  In one aspect, the step of forming an insulating film on the substrate, the step of forming a wiring layer inside the insulating film, the electrical connection to the wiring layer, the first surface is in contact with the insulating film, Forming a pad that penetrates from the second surface opposite to the first surface to the first surface, and the second surface side has a narrower through-hole than the first surface side. It is a manufacturing method.

  As one side surface, peeling of the pad from the insulating film can be suppressed.

1A is a cross-sectional view of a circuit board according to the first embodiment, FIG. 1B is a cross-sectional view of a pad, and FIG. 1C is a plan view of the pad. 2A to 2D are cross-sectional views (part 1) illustrating the method for manufacturing the circuit board according to the first embodiment. FIG. 3A to FIG. 3D are cross-sectional views (part 2) illustrating the method for manufacturing the circuit board according to the first embodiment. 4A to 4C are cross-sectional views (part 3) illustrating the method for manufacturing the circuit board according to the first embodiment. 5 (a) is a plan view of the mask layer in FIG. 3 (d), FIG. 5 (b) is a plan view of the pad in FIG. 4 (a), and FIG. 5 (c) is in FIG. 4 (b). It is a top view of a pad. FIG. 6 is a cross-sectional SEM (Scanning Electron Microscope) image of the pad in Example 1. FIG. 7A is a cross-sectional view of a circuit board according to Comparative Example 1, and FIG. 7B is a plan view of a pad. FIG. 8A is a cross-sectional view of an electronic device in which the circuit board of Comparative Example 1 is flip-chip mounted on a package substrate, and FIG. 8B is the circuit board of Example 1 flip-chip mounted on the package substrate. It is sectional drawing of an electronic device. FIG. 9A and FIG. 9B are cross-sectional views for explaining the reason why peeling of the pad from the insulating film is suppressed. FIG. 10 is a diagram illustrating a result of a thermal shock test performed on an electronic device in which the circuit board of Example 1 is mounted on a package substrate. FIG. 11A and FIG. 11B are cross-sectional views showing other examples of through holes. 12A is a cross-sectional view of a circuit board according to the second embodiment, and FIG. 12B is a cross-sectional view of a pad. FIG. 13A is a cross-sectional view of a circuit board according to the third embodiment, and FIG. 13B is a cross-sectional view of a pad.

  Embodiments of the present invention will be described below with reference to the drawings.

  1A is a cross-sectional view of a circuit board according to the first embodiment, FIG. 1B is a cross-sectional view of a pad, and FIG. 1C is a plan view of the pad. The circuit board 100 according to the first embodiment is, for example, a fan-out wafer level package (FOWLP). As shown in FIGS. 1A to 1C, the circuit board 100 according to the first embodiment includes a substrate 10, an electronic component 12, an insulating film 14, a wiring layer 16, pads 18, and solder bumps 20. The substrate 10 is a component built-in substrate in which the electronic component 12 is embedded in a resin such as a mold resin. The electronic component 12 includes at least one of an active element and a passive element. Examples of the active element include a semiconductor element using silicon or a compound semiconductor (such as GaAs), and examples thereof include a transistor, an integrated circuit, and a CMOS sensor. Examples of the passive element include a resistor, a capacitor, and an inductor.

  An insulating film 14 is provided on one surface of the substrate 10. The insulating film 14 is, for example, a resin film such as polyimide, epoxy resin, or phenol resin, and may contain a filler. The insulating film 14 may be an inorganic insulating film such as silicon dioxide. A wiring layer 16 electrically connected to the electronic component 12 is provided inside the insulating film 14. The wiring layer 16 is made of a metal such as copper, for example.

  A pad 18 electrically connected to the wiring layer 16 is provided on the insulating film 14. The first surface 26 of the pad 18 is provided in contact with the insulating film 14. The second surface 28 opposite to the first surface 26 of the pad 18 is not in contact with the insulating film 14 but is exposed from the insulating film 14. The pad 18 is an electrode pad for soldering the circuit board 100 to another member, and may include an electrode called an under bump metal. The pad 18 has, for example, a circular shape in plan view. The pad 18 is formed of a single metal film such as copper, aluminum, gold, platinum, silver, nickel, titanium, tungsten, tantalum, tin, or chromium, a laminated metal film thereof, or an alloy film thereof. . On the second surface 28 of the pad 18, solder bumps 20 used when connecting the circuit board 100 to other members are provided. The solder bump 20 is, for example, silver tin (AgSn) solder or gold tin (AuSn) solder.

  When the pad 18 is a laminated metal film, the metal film in contact with the insulating film 14 is formed of a metal having good adhesion to the insulating film 14, and the metal film in contact with the solder bump 20 is a metal in which mutual diffusion with solder hardly occurs. Is preferably formed. This is because mutual diffusion with the solder may cause an increase in connection resistance or disconnection. Examples of the metal having good adhesion to the insulating film 14 include titanium, tungsten, tantalum, tin, chromium, and an alloy containing these metals.

  The pad 18 is provided with a plurality of through holes 22 penetrating from the second surface 28 to the first surface 26 of the pad 18. The plurality of through holes 22 are provided, for example, arranged in a lattice pattern over the entire surface of the pad 18. The through-hole 22 has a trapezoidal shape in which the second surface 28 side is narrow and the first surface 26 side is wide in a cross-sectional view. That is, the through hole 22 has a shape that continuously spreads from the second surface 28 to the first surface 26 in a cross-sectional view. For this reason, the size of the through hole 22 in the second surface 28 of the pad 18 is smaller than the size of the through hole 22 in the first surface 26 of the pad 18. Further, the side surface exposed to the through hole 22 of the pad 18 has a hook shape in which the second surface 28 side protrudes in the lateral direction from the first surface 26 side in a cross-sectional view.

  The size of the through hole 22 in the second surface 28 of the pad 18 is, for example, not less than 5 μm and not more than 50 μm. By making the size of the through holes 22 such as this, there is an advantage that the number of through holes arranged per unit area can be increased. The angle θ of the side surface of the through hole 22 is, for example, 55 ° or more and 80 ° or less. By setting the side surface of the through hole 22 to such an angle, there is a merit that the penetration of solder having a high thermal expansion coefficient into the through hole can be suppressed. The through-hole 22 has, for example, a circular shape in plan view, but may have a rectangular shape, a polygonal shape, an elliptical shape, or a slit shape. The plurality of through holes 22 may include a plurality of these shapes.

  Next, a method for manufacturing a circuit board according to the first embodiment will be described. FIG. 2A to FIG. 4C are cross-sectional views illustrating a method for manufacturing a circuit board according to the first embodiment. 5 (a) is a plan view of the mask layer in FIG. 3 (d), FIG. 5 (b) is a plan view of the pad in FIG. 4 (a), and FIG. 5 (c) is in FIG. 4 (b). It is a top view of a pad. The manufacturing method of the circuit board of Example 1 is a manufacturing method using a multi-chamfer structure. In FIG. 2A to FIG. 4C, a part of the circuit board according to the first embodiment is illustrated for clarity.

  As shown in FIG. 2A, a substrate 10 that is a component-embedded substrate in which an electronic component 12 is embedded in a resin such as a mold resin is prepared. An insulating film 14 a having positive photosensitivity is formed on one surface of the substrate 10. The insulating film 14a is formed by, for example, spin-coating and then performing pre-baking at 80 ° C. for 30 minutes. The thickness of the insulating film 14a is 5 μm, for example.

  As shown in FIG. 2B, the insulating film 14a is exposed and developed to form an opening pattern 30 for via wiring. The opening pattern 30 is formed so as to penetrate the insulating film 14a. The exposure is performed using, for example, a broadband equal magnification stepper. The diameter of the opening pattern 30 is 15 μm, for example. After the opening pattern 30 is formed, the insulating film 14a is cured, for example, in a nitrogen atmosphere at 200 ° C. for 30 minutes. Thereafter, a seed layer 50 is formed on the insulating film 14a. The seed layer 50 is formed by, for example, a sputtering method. The seed layer 50 is, for example, a metal film in which a titanium layer and a copper layer are stacked from the substrate 10 side. The thickness of the titanium layer is 50 nm, for example, and the thickness of the copper layer is 100 nm, for example.

  A positive resist film 52 is formed on the seed layer 50 as shown in FIG. The resist film 52 is formed by, for example, spin-coating and then performing pre-baking at 80 ° C. for 30 minutes. Thereafter, the resist film 52 is exposed and developed using, for example, a broadband equal stepper to form an opening pattern 32 for land electrodes and an opening pattern 34 for wiring. The opening patterns 32 and 34 are formed through the resist film 52. The opening pattern 32 is formed on the opening pattern 30 formed through the insulating film 14a. The diameter of the land electrode opening pattern 32 is 60 μm, for example, and the diameter of the wiring opening pattern 34 is 10 μm, for example.

  As shown in FIG. 2D, a plating film 54 is formed in the opening patterns 30, 32, 34 by electrolytic plating using the resist film 52 as a mask. The plating film 54 is, for example, a copper plating film.

  As shown in FIG. 3A, after the resist film 52 is peeled off, the seed layer 50 is removed by etching using the plating film 54 as a mask. For the etching of the seed layer 50, for example, a dry etching method is used. Thereby, the via wiring 60, the land electrode 62 provided in contact with the upper surface of the via wiring 60, and the wiring 64 are formed. The via wiring 60, the land electrode 62, and the wiring 64 are electrically connected to the electronic component 12.

  As shown in FIG. 3B, an insulating film 14b having positive photosensitivity is formed on the insulating film 14a. The insulating film 14 b is formed by embedding the land electrode 62 and the wiring 64. The insulating film 14b is formed by applying, for example, a spin coating method and then pre-baking at 80 ° C. for 30 minutes, for example, in the same manner as the insulating film 14a. The thickness of the insulating film 14b is, for example, 10 μm.

  As shown in FIG. 3C, the insulating film 14b is exposed and developed using, for example, a broadband equal magnification stepper to form an opening pattern 36 for via wiring. The opening pattern 36 is formed so as to penetrate the insulating film 14 b, and the land electrode 62 is exposed by the opening pattern 36. The diameter of the opening pattern 36 is 15 μm, for example. Next, the insulating film 14b is cured, for example, in a nitrogen atmosphere at 200 ° C. for 30 minutes. Thereafter, a seed layer 56 is formed on the insulating film 14b by using, for example, a sputtering method. The seed layer 56 is a laminated film of, for example, a 50 nm titanium layer and a 100 nm copper layer, like the seed layer 50.

  As shown in FIGS. 3D and 5A, a positive resist is applied on the seed layer 56 by, eg, spin coating, and then pre-baked at, for example, 80 ° C. for 30 minutes. A mold resist film 58 is formed. Next, the resist film 58 is exposed and developed by overexposure with an exposure amount larger than the recommended exposure amount of the resist material. For example, the resist film 58 is exposed with an exposure amount of about 1.5 times the recommended exposure amount of the resist material. As a result, an opening pattern 38 for land electrodes, an opening pattern 40 for wiring, and an opening pattern 42 for pads are formed. A plurality of island patterns 44 are left in the pad opening pattern 42. By overexposure, the side surfaces of the plurality of island patterns 44 have a forward tapered shape in a cross-sectional view. The diameter of the land electrode opening pattern 38 is, for example, 60 μm, the diameter of the wiring opening pattern 40 is, for example, 10 μm, and the diameter of the pad opening pattern 42 is, for example, 400 μm.

  As shown in FIGS. 4A and 5B, plating films are formed in the opening patterns 36, 38, 40, and 42 by electrolytic plating using the resist film 58 as a mask. Thereafter, after removing the resist film 58, the seed layer 56 is removed by etching using the plating film as a mask. Thereby, the via wiring 66 provided in contact with the upper surface of the land electrode 62, the land electrode 68 provided in contact with the upper surface of the via wiring 66, the wiring 70, and the pad 18 are formed. Since the plurality of island patterns 44 having the side surface with the forward taper shape are provided in the opening pattern 42 for the pad, the plurality of through holes 22 having the side surface with the reverse taper shape are formed in the pad 18.

  As shown in FIGS. 4B and 5C, a positive-type photosensitive insulating film 14c is formed on the insulating film 14b. The insulating film 14 c is formed by embedding the land electrode 68, the wiring 70, and the pad 18. The insulating film 14c is formed by applying, for example, a spin coating method and then pre-baking at, for example, 80 ° C. for 30 minutes, like the insulating films 14a and 14b. The thickness of the insulating film 14c is, for example, 10 μm. The insulating film 14 provided on the substrate 10 is composed of insulating films 14a to 14c. In addition, the wiring layers 16 provided inside the insulating film 14 are configured by the via wirings 60 and 66, the land electrodes 62 and 68, and the wirings 64 and 70.

  Thereafter, the insulating film 14c is exposed and developed using, for example, a broadband equal stepper to form an opening 46 in the insulating film 14c in the pad 18. The diameter of the opening 46 is 400 μm, for example. The metal portion exposed at the opening 46 becomes the pad 18. Next, the insulating film 14c is cured, for example, in a nitrogen atmosphere at 200 ° C. for 30 minutes.

  As shown in FIG. 4C, the solder bump 20 is formed on the pad 18 exposed at the opening 46. Thereby, the circuit board 100 of Example 1 is formed.

  FIG. 6 is a cross-sectional SEM (Scanning Electron Microscope) image of the pad in Example 1. In FIG. 6, the pad 18 in the circuit board manufactured by the manufacturing method described with reference to FIGS. 2A to 5C using phenol resin for the insulating film 14, copper for the pad 18, and silver tin solder for the solder bump 20. The cross-sectional SEM image of is shown. As shown in FIG. 6, since the through hole 22 is narrower on the second surface 28 side of the pad 18 than on the first surface 26 side, the solder bump 20 is not embedded in the through hole 22 and a void is formed. For example, in FIG. 6, the width of the through hole 22 is about 16 μm on the first surface 26 of the pad 18, and is about 12 μm on the second surface 28.

  Here, in describing the effect of the first embodiment, the circuit board of the first comparative example will be described. FIG. 7A is a cross-sectional view of a circuit board according to Comparative Example 1, and FIG. 7B is a plan view of a pad. As shown in FIG. 7A and FIG. 7B, in the circuit board 500 of Comparative Example 1, the through hole 22 is not provided in the pad 18. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  FIG. 8A is a cross-sectional view of an electronic device in which the circuit board of Comparative Example 1 is flip-chip mounted on a package substrate, and FIG. 8B is the circuit board of Example 1 flip-chip mounted on the package substrate. It is sectional drawing of an electronic device. The electronic device is formed by heating the circuit board to a high temperature of, for example, 200 ° C. or more to melt the solder bumps 20 and bonding them to the package substrate 80.

  As shown in FIG. 8A, in the electronic device 600 in which the circuit substrate 500 of Comparative Example 1 is flip-chip mounted on the package substrate 80 with the solder bumps 20, the pad 18 may be peeled off from the insulating film 14. The peeling of the pad 18 from the insulating film 14 is considered to occur for the following two reasons. The first reason is considered to be due to the stress generated due to the difference in thermal expansion coefficient between the pad 18 and the insulating film 14. That is, since the pad 18 is made of metal and the insulating film 14 is made of an insulator, the difference in thermal expansion coefficient is large. For this reason, a large stress due to the difference in thermal expansion coefficient between the pad 18 and the insulating film 14 is generated by being heated to 200 ° C. or higher during solder bonding. As a result, the pad 18 is considered to be peeled from the insulating film 14. The second reason is that the main component and the contamination component of the insulating film 14 are vaporized from the insulating film 14 by being heated to 200 ° C. or higher at the time of solder bonding, and this gas peels the pad 18 from the insulating film 14. Apply pressure in the direction. As a result, the pad 18 is considered to be peeled from the insulating film 14.

  On the other hand, as shown in FIG. 8B, in the electronic device 400 in which the circuit board 100 of Example 1 is flip-chip mounted on the package substrate 80 by the solder bumps 20, the pads 18 are prevented from being peeled off from the insulating film 14. . The reason why the separation of the pad 18 from the insulating film 14 is suppressed is because the pad 18 is provided with a through hole 22 narrower on the second surface 28 side than on the first surface 26 side. This will be described with reference to FIGS. 9A and 9B.

  FIG. 9A and FIG. 9B are cross-sectional views for explaining the reason why peeling of the pad from the insulating film is suppressed. As shown in FIG. 9A, the through hole 22 provided in the pad 18 is narrower on the second surface 28 side than on the first surface 26 side. Since the through hole 22 on the second surface 28 of the pad 18 is small, the solder bump 20 is less likely to enter the through hole 22. Since the through-hole 22 in the first surface 26 of the pad 18 is large, the contact area between the insulating film 14 and the pad 18 is reduced, and the stress generated due to the difference in thermal expansion coefficient is reduced. For this reason, it is considered that peeling of the pad 18 from the insulating film 14 is suppressed. Further, since a part of the gas generated from the insulating film 14 is discharged into the through hole 22 by being heated to a high temperature at the time of soldering, it is added to the direction in which the pad 18 is separated from the insulating film 14 by the gas. Less pressure is applied. For this reason, it is considered that peeling of the pad 18 from the insulating film 14 is suppressed.

  As shown in FIG. 9B, depending on the size of the through hole 22 on the second surface 28 side of the pad 18, the solder bump 20 may enter the through hole 22. Since the solder bump 20 enters the through hole 22, the contact area between the insulating film 14 and the metal (the pad 18 and the solder bump 20) is larger than that in FIG. The resulting stress increases. However, since the through hole 22 is narrower on the second surface 28 side than on the first surface 26 side, the side surface exposed to the through hole 22 of the pad 18 is on the second surface 28 side than the first surface 26 side in a sectional view. It has a bowl shape protruding in the lateral direction. As a result, the solder bump 20 is hardly embedded in the lower portion of the side surface exposed to the through hole 22 of the pad 18, and a gap 24 is formed. By forming the gap 24, the contact area between the insulating film 14 and the metal becomes smaller than that in the first comparative example, and the gas from the insulating film 14 can be discharged into the gap 24, thereby insulating the pad 18. It is considered that peeling from the film 14 is suppressed.

  As described above, according to the first embodiment, the pad 18 is provided with the through hole 22 penetrating from the second surface 28 to the first surface 26 and narrower on the second surface 28 side than on the first surface 26 side. As a result, as described above, the stress due to the difference in thermal expansion coefficient between the insulating film 14 and the pad 18 can be reduced, and the gas generated from the insulating film 14 can be discharged to the through-hole 22. Separation from the insulating film 14 can be suppressed.

  As shown in FIGS. 2A to 4C, an insulating film 14 is formed on the substrate 10. A wiring layer 16 is formed inside the insulating film 14. A through hole 22 that is electrically connected to the wiring layer 16, the first surface 26 is in contact with the insulating film 14, penetrates from the second surface 28 to the first surface 26, and the second surface 28 side is narrower than the first surface 26 side. The pad 18 having the following is formed. The circuit board 100 of Example 1 can be manufactured including these steps.

  Further, as shown in FIGS. 3D and 5A, a resist film 58 having an opening pattern 42 and an island pattern 44 provided in the opening pattern 42 and having a forward tapered shape on the side surface is formed. . 4A and 5C, the pad 18 is formed by depositing a metal film using the resist film 58 as a mask. Thereby, the pad 18 which penetrates from the 2nd surface 28 to the 1st surface 26 and has the through-hole 22 in which the 2nd surface 28 side is narrower than the 1st surface 26 side can be formed easily.

  Next, an experiment conducted by the inventor will be described. As shown in FIG. 8B, the inventor conducted a thermal shock test on the electronic device 400 in which the circuit board 100 of Example 1 was mounted on the package substrate 80. In the experiment, phenol resin was used for the insulating film 14, copper was used for the pads 18, silver tin solder was used for the solder bumps 20, and an FR4 (Flame Retardant Type 4) substrate was used for the package substrate 80. The plurality of through holes 22 have a circular shape with a diameter of 20 μm on the second surface 28 of the pad 18. Then, a plurality of samples having different total areas of the plurality of through holes 22 on the second surface 28 of the pad 18 were produced and subjected to a thermal shock test. The thermal shock test was performed after the precondition test. In the precondition test, screening was performed at 125 ° C. for 24 hours in a dry environment and then at 30 ° C. for 192 hours in an environment with a relative humidity of 60%, and then IR reflow was performed three times at 260 ° C. for 1 minute. . The thermal shock test was performed at 1000 cycles for 5 minutes at -65 ° C and 5 minutes at 150 ° C for one cycle.

  FIG. 10 is a diagram illustrating a result of a thermal shock test performed on an electronic device in which the circuit board of Example 1 is mounted on a package substrate. The horizontal axis of FIG. 10 indicates the ratio of the total area of the plurality of through holes 22 to the area of the pad 18 when the through holes 22 are not provided on the second surface 28 of the pad 18 (the through holes 22 Occupied area ratio). The vertical axis represents the rate of change in resistance before and after the thermal shock test. The resistance change rate is a value calculated by dividing the resistance before the thermal shock test measured by the four-end method and the resistance after the thermal shock test. As shown in FIG. 10, it can be seen that the rate of change in resistance rapidly increases when the occupied area ratio of the through-hole 22 is lower than 0.3% and larger than 30%. The resistance change rate increased when the occupied area ratio of the through-hole 22 was lower than 0.3% because the contact area between the insulating film 14 and the pad 18 was increased, and the effects of stress relaxation and gas discharge were reduced. This is probably because The reason why the rate of change in resistance increases when the occupied area ratio of the through-holes 22 is larger than 30% is considered to be because the contact area between the insulating film 14 and the pad 18 becomes too small and the adhesion strength decreases. From this result, in the second surface 28 of the pad 18, the ratio of the total area of the through holes 22 to the area of the pad 18 when the through holes 22 are not provided is 0.3% or more and 30% or less. Is preferred. From the viewpoint of reducing the rate of change in resistance, the ratio of the total area of the through holes 22 is preferably 1% or more and 20% or less, more preferably 5% or more and 15% or less.

  Further, according to the first embodiment, as shown in FIG. 1A, the solder bumps 20 are not embedded in the through holes 22 provided in the pads 18. Thereby, it is possible to effectively reduce the stress caused by the difference in thermal expansion coefficient between the insulating film 14 and the pad 18 and discharge the gas generated from the insulating film 14.

  As shown in FIG. 1C, the through hole 22 preferably has a circular shape in plan view. As described above, by tapering the side surface of the through-hole 22, stress relaxation and gas discharge effects can be obtained, and by forming the through-hole 22 in a circular shape, many tapered portions can be formed in a narrow range. It is. Note that the through hole 22 may have a rectangular shape or a polygonal shape in plan view. In this case, in order to prevent cracks and peeling from the corner portion due to stress, the corner portion is preferably rounded. .

  As shown in FIG. 1C, the pad 18 preferably has a circular shape in plan view. Thereby, the stress generated by the difference in thermal expansion coefficient between the insulating film 14 and the pad 18 can be applied uniformly to the pad 18. Note that the pad 18 may have a rectangular shape or a polygonal shape in plan view, but in this case, in order to prevent stress from concentrating on the corner portion and causing cracks and peeling, the corner portion has a round shape. It is preferable to make it.

  As shown in FIG. 1C, the through holes 22 provided in the pad 18 are preferably provided over the entire second surface 28 of the pad 18, and are provided at equal intervals. More preferred. Examples of the arrangement of such through holes include a lattice form and a staggered arrangement. Thereby, it can suppress effectively that the pad 18 peels from the insulating film 14. FIG.

  In the first embodiment, the through hole 22 provided in the pad 18 has a trapezoidal shape that continuously spreads linearly from the second surface 28 side to the first surface 26 side in a cross-sectional view. However, other shapes may be used. FIG. 11A and FIG. 11B are cross-sectional views showing other examples of through holes. As shown in FIG. 11A, the through-hole 22 may continuously extend in an arc shape from the second surface 28 side to the first surface 26 side of the pad 18 in a cross-sectional view. As shown in FIG. 11B, the through hole 22 may extend stepwise from the second surface 28 side to the first surface 26 side of the pad 18 in a sectional view.

  In the first embodiment, the case where the circuit board 100 is a fan-out level package is shown as an example, but other cases may be used. That is, the electronic component 12 is not limited to being built in the substrate 10 and may be mounted on the surface of the substrate 10. In this case, the substrate 10 may be a semiconductor substrate such as a silicon substrate, a ceramic substrate such as an alumina substrate, or another substrate such as an insulating substrate.

  12A is a cross-sectional view of a circuit board according to the second embodiment, and FIG. 12B is a cross-sectional view of a pad. As shown in FIG. 12A and FIG. 12B, in the circuit board 200 of the second embodiment, the through hole 22 provided in the pad 18 penetrates the pad 18 and digs up to a part of the insulating film 14. It is rare. Other configurations are the same as those of the first embodiment illustrated in FIGS. 1A to 1C, and thus description thereof is omitted.

  According to the second embodiment, the through hole 22 penetrates from the second surface 28 of the pad 18 to the first surface 26 and is dug to a part of the insulating film 14. Thereby, since the surface area of the insulating film 14 exposed to the through hole 22 can be increased, the gas generated in the insulating film 14 can be effectively discharged into the through hole 22.

  In order to effectively discharge the gas generated in the insulating film 14 into the through hole 22, the amount of digging of the insulating film 14 by the through hole 22 is preferably 250 nm or more, more preferably 500 nm or more, and 800 nm. The above case is more preferable. On the other hand, if the digging of the insulating film 14 becomes too deep, internal destruction may occur in the insulating film 14. Therefore, the digging amount of the insulating film 14 by the through hole 22 is preferably 2000 nm or less, more preferably 1500 nm or less, and further preferably 1200 nm or less.

  FIG. 13A is a cross-sectional view of a circuit board according to the third embodiment, and FIG. 13B is a cross-sectional view of a pad. As shown in FIGS. 13A and 13B, in the circuit board 300 of the third embodiment, the electronic component 12 is not built in the board 10. Other configurations are the same as those of the first embodiment illustrated in FIGS. 1A to 1C, and thus description thereof is omitted.

  In the first embodiment, the circuit board 100 in which the electronic component 12 is mounted on the substrate 10 is described as an example. However, as in the third embodiment, the circuit board 300 in which the electronic component is not mounted on the substrate 10 may be used. That is, the circuit board may or may not include an electronic component. When the electronic component 12 is not mounted on the substrate 10, the substrate 10 may be a semiconductor substrate such as a silicon substrate, a ceramic substrate such as an alumina substrate, an insulating substrate such as a resin substrate, or another substrate. . Further, FIG. 10 shows a case where the solder bump 20 is provided, but a case where the solder bump 20 is not provided may be used.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

In addition, the following additional notes are disclosed regarding the above description.
(Supplementary Note 1) An insulating film provided on a substrate, a wiring layer provided inside the insulating film, and electrically connected to the wiring layer, a first surface being in contact with the insulating film, A circuit board comprising: a pad penetrating from the second surface opposite to the surface to the first surface and having a through hole narrower on the second surface side than the first surface side.
(Supplementary note 2) The circuit board according to supplementary note 1, wherein the through hole has a trapezoidal shape in a cross-sectional view.
(Supplementary Note 3) In the second surface of the pad, the ratio of the total area of the through holes to the area of the pad when the through holes are not provided is 0.3% or more and 30% or less. The circuit board according to appendix 1 or 2, wherein
(Supplementary note 4) The circuit board according to any one of Supplementary notes 1 to 3, wherein the through hole penetrates from the second surface to the first surface of the pad and is dug to a part of the insulating film. .
(Supplementary note 5) The circuit board according to any one of supplementary notes 1 to 4, wherein the through hole has a circular shape in plan view.
(Appendix 6) The circuit board according to any one of appendices 1 to 5, wherein the through hole is provided over the entire surface of the pad.
(Supplementary note 7) The circuit board according to any one of supplementary notes 1 to 6, wherein the plurality of through holes are arranged at equal intervals.
(Supplementary note 8) Any one of Supplementary notes 1 to 7, comprising: an electronic component mounted on the substrate and electrically connected to the wiring layer; and a solder bump mounted on the second surface of the pad. Circuit board according to item.
(Supplementary note 9) The circuit board according to supplementary note 8, wherein the solder bump is not embedded in the through hole provided in the pad.
(Supplementary note 10) a substrate, an electronic component mounted on the substrate, an insulating film provided on the substrate, a wiring layer provided inside the insulating film and electrically connected to the electronic component; , Electrically connected to the wiring layer, the first surface is in contact with the insulating film, penetrates from the second surface opposite to the first surface to the first surface, and the second surface side is the first surface A circuit board including a pad having a through hole narrower than a surface side, a solder bump mounted on the second surface of the pad, and a package substrate on which the circuit board is mounted by the solder bump. , Electronic devices.
(Additional remark 11) The process of forming an insulating film on a board | substrate, The process of forming a wiring layer inside the said insulating film, It is electrically connected to the said wiring layer, 1st surface is in contact with the said insulating film, Forming a pad that penetrates from the second surface opposite to the first surface to the first surface, and the second surface side has a through hole that is narrower than the first surface side. Method.
(Supplementary Note 12) The step of forming the pad includes depositing a metal film using a mask layer having an opening pattern and an island pattern provided in the opening pattern and having a side surface having a forward tapered shape as a mask. The method for manufacturing a circuit board according to appendix 11, wherein the pad having holes is formed.

DESCRIPTION OF SYMBOLS 10 Board | substrate 12 Electronic component 14-14c Insulating film 16 Wiring layer 18 Pad 20 Solder bump 22 Through-hole 24 Space | gap 26 The 1st surface of a pad 28 The 2nd surface of a pad 30-42 Opening pattern 44 Island pattern 46 Opening 50, 56 Seed layer 52 resist film 54 plating film 60, 66 via wiring 62, 68 land electrode 64, 70 wiring 80 package substrate 100-300 circuit substrate 400 electronic device

Claims (9)

An insulating film provided on the substrate;
A wiring layer provided inside the insulating film;
Electrically connected to the wiring layer, the first surface is in contact with the insulating film, penetrates from the second surface opposite to the first surface to the first surface, and the second surface side is the first surface side And a pad having a narrower through hole.   The circuit board according to claim 1, wherein the through hole has a trapezoidal shape in a sectional view.   The ratio of the total area of the through holes to the area of the pad when the through holes are not provided in the second surface of the pad is 0.3% or more and 30% or less. The circuit board according to 1 or 2.   4. The circuit board according to claim 1, wherein the through hole penetrates from the second surface to the first surface of the pad and is dug to a part of the insulating film. 5. An electronic component mounted on the substrate and electrically connected to the wiring layer;
The circuit board according to claim 1, further comprising a solder bump mounted on the second surface of the pad.   The circuit board according to claim 5, wherein the solder bump is not embedded in the through hole provided in the pad. A substrate; an electronic component mounted on the substrate; an insulating film provided on the substrate; a wiring layer provided inside the insulating film and electrically connected to the electronic component; and the wiring layer The first surface is in contact with the insulating film, penetrates from the second surface opposite to the first surface to the first surface, and the second surface side is more than the first surface side. A circuit board comprising a pad having a narrow through hole and a solder bump mounted on the second surface of the pad;
An electronic device comprising: a circuit board on which the circuit board is mounted by the solder bumps. Forming an insulating film on the substrate;
Forming a wiring layer inside the insulating film;
Electrically connected to the wiring layer, the first surface is in contact with the insulating film, penetrates from the second surface opposite to the first surface to the first surface, and the second surface side is the first surface Forming a pad having a through hole narrower than the side, and a method of manufacturing a circuit board. The step of forming the pad includes depositing a metal film using a mask layer having an opening pattern and an island pattern provided in the opening pattern and having a side surface having a forward taper shape as a mask, thereby providing the through hole. The method for manufacturing a circuit board according to claim 8, wherein a pad is formed.

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