JP2018133475A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of gaining a sufficient Low-High doping impurity distribution even near an end of an element isolation body.SOLUTION: A Low-High doping MOSFET 1 comprises: element isolation bodies 14 formed in a silicon substrate 11; a high impurity concentration layer 15 provided in contact with the element isolation bodies 14; an impurity diffusion prevention layer 16 laminated on the high impurity concentration layer 15; an epi silicon layer 17 which is laminated on the impurity diffusion prevention layer 16 so as to be included within the impurity diffusion prevention layer 16 in top view and in which an impurity is diffused with lower concentration than the high impurity concentration layer 15; insulator side walls 13a which are formed on the high impurity concentration layer 15 and between the element isolation bodies 14 and the impurity diffusion prevention layer 16 and in contact with the element isolation bodies 14 and the impurity diffusion prevention layer 16; a gate insulation film 18 laminated on a surface of the epi silicon layer 17; and a gate electrode 19 provided so as to cover the element isolation bodies 14, the insulator side walls 13a and the gate insulation film 18.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

A general planar type MOSFET (field effect transistor) 100 has a configuration shown in the schematic diagram of FIG. 4, for example. That is, as shown in FIG. 4, for example, the source electrode 102 and the drain electrode 103 are formed on the silicon substrate 101. In addition, a gate insulating film 104 is formed over the channel region between the source electrode 102 and the drain electrode 103, and the gate electrode 105 is stacked over the gate insulating film 104. Further, sidewalls 106 are formed on the side surfaces of the gate electrode 105 and the gate insulating film 104.
In the MOSFET 100 having such a configuration, an inversion layer is generated in the vicinity of the gate insulating film 104 of the silicon substrate 101 by the voltage applied to the gate electrode 105, thereby generating a channel connecting the source electrode 102 and the drain electrode 103. Current flows. In order to control a gate electrode voltage necessary for generating the inversion layer, that is, a threshold voltage Vth, the silicon substrate 101 is doped with a p-type or n-type impurity. This impurity is generally implanted by uniform depth doping so as to be uniform in the depth direction of the silicon substrate 101 as indicated by the solid line L1 in FIG. In FIG. 5, the horizontal axis represents the substrate depth, and the vertical axis represents the impurity concentration.

  However, when doping is performed so that the impurities are uniform in the depth direction, the impurities in the vicinity of the channel cause carrier scattering and potential variation, resulting in a decrease in mobility, an increase in 1 / f noise, and a threshold voltage. It causes deterioration of electrical characteristics such as an increase in mismatch of Vth. Therefore, in order to improve this, as indicated by a broken line L2 in FIG. 5, the impurity concentration in the vicinity of the channel is reduced, and doping is performed so that the impurity concentration is sufficient at a position away from the channel. Doping MOSFETs have been proposed.

As a technique for realizing this Low-High doping type MOSFET, for example, a planar type MOSFET described in Non-Patent Document 1 has been proposed.
6 is a schematic diagram of a Low-High doping type MOSFET proposed in Non-Patent Document 1, and FIG. 6A is a top view showing an example of a Low-High doping type MOSFET 200. 6B is a sectional view taken along line XX ′ in FIG. 6A, and FIG. 6C is a sectional view taken along line YY ′ in FIG. In FIG. 6A, 201 is an active region, and 202 is a gate electrode.

The MOSFET 200 shown in FIG. 6 is provided with an impurity diffusion prevention layer 204 in the element formation region separated by the element separator 203 of the general planar MOSFET 100 shown in FIG. An episilicon layer 205 obtained by epitaxially growing a Si layer is provided thereon. With such a configuration, the impurity concentration of the channel portion is reduced. In FIG. 6, the same parts as those of the MOSFET 100 shown in FIG.
In Non-Patent Document 1, a planar type MOSFET having a gate size as small as 25 nm is taken up as the Low-High doping type MOSFET 200 shown in FIG. 6, but the mobility, 1 / f noise, Vth mismatch or the like is an important parameter even in a MOSFET for an analog circuit having a gate size of about 180 nm, and a low-high doping type MOSFET is desired for a MOSFET for an analog circuit having a gate size of about 180 nm.

Here, as shown in FIG. 6, the selective epi type MOSFET 200 in which the epi silicon layer 205 is laminated only on the impurity diffusion preventing layer 204 is manufactured, for example, by the procedure shown in FIG.
First, as shown in FIG. 7A, an element separator 203 is formed on the silicon substrate 101, and then, as shown in FIG. 7B, high-concentration ion implantation is performed to separate the elements separated by the element separator 203. A high concentration impurity region 301 for adjusting the threshold voltage Vth of the MOSFET 200 is formed in the formation region (FIG. 7C).
Thereafter, for example, a Si—C (silicon carbide) layer as the impurity diffusion preventing layer 204 is selectively formed only on the element formation region separated by the element separator 203 of the silicon substrate 101, that is, only on the high concentration impurity region 301. Epitaxially grow. Further, as shown in FIG. 7D, an epitaxial silicon layer 205 that becomes a low impurity concentration channel portion is selectively epitaxially grown only on the impurity diffusion preventing layer 204. Thereafter, as shown in FIG. 7E, a gate insulating film 104 is formed so as to cover the epitaxial silicon layer 205, and as shown in FIG. 7F, a gate electrode 105 is formed on the gate insulating film 104. To do.

Thereafter, ion implantation into the extension region and ion implantation into the source region and the drain region to be the source electrode and the drain electrode are performed to complete a Low-High doping type MOSFET as shown in FIG.
In a device manufactured using such a method, impurity diffusion due to heat applied in the CMOS process is inhibited by the impurity diffusion preventing layer 204, whereby a low-high doping type impurity distribution can be obtained.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.58, No.5, MAY 2011 “25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)”

In the case of a low-high doping type MOSFET using a low impurity concentration region formation technique by selective epi growth for the purpose of reducing carrier impurity scattering, as shown in FIG. In the vicinity of the interface X between the silicon substrate 101 and the silicon substrate 101, the impurity diffusion prevention layer 204 becomes thinner. For this reason, sufficient impurity diffusion prevention cannot be performed in the vicinity of the region where the thickness of the impurity diffusion prevention layer 204 of the silicon substrate 101 becomes thin, and as a result, a low-high doping type impurity distribution cannot be realized locally. There are challenges.
Accordingly, the present invention has been made in view of such circumstances, and a semiconductor device capable of obtaining a sufficient low-high doping type impurity distribution near the edge of an element isolation body and a method for manufacturing the same. It is intended to provide.

  In order to achieve the above object, a semiconductor device according to one embodiment of the present invention is provided with an element separator formed in an element isolation region of a semiconductor substrate and in contact with the element separator in the element formation region of the semiconductor substrate. A first impurity diffusion layer in which impurities are diffused, an impurity diffusion prevention layer stacked on a surface of the first impurity diffusion layer, and a surface of the impurity diffusion prevention layer included in the impurity diffusion prevention layer in a top view And a second impurity diffusion layer in which impurities of the same conductivity type as the first impurity diffusion layer are diffused at a lower concentration, and the element separator is formed on the surface of the first impurity diffusion layer. Insulating sidewalls provided between and in contact with the impurity diffusion preventing layer, a gate insulating film laminated on the surface of the second impurity diffusion layer, the element separator, the sidewalls, and the Get It is characterized by comprising a gate electrode provided so as to cover the gate insulating film.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a mask layer forming step of forming a mask layer inside an element formation region of a semiconductor substrate; and the element formation region from the side surface to the side surface of the mask layer. A sidewall forming step for forming a sidewall covering up to the end of the semiconductor substrate; a trench forming step for forming a trench in an element isolation region of the semiconductor substrate; and an element isolation body in contact with the inner surface of the trench and the side surface of the sidewall. A first conductive layer is formed on the element formation region exposed by removing the mask layer and removing the mask layer so that the sidewall remains after the element separator is formed; A first impurity diffusion layer forming step of forming a first impurity diffusion layer by ion-implanting a type impurity, and a side surface on the surface of the first impurity diffusion layer. Impurity diffusion prevention layer forming step of forming an impurity diffusion prevention layer in contact with the wall by epitaxial growth, and the impurity of the first conductivity type is diffused on the surface of the impurity diffusion prevention layer at a concentration lower than that of the first impurity diffusion layer. A low impurity concentration layer forming step of forming the second impurity diffusion layer by epitaxial growth, a gate insulating film forming step of forming a gate insulating film on the surface of the second impurity diffusion layer, the element separator, the sidewall, and And a gate electrode forming step of forming a gate electrode so as to cover the surface of the gate insulating film.

  According to one embodiment of the present invention, a semiconductor device capable of obtaining a sufficient Low-High doping type impurity distribution even in the vicinity of an end portion of an element separator can be obtained.

It is sectional drawing which shows an example of Low-High doping type MOSFET which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the manufacturing process of Low-High doping type MOSFET of this invention. It is a continuation of FIG. It is sectional drawing which shows an example of the conventional Low-High doping type MOSFET. It is a characteristic view showing the impurity concentration of the depth direction of a silicon substrate. It is a block diagram which shows an example of the conventional Low-High doping type MOSFET. It is sectional drawing which shows an example of the manufacturing process of the conventional Low-High doping type MOSFET.

In the following detailed description, numerous specific specific configurations are described to provide a thorough understanding of embodiments of the invention. However, it is apparent that other embodiments can be implemented without being limited to such specific specific configurations. Further, the following embodiments do not limit the invention according to the claims, but include all combinations of characteristic configurations described in the embodiments.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same portions are denoted by the same reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

FIG. 1 is a cross-sectional view showing an example of a Low-High doping type MOSFET 1 as a semiconductor device according to an embodiment of the present invention. A top view of the MOSFET 1 is equivalent to the conventional Low-High doping type MOSFET 200 shown in FIG. 6A, and FIG. 1 corresponds to a cross-sectional view taken along line YY ′ in FIG. The XX ′ sectional view of the MOSFET 1 is equivalent to the XX ′ sectional view of the conventional MOSFET 200 shown in FIG.
As shown in FIG. 1, the MOSFET 1 includes a silicon substrate 11 as a semiconductor substrate, an element separator 14 formed in the element isolation region a <b> 1, and an element formation region a <b> 2 separated by the element separator 14 of the silicon substrate 11. A high impurity concentration layer 15 as a first impurity diffusion layer formed in contact with the element separator 14 and diffused with impurities of the first conductivity type, and more than the end of the high impurity concentration layer 15 on the high impurity concentration layer 15 The impurity diffusion prevention layer 16 formed by epitaxial growth on the inside and the first conductivity type impurity formed by epitaxial growth are diffused only on the impurity diffusion prevention layer 16, so that the low impurity concentration is lower than that of the high impurity concentration layer 15. An episilicon layer 17 as a second impurity diffusion layer formed of a silicon layer having a concentration, an impurity diffusion prevention layer 16 and an episilicon layer 17; Insulating side wall 7 formed on the high impurity concentration layer 15 between the child isolator 14 and the impurity diffusion preventing layer 16, the episilicon layer 17, and the element isolator 14, and only the episilicon layer 17. A gate insulating film 18 formed thereon, and a gate electrode 19 formed in a region including the gate insulating film 18 and the element separator 14.

  As shown in FIG. 1, the stacked body of the impurity diffusion preventing layer 16 and the episilicon layer 17 is formed only on the high impurity concentration layer 15, and the stacked body of the impurity diffusion preventing layer 16 and the episilicon layer 17 An insulating sidewall 13a is formed between and in contact with the element separator 14. That is, a region on the high impurity concentration layer 15 having a certain thickness near the interface between the side surface of the element isolation 14 and the silicon substrate 11 and having a certain width from the interface between the element isolation 14 and the silicon substrate 11 is formed. A covering insulator side wall 13a is disposed. The insulator side wall 13a formed in the vicinity of the interface between the element separator 14 and the silicon substrate 11 acts as an impurity diffusion prevention layer, and is given in a subsequent process such as a CMOS process using the MOSFET 1. Impurity diffusion due to heat is inhibited by the impurity diffusion preventing layer 16 and the insulator sidewall 13a. Therefore, impurity diffusion can be sufficiently prevented by the impurity diffusion preventing layer 16 and the insulator sidewall 13a in the vicinity of the interface between the element separator 14 and the silicon substrate 11.

Next, a method for manufacturing MOSFET 1 will be described.
2 and 3 are cross-sectional views showing an example of the manufacturing process of the MOSFET 1.
First, as shown in FIG. 2A, a mask layer 12 for forming an element isolator is formed of, for example, silicon nitride in the element formation region a2 of the silicon substrate 11. At this time, the mask layer 12 is formed so as to be inside the end portion of the element formation region a2. Next, as shown in FIG. 2B, an insulating film 13 for forming a sidewall is formed on the silicon substrate 11 so as to cover the mask layer 12. The insulating film 13 has a sufficient selectivity with respect to the silicon substrate 11 in the subsequent process of etching the element isolation region, and the selectivity with the mask layer 12 in the mask layer removal process after the element isolation body is formed. A film that can be sufficiently removed, for example, silicon oxide is used.

Next, as shown in FIG. 2C, the insulating film 13 on the element isolation region is removed by anisotropic etching or the like. As a result, the insulating film 13 remains only on the side surface of the mask layer 12. That is, the insulator sidewall 13 a is formed on the side surface of the mask layer 12.
Next, as shown in FIG. 2D, the silicon substrate 11 is etched using the mask layer 12 and the insulator sidewalls 13a as masks to form trenches 11a. Next, as shown in FIG. 2E, an insulator such as silicon oxide is buried in the trench 11a, and then planarized by CMP (chemical mechanical polishing) to form an element isolation body 14. .
Further, as shown in FIG. 2F, the mask layer 12 for forming an element isolation body is removed.

  Next, as shown in FIG. 3A, ion implantation is performed on the element formation region a2 of the silicon substrate 11 after the mask layer 12 is removed to form a high impurity concentration layer 15 for adjusting the threshold voltage Vth. Thereafter, as shown in FIG. 3B, for example, an Si—C layer is selectively grown only in the element formation region on the silicon substrate 11 to form the impurity diffusion preventing layer 16. Further, an Si layer is epitaxially grown on the impurity diffusion preventing layer 16 to form an epitaxial silicon layer 17 serving as a low impurity concentration channel portion. At this time, since the insulator sidewall 13a is formed, the side surfaces of the impurity diffusion prevention layer 16 and the epitaxial silicon layer 17 that are epitaxially grown are in contact with the insulator sidewall 13a.

  In addition, since the Si—C layer is epitaxially grown in the region surrounded by the insulator sidewall 13a formed of silicon oxide and the silicon substrate 11, the impurity diffusion prevention layer 16 is formed. It is easy to grow evenly in the thickness direction, and it is easy to grow uniformly in close contact with the insulator side wall 13a. Similarly, the epitaxial silicon layer 17 is also likely to grow uniformly in the thickness direction, and is also likely to grow uniformly in close contact with the insulator sidewall 13a. That is, as the insulator sidewall 13a, the semiconductor substrate (silicon substrate 11), the impurity diffusion prevention layer 16, and the low concentration impurity diffusion layer (episilicon layer 17), the impurity diffusion prevention layer 16 formed by epitaxial growth and the low concentration impurity diffusion layer 16 are formed. By using a material that allows the impurity diffusion layer to easily grow uniformly in the thickness direction and to grow in close contact with the insulator sidewall 13a, the impurity diffusion layer has a uniform thickness and is in close contact with the insulator sidewall 13a. This is advantageous in obtaining the impurity diffusion preventing layer 16 and the low-concentration impurity diffusion layer.

  Here, an insulator sidewall 13a formed of silicon oxide, a silicon substrate 11, an impurity diffusion prevention layer 16 formed of a Si-C layer, and a low concentration impurity diffusion layer formed of a Si layer are applied. Although the case is described, the present invention is not limited to this. As shown in FIG. 3A, the insulator sidewall 13a can selectively remove the mask layer 12, and the semiconductor substrate (silicon substrate 11), the impurity diffusion prevention layer 16, and the low concentration impurity diffusion layer (episilicon layer 17). As long as it is formed of a material that can be insulated. The impurity diffusion preventing layer 16 may be formed of a material that can prevent impurity diffusion from the semiconductor substrate (silicon substrate 11). The low-concentration impurity diffusion layer (episilicon layer 17) only needs to be formed of a material that can provide the mobility necessary for FET channel formation.

  As a result of forming the epi silicon layer 17 and the impurity diffusion prevention layer 16 by such a procedure, it is possible to prevent the epi silicon layer 17 and the impurity diffusion prevention layer 16 from being thinned in the vicinity of the element separator 14. For this reason, the impurity diffusion preventing layer 16 can sufficiently prevent the diffusion of impurities into the episilicon layer 17 even at the end portion, and can sufficiently exhibit the function as the impurity diffusion preventing layer. Furthermore, since the insulator side wall 13a is provided between the element separator 14 and the impurity diffusion preventing layer 16, impurity diffusion can be reliably prevented even in the vicinity of the end of the element separator. A sufficient low-high doping type impurity distribution can be realized.

Next, as shown in FIG. 3C, a gate insulating film 18 is formed on the epitaxial silicon layer 17, and then the gate insulating film 18 and the element separator 14 are covered as shown in FIG. Then, the gate electrode 19 is formed.
The low-high doping type MOSFET 1 is completed through ion implantation into the extension region and ion implantation into the source region and the drain region to be the source electrode and the drain electrode.
When the impurity diffusion preventing layer 16 and the episilicon layer 17 are epitaxially grown or when ion implantation or the like is performed, a mask layer or the like is formed in a region other than the target region.

The MOSFET 1 formed in this manner can sufficiently obtain a low-high doping type impurity distribution even in the vicinity of the end portion of the element separator 14.
In the above-described embodiment, the case where both the epitaxial silicon layer 17 and the impurity diffusion prevention layer 16 are epitaxially grown so as to be in close contact with the insulator sidewall 13a has been described. Even when formed so as to be in close contact with the silicon substrate 11, impurity diffusion can be suppressed.
As mentioned above, although embodiment of this invention was described, the said embodiment has illustrated the apparatus and method for materializing the technical idea of this invention, and the technical idea of this invention is a component. It does not specify the material, shape, structure, arrangement, etc. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

1 Low-High doping type MOSFET
DESCRIPTION OF SYMBOLS 11 Silicon substrate 12 Mask layer 13 Insulating film 13a Insulator side wall 14 Element isolator 15 High impurity concentration layer 16 Impurity diffusion prevention layer 17 Epi silicon layer 18 Gate insulating film 19 Gate electrode

Claims (6)

An element isolation body formed in an element isolation region of a semiconductor substrate;
A first impurity diffusion layer provided in contact with the element separator in the element formation region of the semiconductor substrate and having impurities diffused;
An impurity diffusion preventing layer laminated on the surface of the first impurity diffusion layer;
A second impurity diffusion layered on the surface of the impurity diffusion prevention layer so as to be included in the impurity diffusion prevention layer in a top view, and having the same conductivity type as the first impurity diffusion layer diffused at a lower concentration Layers,
An insulating sidewall formed on the surface of the first impurity diffusion layer and provided between and in contact with the element isolation body and the impurity diffusion prevention layer;
A gate insulating film laminated on the surface of the second impurity diffusion layer;
A gate electrode provided to cover the element separator, the sidewall and the gate insulating film;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the impurity diffusion preventing layer has a uniform thickness.   The semiconductor device according to claim 1, wherein the second impurity diffusion layer has a uniform thickness. A mask layer forming step of forming a mask layer inside the element forming region of the semiconductor substrate;
A sidewall forming step of forming a sidewall covering the side surface of the mask layer from the side surface to the end of the element formation region;
Forming a trench in the element isolation region of the semiconductor substrate; and
An element isolation formation step for forming an element isolation in contact with the inner surface of the trench and the side surface of the sidewall;
The mask layer is removed so that the sidewall remains after the element separator is formed, and a first conductivity type impurity is ion-implanted into the element formation region exposed by removing the mask layer. A first impurity diffusion layer forming step of forming one impurity diffusion layer;
An impurity diffusion prevention layer forming step of forming, on the surface of the first impurity diffusion layer, an impurity diffusion prevention layer whose side surface is in contact with the sidewall by epitaxial growth;
A low impurity concentration layer forming step of forming, on the surface of the impurity diffusion preventing layer, a second impurity diffusion layer in which the impurity of the first conductivity type is diffused at a lower concentration than the first impurity diffusion layer by epitaxial growth;
Forming a gate insulating film on the surface of the second impurity diffusion layer; and
Forming a gate electrode so as to cover a surface of the element separator, the sidewall and the gate insulating film; and
A method for manufacturing a semiconductor device comprising:   5. The method of manufacturing a semiconductor device according to claim 4, wherein, in the sidewall forming step, the sidewall is formed using a material having a high selectivity with respect to a material of the semiconductor substrate and a material of the mask layer.   The method for manufacturing a semiconductor device according to claim 4, wherein in the element isolation formation step, an insulator is embedded in the trench so as to be in contact with a side surface of the sidewall.

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