JP2018067615A - Solid-state imaging device, method of manufacturing the same, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging device in which carriers generated by irradiating light to a peripheral region are inhibited from flowing into a photoelectric conversion region to reduce variations in photoelectric conversion characteristics or to improve disturbance noise immunity.SOLUTION: This solid-state imaging device includes: a first P-type semiconductor layer; a plurality of N type impurity regions arranged in the first P type semiconductor layer and constituting a plurality of photoelectric conversion regions together with the first P type semiconductor layer; an N-type semiconductor layer surrounding side surfaces and a bottom surface of the first P-type semiconductor layer; and a second P type semiconductor layer surrounding the N type semiconductor layer in plan view.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof. Furthermore, the present invention relates to an electronic device using such a solid-state imaging device.

  Conventionally, CCDs have been the mainstream as solid-state imaging devices. However, in recent years, CMOS sensors that can be driven at a low voltage and can also be embedded with peripheral circuits have been remarkably developed. The CMOS sensor has been developed into a device that surpasses CCDs in terms of mass, with countermeasures by manufacturing processes such as complete transfer technology and dark current prevention structure and measures such as CDS (correlated double sampling). doing. The factor of the CMOS sensor leap is that the image quality has been greatly improved. One of them is the improvement of charge transfer technology.

  As a related technique, Patent Document 1 discloses a solid-state imaging device having a high spatial resolution by arranging a plurality of semiconductor elements that can realize complete transfer of signal charges as pixels. The semiconductor element includes a first conductive type semiconductor region, a second conductive type light receiving surface embedded region that is embedded in the upper portion of the semiconductor region, and a light receiving surface embedded in the upper portion of the semiconductor region. A charge accumulation region of the second conductivity type that accumulates the signal charge generated by the buried region, a charge readout region that accepts the signal charge accumulated in the charge accumulation region, and a signal from the light receiving surface buried region to the charge accumulation region First potential control means for transferring charges, and second potential control means for transferring signal charges from the charge storage region to the charge readout region.

Japanese Patent Laying-Open No. 2008-103647 (paragraphs 0006-0007, FIG. 3)

  FIG. 3 of Patent Document 1 shows a P-type semiconductor substrate 1 and a light-receiving surface buried region (light-receiving cathode region) 11 a that is an N-type impurity region disposed on the semiconductor substrate 1. A photodiode D1 is configured by the light receiving cathode region 11a and the semiconductor substrate 1 (anode region) immediately below the light receiving cathode region 11a. Thus, by forming the photodiode D1 on the P-type semiconductor substrate 1, it becomes easy to mount peripheral circuits including CMOS transistors on the same substrate.

  However, when light is irradiated to the photodiode, the region other than the photodiode (hereinafter also referred to as a peripheral region) is irradiated with light, and positive carriers and negative carriers are generated in the peripheral region. . Negative carriers (electrons) generated in the peripheral region of the P-type semiconductor substrate may flow into the anode region of the photodiode and affect the original photoelectric conversion characteristics of the photodiode.

  For example, the sensitivity of the photodiode varies depending on the planar position of the photodiode disposed on the semiconductor substrate, or the photodiode becomes vulnerable to disturbance noise. As a result, there is a problem that variation in photoelectric conversion characteristics of the photodiodes increases or disturbance noise resistance decreases, and desired characteristics of the solid-state imaging device cannot be obtained.

  Some aspects of the present invention suppress the inflow of carriers generated by irradiating light to the peripheral region into the photoelectric conversion region, reduce variations in photoelectric conversion characteristics, or improve disturbance noise resistance. Related to providing a solid-state imaging device. Further, some aspects of the present invention relate to providing an electronic device or the like using such a solid-state imaging device.

  The solid-state imaging device according to the first aspect of the present invention is disposed in a first P-type semiconductor layer and the first P-type semiconductor layer, and forms a plurality of photoelectric conversion regions together with the first P-type semiconductor layer. A plurality of N-type impurity regions; an N-type semiconductor layer surrounding a side surface and a bottom surface of the first P-type semiconductor layer; and a second P-type semiconductor layer surrounding the N-type semiconductor layer in plan view. In the present application, the semiconductor layer refers to a semiconductor substrate, a well formed in the semiconductor substrate, or an epitaxial layer formed on the semiconductor substrate.

  According to the first aspect of the present invention, since the N-type semiconductor layer is provided so as to surround the side surface and the bottom surface of the first P-type semiconductor layer constituting the plurality of photoelectric conversion regions, the first P-type The semiconductor layer is separated from the second P-type semiconductor layer by the N-type semiconductor layer. Thereby, it is possible to reduce the variation in photoelectric conversion characteristics or improve the disturbance noise resistance by suppressing the carriers generated by light irradiation to the second P-type semiconductor layer from flowing into the photoelectric conversion region. Can do.

  Here, the solid-state imaging device may further include a wiring for supplying a power supply potential on the high potential side to the N-type semiconductor layer. Thereby, since negative carriers (electrons) generated by irradiating light to the peripheral region are captured by the N-type semiconductor layer, inflow of carriers to the photoelectric conversion region can be further suppressed.

  In the above, the N-type semiconductor layer may have an impurity concentration that decreases according to the depth from the main surface. Since such a concentration distribution can be easily realized by using a normal semiconductor manufacturing process, it is possible to reduce the cost of the solid-state imaging device and to share the manufacturing process with peripheral circuits.

  Alternatively, the N-type semiconductor layer has a first impurity concentration in a region surrounding the side surface of the first P-type semiconductor layer, and is higher than the first impurity concentration in a region surrounding the bottom surface of the first P-type semiconductor layer. The second impurity concentration may be high. Thereby, the potential of the N-type semiconductor layer surrounding the bottom surface of the first P-type semiconductor layer constituting the plurality of photoelectric conversion regions is increased, and negative carriers (electrons) generated by irradiating the peripheral region with light are captured. Can be made easier.

  An electronic apparatus according to a second aspect of the present invention includes any one of the solid-state imaging devices described above. According to the second aspect of the present invention, the image quality of image data obtained by imaging a subject is improved by using a solid-state imaging device with reduced variations in photoelectric conversion characteristics or improved resistance to disturbance noise. An electronic device can be provided.

  The solid-state imaging device manufacturing method according to the third aspect of the present invention includes a step (a) of preparing a P-type semiconductor substrate, a step (b) of forming an N-type semiconductor layer on the semiconductor substrate, and an N-type semiconductor. A step (c) of forming a P-type semiconductor layer in the layer so that the N-type semiconductor layer surrounds the side surface and the bottom surface of the P-type semiconductor layer; And (d) forming a plurality of N-type impurity regions constituting the conversion region.

  According to the third aspect of the present invention, an N-type semiconductor layer is formed on a P-type semiconductor substrate, and a P-type semiconductor layer is formed on the N-type semiconductor layer, thereby forming a plurality of photoelectric conversion regions. The semiconductor layer is separated from the P-type region of the semiconductor substrate by the N-type semiconductor layer. As a result, a solid generated by suppressing the inflow of carriers generated by irradiating light onto the P-type region of the semiconductor substrate into the photoelectric conversion region, reducing variations in photoelectric conversion characteristics, or improving disturbance noise resistance. An imaging device can be provided.

  Here, the step (b) may include forming an N-type semiconductor layer by implanting and diffusing an N-type impurity in a partial region of the semiconductor substrate. Since such a process is included in a normal semiconductor manufacturing process, the cost of the solid-state imaging device can be reduced, and the manufacturing process can be shared with peripheral circuits.

  The solid-state imaging device manufacturing method according to the fourth aspect of the present invention includes a step (a) of preparing a P-type semiconductor substrate, a step (b) of forming a first N-type semiconductor layer on the semiconductor substrate, A step (c) of forming a P-type semiconductor layer on the semiconductor substrate on which the first N-type semiconductor layer is formed; and a second N-type semiconductor layer reaching the first N-type semiconductor layer on the P-type semiconductor layer. By forming, the P-type semiconductor layer is separated into the first P-type semiconductor layer and the second P-type semiconductor layer, and the first and second N-type semiconductor layers are formed of the first P-type semiconductor layer. A step (d) of enclosing the side surface and the bottom surface, and a step of forming a plurality of N-type impurity regions constituting a plurality of photoelectric conversion regions together with the first P-type semiconductor layer in the first P-type semiconductor layer. (E).

  According to the fourth aspect of the present invention, the P-type semiconductor layer is formed on the P-type semiconductor substrate on which the first N-type semiconductor layer is formed, and the first N-type semiconductor layer is formed on the P-type semiconductor layer. By forming the second N-type semiconductor layer reaching the first P-type semiconductor layer, the first P-type semiconductor layer constituting the plurality of photoelectric conversion regions becomes the second P-type semiconductor layer by the first and second N-type semiconductor layers. Separated from. As a result, the carriers generated by irradiating the second P-type semiconductor layer with light are suppressed from flowing into the photoelectric conversion region, and variations in photoelectric conversion characteristics are reduced, or disturbance noise resistance is improved. A solid-state imaging device can be provided.

  Here, the step (b) includes injecting an N-type impurity into a partial region of the semiconductor substrate to form a buried layer, and the step (c) is performed on the semiconductor substrate on which the buried layer is formed. Forming a plug diffusion layer reaching the buried layer by injecting and diffusing an N type impurity in a partial region of the epitaxial layer, including forming a P type epitaxial layer; May be included.

  In that case, it is possible to form a buried layer having a high impurity concentration in the semiconductor substrate prior to forming the epitaxial layer on the semiconductor substrate. Accordingly, the potential of the buried layer surrounding the bottom surface of the first P-type semiconductor layer constituting the plurality of photoelectric conversion regions is increased, and negative carriers (electrons) generated by irradiating the peripheral region with light are easily captured. can do.

The perspective view which shows the structural example of a CIS module. The block diagram which shows the structural example of the scanner apparatus using a CIS module. The block diagram which shows the structural example of an image sensor chip. FIG. 6 is a circuit diagram showing an equivalent circuit of a pixel portion and a readout circuit portion for one pixel. 1 is a plan view of a part of a solid-state imaging device according to a first embodiment of the present invention. Sectional drawing in VI-VI shown in FIG. FIG. 6 is a process cross-sectional view of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 6 is a process cross-sectional view of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 6 is a process cross-sectional view of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 6 is a process cross-sectional view of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 6 is a process cross-sectional view of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 6 is a process cross-sectional view of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 6 is a plan view of a part of a solid-state imaging device according to a second embodiment of the present invention. Sectional drawing in XIV-XIV shown in FIG. Process sectional drawing of the manufacturing method of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. Process sectional drawing of the manufacturing method of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. Process sectional drawing of the manufacturing method of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. Process sectional drawing of the manufacturing method of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. Process sectional drawing of the manufacturing method of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. Process sectional drawing of the manufacturing method of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. Process sectional drawing of the manufacturing method of the solid-state imaging device which concerns on the 2nd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
<Electronic equipment>
In the following, a CIS scanner using a contact image sensor (CIS) module including a solid-state imaging device (image sensor chip) according to any embodiment of the present invention as an electronic apparatus according to an embodiment of the present invention. The apparatus will be described.

  FIG. 1 is a perspective view showing a configuration example of a CIS module, and FIG. 2 is a block diagram showing a configuration example of a scanner device using the CIS module shown in FIG. As shown in FIG. 1, the CIS module 10 includes a light guide 11 that irradiates light on the document 1, a lens array 12 that forms an image of reflected light from the document 1, and a photodiode that is disposed at the imaging position. And an image sensor 13 having a light receiving element.

  Referring to FIGS. 1 and 2, the CIS module 10 includes a light source 14 that generates light incident on an end of the light guide 11. In the case of a color scanner, the light source 14 includes, for example, red (R), green (G), and blue (B) LEDs. The three color LEDs are pulse-lit in a time division manner. The light guide 11 guides the light so that the light generated by the light source 14 is applied to the area of the document 1 along the main scanning direction A.

  The lens array 12 is composed of, for example, a rod lens array. The image sensor 13 has a plurality of pixels along the main scanning direction A, and moves in the sub scanning direction B together with the light guide 11 and the lens array 12.

  As shown in FIG. 2, the image sensor 13 may be configured by connecting a plurality of image sensor chips 20 in series. The CIS module 10 movable in the sub-scanning direction B is connected to a main substrate 16 fixed to the scanner device via a flexible wiring 15. On the main board 16, a system-on-chip (SoC) 17, an analog front end (AFE) 18, and a power supply circuit 19 are mounted.

  The system on chip 17 supplies a control signal, a clock signal, and the like to the CIS module 10. Pixel signals generated by the CIS module 10 are supplied to the analog front end 18. The analog front end 18 performs analog / digital conversion on the analog pixel signal and outputs digital pixel data to the system-on-chip 17.

  The power supply circuit 19 supplies a power supply voltage to the system-on-chip 17 and the analog front end 18 and supplies a power supply voltage, a reference voltage, and the like to the CIS module 10. Note that the analog front end 18, a part of the power supply circuit 19, or a light source driver may be mounted on the CIS module 10.

<Solid-state imaging device>
FIG. 3 is a block diagram illustrating a configuration example of an image sensor chip that is a solid-state imaging device according to any embodiment of the present invention. As shown in FIG. 3, the image sensor chip 20 includes a pixel unit 30, a readout circuit unit 40, and a control circuit unit 50, and may further include capacitors 61 to 64.

  In the pixel unit 30, light receiving elements (for example, photodiodes) are arranged in a plurality of pixels. The readout circuit unit 40 converts the signal charge output from the pixel unit 30 into a signal voltage and reads out pixel information. The control circuit unit 50 performs control for generating a pixel signal based on the output voltage of the readout circuit unit 40. For example, the control circuit unit 50 includes a correlated double sampling (CDS) circuit 51, an output circuit 52, and a logic circuit 53.

  The correlated double sampling circuit 51 performs correlated double sampling processing on the output voltage of the readout circuit unit 40. That is, the correlated double sampling circuit 51 samples the voltage immediately after the reset and the voltage after the exposure, and performs a difference process between them to cancel the reset noise and generate an output voltage corresponding to the light intensity. To do. The output circuit 52 generates and outputs a pixel signal based on the output voltage of the correlated double sampling circuit 51. A control signal, a clock signal, and the like are supplied to the logic circuit 53 from the system-on-chip 17 illustrated in FIG.

  The capacitor 61 is connected between the high-potential-side power supply potential wiring and the low-potential-side power supply potential wiring arranged in the first region AR1 of the image sensor chip 20, and stabilizes the power supply voltage. Further, the capacitors 62 to 64 are connected between the high-potential-side power supply potential wiring and the low-potential-side power supply potential wiring arranged in the second region AR2 of the image sensor chip 20, and supply the power supply voltage. Stabilize.

<Pixel part and readout circuit part>
FIG. 4 is a circuit diagram showing an equivalent circuit of a pixel portion and a readout circuit portion for one pixel. For example, a photodiode PD is disposed in one pixel of the pixel unit 30 illustrated in FIG. 3 as a light receiving element having a photoelectric conversion function. The photodiode PD generates and accumulates signal charges corresponding to the intensity of incident light.

  In order to read out signal charges from the photodiode PD, the readout circuit section 40 shown in FIG. 3 includes a front-stage transfer gate TG1, a charge holding capacitor C1, a rear-stage transfer gate TG2, and a charge holding capacitor C2. Further, the read circuit section 40 includes a transistor (also referred to as a buffer transistor in this application) QN1, a reset transistor QN2, and a selection transistor QN3 that constitute a read buffer amplifier. In the line sensor, when an analog shift register is provided in the final stage of the readout circuit unit 40, the selection transistor QN3 can be included in the analog shift register.

  Here, the charge holding capacitor C1 is formed of a storage diode having an anode formed of a P-type semiconductor layer and a cathode formed of an N-type charge holding region CH disposed in the P-type semiconductor layer. The charge retention capacitor C2 includes a P-type semiconductor layer and an N-type floating diffusion region (floating diffusion) FD disposed in the P-type semiconductor layer.

  The front transfer gate TG1 constitutes a part of an N-channel MOS transistor having the cathode of the photodiode PD and the cathode of the storage diode as the source and drain. Further, the rear transfer gate TG2 constitutes a part of an N channel MOS transistor having the source and drain of the storage diode cathode and the floating diffusion region FD.

  The photodiode PD, the front-stage transfer gate TG1, and the rear-stage transfer gate TG2 are connected in series between the low-potential-side power supply potential VSS line and the gate electrode of the buffer transistor QN1. The drain of the buffer transistor QN1 is connected to the wiring of the power supply potential VDD on the high potential side. In the following, it is assumed that the power supply potential VSS is the ground potential 0V.

  The reset transistor QN2 has a drain connected to the wiring of the power supply potential VDD, a source connected to the gate electrode of the buffer transistor QN1, and a gate electrode to which the reset signal RST is supplied. The selection transistor QN3 has a drain connected to the source of the buffer transistor QN1, a source connected to the output terminal of the readout circuit unit 40, and a gate electrode to which the selection signal SEL is supplied.

  The pre-stage transfer gate TG1 transfers the signal charge accumulated in the photodiode PD to the charge holding capacitor C1 when the control signal Tx1 is activated to a high level. The charge holding capacitor C1 holds the signal charge transferred by the previous transfer gate TG1. After the control signal Tx1 is deactivated to the low level, the control signal Tx2 is activated to the high level.

  The rear transfer gate TG2 transfers the signal charge held in the charge holding capacitor C1 to the charge holding capacitor C2 when the control signal Tx2 is activated to a high level. The charge holding capacitor C2 holds the signal charge transferred by the subsequent transfer gate TG2, and converts the signal charge into a signal voltage.

  The reset transistor QN2 resets the gate potential of the buffer transistor QN1 to an initial state potential (for example, the power supply potential VDD) when the reset signal RST is activated to a high level. When the reset is released, the buffer transistor QN1 outputs an output voltage corresponding to the signal voltage across the charge holding capacitor C2 from the source.

  The selection transistor QN3 selects the output voltage of the buffer transistor QN1 when the selection signal SEL is activated to a high level. As a result, the output voltage of the buffer transistor QN1 is output to the output terminal of the read circuit section 40 via the selection transistor QN3 and becomes the output voltage Vs.

  Here, the transfer of charges between the light receiving element such as the photodiode PD shown in FIG. 4 and the charge holding capacitor C2 may be controlled by one transfer gate, and in this case, the front transfer gate TG1 and the rear transfer One of the gates TG2 and the charge holding capacitor C1 are omitted. Hereinafter, as an example, a case where the transfer of charges between the light receiving element and the charge holding capacitor C2 is controlled by one transfer gate will be described.

<First Embodiment>
FIG. 5 is a plan view of a part of the solid-state imaging device according to the first embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG. As shown in FIGS. 5 and 6, this solid-state imaging device includes a P-type semiconductor substrate 100, an N-well (N ⁻⁻ ) 110 that is an N-type semiconductor layer disposed on the semiconductor substrate 100, and an N-well 110. And a P-well (P ⁻ ) 120 that is a first P-type semiconductor layer.

Thus, a triple well structure is formed, and the N well 110 surrounds the side surface and the bottom surface of the P well 120. Here, the P-type region (P ⁻ ) of the semiconductor substrate 100 corresponds to a second P-type semiconductor layer surrounding the N well 110 in plan view. In the present application, the “plan view” means that each part is seen through from a direction perpendicular to the main surface of the semiconductor substrate 100.

The solid-state imaging device further includes a plurality of N-type impurity regions (N ⁻⁻ ) 131 and a plurality of floating diffusion regions (N ⁺ ) 132 disposed in the P well 120. FIG. 5 shows four N-type impurity regions 131 and four floating diffusion regions 132 as an example. The plurality of N-type impurity regions 131 together with the P well 120 constitute a plurality of photoelectric conversion regions. That is, each photodiode PD has an anode composed of a P well 120 and a cathode composed of an N-type impurity region 131.

As shown in FIG. 6, in the N-type impurity region 131, an N-type impurity region (N ⁻ ) 131a having a relatively higher impurity concentration than the surroundings is arranged in a part of the region near the floating diffusion region 132. May be. Further, a high-concentration P-type impurity region (pinning layer) 141 may be disposed on the N-type impurity region 131. When the pinning layer is provided, dark current generated in the N-type impurity region 131 can be reduced.

  In addition, the solid-state imaging device includes a transfer gate TG having a gate electrode 150 disposed via a gate insulating film on a region between the photodiode PD and the floating diffusion region 132 in the semiconductor substrate 100. The gate electrode 150 may be made of, for example, polysilicon having conductivity doped with impurities, and may overlap part of the N-type impurity region 131 and the floating diffusion region 132 in plan view.

  Further, the solid-state imaging device includes an interlayer insulating film 160 disposed on the semiconductor substrate 100, contact plugs 171 to 173 disposed in the contact holes of the interlayer insulating film 160, and wiring disposed on the interlayer insulating film 160. Layer wirings 181 to 183 are provided. Note that two or more interlayer insulating films and wiring layers may be used as necessary. Further, a light shielding film that shields the P well 120 around the photodiode PD may be disposed on any of the interlayer insulating films. This light shielding film may shield light up to the N well 110 around the P well 120. The light shielding film is preferably formed of a metal layer.

The interlayer insulating film 160 is made of, for example, BPSG (Boron Phosphorus Silicon Glass) or a silicon oxide film (SiO ₂ ). The contact plugs 171 to 173 include, for example, tungsten (W), aluminum (Al), copper (Cu), or the like. The wirings 181 to 183 include, for example, aluminum (Al) or copper (Cu).

In the P-type region of the semiconductor substrate 100, a P-type contact region (P ⁺ ) 100 a is disposed along the periphery of the N well 110 in plan view. The contact region 100a is electrically connected to the wiring of the power supply potential VSS via the contact plug 171 and the wiring 181. As a result, the power supply potential VSS is supplied to the P-type region of the semiconductor substrate 100.

In the N well 110, an N-type contact region (N ⁺ ) 110a is arranged along the periphery of the P well 120 in plan view. The contact region 110a is electrically connected to the wiring of the power supply potential VDD through the contact plug 172 and the wiring 182. As a result, the power supply potential VDD is supplied to the N well 110.

  In the floating diffusion region 132, a high-concentration N-type contact region 132a is disposed. The contact region 132a is connected to the gate electrode of the buffer transistor QN1 shown in FIG. 4 via the contact plug 173 and the wiring 183. The buffer transistor QN1 generates an output voltage based on the signal charge transferred from the cathode of the photodiode PD to the floating diffusion region 132 by the transfer gate TG.

  In general, when light is radiated to the photodiode PD, the region other than the photodiode PD (peripheral region) is also irradiated with light, and positive carriers (marked by + in FIG. 6) and negative carriers in the peripheral region. (-Mark in FIG. 6) occurs. Negative carriers (electrons) generated in the peripheral region of the P-type semiconductor substrate 100 may flow into the anode region of the photodiode PD and affect the original photoelectric conversion characteristics of the photodiode. As a result, the variation in the photoelectric conversion characteristics of the photodiode PD increases, or disturbance noise resistance decreases.

  On the other hand, according to the present embodiment, since the N well 110 is provided so as to surround the side surface and the bottom surface of the P well 120 constituting the plurality of photoelectric conversion regions, the P well 120 is formed on the semiconductor substrate by the N well 110. Separated from 100 P-type regions. Accordingly, it is possible to suppress the carriers generated by irradiating light to the P-type region of the semiconductor substrate 100 from flowing into the photoelectric conversion region, thereby reducing variation in photoelectric conversion characteristics, or improving disturbance noise resistance. Can do.

  In addition, the solid-state imaging device according to the present embodiment includes a wiring 182 that supplies the power potential VDD on the high potential side to the N well 110. As a result, negative carriers (electrons) generated by irradiating the peripheral region with light are captured by the N well 110, so that the inflow of carriers to the photoelectric conversion region can be further suppressed.

Furthermore, in the present embodiment, the N well 110 has an impurity concentration that decreases according to the depth from the main surface (the upper surface in the drawing). Since such a concentration distribution can be easily realized by using a normal semiconductor manufacturing process, it is possible to reduce the cost of the solid-state imaging device and to share the manufacturing process with peripheral circuits. For example, the N well 110 has an impurity concentration of about 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ³ .

<Manufacturing method 1>
Next, a method for manufacturing the solid-state imaging device shown in FIGS. 5 and 6 will be described.
7 to 12 are process cross-sectional views for explaining the manufacturing method of the solid-state imaging device according to the first embodiment of the present invention. First, a P-type semiconductor substrate 100 is prepared. As the semiconductor substrate 100, for example, a silicon (Si) substrate containing a P-type impurity such as boron (B) is used.

Next, as shown in FIG. 7, an N well (N ⁻⁻ ) 110 that is an N-type semiconductor layer is formed in the semiconductor substrate 100. For example, a thermal oxide film serving as a transmission film at the time of ion implantation is formed on the main surface of the semiconductor substrate 100. Thereafter, N-type impurity ions such as phosphorus (P) or arsenic (As) are implanted into a partial region of the semiconductor substrate 100 using a photoresist formed by photolithography as a mask, and heat treatment is performed to remove the impurities. By diffusing, an N well 110 is formed in the semiconductor substrate 100.

Next, as shown in FIG. 8, a P well (P ⁻ ) 120 that is a P type semiconductor layer is formed in the N well 110. Thereby, a triple well structure is formed, and the N well 110 surrounds the side surface and the bottom surface of the P well 120. For example, by using a photoresist formed by a photolithography method as a mask, P-type impurity ions such as boron (B) are implanted into a partial region of the N well 110, and heat treatment is performed to diffuse the impurities. A P well 120 is formed in the N well 110.

  Next, the photoresist is removed, and a plurality of N-type impurity regions 131 that form a plurality of photoelectric conversion regions together with the P well 120 are formed in the P well 120. For example, as shown in FIG. 9, a photoresist PH1 is formed by photolithography on the semiconductor substrate 100 in which the N well 110 and the P well 120 are formed. The photoresist PH1 has an opening in a region where a photodiode is formed.

Using the photoresist PH1 as a mask, N-type impurity ions (N ⁻⁻ ) are implanted into a partial region of the P-well 120 to diffuse the impurities, thereby forming an N-type impurity region (that forms the cathode of the photodiode). N ⁻⁻ ) 131 is formed in the P well 120. Furthermore, an N-type impurity region (N ⁻ ) 131a or a high-concentration P-type impurity region (pinning layer) 141 shown in FIG. 6 may be formed.

  Next, as shown in FIG. 10, the photoresist PH1 is removed, and a photoresist PH2 is formed by photolithography on the semiconductor substrate 100 on which the N-type impurity region 131 and the like are formed. The photoresist PH2 has an opening in a region where the floating diffusion region 132 is formed.

The floating diffusion region (N ⁺ ) 132 is formed in the P well 120 by implanting N-type impurity ions (N ⁺ ) into a partial region of the semiconductor substrate 100 using the photoresist PH2 as a mask.

  Next, after the photoresist PH2 is removed and the thermal oxide film used as a permeable film at the time of ion implantation is peeled off, an insulating film and a polysilicon film are sequentially formed on the semiconductor substrate 100. Further, the polysilicon film is patterned using a photoresist formed by photolithography as a mask. The insulating film may not be patterned.

  Thereby, as shown in FIG. 11, the gate electrode 150 of the transfer gate TG is formed on the semiconductor substrate 100 via the insulating film. At that time, the mutual positions may be adjusted so that the gate electrode 150 overlaps with part of the N-type impurity region 131 and the floating diffusion region 132 in plan view. Similarly, in other regions of the semiconductor substrate 100, gate electrodes of a plurality of MOS transistors including the buffer transistor QN1, the reset transistor QN2 (FIG. 4), and the like are formed.

Next, N-type impurity ions (N ⁺ ) are implanted into a partial region of the semiconductor substrate 100 using a photoresist formed by photolithography as a mask, as shown in FIG. A contact region (N ⁺ ) 110 a is formed in the N well 110. Similarly, in other regions of the semiconductor substrate 100, N-type impurity regions serving as sources and drains of a plurality of N-channel MOS transistors including the buffer transistor QN1, the reset transistor QN2 (FIG. 4), and the like are formed.

Next, the photoresist is removed, and P-type impurity ions are implanted into a partial region of the semiconductor substrate 100 using the photoresist newly formed by photolithography as a mask, as shown in FIG. , A P-type contact region (P ⁺ ) 100 a is formed in the P-type region (P ⁻ ) of the semiconductor substrate 100. Similarly, in other regions of the semiconductor substrate 100, P-type impurity regions serving as sources and drains of a plurality of P-channel MOS transistors are formed.

  Next, the photoresist is removed, and an interlayer insulating film 160 having a plurality of contact holes is formed on the semiconductor substrate 100 on which the gate electrode 150 and the like are formed, as shown in FIG. Further, a photoresist is formed on a part of the interlayer insulating film 160, and N-type impurity ions are implanted into a part of the floating diffusion region 132 using the interlayer insulating film 160 and the photoresist as a mask. An N-type contact region 132a having a concentration is formed.

  Next, contact plugs 171 to 173 electrically connected to the contact regions 100a, 110a, and 132a are formed in the contact holes of the interlayer insulating film 160. Further, wirings 181 to 183 electrically connected to the contact plugs 171 to 173 are formed on the interlayer insulating film 160. Note that two or more interlayer insulating films and wiring layers may be used as necessary.

  According to the present embodiment, the N well 110 is formed in the P-type semiconductor substrate 100, and the P well 120 is formed in the N well 110, whereby the P well 120 constituting a plurality of photoelectric conversion regions becomes the N well 110. Is separated from the P-type region of the semiconductor substrate 100. As a result, the carriers generated by irradiating light onto the P-type region of the semiconductor substrate 100 are prevented from flowing into the photoelectric conversion region, and variations in photoelectric conversion characteristics are reduced, or disturbance noise resistance is improved. A solid-state imaging device can be provided.

  In addition, since the process of forming the N well 110 in the semiconductor substrate 100 is included in a normal semiconductor manufacturing process, it is possible to reduce the cost of the solid-state imaging device and to share the manufacturing process with peripheral circuits. It is.

<Second Embodiment>
FIG. 13 is a plan view of a part of the solid-state imaging device according to the second embodiment of the present invention, and FIG. 14 is a cross-sectional view taken along the line XIV-XIV shown in FIG. As shown in FIGS. 13 and 14, the solid-state imaging device includes a P-type semiconductor substrate 100 and an N-type buried layer (N ⁺ ) 111 disposed on the semiconductor substrate 100.

  The solid-state imaging device also includes a P-type epitaxial layer 101 disposed by epitaxial growth on the semiconductor substrate 100 in which the buried layer 111 is disposed, and an N-type plug diffusion layer (N) 112 disposed in the epitaxial layer 101. And. The plug diffusion layer 112 reaches the buried layer 111 and surrounds a plurality of photoelectric conversion regions.

The plug diffusion layer 112 separates the P type epitaxial layer 101 into a first P type semiconductor layer (P ⁻ ) 121 and a second P type semiconductor layer (P ⁻ ) 122. Here, the buried layer 111 and the plug diffusion layer 112 correspond to an N-type semiconductor layer surrounding the side surface and the bottom surface of the first P-type semiconductor layer 121. The second P-type semiconductor layer 122 surrounds the N-type semiconductor layer in plan view.

Furthermore, the solid-state imaging device includes a plurality of N-type impurity regions (N ⁻⁻ ) 131 and a plurality of floating diffusion regions (N ⁺ ) 132 arranged in the first P-type semiconductor layer 121. FIG. 13 shows four N-type impurity regions 131 and four floating diffusion regions 132 as an example. The plurality of N-type impurity regions 131 together with the first P-type semiconductor layer 121 constitute a plurality of photoelectric conversion regions. That is, each photodiode PD has an anode composed of the first P-type semiconductor layer 121 and a cathode composed of the N-type impurity region 131.

As shown in FIG. 14, in the N-type impurity region 131, an N-type impurity region (N ⁻ ) 131a having a relatively higher impurity concentration than the surroundings is arranged in a part of the region near the floating diffusion region 132. May be. Further, a high-concentration P-type impurity region (pinning layer) 141 may be disposed on the N-type impurity region 131. When the pinning layer is provided, dark current generated in the N-type impurity region 131 can be reduced.

  In addition, the solid-state imaging device includes a transfer gate TG having a gate electrode 150 disposed through a gate insulating film on a region between the photodiode PD and the floating diffusion region 132 in the epitaxial layer 101. The gate electrode 150 may be made of, for example, polysilicon having conductivity doped with impurities, and may overlap part of the N-type impurity region 131 and the floating diffusion region 132 in plan view.

  Further, the solid-state imaging device includes an interlayer insulating film 160 disposed on the epitaxial layer 101, contact plugs 171 to 173 disposed in the contact holes of the interlayer insulating film 160, and wiring disposed on the interlayer insulating film 160. Layer wirings 181 to 183 are provided. Note that two or more interlayer insulating films and wiring layers may be used as necessary. Further, a light shielding film that shields the first P-type semiconductor layer 121 around the photodiode PD may be disposed on any of the interlayer insulating films. This light shielding film may shield light up to the plug diffusion layer 112 around the first P-type semiconductor layer 121. The light shielding film is preferably formed of a metal layer.

In the second P-type semiconductor layer 122, a P-type contact region (P ⁺ ) 122a is disposed along the periphery of the plug diffusion layer 112 in plan view. The contact region 122a is electrically connected to the power supply potential VSS via the contact plug 171 and the wiring 181. As a result, the power supply potential VSS is supplied to the second P-type semiconductor layer 122 and the P-type region (P ⁻ ) of the semiconductor substrate 100.

In the plug diffusion layer 112, an N-type contact region (N ⁺ ) 112a is arranged along the periphery of the first P-type semiconductor layer 121 in plan view. The contact region 112a is electrically connected to the wiring of the power supply potential VDD through the contact plug 172 and the wiring 182. As a result, the power supply potential VDD is supplied to the plug diffusion layer 112 and the buried layer 111.

  In the floating diffusion region 132, a high-concentration N-type contact region 132a is disposed. The contact region 132a is connected to the gate electrode of the buffer transistor QN1 shown in FIG. 4 via the contact plug 173 and the wiring 183. The buffer transistor QN1 generates an output voltage based on the signal charge transferred from the cathode of the photodiode PD to the floating diffusion region 132 by the transfer gate TG.

  According to the present embodiment, the buried layer 111 and the plug diffusion layer 112 are provided so as to surround the side surface and the bottom surface of the first P-type semiconductor layer 121 constituting the plurality of photoelectric conversion regions. The type semiconductor layer 121 is separated from the second P type semiconductor layer 122 by the buried layer 111 and the plug diffusion layer 112. As a result, the carriers generated by irradiating the second P-type semiconductor layer 122 with light are suppressed from flowing into the photoelectric conversion region, and variations in photoelectric conversion characteristics are reduced, or disturbance noise resistance is improved. be able to.

  In addition, the solid-state imaging device according to this embodiment includes a wiring 182 that supplies the plug diffusion layer 112 with the power supply potential VDD on the high potential side. As a result, negative carriers (electrons) generated by irradiating light to the peripheral region are captured by the plug diffusion layer 112 or the buried layer 111, so that the inflow of carriers to the photoelectric conversion region can be further suppressed.

  Furthermore, in the present embodiment, the plug diffusion layer 112 has a first impurity concentration in a region surrounding the side surface of the first P-type semiconductor layer 121, and the buried layer 111 is the first P-type semiconductor layer 121. In the region surrounding the bottom surface of the first impurity concentration, the second impurity concentration is higher than the first impurity concentration. Thereby, the potential of the buried layer 111 surrounding the bottom surface of the first P-type semiconductor layer 121 constituting the plurality of photoelectric conversion regions is increased, and negative carriers (electrons) generated by irradiating the peripheral region with light are captured. Can be made easier.

For example, the plug diffusion layer 112 has an impurity concentration of about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ³ , and the buried layer 111 has an impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ^3. Have a concentration. In that case, since the impurity concentration of the plug diffusion layer 112 is also higher than the impurity concentration of the normal N well, the peripheral region is irradiated with light also in the plug diffusion layer 112 surrounding the side surface of the first P-type semiconductor layer 121. Thus, the negative carriers (electrons) generated can be easily captured.

<Manufacturing method 2>
Next, a method for manufacturing the solid-state imaging device shown in FIGS. 13 and 14 will be described.
15 to 21 are process cross-sectional views for explaining the method for manufacturing the solid-state imaging device according to the second embodiment of the present invention. First, a P-type semiconductor substrate 100 is prepared. As the semiconductor substrate 100, for example, a silicon (Si) substrate containing a P-type impurity such as boron (B) is used.

Next, as shown in FIG. 15, a buried layer (N ⁺ ) 111 that is a first N-type semiconductor layer is formed on the semiconductor substrate 100. For example, a thermal oxide film serving as a transmission film at the time of ion implantation is formed on the main surface of the semiconductor substrate 100. Thereafter, by using a photoresist formed by a photolithography method as a mask, N-type impurity ions such as phosphorus (P) or arsenic (As) are implanted into a part of the semiconductor substrate 100 and thermally diffused. A buried layer 111 is formed on the semiconductor substrate 100.

Next, the photoresist is removed, and as shown in FIG. 16, an epitaxial layer (P ⁻ ) 101 that is a P-type semiconductor layer is formed on the semiconductor substrate 100 on which the buried layer 111 is formed by an epitaxial growth method. For example, when a silicon layer is epitaxially grown on a silicon substrate, a P-type epitaxial layer 101 having a desired conductivity (specific resistance) is formed by mixing a gas of a P-type impurity such as boron (B). be able to.

  Next, as shown in FIG. 17, the plug diffusion layer 112, which is the second N-type semiconductor layer, reaches the buried layer 111 in the epitaxial layer 101 and surrounds the region where a plurality of photoelectric conversion regions are formed. It is formed to surround. Thereby, the P-type epitaxial layer 101 is separated into the first P-type semiconductor layer 121 and the second P-type semiconductor layer 122, and the buried layer 111 and the plug diffusion layer 112 become the first P-type semiconductor layer 121. It surrounds the side and bottom of the.

  For example, N type impurity ions such as phosphorus (P) or arsenic (As) are implanted into a partial region of the epitaxial layer 101 using a photoresist formed by photolithography as a mask. Furthermore, by diffusing the N-type impurity by heat, the N-type impurity reaches the buried layer 111, and the plug diffusion layer 112 reaching the buried layer 111 is formed. At that time, a part of the buried layer 111 may extend to the epitaxial layer 101 by thermal diffusion of impurities.

  Next, the photoresist is removed, and a plurality of N-type impurity regions 131 that form a plurality of photoelectric conversion regions together with the first P-type semiconductor layer 121 are formed in the first P-type semiconductor layer 121. For example, as shown in FIG. 18, a photoresist PH1 is formed on the epitaxial layer 101 on which the plug diffusion layer 112 is formed by a photolithography technique. The photoresist PH1 has an opening in a region where a photodiode is formed.

By using the photoresist PH1 as a mask, N-type impurity ions (N ⁻⁻ ) are implanted into a partial region of the first P-type semiconductor layer 121 to diffuse the impurities, thereby forming N constituting the cathode of the photodiode. A type impurity region (N ⁻⁻ ) 131 is formed in the first P-type semiconductor layer 121. Furthermore, an N-type impurity region (N ⁻ ) 131a or a high-concentration P-type impurity region (pinning layer) 141 shown in FIG. 14 may be formed.

  Next, as shown in FIG. 19, the photoresist PH <b> 1 is removed, and a photoresist PH <b> 2 is formed by photolithography on the epitaxial layer 101 in which the N-type impurity region 131 and the like are formed. The photoresist PH2 has an opening in a region where the floating diffusion region 132 is formed.

A floating diffusion region (N ⁺ ) 132 is formed in the first P-type semiconductor layer 121 by implanting N-type impurity ions (N ⁺ ) into a partial region of the epitaxial layer 101 using the photoresist PH 2 as a mask. Is done.

  Next, after the photoresist PH2 is removed and the thermal oxide film used as the permeable film at the time of ion implantation is peeled off, an insulating film and a polysilicon film are sequentially formed on the epitaxial layer 101. Further, the polysilicon film is patterned using a photoresist formed by photolithography as a mask. The insulating film may not be patterned.

  Thereby, as shown in FIG. 20, the gate electrode 150 of the transfer gate TG is formed on the epitaxial layer 101 via the insulating film. At that time, the mutual positions may be adjusted so that the gate electrode 150 overlaps with part of the N-type impurity region 131 and the floating diffusion region 132 in plan view. Similarly, in other regions of the epitaxial layer 101, gate electrodes of a plurality of MOS transistors including the buffer transistor QN1, the reset transistor QN2 (FIG. 4), and the like are formed.

Next, N-type impurity ions (N ⁺ ) are implanted into a partial region of the epitaxial layer 101 using a photoresist formed by photolithography as a mask, as shown in FIG. Contact region (N ⁺ ) 112 a is formed in plug diffusion layer 112. Similarly, in other regions of the epitaxial layer 101, N-type impurity regions serving as sources and drains of a plurality of N-channel MOS transistors including the buffer transistor QN1, the reset transistor QN2 (FIG. 4), and the like are formed.

Next, the photoresist is removed, and P-type impurity ions are implanted into a partial region of the second P-type semiconductor layer 122 using the photoresist newly formed by photolithography as a mask. As shown in FIG. 21, a P-type contact region (P ⁺ ) 122 a is formed in the second P-type semiconductor layer 122. Similarly, in other regions of the epitaxial layer 101, P-type impurity regions serving as sources and drains of a plurality of P-channel MOS transistors are formed.

  Next, the photoresist is removed, and an interlayer insulating film 160 having a plurality of contact holes is formed on the epitaxial layer 101 on which the gate electrode 150 and the like are formed, as shown in FIG. Further, a photoresist is formed on a part of the interlayer insulating film 160, and N-type impurity ions are implanted into a part of the floating diffusion region 132 using the interlayer insulating film 160 and the photoresist as a mask. An N-type contact region 132a having a concentration is formed.

  Next, contact plugs 171 to 173 electrically connected to the contact regions 122a, 112a, and 132a are formed in the contact holes of the interlayer insulating film 160. Further, wirings 181 to 183 electrically connected to the contact plugs 171 to 173 are formed on the interlayer insulating film 160. Note that two or more interlayer insulating films and wiring layers may be used as necessary.

  According to the present embodiment, the P type epitaxial layer 101 is formed on the P type semiconductor substrate 100 on which the N type buried layer 111 is formed, and the N type plug diffusion reaching the buried layer 111 is formed in the epitaxial layer 101. By forming the layer 112, the first P-type semiconductor layer 121 constituting the plurality of photoelectric conversion regions is separated from the second P-type semiconductor layer 122 by the buried layer 111 and the plug diffusion layer 112. Thereby, it is possible to suppress the occurrence of carriers generated by irradiating light on the second P-type semiconductor layer 122 into the photoelectric conversion region, thereby reducing variation in photoelectric conversion characteristics, or improving disturbance noise resistance. A solid-state imaging device can be provided.

  Prior to forming the epitaxial layer 101 on the semiconductor substrate 100, the buried layer 111 having a high impurity concentration can be formed in the semiconductor substrate 100. Thereby, the potential of the buried layer 111 surrounding the bottom surface of the first P-type semiconductor layer 121 constituting the plurality of photoelectric conversion regions is increased, and negative carriers (electrons) generated by irradiating the peripheral region with light are captured. Can be made easier.

  As described in the above embodiments, the image quality of image data obtained by imaging a subject is improved by using a solid-state imaging device with reduced variations in photoelectric conversion characteristics or improved disturbance noise resistance. Electronic equipment can be provided.

  In addition to the scanner device, the solid-state imaging device according to the above embodiment includes, for example, a drive recorder, a digital movie, a digital still camera, a mobile terminal such as a mobile phone, a videophone, a crime prevention TV monitor, a measuring device, and It can be used in an electronic device that images a subject and generates image data, such as a medical device.

  Although the case where an N-type impurity region or the like is formed in a P-type semiconductor layer has been described in the above embodiment, the present invention is not limited to the above-described embodiment. For example, the present invention can also be applied when a P-type impurity region or the like is formed in an N-type semiconductor layer. As described above, many modifications can be made within the technical idea of the present invention according to persons having ordinary knowledge in the technical field.

  DESCRIPTION OF SYMBOLS 1 ... Original, 10 ... CIS module, 11 ... Light guide, 12 ... Lens array, 13 ... Image sensor, 14 ... Light source, 15 ... Flexible wiring, 16 ... Main board, 17 ... System on chip, 18 ... Analog front end, DESCRIPTION OF SYMBOLS 19 ... Power supply circuit, 20 ... Image sensor chip, 30 ... Pixel part, 40 ... Read-out circuit part, 50 ... Control circuit part, 51 ... Correlated double sampling circuit, 52 ... Output circuit, 53 ... Logic circuit, 61-64 ... Capacitor, 100 ... Semiconductor substrate, 100a, 110a, 112a, 122a, 132a ... Contact region, 101 ... Epitaxial layer, 110 ... N well, 111 ... Buried layer, 112 ... Plug diffusion layer, 120 ... P well, 121 ... First P-type semiconductor layer 122, second P-type semiconductor layer 131, 131a,. Type impurity region, 132, FD ... floating diffusion region, 141 ... P type impurity region (pinning layer), 150 ... gate electrode, 160 ... interlayer insulating film, 171-173 ... contact plug, 181-183 ... wiring, PD ... Photodiode, CH... Charge holding region, TG1... Previous stage transfer gate, TG2... Post stage transfer gate, TG... Transfer gate, QN1. PH1 ... photoresist, PH2 ... photoresist

Claims (9)

A first P-type semiconductor layer;
A plurality of N-type impurity regions disposed in the first P-type semiconductor layer and constituting a plurality of photoelectric conversion regions together with the first P-type semiconductor layer;
An N-type semiconductor layer surrounding a side surface and a bottom surface of the first P-type semiconductor layer;
A second P-type semiconductor layer surrounding the N-type semiconductor layer in plan view;
A solid-state imaging device.   The solid-state imaging device according to claim 1, further comprising a wiring for supplying a power potential on the high potential side to the N-type semiconductor layer.   The solid-state imaging device according to claim 1, wherein the N-type semiconductor layer has an impurity concentration that decreases according to a depth from a main surface.   The N-type semiconductor layer has a first impurity concentration in a region surrounding the side surface of the first P-type semiconductor layer, and the first impurity concentration in a region surrounding the bottom surface of the first P-type semiconductor layer. 3. The solid-state imaging device according to claim 1, wherein the solid-state imaging device has a higher second impurity concentration.   An electronic apparatus comprising the solid-state imaging device according to claim 1. A step (a) of preparing a P-type semiconductor substrate;
A step (b) of forming an N-type semiconductor layer on the semiconductor substrate;
(C) forming a P-type semiconductor layer on the N-type semiconductor layer so that the N-type semiconductor layer surrounds a side surface and a bottom surface of the P-type semiconductor layer;
A step (d) of forming a plurality of N-type impurity regions constituting a plurality of photoelectric conversion regions together with the P-type semiconductor layer in the P-type semiconductor layer;
A method for manufacturing a solid-state imaging device.   The solid-state imaging device manufacturing method according to claim 6, wherein the step (b) includes forming the N-type semiconductor layer by implanting and diffusing an N-type impurity in a partial region of the semiconductor substrate. Method. A step (a) of preparing a P-type semiconductor substrate;
Forming a first N-type semiconductor layer on the semiconductor substrate (b);
Forming a P-type semiconductor layer on the semiconductor substrate on which the first N-type semiconductor layer is formed;
By forming a second N-type semiconductor layer reaching the first N-type semiconductor layer in the P-type semiconductor layer, the P-type semiconductor layer is divided into a first P-type semiconductor layer and a second P-type semiconductor layer. (D) separating the first and second N-type semiconductor layers so as to surround side and bottom surfaces of the first P-type semiconductor layer;
A step (e) of forming a plurality of N-type impurity regions constituting a plurality of photoelectric conversion regions together with the first P-type semiconductor layer in the first P-type semiconductor layer;
A method for manufacturing a solid-state imaging device. Step (b) includes implanting an N-type impurity into a partial region of the semiconductor substrate to form a buried layer;
Step (c) includes forming a P-type epitaxial layer on the semiconductor substrate on which the buried layer is formed;
Step (d) includes forming a plug diffusion layer reaching the buried layer by implanting and diffusing an N-type impurity in a partial region of the epitaxial layer.
The manufacturing method of the solid-state imaging device of Claim 8.

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