JP2018064223A - Satellite broadcast receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a satellite broadcast receiver capable of synchronous processing of a single carrier with a simple configuration.SOLUTION: A satellite broadcast receiver includes: an orthogonal demodulator for outputting a demodulated signal obtained by demodulating a received communication signal in accordance with ARIB (Association of Radio Industries and Businesses) STD-B44; an A/D converter for converting the demodulated signal received from the orthogonal demodulator into a digital signal; a detection unit for using a prescribed synchronous pattern indicated by a plurality of symbols modulated by BPSK (Binary Phase Shift Keying) included in the digital signal obtained by conversion by the A/D converter to detect an error of a carrier frequency at the orthogonal demodulator and an error of a sampling frequency at the A/D converter; and an adjustment unit for adjusting the carrier frequency and the sampling frequency on the basis of a detection result of the detection unit.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a satellite broadcast receiving apparatus.

  Conventionally, a technique for establishing frequency and time synchronization using a synchronization signal included in a received radio wave has been developed.

  For example, Non-Patent Document 1 (Kiyotaka Ishikawa, Tomohisa Wada, “Study on Detection of Frequency Error and Sampling Frequency Error in LTE”, IEICE Technical Report, SIP 2010-88, RCS 2010-218, P. 115-119) The following techniques are disclosed. That is, the carrier frequency error and the sampling frequency error are detected using the rotation amount of the cyclic shift included in the received PSS (Primary Synchronization Signal) and SSS (Secondary Synchronization Signal). The carrier frequency error causes rotation of all carriers regardless of the carrier number of the subcarrier. On the other hand, the sampling frequency error causes rotation in proportion to the carrier number. That is, the average value of the rotation amount on the high frequency side and the average value of the rotation amount on the low frequency side are calculated, and a straight line indicating the change in the rotation amount with respect to the frequency is obtained based on each calculated average value. A carrier frequency error and a sampling frequency error are obtained from the intercept and the slope, respectively. Therefore, the carrier frequency error and the sampling frequency error are detected using the average rotation amount on the low frequency side and the average rotation amount on the high frequency side of the symbol.

JP 2004-165896 A JP-A-10-164164

Kiyotaka Ishikawa, Tomohisa Wada, “Study on Detection of Frequency Error and Sampling Frequency Error in LTE”, IEICE Technical Report, SIP 2010-88, RCS 2010-218, P.A. 115-119 Japan Radio Industry Association, “Advanced Broadband Satellite Digital Broadcasting Transmission System (ISDB-S3) Standard ARIB (Registered Trademark) STD-B44 Version 2.1”, [online], [Search June 21, 2016] Internet <URL: http: // www. arib. or. jp / english / html / overview / doc / 2-STD-B44v2_1. pdf>

  By using the technique described in Non-Patent Document 1 for a multi-carrier modulation scheme such as OFDM (Orthogonal Frequency Division Multiplexing), it is possible to detect a carrier frequency error and a sampling frequency error. However, the above technique cannot be applied to single carrier satellite broadcast waves.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a satellite broadcast receiving apparatus capable of performing synchronization processing on a single carrier with a simple configuration.

  (1) In order to solve the above problems, a satellite broadcast receiving apparatus according to an aspect of the present invention outputs a demodulated signal obtained by demodulating a received communication signal according to ARIB (Association of Radio Industries and Businesses) STD-B44. Included in the quadrature demodulator, an A / D (Analog-to-Digital) converter that converts the demodulated signal received from the quadrature demodulator into a digital signal, and the digital signal converted by the A / D converter And detecting a carrier frequency error in the quadrature demodulator and a sampling frequency error in the A / D converter using a predetermined synchronization pattern indicated by a plurality of symbols modulated by BPSK (Binary Phase Shift Keying). detection If, and an adjustment unit for adjusting the carrier frequency and the sampling frequency based on a detection result of the detecting unit.

  The present invention can be realized not only as a satellite broadcast receiving apparatus including such a characteristic processing unit, but also as a satellite broadcast receiving system including a satellite broadcast receiving apparatus, or performing such characteristic processing as a step. Or a program for causing a computer to execute such steps. Further, it can be realized as a semiconductor integrated circuit that realizes part or all of the satellite broadcast receiving apparatus.

  According to the present invention, synchronization processing can be performed on a single carrier with a simple configuration.

FIG. 1 is a diagram showing a configuration of a satellite broadcast receiving system according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of a modulation slot included in a satellite broadcast wave received by the satellite broadcast receiver according to the embodiment of the present invention. FIG. 3 is a diagram showing the configuration of the satellite broadcast receiving apparatus in the satellite broadcast receiving system according to the embodiment of the present invention. FIG. 4 is a diagram showing a configuration of an orthogonal demodulator in the satellite broadcast receiving apparatus according to the embodiment of the present invention. FIG. 5 is a diagram showing a configuration of a synchronization processing unit in the satellite broadcast receiving apparatus according to the embodiment of the present invention. FIG. 6 is a diagram showing an example of a constellation showing a demodulated signal demodulated by the satellite broadcast receiving apparatus according to the embodiment of the present invention. FIG. 7 is a diagram illustrating an example of a frame synchronization signal calculation process performed by the synchronization processing unit in the satellite broadcast receiving apparatus according to the embodiment of the present invention. FIG. 8 is a diagram illustrating an example of a change for each symbol of the shift angle θ calculated by the symbol synchronization detection unit in the satellite broadcast receiving device according to the embodiment of the present invention. FIG. 9 is a diagram illustrating an example of a change in the shift angle θ for each symbol when the feedback function is applied to the straight line illustrated in FIG. 8. FIG. 10 is a diagram showing an example of a change for each symbol of the shift angle θ calculated by the symbol synchronization detection unit in the satellite broadcast receiving apparatus according to the embodiment of the present invention. FIG. 11 is a diagram illustrating an example of a change for each symbol of the shift angle θ calculated by the symbol synchronization detection unit in the satellite broadcast receiving device according to the embodiment of the present invention. FIG. 12 is a diagram showing an example of a change for each symbol of the shift angle θ calculated by the symbol synchronization detection unit in the satellite broadcast receiving apparatus according to the embodiment of the present invention. FIG. 13 is a diagram illustrating an example of a change for each symbol of the shift angle θ calculated by the symbol synchronization detection unit in the satellite broadcast receiving device according to the embodiment of the present invention.

  First, the contents of the embodiment of the present invention will be listed and described.

  (1) A satellite broadcast receiving apparatus according to an embodiment of the present invention includes: a quadrature demodulator that outputs a demodulated signal obtained by demodulating a received communication signal according to ARIB (Association of Radio Industries and Businesses) STD-B44; An A / D (Analog-to-Digital) converter that converts the demodulated signal received from the demodulator into a digital signal, and a BPSK (Binary Phase Shift) included in the digital signal converted by the A / D converter. A detecting unit for detecting an error in a carrier frequency in the quadrature demodulator and an error in a sampling frequency in the A / D converter using a predetermined synchronization pattern indicated by a plurality of symbols modulated by the keying; and the detecting unit In the detection result Zui and and an adjusting unit for adjusting the carrier frequency and the sampling frequency.

  In this way, with the configuration in which the predetermined synchronization pattern is BPSK-modulated, the predetermined synchronization pattern can be demodulated without performing special processing such as other clock synchronization processing. Then, by using a predetermined synchronization pattern, a carrier frequency error and a sampling frequency error in a quadrature demodulator that demodulates a single carrier communication signal according to ARIB STD-B44, and a carrier frequency error for a single carrier, and A sampling frequency error can be easily detected. In addition, synchronization with the communication signal according to ARIB STD-B44 can be established by adjusting the carrier frequency and the sampling frequency based on the detection result. Therefore, it is possible to perform synchronization processing for a single carrier with a simple configuration.

  (2) Preferably, the detection unit detects an error in the sampling frequency based on a plurality of symbols indicating successive logical values among a plurality of symbols indicating the synchronization pattern.

  In the case where an error is included in the sampling frequency, in the constellation, characteristic positional deviations of a plurality of symbols indicating continuous logical values are observed. An error in the sampling frequency can be correctly detected from such a characteristic positional deviation.

  (3) More preferably, the detection unit is based on a plurality of symbols indicating a continuous logical value of zero and a plurality of symbols indicating a continuous logical value among a plurality of symbols indicating the synchronization pattern. An error of the sampling frequency is detected.

  In the case where an error is included in the sampling frequency, in the constellation, a more characteristic positional shift of a plurality of symbols indicating a continuous zero logical value and a plurality of symbols indicating a continuous one logical value is observed. An error in the sampling frequency can be detected more correctly from such a characteristic positional deviation.

  (4) Preferably, the adjustment unit includes a complex multiplier that calculates the digital signal when the carrier frequency is adjusted, and an interpolator that calculates the digital signal when the sampling frequency is adjusted.

  With such a configuration, the entire satellite broadcast receiving apparatus can be realized by a digital circuit, so that the carrier frequency and sampling frequency can be adjusted by software. That is, all processes can be completed within the digital circuit of the same clock without adjusting the carrier frequency and sampling frequency by hardware such as PLL (Phase Locked Loop). Thereby, a satellite broadcast receiving apparatus can be easily realized using a program logic IC such as an FPGA (Field-Programmable Gate Array). In addition, the prototype of the apparatus can be easily made and the entire apparatus can be simplified.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. Moreover, you may combine arbitrarily at least one part of embodiment described below.

[Configuration and basic operation]
FIG. 1 is a diagram showing a configuration of a satellite broadcast receiving system according to an embodiment of the present invention.

  Referring to FIG. 1, a satellite broadcast receiving system 301 includes a satellite broadcast receiving device 101 and a stream processing device 151.

  For example, Non-Patent Document 2 (Radio Industry Association, “Transmission System for Advanced Broadband Satellite Digital Broadcasting (ISDB-S3) Standard ARIB STD-B44 2.1 Version”, [online], [2016] June 21, 2009], the standard described in the Internet <URL: http://www.arib.or.jp/english/html/overview/doc/2-STD-B44v2_1.pdf>), that is, ARIB STD-B44 A single carrier satellite broadcast wave, which is an example of a communication signal according to the above, is received.

  FIG. 2 is a diagram showing an example of a modulation slot included in a satellite broadcast wave received by the satellite broadcast receiver according to the embodiment of the present invention.

  Referring to FIG. 2, the satellite broadcast wave includes, for example, a π / 2 BPSK (Binary Phase Shift Keying) modulated frame synchronization signal. The frame synchronization signal is composed of 24 symbols and includes, for example, one of 52F866h and AD0799h as a logical value. Here, “h” means a hexadecimal number.

  The modulation slot may include a slot synchronization signal instead of the frame synchronization signal. The slot synchronization signal consists of 24 symbols and includes, for example, 36715Ah as a logical value. The frame synchronization signal and the slot synchronization signal are repeatedly transmitted, for example.

  Referring to FIG. 1 again, antenna 111 down-converts the received satellite broadcast wave into an IF signal having BS-IF (BS Intermediate Frequency).

  The satellite broadcast receiving apparatus 101 receives an IF signal from the antenna 111 and generates a baseband signal by performing direct conversion on the received IF signal, for example.

  The satellite broadcast receiving apparatus 101 detects a synchronization signal from the generated baseband signal, and establishes frequency and time synchronization using the detected synchronization signal. Then, the satellite broadcast receiving apparatus 101 generates a stream from the baseband signal and transmits the generated stream to the stream processing apparatus 151.

  The stream processing device 151 is, for example, a recording device or a television, and records a stream received from the satellite broadcast receiving device 101 or reproduces it on a display.

  FIG. 3 is a diagram showing the configuration of the satellite broadcast receiving apparatus in the satellite broadcast receiving system according to the embodiment of the present invention.

  Referring to FIG. 3, satellite broadcast receiving apparatus 101 includes analog signal processing unit 1 and digital signal processing unit 2. The analog signal processing unit 1 includes an orthogonal demodulator 11, A / D converters (ADC) 12I and 12Q, a reference signal source oscillator 13, and a clock generation circuit 14. The digital signal processing unit 2 includes RRF (Root Roll-Off Filter) 15I and 15Q, a synchronization processing unit 16, and an LDPC (Low Density Parity Check) decoding unit 17. Hereinafter, each of the A / D converters 12I and 12Q is also referred to as an A / D converter 12.

  The reference signal source oscillator 13 is, for example, a crystal oscillator, generates a reference signal having a frequency of 27 MHz, and outputs the generated reference signal to the quadrature demodulator 11.

  The clock generation circuit 14 generates a clock signal and outputs the generated clock signal to the A / D converter 12.

  FIG. 4 is a diagram showing a configuration of an orthogonal demodulator in the satellite broadcast receiving apparatus according to the embodiment of the present invention.

  Referring to FIG. 4, quadrature demodulator 11 includes an AGC (Automatic Gain Control) amplifier 31, a PLL unit 32, mixers 33I and 33Q, and low-pass filters 34I and 34Q.

  The quadrature demodulator 11 outputs a demodulated signal obtained by demodulating the received IF signal. More specifically, the AGC amplifier 31 in the quadrature demodulator 11 amplifies the IF signal received from the antenna 111 so that the signal is input with the optimum amplitude in the A / D converter 12 in the subsequent stage, The IF signal is output to the mixers 33I and 33Q.

  The PLL unit 32 generates a local signal LI that is a local oscillation signal synchronized with the reference signal received from the reference signal source oscillator 13 and generates a local signal LQ whose phase is shifted by π / 2 with respect to the local signal LI. The PLL unit 32 outputs the generated local signals LI and LQ to the mixers 33I and 33Q, respectively.

  The mixer 33I generates a baseband signal BI which is an example of a demodulated signal by down-converting the IF signal received from the AGC amplifier 31 using the local signal LI received from the PLL unit 32, and the generated baseband signal BI is Output to the low-pass filter 34I.

  The mixer 33Q generates a baseband signal BQ that is an example of a demodulated signal by down-converting the IF signal received from the AGC amplifier 31 using the local signal LQ received from the PLL unit 32, and the generated baseband signal BQ is Output to the low-pass filter 34Q.

  The low-pass filter 34I attenuates a component having a frequency equal to or higher than a predetermined frequency among the frequency components of the baseband signal BI generated by the mixer 33I.

  The low-pass filter 34Q attenuates a component having a predetermined frequency or higher among the frequency components of the baseband signal BQ generated in the mixer 33Q.

  Referring to FIG. 3 again, A / D converter 12 converts the baseband signal received from quadrature demodulator 11 into a digital signal. Specifically, the A / D converters 12I and 12Q perform sampling processing of the baseband signals BI and BQ at the frequency of the clock signal received from the clock generation circuit 14, respectively.

  More specifically, the A / D converter 12I converts the baseband signal BI that has passed through the low-pass filter 34I into a digital baseband signal DI of q bits (q is an integer of 2 or more) for each sampling period. The A / D converter 12I outputs the converted baseband signal DI to the digital signal processing unit 2.

  The A / D converter 12Q converts the baseband signal BQ that has passed through the low-pass filter 34Q into a q-bit digital baseband signal DQ for each sampling period. The A / D converter 12Q outputs the converted baseband signal DQ to the digital signal processing unit 2.

  The digital signal processing unit 2 is realized by a semiconductor integrated circuit constituting an FPGA, for example.

  For example, the RRF 15I in the digital signal processing unit 2 performs a band roll-off filter process on the baseband signal DI received from the A / D converter 12I with a roll-off rate of 0.03, thereby providing a bandwidth to the baseband signal DI. The restriction is applied and the processed baseband signal DI is output to the synchronization processing unit 16.

  For example, the RRF 15Q performs a root roll-off filter process with a roll-off rate of 0.03 on the base band signal DQ received from the A / D converter 12Q, thereby adding a band limitation to the base band signal DQ. The baseband signal DQ is output to the synchronization processing unit 16.

  FIG. 5 is a diagram showing a configuration of a synchronization processing unit in the satellite broadcast receiving apparatus according to the embodiment of the present invention.

  Referring to FIG. 5, synchronization processing unit 16 includes a symbol synchronization detection unit 44 and an adjustment unit 45. The adjustment unit 45 includes an interpolator 41, digital LPFs (low pass filters) 42 </ b> I and 42 </ b> Q, and a complex multiplier 43. The interpolator 41 includes a tap coefficient holding unit 46. The adjustment unit 45 may be configured not to include the digital LPFs 42I and 42Q.

  The interpolator 41 can calculate the baseband signals DI and DQ when the sampling frequency is adjusted, for example.

  More specifically, the tap coefficient holding unit 46 in the interpolator 41 is, for example, a RAM (Random Access Memory), and holds a tap coefficient for each sampling frequency adjustment ratio.

  Here, the tap coefficient is a coefficient for converting the digital signal D1 sampled at the sampling frequency A1 into the digital signal D2 sampled at the sampling frequency A2 obtained by multiplying the target adjustment ratio and the sampling frequency A1.

  By using the tap coefficient, it is possible to easily calculate the digital signal D2 to be obtained by resampling the signal generated by oversampling the digital signal D1 at the sampling frequency A2.

  The interpolator 41 holds, for example, baseband signals DI and DQ having a plurality of sampling timings received from the RRFs 15I and 15Q, respectively.

  Further, the interpolator 41 outputs the held baseband signals DI and DQ to the digital LPFs 42I and 42Q without adjusting the sampling frequency until, for example, frequency error information SE described later is received from the symbol synchronization detection unit 44.

  The digital LPF 42 </ b> I attenuates a component having a frequency equal to or higher than a predetermined frequency among the frequency components of each baseband signal DI received from the interpolator 41 and outputs each attenuated baseband signal DI to the complex multiplier 43.

  The digital LPF 42 </ b> Q attenuates components of a predetermined frequency or higher among the frequency components of each baseband signal DQ received from the interpolator 41, and outputs each attenuated baseband signal DQ to the complex multiplier 43.

  For example, the complex multiplier 43 can calculate the baseband signals DI and DQ when the carrier frequency is adjusted.

  More specifically, the complex multiplier 43 receives the baseband signals DI and DQ from the digital LPFs 42I and 42Q, respectively, and performs the following processing.

  That is, the complex multiplier 43 generates a target complex number that is a complex number having the value of the baseband signal DI and the value of the DQ as the real number and the imaginary number at the same sampling timing at each sampling timing.

  The complex multiplier 43 does not adjust the phase of the target complex number accompanying the adjustment of the carrier frequency until, for example, frequency error information CE described later is received from the symbol synchronization detection unit 44.

  The complex multiplier 43 outputs the real part and the imaginary part of the target complex number at each sampling timing to the LDPC decoding unit 17 as baseband signals DI and DQ, respectively, and to the symbol synchronization detection unit 44.

  FIG. 6 is a diagram showing an example of a constellation showing a demodulated signal demodulated by the satellite broadcast receiving apparatus according to the embodiment of the present invention.

  In FIG. 6, the horizontal axis represents the I axis, and the vertical axis represents the Q axis. The azimuth angle φ in the IQ plane is defined so that the I-axis direction is 0 ° and increases in the counterclockwise direction. On the IQ plane, a circle C1 having a radius of the square root of the sum of the square of the value of the baseband signal DI and the square of the value of the baseband signal DQ is a position of (I = 0, Q = 0). Is shown in the center.

  Referring to FIG. 6, the π / 2 BPSK modulated frame synchronization signal and slot synchronization signal are plotted on a circle C1 in the IQ plane. More specifically, for example, the frame synchronization signal F1 having a value of 52F866h includes 24 symbols indicating a logical value of 0101 0010 1111 1000 0110 0110.

  Among these symbols, for symbols with an odd symbol number k (k is an integer equal to or greater than 1), a symbol indicating a logical value of 0 is plotted at a position of φ = π / 4 in the circle C1, and A symbol indicating a logical value of 1 is plotted at a position of φ = 5π / 4 in the circle C1.

  On the other hand, for symbols with an even symbol number k, a symbol indicating a logical value of 0 is plotted at a position of φ = 3π / 4 in the circle C1, and a symbol indicating a logical value of 1 is plotted in the circle C1. = Plotted at 7π / 4 position.

  That is, for symbols with an odd symbol number k, the signs of the I component and Q component are the same in phase, and for symbols with an even symbol number k, the signs of the I component and Q component are different.

  FIG. 7 is a diagram illustrating an example of a frame synchronization signal calculation process performed by the synchronization processing unit in the satellite broadcast receiving apparatus according to the embodiment of the present invention.

  Referring to FIG. 7, symbol synchronization detection unit 44 monitors baseband signals DI and DQ at each sampling timing received from complex multiplier 43. For example, when frame synchronization signal F1 is detected, symbol synchronization detection unit 44 performs the following processing.

  That is, the symbol synchronization detection unit 44 calculates azimuth angles φ1 to φ24 of each signal, that is, each symbol in the frame synchronization signal F1, based on the baseband signal DI, that is, the I component, and the baseband signal DQ, that is, the Q component.

  The symbol synchronization detection unit 44 adds an offset angle α to each of the azimuth angles φ1 to φ24 so that the calculated azimuth angle φ1 becomes, for example, π / 4.

  Then, the symbol synchronization detection unit 44 calculates the remainder when the azimuth angles φ1 to φ24 are divided by π / 2 as the deviation angles θ1 to θ24, respectively.

  FIG. 8 is a diagram illustrating an example of a change for each symbol of the shift angle θ calculated by the symbol synchronization detection unit in the satellite broadcast receiving device according to the embodiment of the present invention. In FIG. 8, the vertical axis indicates the deviation angle θ, and the horizontal axis indicates the symbol number k.

  In FIG. 8, the reference signal source oscillator 13 causes the PLL unit 32 to shift by 50 ppm from a carrier frequency (hereinafter also referred to as a transmission-side carrier frequency) in a device that transmits satellite broadcast waves (hereinafter referred to as a reception-side carrier frequency). ), And the A / D converter 12 has the same sampling frequency (hereinafter referred to as the receiving side sampling frequency) as the sampling frequency of the D / A converter in the device (hereinafter also referred to as the transmitting side sampling frequency). The change of the shift angle θ for each symbol in the operation state is also shown.

  Referring to FIGS. 2 and 8, symbol synchronization detection unit 44 uses a predetermined synchronization pattern indicated by a plurality of BPSK-modulated symbols included in the digital signal converted by A / D converter 12. An error in the carrier frequency in the quadrature demodulator 11 and an error in the sampling frequency in the A / D converter 12 are detected.

  Specifically, the symbol synchronization detection unit 44 detects an error in the carrier frequency and an error in the sampling frequency using the pattern of the frame synchronization signal F1.

  More specifically, the symbol synchronization detection unit 44 calculates the straight line SL1 using the calculated deviation angles θ1 to θ24, and detects the presence or absence of an error in the carrier frequency based on the calculated slope of the straight line SL1.

  Specifically, since the slope of the straight line SL1 is not zero, the symbol synchronization detection unit 44 determines that the carrier frequency error is not zero, that is, the reception-side carrier frequency and the transmission-side carrier frequency are shifted.

  Then, the symbol synchronization detection unit 44 calculates a feedback function that is a function of the symbol number k based on, for example, the slope of the straight line SL1.

  More specifically, the symbol synchronization detection unit 44 determines which of the reception-side carrier frequency and the transmission-side carrier frequency is larger from the sign of the slope of the straight line SL1, for example. If the symbol synchronization detection unit 44 determines that the reception-side carrier frequency is higher than the transmission-side carrier frequency, it calculates exp (−iωk + α) as a feedback function, and also determines that the reception-side carrier frequency is lower than the transmission-side carrier frequency. In this case, exp (iωk + α) is calculated as a feedback function. Here, ω is a difference frequency between the transmission side carrier frequency and the reception side carrier frequency.

  FIG. 9 is a diagram illustrating an example of a change in the shift angle θ for each symbol when the feedback function is applied to the straight line illustrated in FIG. 8. In FIG. 9, the vertical axis indicates the deviation angle θ, and the horizontal axis indicates the symbol number k.

  Referring to FIG. 9, by multiplying the 24 target complex numbers corresponding to the symbols of k = 1 to 24 shown in FIG. 8 by the output values of the feedback function when the corresponding variable k is input, The straight line SL1 can be converted into the straight line SL2. That is, the slope of the straight line SL1 can be made zero, and the azimuth angle φ of the first symbol can be made π / 4 without adding the offset angle α.

  FIG. 10 is a diagram showing an example of a change for each symbol of the shift angle θ calculated by the symbol synchronization detection unit in the satellite broadcast receiving apparatus according to the embodiment of the present invention. In FIG. 10, the vertical axis indicates the deviation angle θ, and the horizontal axis indicates the symbol number k.

  In FIG. 10, the reference signal source oscillator 13 causes the PLL unit 32 to generate a local oscillation signal having a reception side carrier frequency shifted by 50 ppm from the transmission side carrier frequency, and the A / D converter 12 performs transmission side sampling. A change for each symbol of the shift angle θ in the state of operating at the reception side sampling frequency of 255/256 times the frequency, that is, the state where the reception side sampling frequency is lower than the transmission side sampling frequency is shown.

  FIG. 11 is a diagram illustrating an example of a change for each symbol of the shift angle θ calculated by the symbol synchronization detection unit in the satellite broadcast receiving device according to the embodiment of the present invention. In FIG. 11, the vertical axis indicates the deviation angle θ, and the horizontal axis indicates the symbol number k.

  In FIG. 11, the reference signal source oscillator 13 causes the PLL unit 32 to generate a local oscillation signal having a reception side carrier frequency shifted by 50 ppm from the transmission side carrier frequency, and the A / D converter 12 performs transmission side sampling. A change for each symbol of the shift angle θ in a state of operating at a reception side sampling frequency 257/256 times the frequency, that is, a state in which the reception side sampling frequency is higher than the transmission side sampling frequency is shown.

  Referring to FIGS. 10 and 11, unlike in the case of FIG. 8, the symbol synchronization detection unit 44, when the change of the deviation angle θ for each symbol does not become a straight line as in FIGS. Is detected as follows.

  That is, for example, the symbol synchronization detection unit 44 groups 24 shift angles θ corresponding to the frame synchronization signal F1 into 4 groups sequentially from the front, and calculates an average value of the shift angles θ for each group. . Then, the symbol synchronization detection unit 44 obtains a straight line passing through the vicinity of each calculated average value, and calculates a feedback function based on the obtained inclination of the straight line.

  Note that the symbol synchronization detection unit 44 may calculate, for example, a straight line passing through the vicinity of the 24 deviation angles θ using the least square method, and calculate a feedback function based on the obtained inclination of the straight line.

  The symbol synchronization detection unit 44 creates frequency error information CE including the calculated feedback function, and outputs the created frequency error information CE to the complex multiplier 43.

  Referring to FIG. 5 again, adjustment unit 45 adjusts the carrier frequency and sampling frequency based on the detection result of symbol synchronization detection unit 44.

  More specifically, when receiving the frequency error information CE from the symbol synchronization detection unit 44, the complex multiplier 43 in the adjustment unit 45 acquires a feedback function from the received frequency error information CE.

  Then, the complex multiplier 43 calculates the baseband signals DI and DQ when the carrier frequency is adjusted by adjusting the phase of the target complex number at each sampling timing using the acquired feedback function.

  Specifically, the complex multiplier 43, for example, multiplies the target complex number at the first sampling timing by the output value of the feedback function when the corresponding variable k, in this example, 1 is input. Shift the phase of complex numbers. Here, the target complex number at the first sampling timing is, for example, the target complex number corresponding to the first symbol in the frame synchronization signal F1.

  The complex multiplier 43 performs the same process for the target complex numbers at the second and subsequent sampling timings, and shifts the phase of the target complex number at each sampling timing.

  The complex multiplier 43 outputs the real part and the imaginary part of the target complex number at each sampling timing to the LDPC decoding unit 17 as baseband signals DI and DQ, respectively, and to the symbol synchronization detection unit 44.

  FIG. 12 is a diagram showing an example of a change for each symbol of the shift angle θ calculated by the symbol synchronization detection unit in the satellite broadcast receiving apparatus according to the embodiment of the present invention. In FIG. 12, the vertical axis indicates the deviation angle θ, and the horizontal axis indicates the symbol number k.

  In FIG. 12, in the change for each symbol of the deviation angle θ shown in FIG. 10, the state where the carrier frequency deviation is eliminated and the reception side sampling frequency is shifted to the lower side with respect to the transmission side sampling frequency is maintained. Changes are shown.

  FIG. 13 is a diagram illustrating an example of a change for each symbol of the shift angle θ calculated by the symbol synchronization detection unit in the satellite broadcast receiving device according to the embodiment of the present invention. In FIG. 13, the vertical axis indicates the deviation angle θ, and the horizontal axis indicates the symbol number k.

  FIG. 13 maintains the state in which the shift of the carrier frequency is eliminated and the reception side sampling frequency is shifted to the higher side with respect to the transmission side sampling frequency in the change of the deviation angle θ shown in FIG. 11 for each symbol. Changes are shown.

  Referring to FIGS. 12 and 13, symbol synchronization detection unit 44 calculates the sampling frequency error based on, for example, a plurality of symbols indicating successive logical values among a plurality of symbols indicating the pattern of frame synchronization signal F <b> 1. To detect.

  More specifically, the symbol synchronization detection unit 44, for example, among a plurality of symbols indicating the pattern of the frame synchronization signal F1, a plurality of symbols indicating a logical value of consecutive zeros and a plurality of symbols indicating a continuous logical value of one. The sampling frequency error is detected based on the symbols.

  Specifically, the symbol synchronization detection unit 44 detects an error of the sampling frequency based on, for example, 0110 0110 symbols in which k is 17-24.

  More specifically, since the symbol synchronization detection unit 44 does not change the deviation angle θ for each symbol in a straight line, the sampling frequency error is not zero, that is, the reception side sampling frequency and the transmission side sampling frequency are shifted. Judge that

  Then, the symbol synchronization detection unit 44 determines which of the reception-side sampling frequency and the transmission-side sampling frequency is larger, for example, based on the change pattern of the shift angle θ of k = 17-24.

  More specifically, the symbol synchronization detection unit 44 indicates that, for example, as shown in a region Rs in FIG. 12, k indicates a larger value of the shift angle θ of 17, 20, 21, 24, and k is 18, 19 , 22 and 23 indicate that the reception side sampling frequency is smaller than the transmission side sampling frequency.

  Then, the symbol synchronization detection unit 44, for example, the absolute value of the difference between the average value of the deviation angles θ where k is 17, 20, 21, 24 and the average value of the deviation angles θ where k is 18, 19, 22, 23. Is calculated as the magnitude of the error.

  On the other hand, as shown in the region Rf of FIG. 13, the symbol synchronization detection unit 44 indicates that k is a smaller value of the shift angle θ of 17, 20, 21, 24, and k is 18, 19, 22, 23. When the shift angle θ indicates a larger value, it is determined that the reception side sampling frequency is higher than the transmission side sampling frequency.

  Then, the symbol synchronization detection unit 44, for example, the absolute value of the difference between the average value of the deviation angles θ where k is 17, 20, 21, 24 and the average value of the deviation angles θ where k is 18, 19, 22, 23. Is calculated as the magnitude of the error.

  The symbol synchronization detection unit 44 creates frequency error information SE including the determination result and the magnitude of the error, and outputs the created frequency error information SE to the interpolator 41.

  Referring to FIG. 5 again, when interpolator 41 receives frequency error information SE from symbol synchronization detector 44, interpolator 41 obtains baseband signals DI and DQ when the sampling frequency is adjusted based on the received frequency error information SE. calculate.

  More specifically, the interpolator 41 acquires the determination result and the error magnitude from the frequency error information SE, and calculates the adjustment ratio based on the acquired determination result and the error magnitude.

  Specifically, for example, when the determination result indicates that the reception-side sampling frequency is smaller than the transmission-side sampling frequency, the adjustment ratio is greater than 1. On the other hand, when the determination result indicates that the reception side sampling frequency is higher than the transmission side sampling frequency, the adjustment ratio is smaller than 1.

  The interpolator 41 acquires the tap coefficient corresponding to the calculated adjustment ratio from the tap coefficient holding unit 46.

  The interpolator 41 multiplies the values of the baseband signals DI and DQ received and held from the RRFs 15I and 15Q by the tap coefficient, and outputs the processed baseband signals DI and DQ to the digital LPFs 42I and 42Q, respectively.

  The change for each symbol of the shift angle θ for each baseband signal DI, DQ received by the symbol synchronization detection unit 44 via the digital LPFs 42I, 42Q and the complex multiplier 43 is as shown by a straight line SL2 shown in FIG.

  That is, since good synchronization with the satellite broadcast wave can be established, even when a satellite broadcast wave modulated by the 32 APSK (Amplitude and Phase Shift Keying) modulation method and the 16 APSK modulation method is received, the satellite broadcast The logical value of each symbol can be obtained well from the wave.

  Referring to FIG. 3 again, LDPC decoding unit 17 performs a low density parity check on baseband signals DI and DQ received from complex multiplier 43, and streams a stream based on processed baseband signals DI and DQ. Transmit to the processing device 151.

  The satellite broadcast receiving apparatus 101 is configured to adjust the sampling frequency after adjusting the carrier frequency, but is not limited thereto, and is configured to adjust the carrier frequency after adjusting the sampling frequency. There may be a configuration in which the sampling frequency and the carrier frequency are adjusted simultaneously.

  In the satellite broadcast receiving apparatus according to the embodiment of the present invention, the interpolator 41 and the complex multiplier 43 in the adjustment unit 45 are configured to adjust the sampling frequency and the carrier frequency in the digital circuit, respectively. It is not limited. In the satellite broadcast receiving apparatus 101, the adjustment unit 45 adjusts the sampling frequency and the carrier frequency in the analog circuit by adjusting the clock frequency of the clock generation circuit 14 and the oscillation frequency of the reference signal source oscillator 13, respectively. May be.

  In the satellite broadcast receiving apparatus according to the embodiment of the present invention, the symbol synchronization detection unit 44 is configured to detect the carrier frequency error and the sampling frequency error using the pattern of the frame synchronization signal F1. However, the present invention is not limited to this. The symbol synchronization detection unit 44 may be configured to detect a carrier frequency error and a sampling frequency error using a frame synchronization signal or slot synchronization signal including the value of AD0799h instead of the frame synchronization signal F1.

  By the way, it is possible to detect a carrier frequency error and a sampling frequency error by using the technique described in Non-Patent Document 1 for a multicarrier modulation scheme such as OFDM. However, the above technique cannot be applied to single carrier satellite broadcast waves.

  In contrast, in the satellite broadcast receiving apparatus according to the embodiment of the present invention, quadrature demodulator 11 outputs a demodulated signal obtained by demodulating the received communication signal according to ARIB STD-B44. The A / D converter 12 converts the demodulated signal received from the quadrature demodulator 11 into a digital signal. The symbol synchronization detection unit 44 uses a predetermined synchronization pattern indicated by a plurality of BPSK-modulated symbols included in the digital signal converted by the A / D converter 12, so that the error of the carrier frequency in the quadrature demodulator 11. And the error of the sampling frequency in the A / D converter 12 is detected. Then, the adjustment unit 45 adjusts the carrier frequency and the sampling frequency based on the detection result of the symbol synchronization detection unit 44.

  In this way, with the configuration in which the predetermined synchronization pattern is BPSK-modulated, the predetermined synchronization pattern can be demodulated without performing special processing such as other clock synchronization processing. A carrier frequency error for a single carrier is detected by using a predetermined synchronization pattern to detect a carrier frequency error and a sampling frequency error in a quadrature demodulator 11 that demodulates a single carrier communication signal according to ARIB STD-B44. In addition, the sampling frequency error can be easily detected. In addition, synchronization with the communication signal according to ARIB STD-B44 can be established by adjusting the carrier frequency and the sampling frequency based on the detection result. Therefore, it is possible to perform synchronization processing for a single carrier with a simple configuration.

  Moreover, in the satellite broadcast receiving apparatus according to the embodiment of the present invention, the symbol synchronization detection unit 44 calculates an error in sampling frequency based on a plurality of symbols indicating successive logical values among a plurality of symbols indicating synchronization patterns. To detect.

  In the case where an error is included in the sampling frequency, in the constellation, characteristic positional deviations of a plurality of symbols indicating continuous logical values are observed. An error in the sampling frequency can be correctly detected from such a characteristic positional deviation.

  Moreover, in the satellite broadcast receiving apparatus according to the embodiment of the present invention, the symbol synchronization detection unit 44 includes a plurality of symbols indicating a logical value of zero and a continuous one of a plurality of symbols indicating a synchronization pattern. An error in sampling frequency is detected based on a plurality of symbols indicating logical values.

  In the case where an error is included in the sampling frequency, in the constellation, a more characteristic positional shift of a plurality of symbols indicating a continuous zero logical value and a plurality of symbols indicating a continuous one logical value is observed. An error in the sampling frequency can be detected more correctly from such a characteristic positional deviation.

  In the satellite broadcast receiving apparatus according to the embodiment of the present invention, the adjustment unit 45 calculates a complex multiplier 43 that calculates a digital signal when the carrier frequency is adjusted, and a digital signal when the sampling frequency is adjusted. Interpolator 41.

  With such a configuration, the entire satellite broadcast receiving apparatus 101 can be realized by a digital circuit, so that the carrier frequency and sampling frequency can be adjusted by software. That is, all processes can be completed within the digital circuit of the same clock without adjusting the carrier frequency and sampling frequency by hardware such as PLL. Thereby, the satellite broadcast receiving apparatus 101 can be easily realized using a program logic IC such as an FPGA. In addition, the prototype of the apparatus can be easily made and the entire apparatus can be simplified.

  The above embodiment should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The above description includes the following features.

[Appendix 1]
A quadrature demodulator that outputs a demodulated signal obtained by demodulating a received communication signal according to ARIB (Association of Radio Industries and Businesses) STD-B44;
An A / D (Analog-to-Digital) converter that converts the demodulated signal received from the quadrature demodulator into a digital signal;
An error of a carrier frequency in the quadrature demodulator using a predetermined synchronization pattern indicated by a plurality of BPSK (Binary Phase Shift Keying) symbols included in the digital signal converted by the A / D converter, And a detector for detecting an error in sampling frequency in the A / D converter,
An adjustment unit for adjusting the carrier frequency and the sampling frequency based on the detection result of the detection unit;
The detection unit detects an error of the carrier frequency using a logic value pattern of 0101 0010 1111 1000 0110 0110, which is indicated by a symbol of a π / 2 BPSK modulated frame synchronization signal,
The satellite broadcast receiving apparatus, wherein the detection unit detects an error in the carrier frequency using a logical value pattern of 0110 0110 indicated by a symbol of the frame synchronization signal.

DESCRIPTION OF SYMBOLS 1 Analog signal processing part 2 Digital signal processing part 11 Quadrature demodulator 12 A / D converter 13 Reference signal source oscillator 14 Clock generation circuit 15I, 15Q RRF
16 synchronization processing unit 17 LDPC decoding unit 31 AGC amplifier 32 PLL unit 33I, 33Q mixer 34I, 34Q low-pass filter 41 interpolator 42I, 42Q digital LPF
43 Complex Multiplier 44 Symbol Synchronization Detection Unit 45 Adjustment Unit 46 Tap Coefficient Holding Unit 101 Satellite Broadcast Reception Device 111 Antenna 151 Stream Processing Device 301 Satellite Broadcast Reception System

Claims (4)

A quadrature demodulator that outputs a demodulated signal obtained by demodulating a received communication signal according to ARIB (Association of Radio Industries and Businesses) STD-B44;
An A / D (Analog-to-Digital) converter that converts the demodulated signal received from the quadrature demodulator into a digital signal;
An error of a carrier frequency in the quadrature demodulator using a predetermined synchronization pattern indicated by a plurality of BPSK (Binary Phase Shift Keying) symbols included in the digital signal converted by the A / D converter, And a detector for detecting an error in sampling frequency in the A / D converter,
A satellite broadcast receiving apparatus comprising: an adjustment unit that adjusts the carrier frequency and the sampling frequency based on a detection result of the detection unit.   The satellite broadcast receiving apparatus according to claim 1, wherein the detection unit detects an error in the sampling frequency based on a plurality of symbols indicating successive logical values among a plurality of symbols indicating the synchronization pattern.   The detection unit detects an error of the sampling frequency based on a plurality of symbols indicating a continuous zero logic value and a plurality of symbols indicating a continuous 1 logic value among a plurality of symbols indicating the synchronization pattern. The satellite broadcast receiver according to claim 2.   The adjustment unit includes a complex multiplier that calculates the digital signal when the carrier frequency is adjusted, and an interpolator that calculates the digital signal when the sampling frequency is adjusted. The satellite broadcast receiver according to any one of the above.

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