JP2018018933A - Debonding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a debonding device used for improving producibility of a semiconductor device.SOLUTION: A debonding device for exfoliating an adhesive layer, formed on the other side of a wiring board mounting a semiconductor chip on one side, from the wiring board includes a peeling tape placed in the transport direction of the wiring board, and coming into contact with the surface of the adhesive layer opposite to the surface where the wiring board is formed, a pair of rolls clamping the wiring board on which the adhesive layer is formed and the peeling tape, a pair of spike rolls placed farther on the transport direction side than the pair of rolls, and sandwiching the wiring board on which the adhesive layer is formed and the peeling tape, and a peeling part placed farther on the transport direction than the pair of rolls, and peeling the adhesive layer from the wiring board.SELECTED DRAWING: Figure 9

Description

  The present invention relates to a debonding apparatus.

  In recent years, semiconductor devices using semiconductor chips and external connection members have been used in various fields such as electronic devices and automobiles. Patent Document 1 below describes a method of manufacturing a semiconductor device in which an external connection member having a rewiring layer and an external connection terminal is directly formed on a semiconductor chip. In this manufacturing method, an external connection member having a rewiring layer and external connection terminals is formed in the semiconductor chip region. A semiconductor device provided by the manufacturing method is called a Fan-in type WLP (Wafer Level Package).

  In Patent Document 2 below, there is an external connection member that forms an insulating layer that covers the periphery of a semiconductor chip fixed to a support substrate, and that has a rewiring layer and an external connection terminal on the semiconductor chip and the insulating layer. A method of manufacturing the semiconductor device to be formed is described. In this manufacturing method, the external connection member having the rewiring layer and the external connection terminals is also formed in the peripheral region outside the outer edge of the semiconductor chip. A semiconductor device provided by the manufacturing method is called a fan-out type WLP.

  Patent Document 3 listed below provides a continuous supply in which a heat resistant film is automatically peeled downward from a molded product in which a semiconductor chip is sealed with a mold resin, and the molded product from which the heat resistant film has been peeled is conveyed to a dicing process. An apparatus is described.

JP-A-11-111896 JP 2011-187473 A JP 2014-7315 A

  An object of the present invention is to provide a debonding apparatus that is used to improve the manufacturing efficiency of a semiconductor device.

  In order to achieve the above object, the present invention provides a debonding apparatus for peeling an adhesive layer formed on the other side of a wiring board having a semiconductor chip mounted on one side from the wiring board, in the direction of transport of the wiring board And a pair of rolls sandwiching the wiring board on which the adhesive layer is formed and the peeling tape, and a pair of rolls. A pair of spike rolls sandwiched between the wiring board on which the adhesive layer is formed and the peeling tape that are arranged on the conveyance direction side, and a peeling unit that is arranged closer to the conveyance direction side than the pair of spike rolls and peels the adhesive layer from the wiring board It is characterized by providing.

  Moreover, it is preferable that a pair of spike roll peels the edge part of the conveyance direction side of an contact bonding layer.

  The pair of spike rolls is preferably formed of a metal material.

  Moreover, it is preferable that a peeling part guides a peeling tape in the direction orthogonal to a conveyance direction.

  According to the debonding apparatus of the present invention, the manufacturing efficiency of the semiconductor device can be improved.

FIG. 1 is a diagram for explaining the semiconductor device of this embodiment. FIG. 2 is a diagram illustrating the wiring board according to the present embodiment. 3A to 3C are diagrams for explaining an example of a method for manufacturing a wiring board according to the present embodiment. 4A to 4C are diagrams for explaining an example of a method for manufacturing a wiring board according to the present embodiment. 5A to 5C are views for explaining a method of manufacturing the semiconductor device according to this embodiment. 6A to 6C are views for explaining a method of manufacturing the semiconductor device according to this embodiment. 7A to 7C are views for explaining a method of manufacturing the semiconductor device according to this embodiment. FIG. 8 is a schematic diagram illustrating an example of a process of peeling the photosensitive curable resin adhesive layer by a conventional debonding apparatus. FIG. 9 is a schematic diagram illustrating an example of a process for peeling the photosensitive cured resin adhesive layer by the debonding apparatus according to the present embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals are used for the same elements or elements having the same functions, and redundant description is omitted.

  FIG. 1 is a diagram for explaining the semiconductor device of this embodiment. As shown in FIG. 1, the semiconductor device 1 includes a wiring board 21, a semiconductor chip 22, an underfill 24, a mold resin 25, and a plurality of external connection terminals 31. Details of the wiring board 21 will be described later.

  The semiconductor chip 22 is an integrated circuit (IC or LSI) having, for example, a transistor or a diode formed on the surface of a semiconductor substrate, and has a substantially rectangular parallelepiped shape. As the semiconductor substrate used for the semiconductor chip 22, a substrate mainly composed of an inorganic substance such as a silicon substrate (Si substrate), a gallium nitride substrate (GaN substrate), or a silicon carbide substrate (SiC substrate) is used. In the present embodiment, a silicon substrate is used as the semiconductor substrate. The coefficient of linear expansion (CTE: Coefficient of Thermal Expansion) of the semiconductor chip 22 formed using the silicon substrate is about 2 to 4 ppm / ° C. (eg, 3 ppm / ° C.). The linear expansion coefficient in the present embodiment has a length that changes in response to a temperature rise within a temperature range of 20 ° C. to 260 ° C., for example.

  Protruding electrodes (also referred to as bumps) 23 are provided on the surface 22 a of the semiconductor chip 22. The semiconductor chip 22 is electrically connected to a wiring pattern (not shown) exposed on one main surface 21 a of the wiring substrate 21 through the protruding electrodes 23. The protruding electrode 23 is made of, for example, a metal such as Au, Ag, Cu, Al, or an alloy thereof, a metal composite obtained by applying Cu plating to Cu, or Sn, Sn—Pb, Sn—Ag, Sn—Cu, Sn. -Ag-Cu, Sn-Bi, or Au-based solder is used. The protruding electrode 23 may be disposed in the entire region of the semiconductor chip 22 or may be disposed in the peripheral region of the semiconductor chip 22. Examples of a method for connecting the semiconductor chip 22 and the wiring substrate 21 to each other include a wire bonding method and a flip chip method. In the present embodiment, the semiconductor chip 22 and the wiring substrate 21 are connected to each other by a flip-chip method from the viewpoint of reducing the mounting area and improving work efficiency.

  The underfill 24 is an adhesive used for fixing and sealing the semiconductor chip 22 on the wiring substrate 21. As the underfill 24, for example, one of epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin or a mixture of two or more of these resins, silica as a filler, A material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added is used. The underfill 24 may be liquid or film-shaped.

  The mold resin 25 is a sealing resin used for covering and protecting the semiconductor chip 22. As the mold resin 25, for example, one of epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin or a mixture of two or more of these resins, silica as a filler, A material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added is used.

  The external connection terminal 31 is provided on the other main surface 21 b of the wiring board 21. The external connection terminal 31 is electrically connected to the semiconductor chip 22 via a wiring pattern provided in the wiring substrate 21. The external connection terminal 31 is formed of solder such as Sn, Sn—Pb, Sn—Ag, Sn—Cu, Sn—Ag—Cu, or Sn—Bi. When the external connection terminal 31 is formed of solder, before the external connection terminal 31 is formed, for example, Ni plating, Au plating, or Sn is applied to a portion where the wiring pattern is exposed on the other main surface 21b of the wiring substrate 21. Plating may be applied, pre-solder treatment may be applied, or organic coating treatment such as OSP (Organic Solderability Preservative) may be applied.

  FIG. 2 is a diagram illustrating the wiring board according to the present embodiment. As shown in FIG. 2, the wiring board laminate 11 includes a support 12, an adhesive layer 13, a conductive layer 30, and a wiring board 21. The wiring board 21 includes a first resin layer 14, connection pads 15, a wiring pattern 18, a second resin layer 19, and connection terminals 20. The thickness of the wiring board 21 may be, for example, 0.001 mm or more and 1 mm or less, 0.01 mm or more and 0.8 mm or less, 0.03 mm or more and 0.5 mm or less, and 0 0.001 mm to 0.8 mm, 0.001 mm to 0.5 mm, 0.01 mm to 0.8 mm, 0.01 mm to 0.5 mm There may be. When the thickness of the wiring board 21 is 0.001 mm or more, the wiring pattern 18 provided on the wiring board 21 can be protected by the first resin layer 14 and the second resin layer 19. When the thickness of the wiring board 21 is 1 mm or less, it is possible to suppress the warping of the wiring board stacked body 11 due to the difference in the linear expansion coefficient between the support 12 and the wiring board 21. In the present specification, the thickness of the wiring board 21 is a dimension in the thickness direction from the interface with the conductive layer 30 to the uppermost surface of the second resin layer 19 or the wiring pattern 18. That is, the “thickness” is a length along a direction perpendicular to the main surface of the wiring board laminate 11.

  The support 12 is a substrate made of a material having a property of transmitting light (transparency), for example. The main surface 12a of the support 12 has, for example, a substantially rectangular shape, a substantially circular shape, or a substantially elliptical shape. The range of the wavelength of light transmitted through the support 12 may be, for example, 300 nm or more and 2000 nm or less, or 300 nm or more and 1100 nm or less. The support 12 may have a property of transmitting a specific wavelength such as laser light. As the support 12, for example, a glass substrate is used. As the glass, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, sapphire glass, or the like is used. The linear expansion coefficient of the glass is preferably a value close to the linear expansion coefficient of the semiconductor chip 22 described above, and may be, for example, −1 ppm / ° C. or more and 10.0 ppm / ° C. or less, and 0.5 ppm / ° C. or more and 5.0 ppm / ° C. It is better if it is below ℃. The maximum height roughness Rz on the main surface 12a of the support 12 based on JIS B 0601: 2013 may be, for example, 0.01 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less. When the maximum height roughness Rz of the main surface 12a of the support 12 is 0.01 μm or more, an increase in cost for preparing the support 12 can be suppressed. When the maximum height roughness Rz of the main surface 12a of the support 12 is 5 μm or less, disconnection, short circuit, and the like of the wiring pattern 18 due to the unevenness of the main surface 12a can be suppressed.

  The adhesive layer 13 includes a first adhesive layer 13a and a photosensitive curable resin adhesive layer 13b. The 1st adhesive bond layer 13a is provided on the main surface 12a of the support body 12, and contains resin which can be decomposed | disassembled by irradiation of light. Since the light in the present embodiment is laser light, a resin that can be thermally decomposed when irradiated with laser light is used as the resin contained in the first adhesive layer 13a. Examples of the resin contained in the first adhesive layer 13a include one of epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a resin in which two or more of these resins are mixed. Etc. are used. The thickness of the first adhesive layer 13a is, for example, 0.1 μm to 10 μm.

  The photosensitive curable resin adhesive layer 13b is provided on the first adhesive layer 13a, and is a layer for bonding the support 12, the wiring substrate 21, and the conductive layer 30 via the first adhesive layer 13a. It contains a resin that can be cured in response to light. Since the light in this embodiment is UV light, a resin that can be cured by being irradiated with UV light is used as the resin included in the photosensitive curable resin adhesive layer 13b. Examples of the resin contained in the photosensitive curable resin adhesive layer 13b include one of urethane acrylate, acrylic resin acrylate, epoxy acrylate, epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin. A resin in which two or more of these resins are mixed is used. The thickness of the photosensitive curable resin adhesive layer 13b is, for example, 1 μm to 100 μm.

  The conductive layer 30 is a metal layer provided on the adhesive layer 13. For example, one type of conductive metal material such as Cu, Au, Ag, Sn, Ni, or a metal in which two or more of these metals are mixed is used. Is used. The thickness of the conductive layer 30 is, for example, 0.001 μm to 50 μm.

  The first resin layer 14 is a resin layer provided on the conductive layer 30 and has an opening 14a. The first resin layer 14 includes, for example, a resin material such as epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer, or silicone, and a composite material thereof. Moreover, the 1st resin layer 14 may contain the inorganic filler or the organic filler. The 1st resin layer 14 may also contain the material which the epoxy resin and glass fiber combined, for example. As the first resin layer 14, for example, a resist made of an epoxy insulating resin or the like may be used. The thickness of the first resin layer 14 is, for example, 0.5 μm to 30 μm.

  The connection pad 15 is a conductive layer made of a metal such as Au, and is provided in the opening 14 a of the first resin layer 14. The connection pad 15 may be in contact with the adhesive layer 13 in the opening 14a. The thickness of the connection pad 15 is, for example, 0.001 μm to 3 μm.

  The wiring pattern 18 is a conductive layer made of a metal such as Au, Cu, or Ni, and is provided on the first resin layer 14 and the connection pad 15. The wiring pattern 18 is electrically connected to the connection pad 15 through the opening 14 a of the first resin layer 14. The thickness of the wiring pattern 18 is, for example, 1 μm to 20 μm.

  The second resin layer 19 is a resin layer provided on the first resin layer 14, the connection pad 15, and the wiring pattern 18, and has an opening 19a. The second resin layer 19 includes, for example, a resin material such as epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer, or silicone, and a composite material thereof. Further, the second resin layer 19 may contain an inorganic filler or an organic filler. The second resin layer 19 may include, for example, a material in which an epoxy resin and glass fiber are combined. As the second resin layer 19, for example, a solder resist made of an epoxy insulating resin or the like may be used. The opening 19 a provided in the second resin layer 19 does not overlap the opening 14 a of the first resin layer 14 and is provided so as to expose a part of the wiring pattern 18. The thickness of the second resin layer 19 is, for example, 0.5 μm to 30 μm.

  The connection terminal 20 is a terminal provided in the opening 19 a of the second resin layer 19, and is provided so that the wiring pattern 18 can be easily electrically connected to the protruding electrode 23 of the semiconductor chip 22. The connection terminal 20 is formed of eutectic solder or lead-free solder (Sn—Ag, Sn—Cu, Sn—Ag—Cu, Sn—Bi, or the like), for example. The connection terminal 20 may be a terminal in which eutectic solder or lead-free solder is provided on conductive layers made of various metals. Further, the connection terminal 20 may be formed by performing plating treatment of Ni, Au, Sn or the like on the opening 19a or organic coating treatment of OSP or the like. Further, the connection terminal 20 may be formed by performing gold plating on the wiring pattern 18. In this case, the conductivity of the connection terminal 20 is improved, and corrosion of the connection terminal 20 is suppressed. The protruding electrode 23 of the semiconductor chip 22 is a gold ball bump (for example, a gold bump made of Au, an alloy containing Au, or a metal composite having a surface plated with Au, or a bump formed of Au-based solder). In this case, the bondability between the protruding electrode 23 and the connection terminal subjected to gold plating is improved.

  Next, a method for manufacturing a wiring board according to the present embodiment will be described with reference to FIGS. 3 (a) to 3 (c) and FIGS. 4 (a) to 4 (c). FIGS. 3A to 3C and FIGS. 4A to 4C are diagrams illustrating an example of a method for manufacturing a wiring board.

  First, as shown in FIG. 3A, a first adhesive layer 13 a and then a photosensitive curable resin adhesive layer 13 b are formed on the main surface 12 a of the support 12. The first adhesive layer 13a is formed by a known method such as a printing method, a vacuum press method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. Formed and cured after heating. The photosensitive curable resin adhesive layer 13b is a known method such as a printing method, a vacuum press method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. Is formed.

  Next, the conductive layer 30 is formed on the photosensitive curable resin adhesive layer 13b. The conductive layer 30 is laminated by a known method such as a vacuum pressing method, a vacuum laminating method, or a roll laminating method.

  Next, as shown in FIG. 3B, after providing the first resin layer 14 on the adhesive layer 13, an opening 14 a is formed in the first resin layer 14. And the connection pad 15 is formed in the said opening part 14a. The first resin layer 14 is formed by a known method such as a printing method, a vacuum pressing method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. Is done. The opening 14 a is formed by removing a part of the first resin layer 14 by, for example, performing laser irradiation or photolithography on the first resin layer 14. The connection pad 15 is provided by plating, for example. The connection pad 15 is not necessarily provided.

  Next, as shown in FIG. 3C, the seed layer 16 is provided on the first resin layer 14 and the connection pad 15. The seed layer 16 is connected to the connection pad 15 through the opening 14 a of the first resin layer 14. The seed layer 16 is formed by, for example, an electroless plating method, a sputtering method, a CVD method, or the like. Alternatively, the seed layer 16 may be formed by attaching a conductive foil made of Cu or the like to the first resin layer 14. The seed layer 16 is formed of, for example, a Cu layer, a Cu layer plated with Ni, a Cu layer plated with Au, a Cu layer plated with solder, an Al layer, or an Ag / Pd alloy layer. In the present embodiment, a Cu layer is used from the viewpoints of cost, electrical characteristics, and manufacturability.

  Next, as shown in FIG. 4A, a resist 17 having an opening 17 a is provided on the seed layer 16. Then, a part of the seed layer 16 exposed by the opening 17a is thickened by, for example, performing a plating process. Here, in the seed layer 16, a relatively thin region that has not been subjected to plating or the like is referred to as a first region 16a, and a relatively thick region that has been subjected to plating or the like is referred to as a second region 16b. The first region 16 a is a region existing between the first resin layer 14 and the resist 17. The second region 16b is formed of, for example, a Cu layer, a Cu layer plated with Ni, a Cu layer plated with Au, a Cu layer plated with solder, an Al layer, an Ag / Pd alloy layer, or the like. In the present embodiment, a Cu layer is used from the viewpoints of cost, electrical characteristics, and manufacturability. Further, as the resist 17, for example, a negative type or positive type photoresist is used.

  Next, as shown in FIG. 4B, the wiring pattern 18 is formed by removing the resist 17 and the first region 16 a in the seed layer 16. The resist 17 may be removed from the first resin layer 14 by, for example, lift-off, or may be removed by etching. The first region 16a is removed by wet etching or dry etching, for example. By removing the first region 16 a, the second region 16 b becomes the wiring pattern 18. A part of the second region 16b may be etched simultaneously with the first region 16a. That is, the wiring pattern 18 in the present embodiment is formed by a semi-additive method. In the semi-additive method, a seed layer such as a Cu layer is formed, a resist having a desired pattern is formed on the seed layer, and an exposed portion of the seed layer is thickened by an electrolytic plating method or the like to remove the resist. Thereafter, a thin seed layer is etched to obtain a wiring pattern.

  4B, after the wiring pattern 18 is formed, the second resin layer 19 is formed on the first resin layer 14 and the wiring pattern 18, and an opening is formed in a part of the second resin layer 19. A portion 19a is formed. The second resin layer 19 is formed by a known method such as a printing method, a vacuum pressing method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. Is done. The opening 19a is formed by removing a part of the second resin layer 19 by performing laser irradiation or photolithography on the second resin layer 19, for example. A part of the wiring pattern 18 is exposed by forming the opening 19a.

  Finally, as shown in FIG. 4C, the connection terminal 20 is formed in the opening 19a. The connection terminal 20 is provided by supplying eutectic solder or lead-free solder into the opening 19a, for example. As described above, the wiring board laminate 11 including the support 12, the adhesive layer 13, the wiring board 21 including the first resin layer 14, the connection pads 15, the wiring pattern 18, the second resin layer 19, and the connection terminals 20. Form.

  Next, with reference to FIGS. 5A to 5C, FIGS. 6A to 6C, and FIGS. 7A to 7C, a method of manufacturing the semiconductor device according to the present embodiment will be described. explain. FIGS. 5A to 5C, FIGS. 6A to 6C, and FIGS. 7A to 7C are diagrams illustrating an example of a method for manufacturing a semiconductor device.

  First, as shown in FIG. 5A, a wiring board laminate 11 having a support 12, an adhesive layer 13, a conductive layer 30, and a wiring board 21 is prepared. The wiring board laminated body 11 is equivalent to the wiring board laminated body 11 shown by FIG. 2 or FIG.

  Next, as shown in FIG. 5B, a plurality of semiconductor chips 22 are mounted on the wiring board 21. Specifically, the semiconductor chip 22 is mounted on one main surface 21a of the wiring board 21 in the wiring board laminate 11 by a flip chip method. When mounting the semiconductor chip 22 on the wiring board 21, the protruding electrode 23 of the semiconductor chip 22 and the connection terminal 20 (see FIG. 2) of the wiring board 21 are connected to each other. Further, by providing the underfill 24 between the semiconductor chip 22 and the wiring substrate 21, the semiconductor chip 22 is fixed to the wiring substrate 21, and the gap between the semiconductor chip 22 and the wiring substrate 21 is sealed. The underfill 24 may be supplied between the semiconductor chip 22 and the wiring substrate 21 after the semiconductor chip 22 is mounted on the wiring substrate 21. Alternatively, the underfill 24 may be attached to the semiconductor chip 22 or the wiring substrate 21 in advance, and the sealing with the underfill 24 may be completed simultaneously with mounting the semiconductor chip on the wiring substrate 21. For example, the semiconductor chip 22 and the wiring substrate 21 are fixed and sealed by the underfill 24 by applying a curing process to the underfill 24 by heating or light irradiation. The underfill 24 is not necessarily provided.

  Next, as shown in FIG. 5C, a mold resin 25 is formed on one main surface 21 a of the wiring substrate 21. At this time, the semiconductor chip 22 is embedded with the mold resin 25. The mold resin 25 is formed by a known method such as a transfer molding method or a potting method. The semiconductor chip 22 may be covered so as to be sealed with the mold resin 25.

  Next, as shown in FIG. 6A, the first adhesive layer 13 a is irradiated with the laser light L <b> 1 through the support 12. The support 12 may be irradiated with the laser beam L1 or a desired position of the support 12 may be irradiated with the laser beam L1. In this embodiment, from the viewpoint of reliably decomposing the resin in the first adhesive layer 13a, the entire support 12 is irradiated with the laser beam L1 while reciprocating linearly. The laser beam L1 may have a wavelength of 300 nm to 2000 nm, for example, may have a wavelength of 300 nm to 1500 nm, and may have a wavelength of 300 nm to 1100 nm. As an example of a device that emits laser light L1, a YAG laser device that emits light with a wavelength of 1064 nm, a YAG laser device that emits light with a harmonic wave twice as high as 532 nm, or light with a wavelength of 780 to 1300 nm is emitted. And a semiconductor laser device. The support 12 has transparency and transmits the laser light L1. Therefore, the energy of the laser beam L1 that has passed through the support 12 is absorbed by the first adhesive layer 13a. The absorbed energy of the laser beam L1 is converted into thermal energy in the first adhesive layer 13a. By this thermal energy, the resin of the first adhesive layer 13a reaches the thermal decomposition temperature and is thermally decomposed. As a result, the force by which the first adhesive layer 13a adheres the support 12 and the wiring board 21 is weakened.

  Next, as shown in FIG. 6B, the support 12 is peeled from the wiring board 21. The method of peeling the support 12 from the wiring substrate 21 may be performed manually or using a machine. Since the photosensitive curable resin adhesive layer 13 b is attached to the wiring substrate 21 peeled from the support 12, the photosensitive curable resin adhesive layer 13 b is peeled from the wiring substrate 21. The detail of the peeling process of the photosensitive cured resin adhesive layer 13b will be described later.

  Next, as shown in FIG. 7A, a plurality of external connection terminals 31 are formed on the other main surface 21 b of the wiring board 21. Specifically, the external connection terminals 31 are formed in portions corresponding to the connection pads 15 (see FIG. 2) of the wiring board 21. For example, the external connection terminal 31 is formed by a solder ball mounting method or the like.

  Next, as shown in FIG. 7B, after the dicing tape 32 is attached to the mold resin 25, the laminate 21 and the mold resin 25 located in the region between the semiconductor chips 22 are cut and separated. Tidy up. For example, the laminate 21 and the mold resin 25 are cut using a dicing saw or a laser. As described above, the semiconductor device 1 is manufactured as shown in FIG.

  The wiring board laminate 11 according to the present embodiment described above includes the wiring board 21 that functions as an external connection member for connecting the semiconductor chip 22 in the semiconductor device 1 to an external device. Thereby, since the semiconductor chip 22 and the wiring substrate 21 having the external connection member can be separately manufactured, the manufacturing efficiency of the semiconductor device 1 is improved. Moreover, in this wiring board laminated body 11, the support body 12 has transparency. Thereby, resin is decomposed | disassembled by irradiating light to the 1st adhesive bond layer 13a via the support body 12, and the adhesive force of the 1st adhesive bond layer 13a can be weakened. Therefore, after bonding the semiconductor chip 22 and the wiring board 21 of the wiring board laminate 11, the support 12 can be easily peeled from the wiring board 21, and the semiconductor device 1 manufactured using the wiring board 21. Can be made thinner. Further, by manufacturing the semiconductor device 1 using the wiring board laminate 11 having the support 12, the wiring board 21 can be easily handled.

  Further, the linear expansion coefficient of the support 12 may be −1 ppm / ° C. or more and 10 ppm / ° C. or less. In this case, since the semiconductor chip 22 is manufactured from a substrate mainly composed of an inorganic substance such as a silicon substrate, the linear expansion coefficient of the semiconductor chip 22 and the linear expansion coefficient of the support 12 are close to each other. For this reason, it is possible to suppress misalignment that occurs when the semiconductor chip 22 is mounted on the wiring substrate 21. Therefore, it becomes possible to prevent the semiconductor chip 22 from being mounted on the wiring substrate 21 and to destroy the portion where the semiconductor chip 22 and the wiring substrate 21 are joined.

  The support 12 may be a glass substrate. In this case, the support 12 is inexpensive and high in strength, and the support 12 can be easily enlarged. Further, the roughness of the surface of the support 12 can be easily adjusted.

  The maximum height roughness Rz of the main surface 12a of the support 12 may be not less than 0.01 μm and not more than 5 μm. In this case, since the unevenness of the wiring board 21 provided on the support 12 is reduced, disconnection and short circuit of the wiring pattern 18 can be suppressed.

  Further, the thickness of the wiring board 21 may be 0.001 mm or more and 1 mm or less. In this case, the wiring pattern 18 on the wiring board 21 can be protected by the first resin layer 14 and the second resin layer 19, and warping of the wiring board 21 can be suppressed.

  The light may be laser light L1. In this case, heat energy necessary for the resin in the first adhesive layer 13a to be decomposed can be sufficiently applied, and the adhesive force of the first adhesive layer 13a can be effectively weakened. Further, since the laser beam L1 is irradiated to the first adhesive layer 13a through the support 12, the adhesive force of the first adhesive layer 13a can be effectively increased without damaging the semiconductor chip 22 with the laser beam L1. Can weaken.

  In addition, the semiconductor device 1 manufactured using the wiring board laminate 11 according to the present embodiment includes the wiring board 21 from which the support 12 is removed and the protruding electrode 23 on the surface 22a. And a semiconductor chip 22 connected to the wiring pattern 18 of the wiring substrate 21 through the wiring board 21. In this semiconductor device 1, since the semiconductor chip 22 and the wiring substrate 21 that is an external connection member are separately manufactured, the manufacturing efficiency of the semiconductor device 1 is improved. In addition, since the support 12 in the wiring board stack 11 is removed from the wiring board 21, the semiconductor device 1 can be thinned.

  Further, the wiring pattern 18 and the semiconductor chip 22 may be connected to each other via a connection terminal 20 containing solder. In this case, even when a positional deviation occurs between the wiring pattern 18 and the semiconductor chip 22, the deviation can be filled with the solder included in the connection terminal 20, and the gap between the semiconductor chip 22 and the stacked body 21 can be filled. Connection failures that occur can be suppressed.

  The wiring board, the semiconductor device, and the method for manufacturing the semiconductor device are not limited to the above-described embodiments, and various other modifications are possible. For example, you may combine the said embodiment suitably. In addition, a plurality of semiconductor chips 22 stacked on the wiring board 21 may be mounted in a region of the wiring board 21 to be separated. Further, a member other than the semiconductor chip 22 (for example, a passive component such as a capacitor) may be mounted on the wiring board 21.

  For example, the opening 14a in the first resin layer 14 and the opening 19a in the second resin layer 19 may overlap each other. Furthermore, for example, the connection terminals 20 in the wiring board 21 are not necessarily provided.

  In addition, the wiring pattern 18 on the wiring board 21 is formed not only by the semi-additive method but also by a known method such as a subtractive method or a full additive method. Here, the subtractive method is a method in which a resist having a desired pattern is formed on a conductor layer such as a Cu layer, an unnecessary conductor layer is etched, and then the resist is removed to obtain a wiring pattern. In the full additive method, an electroless plating catalyst is adsorbed on the resin layer, a resist having a desired pattern is formed on the resin layer, and the catalyst is activated while leaving the resist as an insulating film. In this method, after a conductor such as Cu is deposited in the resist opening by the method, the resist is removed to obtain a desired wiring pattern.

  Further, a new wiring pattern and a third resin layer may be formed on the second resin layer 19. That is, the wiring board 21 may have three resin layers. Furthermore, by repeating the formation of the wiring pattern and the resin layer described above, it is possible to form a laminate 21 in which a large number of wiring patterns and resin layers are stacked.

(Peeling process of photosensitive curable resin adhesive layer)
FIG. 8 is a schematic diagram illustrating an example of a process of peeling the photosensitive curable resin adhesive layer by a conventional debonding apparatus.

  As shown in FIG. 8, the conventional debonding apparatus 140 includes a peeling tape 41, a pair of rolls 42, and a peeling portion 44. The peeling tape 42 is disposed along the conveying direction of the wiring substrate 21 on which the semiconductor chip 22 is mounted on one surface, and contacts the surface opposite to the surface on which the wiring substrate 21 of the photosensitive curable resin adhesive layer 13b is formed. . The pair of rolls 42 includes a metal roll 42 a on the wiring board 22 side and a rubber roll 42 b on the adhesive tape 41 side. The pair of rolls 42 is narrower than the thickness of the wiring board 21 between the rolls, and sandwiches the wiring board 22 on which the photosensitive cured resin adhesive layer 13b is formed and the peeling tape 41. The peeling unit 44 is disposed closer to the transport direction than the pair of rolls 42 and guides the peeling tape 41 in a direction orthogonal to the transport direction. The photosensitive curable resin adhesive layer 13b is peeled from the wiring board 21 by the peeling tape 41 adhered to the photosensitive curable resin adhesive layer 13b in the peeling portion 44 being guided in a direction orthogonal to the transport direction.

  However, if the photosensitive curable resin adhesive layer 13b is peeled only by the pair of rolls 42 having the metal roll 42a and the rubber roll 42b, a peeling failure may occur.

  FIG. 9 is a schematic diagram illustrating an example of a process of peeling the photosensitive curable resin adhesive layer by the debonding apparatus according to the present embodiment.

  As shown in FIG. 9, the debonding apparatus 40 according to the present embodiment includes a peeling tape 41, a pair of rolls 42, a pair of spike rolls 43, and a peeling portion 44. The debonding apparatus 40 according to this embodiment is different from the conventional debonding apparatus 140 described above in that it includes a pair of spike rolls 43.

  The pair of spike rolls 43 is arranged on the transport direction side with respect to the pair of rolls 42, and sandwiches the wiring substrate 21 on which the photosensitive curable resin adhesive layer 13b is formed and the peeling tape 41. At this time, the surface of the spike roll 43 comes into contact with the photosensitive curable resin adhesive layer 13b, so that the end of the photosensitive curable resin adhesive layer 13b on the conveyance direction side can be easily peeled off. For this reason, in the peeling part 44, since the photosensitive cured resin adhesive layer 13b is easily peeled off from the wiring board 21 with the peeled end portion of the photosensitive cured resin adhesive layer 13b as a cut, the photosensitive cured resin It is possible to suppress the occurrence of defective peeling of the adhesive layer 13b.

  The pair of spike rolls 43 is preferably formed of a metal material such as SUS (stainless steel), alumina, or chromium plating, but easily peels off the end of the photosensitive cured resin adhesive layer 13b on the conveyance direction side. If it can do, it is not limited to a metal material.

  Moreover, since it becomes possible to peel easily the edge part by the side of the conveyance direction of the photosensitive cured resin adhesive layer 13b with a pair of spike roll 43, the pressing force of the metal roll 42a can be reduced. Therefore, damage to the wiring board 21 on which the semiconductor chip 22 is mounted by the metal roll 42a can be suppressed.

  In addition, in the peeling part 44 which concerns on this embodiment, the structure which guides the peeling tape 41 in the direction orthogonal to a conveyance direction is not specifically limited, What is necessary is just to be able to guide the peeling tape 41 in the direction orthogonal to a conveyance direction.

  The invention is illustrated in more detail in the following examples. The present invention is not limited to these examples.

  As the support 12, soda glass having a thickness of 1 mm and a size of 300 × 300 mm was used. The 1st adhesive bond layer 13a which can be decomposed | disassembled by irradiation of light was formed using Sumitomo 3M Co., Ltd. Light-To-Heat-Conversion (LTHC) Release Coating. As the photosensitive curable resin adhesive layer 13b, UV-Curable-Adhesive LC3200 manufactured by Sumitomo 3M Limited was used. The first adhesive layer 13a and the photosensitive curable resin adhesive layer 13b were both formed by spin coating. The thickness of the first adhesive layer 13a was 1 μm when dry, and the thickness of the photosensitive curable resin adhesive layer 13b was 70 μm when wet. A 10 μm copper foil was used for the conductive layer.

  On the main surface of the support 12, a first adhesive layer 13a, a photosensitive curable resin adhesive layer 13b, a conductive layer 30, and a wiring substrate 21 were formed. Next, the semiconductor chip 22 was mounted on the wiring board 21. Next, the first adhesive layer 13 a was irradiated with laser light L <b> 1 via the support 12, and the support 12 and the first adhesive layer 13 a were peeled from the wiring substrate 21.

  Next, using the debonding apparatus 40 according to the embodiment including the peeling tape 41, the pair of rolls 42, the pair of spike rolls 43, and the peeling portion 44 shown in FIG. The cured resin adhesive layer 13b was peeled off. In the case of using the debonding apparatus 40 according to the example, in the wiring substrate 21 on which 100 photosensitive curable resin adhesive layers 13b are formed, the 100 photosensitive curable resin adhesive layers 13b are peeled off from the wiring substrate 21. We were able to.

  As a comparative example, using a conventional debonding apparatus 140 including a peeling tape 41, a pair of rolls 42, and a peeling portion 44 shown in FIG. 8, the wiring board 21 similar to the wiring board 21 according to the embodiment is used. The photosensitive cured resin adhesive layer 13b was peeled off. When the debonding apparatus 140 according to the comparative example is used, the photosensitive curable resin adhesive layer 13b can be peeled from the wiring substrate 21 in the wiring substrate 21 on which 100 photosensitive curable resin adhesive layers 13b are formed. There were 98 wiring boards 21 completed.

  The present invention can be suitably used for manufacturing a semiconductor device.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Wiring board laminated body 12 Support body 13 Adhesive layer 13a 1st adhesive layer 13b Photosensitive cured resin adhesive layer 14 1st resin layer 14a Opening part 15 of 1st resin layer 14 Connection pad 16 Seed layer 17 Resist 17a Opening 18 of resist 17 Wiring pattern 19 Second resin layer 19a Opening 20 provided in second resin layer 19 Connection terminal 21 Wiring substrate 22 Semiconductor chip 23 Projection electrode 24 Underfill 25 Mold resin 30 Conductive layer 31 External connection terminal 32 Dicing tape 40 Debonding device 41 Peeling tape 42 A pair of rolls 42a A metal roll 42b A rubber roll 43 A pair of spike rolls 44 Peeling part L1 Laser light

Claims (4)

A debonding apparatus for peeling an adhesive layer formed on the other surface of a wiring board having a semiconductor chip mounted on one surface from the wiring board,
A peeling tape that is disposed along the transport direction of the wiring board and that contacts the surface of the adhesive layer opposite to the surface on which the wiring board is formed;
A pair of rolls that sandwich the wiring board on which the adhesive layer is formed and the release tape;
A pair of spike rolls arranged between the pair of rolls on the transport direction side and sandwiching the wiring board on which the adhesive layer is formed and the release tape;
A debonding apparatus, comprising: a peeling portion that is disposed closer to the conveyance direction than the pair of spike rolls and peels the adhesive layer from the wiring board.   2. The debonding apparatus according to claim 1, wherein the pair of spike rolls peels an end of the adhesive layer on the transport direction side.   The debonding apparatus according to claim 1, wherein the pair of spike rolls is formed of a metal material.   The debonding apparatus according to any one of claims 1 to 3, wherein the peeling unit guides the peeling tape in a direction orthogonal to the transport direction.