JP2018005967A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a memory device capable of achieving both the high reliability and the small area of a data storage is provided.SOLUTION: When a power supply voltage is lower than a threshold value, a control device writes a voltage detection bit showing a first column address and a low voltage in a third memory cell (203) selected by a first row address, writes first one bit data in a first memory cell (201) selected by the first row address and the first column address, and writes a second one bit data of the logic inversion of the first one bit data in a second memory cell (202) selected by the first raw address. When the power supply source voltage is higher than the threshold value, maintains the voltage detection bit showing the column address and a standard voltage stored in the third memory cell selected by the first row address, and writes the first one bit data in the first memory cell selected by the first row address and the first column address.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a memory device.

  A semiconductor integrated circuit device having a cell array having a plurality of memory cells, a peripheral circuit for controlling the cell array, and an operation information determination circuit is known (see Patent Document 1). The operation information determination circuit determines one of a first operation mode in which one memory cell is used to store 1 bit and a second operation mode in which two semiconductor memory cells are used to store 1 bit. Then, operation information indicating whether the cell array is operated in the first or second operation mode is given to the peripheral circuit.

  A ferroelectric memory having a bit line pair having a bit line and a bit complementary line, a word line and a plate line arranged so as to cross the bit line pair, and a memory cell portion is known (patent). Reference 2). The memory cell portion has a first memory cell and a second memo cell. The first memory cell is a 1T / 1C type memory cell that stores data input from the bit line according to the potential of the corresponding word line and plate line and outputs data to the bit line. The second memory cell is a 1T / 1C type memory cell that stores data input from the bit complementary line according to the potential of the corresponding word line and plate line and outputs data to the bit complementary line. Further, the ferroelectric memory includes a determination word line and a determination plate line arranged so as to intersect with the bit line pair, and a determination memory cell unit. The determination memory cell unit stores complementary data input from the bit line and bit complementary line according to the potentials of the corresponding determination word line and determination plate line, and outputs complementary data to the bit line and bit complementary line. / 2C type memory cell for determination. The reference potential generation unit includes a first reference potential generation circuit and a second reference potential generation circuit. The first reference potential generating circuit applies a reference potential to the bit line when data is read from the second memory cell to the bit complementary line. The second reference potential generating circuit applies a reference potential to the bit complementary line when data is read from the first memory cell to the bit line. The sense amplifier compares the potentials of the bit line and the bit complementary line, applies a predetermined high level potential to the higher potential line, and applies a predetermined low level potential to the lower potential line. The control unit stores the data read from the determination memory cell in the first memory cell, and then reads the stored data from the first memory cell and writes the data to the determination memory cell with respect to the first memory cell. Do it. Then, the control unit stores the data read from the determination memory cell in the second memory cell, and then reads the stored data from the second memory cell and writes the data to the determination memory cell in the second memory cell. To do.

  There is also known a semiconductor memory device having a voltage monitoring circuit for monitoring a supplied voltage and a memory core having a plurality of memory cells and having a refresh function (see Patent Document 3). The register circuit sets a flag when the voltage monitoring circuit detects that the supplied voltage is equal to or lower than the required voltage when data is written to the memory cell of the memory core. At the same time, the address where the writing is performed is held. The control circuit causes the memory core to perform rewriting by the refresh operation for the address held in the register circuit in accordance with the flag set in the register circuit.

JP 2005-92915 A JP 2004-234788 A Japanese Patent Laying-Open No. 2015-153439

  The 1T1C type memory cell has a smaller area than the 2T2C type memory cell, but the reliability of data storage is low. Conversely, a 2T2C type memory cell has higher data storage reliability but a larger area than a 1T1C type memory cell.

  In one aspect, an object of the present invention is to provide a memory device that can achieve both high reliability of data storage and a small area.

  The memory device is selected by a row address and a column address, each of which is selected by a row address and a plurality of first memory cells each storing 1-bit data by one transistor and one capacitor. A plurality of second memory cells storing one-bit data by one transistor and one capacitor, and a plurality of second memory cells selected by the row address and storing a column address and a voltage detection bit indicating a standard voltage or a low voltage. When the memory cell 3, the voltage detection unit for detecting whether the power supply voltage is lower than the threshold, and the write request to the first row address and the first column address are input, the power supply voltage is lower than the threshold In the third memory cell selected by the first row address, the voltage detection indicating the first column address and the low voltage is performed. Write a bit, write first 1-bit data to a first memory cell selected by the first row address and the first column address, and select a second memory selected by the first row address When the second 1-bit data, which is the logical inversion of the first 1-bit data, is written to the cell and the power supply voltage is higher than a threshold value, it is stored in the third memory cell selected by the first row address. Maintaining the column address and the voltage detection bit indicating the standard voltage, and writing the first 1-bit data to the first memory cell selected by the first row address and the first column address; And a control unit for maintaining 1-bit data of the second memory cell selected by the first row address.

  The memory device is selected by a row address and a column address, each of which is selected by the row address and a plurality of first memory cells each storing 1-bit data by one transistor and one capacitor. Are a plurality of second memory cells that store 1-bit data by one transistor and one capacitor, and a plurality of memory cells that are selected by the row address and store a column address and a standard voltage or a low voltage detection bit. When a read request from the third memory cell and the first row address and the first column address is input, the voltage detection bit stored in the third memory cell selected by the first row address is A column array stored in the third memory cell indicating a low voltage and selected by the first row address. If the memory address is the same as the first column address, the first 1-bit data stored in the first memory cell selected by the first row address and the first column address, and Read data is output based on the second 1-bit data of the logical inversion of the first 1-bit data stored in the second memory cell selected by the first row address, and the first When the voltage detection bit stored in the third memory cell selected by the row address indicates a standard voltage, or the column stored in the third memory cell selected by the first row address If the address is different from the first column address, the address is stored in the first memory cell selected by the first row address and the first column address. And a control unit for outputting the read data based on the first 1-bit data being.

  The memory device is selected by a row address and a column address, each of which is selected by the row address and a plurality of first memory cells each storing 1-bit data by one transistor and one capacitor. Stores a plurality of second memory cells that store complementary 2-bit data by two transistors and two capacitors, and a column detection and a voltage detection bit indicating a standard voltage or a low voltage selected by the row address. When a plurality of third memory cells, a voltage detection unit for detecting whether or not the power supply voltage is lower than a threshold value, and a write request to the first row address and the first column address are input, the power supply voltage is When lower than the threshold value, the first column address and the low voltage are applied to the third memory cell selected by the first row address. A voltage detection bit is written, 1-bit data is written to a first memory cell selected by the first row address and the first column address, and a second memory is selected by the first row address Complementary 2-bit data is written to a cell, and when the power supply voltage is higher than a threshold value, a voltage detection indicating a column address and a standard voltage stored in a third memory cell selected by the first row address 1 bit data is written to the first memory cell selected by the first row address and the first column address, and the bit of the second memory cell selected by the first row address is maintained. And a control unit for maintaining 2-bit data.

  The memory device is selected by a row address and a column address, each of which is selected by the row address and a plurality of first memory cells each storing 1-bit data by one transistor and one capacitor. A plurality of second memory cells storing complementary 2-bit data by two transistors and two capacitors, and a column address and a voltage detection bit of a standard voltage or a low voltage are selected by the row address and stored When a read request from a plurality of third memory cells and a first row address and a first column address is input, voltage detection stored in the third memory cell selected by the first row address The bit stored in the third memory cell indicates a low voltage and is selected by the first row address. If the memory address is the same as the first column address, read data is output based on the complementary 2-bit data stored in the second memory cell selected by the first row address. When the voltage detection bit stored in the third memory cell selected by the first row address indicates a standard voltage, or the third memory cell selected by the first row address 1 bit stored in the first memory cell selected by the first row address and the first column address when the column address stored in the first column address is different from the first column address. And a control unit that outputs read data based on the data.

  The memory device is selected by a row address and a column address, a plurality of first memory cells storing data and error correction information of a first number of bits, and the first bit selected by the row address A plurality of second memory cells storing error correction information of a second number of bits greater than the number, and a plurality of second memory cells selected by the row address and storing a column address and a voltage detection bit indicating a standard voltage or a low voltage. When the memory cell 3, the voltage detection unit for detecting whether the power supply voltage is lower than the threshold, and the write request to the first row address and the first column address are input, the power supply voltage is lower than the threshold Includes writing the first column address and a voltage detection bit indicating a low voltage to a third memory cell selected by the first row address. Thus, data and error correction information of the first number of bits are written into the first memory cell selected by the first row address and the first column address, and selected by the first row address. When the error correction information of the second number of bits is written into the second memory cell and the power supply voltage is higher than the threshold value, the error correction information is stored in the third memory cell selected by the first row address. A voltage detection bit indicating a column address and a standard voltage is maintained, and data and error correction information of the first number of bits are stored in the first memory cell selected by the first row address and the first column address. And a controller for maintaining error correction information of the second number of bits of the second memory cell selected by the first row address.

  The memory device is selected by a row address and a column address, a plurality of first memory cells storing data and error correction information of a first number of bits, and the first bit selected by the row address A plurality of second memory cells storing error correction information having a second number of bits greater than the number, and a plurality of third memory cells selected by the row address and storing a column address and a voltage detection bit of a standard voltage or a low voltage. When a read request from the first memory address and the first row address and the first column address is input, the voltage detection bit stored in the third memory cell selected by the first row address becomes a low voltage. And the column address stored in the third memory cell selected by the first row address is the first address. The first row address selected by the first row address and the data stored in the first memory cell selected by the first column address and the first row address selected by the first row address. The data is error-corrected based on the error correction information of the second number of bits stored in the second memory cell, and stored in the third memory cell selected by the first row address. When the voltage detection bit indicates a standard voltage, or when the column address stored in the third memory cell selected by the first row address is different from the first column address, the first column address The data stored in the first memory cell selected by the row address and the first column address, and the error correction information of the first number of bits Having an error correction unit for correcting errors of the data based on.

  In one aspect, high reliability and small area of data storage can be achieved at the same time.

FIG. 1 is a diagram illustrating a configuration example of a ferroelectric memory device according to the first embodiment. FIG. 2 is a diagram illustrating a configuration example of the memory cell array. FIG. 3A is a diagram showing a write operation when the power supply voltage is a standard voltage, and FIG. 3B is a diagram showing a write operation when the power supply voltage is a low voltage. 4A to 4C are diagrams illustrating a read operation. FIG. 5A is a circuit diagram illustrating a configuration example of the first memory cell, the column selector, and the pre-sense circuit, and FIGS. 5B and 5C are circuit diagrams illustrating a configuration example of the sense amplifier. FIG. 6A is a circuit diagram illustrating a configuration example of the second memory cell, and FIG. 6B is a circuit diagram illustrating a configuration example of the third memory cell and the sense amplifier. FIG. 7 is a diagram showing a configuration example of a part of the ferroelectric memory device according to the second embodiment. FIG. 8 is a diagram showing a write operation when the power supply voltage is a low voltage. FIG. 9 is a diagram showing a write operation when the power supply voltage is a standard voltage. FIG. 10 is a diagram illustrating a read operation. FIG. 11 is a diagram illustrating a configuration example of the memory cell array according to the third embodiment. FIG. 12 is a diagram for explaining error correction information (1ECC) that can correct a 1-bit error. FIG. 13 is a diagram showing a configuration example of a part of the ferroelectric memory device according to the third embodiment. FIG. 14 is a diagram showing a configuration example of a part of the ferroelectric memory device according to the fourth embodiment.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of a ferroelectric memory device according to the first embodiment. Inverter 108 outputs a logical inversion signal of write enable signal / WE to control unit 106 as internal write enable signal intWE. A negative logical sum (NOR) circuit 109 outputs a negative logical sum signal of the internal write enable signal intWE and the output enable signal / OE to the control unit 106 as the internal output enable signal intOE. A negative AND (NAND) circuit 110 outputs a negative logical product signal of the write enable signal / WE and the output enable signal / OE. The logical product (AND) circuit 111 outputs a logical product signal of the output signal of the negative logical product circuit 110 and the logical inversion signal of the first chip enable signal / CE1. The AND circuit 112 outputs a logical product signal of the output signal of the AND circuit 111 and the second chip enable signal CE2 to the address latch 101 and the control unit 106.

  The address latch 101 latches the addresses A0 to A16, outputs the row address RA of the upper bits of the addresses A0 to A16 to the row decoder 102, and outputs the column address CA of the lower bits of the addresses A0 to A16 to the column decoder 103. . The control unit 106 inputs and outputs, for example, 16-bit data with respect to the external terminal 107. Specifically, the control unit 106 interprets a write request or a read request based on the output signal of the AND circuit 112, the internal write enable signal intWE, and the internal output enable signal intOE. In the case of a write request, the control unit 106 inputs data to be written to the memory cell array 104 from the external terminal 107, and in the case of a read request, outputs the data read from the memory cell array 104 to the external terminal 107. To do.

  The memory cell array 104 has a plurality of ferroelectric memory cells arranged in a two-dimensional matrix, and stores data in the ferroelectric memory cells corresponding to addresses A0 to A16. Each ferroelectric memory cell is specified by selecting a word line and a bit line. The row decoder 102 selects a word line corresponding to the row address RA. Column decoder 103 selects a bit line corresponding to column address CA. The amplifier 105 amplifies the data input from the control unit 106 by a write amplifier, and outputs the amplified data to the memory cell array 104 via the column decoder 103. When a write request (write command) is input, in the memory cell array 104, data is written to the ferroelectric memory cells of the selected word line and bit line. When a read request (read command) is input, the memory cell array 104 reads data from the ferroelectric memory cells 103 of the selected word line and bit line. The amplifier 105 amplifies the read data by the sense amplifier and outputs the amplified data to the control unit 106.

  FIG. 2 is a diagram illustrating a configuration example of the memory cell array 104 of FIG. The memory cell array 104 includes a plurality of first memory cells 201 in a matrix form selected by a row address RA and a column address CA, a plurality of second memory cells 202 provided for each row address RA, and a row address RA. And a plurality of third memory cells 203 provided in the. The plurality of first memory cells 201 are 1T1C type memory cells, which are selected by a row address RA and a column address CA, and each store 1-bit data by one transistor and one ferroelectric capacitor. . The second memory cell 202 is a 1T1C type memory cell, and is selected by a row address RA, and each stores 1-bit data by one transistor and one ferroelectric capacitor. The ferroelectric memory device has a voltage detection unit 207. The voltage detection unit 207 detects a power supply voltage and outputs a voltage detection flag (voltage detection bit). The voltage detection unit 207 outputs a voltage detection flag indicating a standard voltage when the power supply voltage is higher than the threshold value, and outputs a voltage detection flag indicating a low voltage when the power supply voltage is lower than the threshold value. This threshold value is set within the range of standard operating conditions with a margin and in the vicinity of the lower limit of the voltage at which the memory device operates stably. For example, the power supply voltage becomes lower than the threshold value due to power off, standby operation, instantaneous voltage drop, and the like. As the threshold, for example, 2.5 V is used when the standard voltage is 3 V, and 1.5 V is used when the standard voltage is 1.8 V. The plurality of third memory cells 203 are selected by a row address RA and store a column address and a voltage detection flag. The initial value of the voltage detection flag stored in the third memory cell 203 is a voltage detection flag indicating a standard voltage. The plurality of third memory cells 203 are 2T2C type memory cells, each of which stores complementary 2-bit data by two transistors and two ferroelectric capacitors.

  When the power supply voltage at the time of writing is a standard voltage, the control unit 106 can perform highly reliable writing to the first memory cell 201, and when the power supply voltage at the time of writing is a low voltage. Therefore, highly reliable writing to the first memory cell 201 cannot be performed. The data storage reliability of the first memory cell 201 written at the standard voltage is high, and the data storage reliability of the first memory cell 201 written at the low voltage is low.

  The 1T1C type memory cell has a smaller area than the 2T2C type memory cell, but the reliability of data storage is low. In contrast, the 2T2C type memory cell has a larger area than the 1T1C type memory cell, but has high data storage reliability. Therefore, when the power supply voltage is the standard voltage, the control unit 106 writes data to the 1T1C type first memory cell 201 and sets a voltage detection flag indicating the standard voltage of the initial value of the third memory cell 203. maintain. When the power supply voltage is low, the control unit 106 writes data to a 2T2C type memory cell using the 1T1C type first memory cell 201 and the 1T1C type second memory cell 202, and A column address CA and a voltage detection flag indicating a low voltage are written in the third memory cell 203. When the voltage is low, the reliability of data storage can be improved by writing to the 2T2C type memory cell.

  FIG. 3A is a diagram showing a write operation when the power supply voltage is a standard voltage. The row decoder 102 includes row decoders 102a and 102b. The row decoder 102a selects the word line of the first memory cell 201 corresponding to the row address RA. The column selector 301 is provided in the column decoder 103 of FIG. 1, selects a bit line corresponding to the column address CA, and outputs write data 302 and reference data (Vref) 303H and 303L to the selected bit line. The reference data 303H is “1” reference data. The reference data 303L is “0” reference data. In the first memory cell 201 selected by the word line (row address RA) and the bit line (column address CA), 16-bit data 302, 1-bit reference data 303H, and 1-bit reference data 303L are stored. Written. The first memory cell 201 is a 1T1C type memory cell. At this time, the control unit 106 does not perform writing to the second memory cell 202. The row decoder 102b selects the word line of the third memory cell 203 corresponding to the row address RA. The control unit 106 does not perform writing corresponding to the external data to the third memory cell 203. The third memory cell 203 rewrites the value read by the sense amplifier and maintains the column address CAP and the voltage detection flag FLG.

  As described above, when the control unit 106 inputs a write request to the first row address RA and the first column address CA, when the power supply voltage is higher than the threshold, the first row address RA and the first row address RA. Each first 1-bit data 302 is written to each first memory cell 201 selected by the column address CA, and each 1-bit data of each second memory cell 202 selected by the first row address RA is written. maintain. The control unit 106 maintains the column address CAP and the voltage detection flag (voltage detection bit) FLG stored in the third memory cell 203 selected by the first row address RA.

  FIG. 3B is a diagram illustrating a write operation when the power supply voltage is a low voltage. The row decoder 102a selects the word lines of the first memory cell 201 and the second memory cell 202 corresponding to the row address RA. The column selector 301 selects a bit line corresponding to the column address CA, and outputs write data 302 and reference data (Vref) 303H and 303L to the selected bit line. In the first memory cell 201 selected by the word line (row address RA) and the bit line (column address CA), 16-bit data 302, 1-bit reference data 303H, and 1-bit reference data 303L are stored. Written. The control unit 106 writes the logic inversion data 304 to the second memory cell 202 selected by the word line (row address RA). Data 304 is data that is logically inverted with respect to data 302. Data 302 and 304 are complementary data. The first memory cell 201 is a 1T1C type memory cell, and the second memory cell 202 is also a 1T1C type memory cell. The first memory cell 201 and the second memory cell 202 constitute a 2T2C type memory cell. The control unit 106 writes the complementary 2-bit data 302 and 304 to the 2T2C type memory cells 201 and 202, respectively. The row decoder 102b selects the word line of the third memory cell 203 corresponding to the row address RA. The voltage detection unit 207 outputs a voltage detection flag FLG indicating a low voltage. The column address CA is input to the write amplifier 305 as the column address CAP. The write amplifier 305 is provided in the amplifier 105 of FIG. 1, amplifies the column address CAP and the voltage detection flag FLG, and outputs the amplified result to the third memory cell 203. The column address CAP and the voltage detection flag FLG are written in the third memory cell 203 selected by the row decoder 102b. The column address CAP is the column address CA where the data 302 is written. The voltage detection flag FLG indicates a low voltage.

  As described above, when the control unit 106 inputs a write request to the first row address RA and the first column address CA, when the power supply voltage is lower than the threshold, the first row address RA and the first row address Each first 1-bit data 302 is written in each first memory cell 201 selected by the column address CA. Then, the control unit 106 writes each second 1-bit data 304 of the logical inversion of each first 1-bit data 302 to each second memory cell 202 selected by the first row address RA. Then, the control unit 106 writes the first column address CA (CAP) and the voltage detection flag FLG indicating a low voltage in the third memory cell 203 selected by the first row address RA.

  FIG. 4A shows the first stage of the read operation. The control unit 106 inputs a read request for the row address RA and the column address CA. The row decoder 102b selects the word line of the third memory cell 203 corresponding to the row address RA. The column address CAP and the voltage detection flag FLG stored in the third memory cell 203 selected by the word line are read to the sense amplifier 105b. The sense amplifier 105b is provided in the amplifier 105 of FIG. 1, and amplifies the column address CAP and the voltage detection flag FLG. The exclusive OR circuit 401 detects whether or not the column address CA and the column address CAP are the same. When the voltage detection flag FLG indicates a standard voltage, or when the column address CA is different from the column address CAP, it indicates that the data is written at the standard voltage, so that the second stage of FIG. Transition. Further, when the voltage detection flag FLG indicates a low voltage and the column address CA is the same as the column address CAP, it indicates that the data is written at the time of the low voltage. Move to the stage.

  FIG. 4B shows a second stage when the voltage detection flag FLG read from the third memory cell 203 indicates a standard voltage, or when the column address CA is different from the column address CAP. The row decoder 102a selects the word line of the first memory cell 201 corresponding to the row address RA. Column selector 301 selects the bit line of first memory cell 201 corresponding to column address CA. Data 302 and reference data 303H and 303L stored in the first memory cell 201 selected by the word line and the bit line are read to the pre-sense circuit BGS. The pre-sense circuit BGS is provided in the amplifier 105 of FIG. 1, converts the data 302 and the reference data 303H and 303L from electric charge to voltage and outputs them to the sense amplifier 105a. The sense amplifier 105a is provided in the amplifier 105 of FIG. 1, differentially amplifies each 16-bit data 302 and reference data 303H, and differentially amplifies each 16-bit data 302 and reference data 303L. Outputs 16-bit data of value. Details thereof will be described later with reference to FIG. In this case, since data is written with a standard voltage and data writing is highly reliable, reading is performed using only the first memory cell 201 without using the second memory cell 202.

  As described above, when the control unit 106 inputs a read request from the first row address RA and the first column address CA, it is stored in the third memory cell 203 selected by the first row address RA. When the detected voltage detection flag FLG indicates a standard voltage, the reading in FIG. 4B is performed. In addition, the control unit 106 also performs the process shown in FIG. 4B when the column address CAP stored in the third memory cell 203 selected by the first row address RA is different from the first column address CA. Read. In FIG. 4B, the control unit 106 includes the first 1-bit data 302 and the reference stored in the first memory cell 201 selected by the first row address RA and the first column address CA. Read data is output based on the data 303H and 303L.

  Note that reading in FIG. 4B is destructive reading, and the stored contents are erased by the reading operation. Therefore, after that, the read data is rewritten. When the power supply voltage at the time of rewriting is higher than the threshold value, the voltage detection unit 207 outputs a voltage detection flag FLG indicating that the power supply voltage is a standard voltage. In that case, as shown in the third memory cell 203 in FIG. 3A, the column address CAP output from the sense amplifier 105b by reading and the voltage detection flag FLG of the voltage detection unit 207 are transmitted via the write amplifier 305. , Data is written to the third memory cell 203 selected by the word line. Further, as shown in the first memory cell 201 in FIG. 3A, the read data 302 and the reference data 303H and 303L are written into the first memory cell 201 through the column selector 301.

  In addition, when the power supply voltage at the time of rewriting is lower than the threshold value, the voltage detection unit 207 outputs a voltage detection flag FLG indicating that the power supply voltage is a low voltage. In that case, as shown in the third memory cell 203 in FIG. 3B, the input column address CA (column address CAP) and the voltage detection flag FLG of the voltage detection unit 207 are transmitted via the write amplifier 305 to the word The data is written to the third memory cell 203 selected by the line. As shown in the first memory cell 201 in FIG. 3B, the read data 302 and the reference data 303H and 303L are written into the first memory cell 201 through the column selector 301. Further, as illustrated in the second memory cell 202 in FIG. 3B, the logic inversion data 304 is written into the second memory cell 202.

  FIG. 4C shows the second stage when the voltage detection flag FLG read from the third memory cell 203 indicates a low voltage and the column address CA is the same as the column address CAP. The row decoder 102a selects the word lines of the first memory cell 201 and the second memory cell 202 corresponding to the row address RA. Column selector 301 selects the bit line of first memory cell 201 corresponding to column address CA. Data 302 stored in the first memory cell 201 selected by the word line and the bit line is read to the pre-sense circuit BGS. Further, the logic inversion data 304 stored in the second memory cell 202 selected by the word line is read out to the pre-sense circuit BGS. The pre-sense circuit BGS converts the data 302 and the logic inversion data 304 from electric charge to voltage and outputs them to the sense amplifier 105a. The sense amplifier 105a differentially amplifies 16-bit data 302 and 16-bit logical inversion data 304 for each bit, and outputs binary 16-bit data. Details thereof will be described later with reference to FIG. In this case, since data is written at a low voltage and data writing reliability is low, reading is performed using complementary data 302 and 304 of the first memory cell 201 and the second memory cell 202. Thus, highly reliable data reading can be performed.

  As described above, when the control unit 106 inputs a read request from the first row address RA and the first column address CA, it is stored in the third memory cell 203 selected by the first row address RA. When the detected voltage detection flag FLG indicates a low voltage and the column address CAP stored in the third memory cell 203 selected by the first row address RA is the same as the first column address CA Reads out the data shown in FIG. In FIG. 4C, the control unit 106 includes each first 1-bit data 302 stored in each first memory cell 201 selected by the first row address RA and the first column address CA, and Read data is output based on each second 1-bit data 304 stored in each second memory cell 202 selected by the first row address RA.

  Note that reading in FIG. 4C is destructive reading, and the stored contents are erased by the reading operation. Therefore, after that, the read data is rewritten. When the power supply voltage at the time of rewriting is higher than the threshold value, the voltage detection unit 207 outputs a voltage detection flag FLG indicating that the power supply voltage is a standard voltage. In this case, the initial value column address CAP and the voltage detection flag FLG indicating the standard voltage are written into the third memory cell 203 selected by the word line via the write amplifier 305. The read data 302 and the reference data 303H and 303L are written into the first memory cell 201 via the column selector 301.

  In addition, when the power supply voltage at the time of rewriting is lower than the threshold value, the voltage detection unit 207 outputs a voltage detection flag FLG indicating that the power supply voltage is a low voltage. In that case, as shown in the third memory cell 203 in FIG. 3B, the input column address CA (column address CAP) and the voltage detection flag FLG of the voltage detection unit 207 are transmitted via the write amplifier 305 to the word The data is written to the third memory cell 203 selected by the line. As shown in the first memory cell 201 in FIG. 3B, the read data 302 and the reference data 303H and 303L are written into the first memory cell 201 through the column selector 301. Further, as illustrated in the second memory cell 202 in FIG. 3B, the logic inversion data 304 is written into the second memory cell 202.

  FIG. 5A is a circuit diagram illustrating a configuration example of the first memory cell 201, the column selector 301, and the pre-sense circuit BGS. The plurality of first memory cells 201 are arranged in a matrix corresponding to the row address RA and the column address CA. Each of the plurality of first memory cells 201 is a 1T1C type memory cell, and stores 1-bit data by one n-channel field effect transistor 501 and one ferroelectric capacitor 502. The n-channel field effect transistor 501 has a gate connected to the word line WL and a source connected to the bit line BL. The ferroelectric capacitor 502 is connected between the drain of the n-channel field effect transistor 501 and the plate line PL. The row decoder 102a sets the word line WL corresponding to the row address RA to a high level. The n-channel field effect transistor 501 is turned on when the gate is at a high level, and the ferroelectric capacitor 502 is connected to the bit line BL.

  When a negative voltage is applied between the bit line BL and the plate line PL, the ferroelectric capacitor 502 is inverted in polarity, and data “1” is written. On the other hand, when a positive voltage is applied between the bit line BL and the plate line PL, the ferroelectric capacitor 502 is not inverted in polarization, and data “0” is written. At the time of reading, when a predetermined voltage is applied to the plate line PL, if the ferroelectric capacitor 502 stores “1” data, a large amount of charge moves to the bit line BL, and the ferroelectric capacitor 502 When “0” data is stored, a small amount of charge moves to the bit line BL.

  The column selector 301 connects the bit line BL corresponding to the column address CA to the pre-sense circuit BGS. That is, the first memory cell 201 is selected by the word line WL corresponding to the row address RA and the bit line BL corresponding to the column address CA.

  The pre-sense circuit BGS includes a switch 503, a p-channel field effect transistor 504, capacitors 505 and 507, and an n-channel field effect transistor 508, and converts the charge on the bit line BL into a voltage. When charge is transferred to the bit line BL, the voltage of the node 506 increases. The output voltage D_SFO of the pre-sense circuit BGS becomes a high voltage when the ferroelectric capacitor 502 stores data “1”, and the ferroelectric capacitor 502 stores data “0”. There is a low voltage.

  FIG. 5B is a circuit diagram illustrating a configuration example of the sense amplifier 105a. The sense amplifier 105 a includes differential amplifiers 511 and 512. Data D_SFO is the output voltage D_SFO of the pre-sense circuit BGS corresponding to the data 302 stored in the first memory cell 201. The reference data VrefH is the output voltage D_SFO of the pre-sense circuit BGS corresponding to the reference data 303H stored in the first memory cell 201. The reference data 303H is “1” data, and the reference data VrefH is a high voltage. The reference data VrefL is the output voltage D_SFO of the pre-sense circuit BGS corresponding to the reference data 303L stored in the first memory cell 201. The reference data 303L is “0” data, and the reference data VrefL is a low voltage. The sense amplifier 105a is activated by turning on the switch in the sense amplifier 105a. Hereinafter, the operation of FIG. 4B will be described with reference to FIG.

  First, the case where the data D_SFO is a low voltage corresponding to “0” will be described. The differential amplifier 511 differentially amplifies the low voltage data D_SFO and the high voltage reference data VrefH. As a result, the node N1 becomes high level and the node N2 becomes low level. The differential amplifier 512 differentially amplifies the reference data VrefL of the low level and the low voltage (voltage approximately equal to the low level) of the node N4. Since the differential amplifier 512 has a small potential difference between the node N4 and the node N3, it takes time to amplify and becomes a metastable state. Since the potential difference between the node N1 and the node N2 is large, the differential amplifier 511 immediately starts amplification, the potential difference is opened, and the differential amplifier 512 is strongly influenced via the resistor. As a result, the nodes N2 and N4 become low level, and the nodes N1 and N3 become high level. Node N2 outputs low-level positive logic data D, and node N1 outputs high-level negative logic data / D.

  Next, the case where the data D_SFO is a high voltage corresponding to “1” will be described. The differential amplifier 512 differentially amplifies the high voltage data D_SFO and the low voltage reference data VrefL. As a result, the node N4 becomes high level and the node N3 becomes low level. The differential amplifier 511 differentially amplifies the reference data VrefH of the high level and high voltage (voltage approximately equal to the high level) of the node N2. Since the differential amplifier 511 has a small potential difference between the node N1 and the node N2, it takes time to amplify and becomes a metastable state. Since the differential amplifier 512 has a large potential difference between the node N4 and the node N3, amplification starts immediately, the potential difference opens, and the differential amplifier 511 is strongly influenced via the resistor. As a result, the node N2 becomes high level and the node N1 becomes low level. Node N2 outputs high-level positive logic data D, and node N1 outputs low-level negative logic data / D.

  FIG. 6A is a circuit diagram illustrating a configuration example of the second memory cell 202. The second memory cell 202 is provided for each word line WL. Each of the plurality of second memory cells 202 is a 1T1C type memory cell, and stores 1-bit data by one n-channel field effect transistor 601 and one ferroelectric capacitor 602. N-channel field effect transistor 601 has a gate connected to word line WL and a source connected to bit line / BL. The ferroelectric capacitor 602 is connected between the drain of the n-channel field effect transistor 601 and the plate line PL. The row decoder 102a sets the word line WL corresponding to the row address RA to a high level. The n-channel field effect transistor 601 is turned on when the gate becomes high level, and the ferroelectric capacitor 602 is connected to the bit line / BL. The operation of the second memory cell 202 is similar to the operation of the first memory cell 201. Since the second memory cell 202 is not selected by the column address CA, the second memory cell 202 is connected to the pre-sense circuit BGS for each bit line / BL without going through the column selector 301.

  FIG. 5C illustrates the operation of the sense amplifier 105a in FIG. The sense amplifier 105a in FIG. 5C inputs logical inversion data / D_SFO instead of the reference data VrefH and VrefL to FIG. 5B. Data D_SFO is the output voltage D_SFO of the pre-sense circuit BGS corresponding to the data 302 stored in the first memory cell 201. The logic inversion data / D_SFO is the output voltage D_SFO of the pre-sense circuit BGS corresponding to the logic inversion data 304 stored in the second memory cell 202. Data 302 and 304 are complementary data. Therefore, when the data D_SFO is at a high voltage, the logic inversion data / D_SFO is at a low voltage. Further, when the data D_SFO has a low voltage, the logic inversion data / D_SFO has a high voltage.

  First, the case where the data D_SFO has a low voltage and the logic inversion data / D_SFO has a high voltage will be described. The differential amplifiers 511 and 512 differentially amplify the low voltage data D_SFO and the high voltage logical inversion data / D_SFO, respectively. As a result, the nodes N1 and N3 become high level, and the nodes N2 and N4 become low level. Node N2 outputs low-level positive logic data D, and node N1 outputs high-level negative logic data / D.

  Next, a case where the data D_SFO is a high voltage and the logic inversion data / D_SFO is a low voltage will be described. The differential amplifiers 511 and 512 differentially amplify the high voltage data D_SFO and the low voltage logic inversion data / D_SFO, respectively. As a result, the nodes N1 and N3 become low level, and the nodes N2 and N4 become high level. Node N2 outputs high-level positive logic data D, and node N1 outputs low-level negative logic data / D.

  FIG. 6B is a circuit diagram illustrating a configuration example of the third memory cell 203 and the sense amplifier 105b. The third memory cell 203 is provided for each word line WL. Each of the plurality of third memory cells 203 is a 2T2C type memory cell, and stores two complementary n-bit data by two n-channel field effect transistors 611a and 611b and two ferroelectric capacitors 612a and 612b. To do. The n-channel field effect transistor 611a has a gate connected to the word line WL and a source connected to the bit line BL. The n-channel field effect transistor 611b has a gate connected to the word line WL and a source connected to the bit line / BL. The ferroelectric capacitor 612a is connected between the drain of the n-channel field effect transistor 611a and the plate line PL. The ferroelectric capacitor 612b is connected between the drain of the n-channel field effect transistor 611b and the plate line PL. The row decoder 102b sets the word line WL corresponding to the row address RA to a high level. The n-channel field effect transistors 611a and 611b are turned on when the gates become high level, the ferroelectric capacitor 612a is connected to the bit line BL, and the ferroelectric capacitor 612b is connected to the bit line / BL. Complementary data is written in the ferroelectric capacitors 612a and 612b. Since the third memory cell 203 is not selected by the column address CA, it is connected to the sense amplifier 105b without going through the column selector 301. The sense amplifier 105b differentially amplifies the voltage of the bit line BL and the voltage of the bit line / BL, and outputs complementary data D and / D.

(Second Embodiment)
FIG. 7 is a diagram showing a configuration example of a part of the ferroelectric memory device according to the second embodiment. Hereinafter, the points of the present embodiment different from the first embodiment will be described. The row decoder 102a selects the word lines WL of the first memory cell 201 and the second memory cell 202 according to the row address RA. Each of the first memory cells 201 is a 1T1C type memory cell and stores data 302 and reference data 303H and 303L. Each of the second memory cells 202 is a 2T2C type memory cell and stores complementary data 304p and 304n. The data 304p is the same data as the data 302. The column selector 301 selects the bit line BL of the first memory cell 201 according to the column address CA. The write amplifier 305a amplifies the write data and outputs the amplified write data to the 1T1C type first memory cell 201. The write amplifier 305b amplifies the write data and outputs the amplified write data to the 2T2C type second memory cell 202. The pre-sense circuit BGS converts the charge input from the first memory cell 201 into a voltage via the column selector 301. The sense amplifier 105a amplifies the output voltage of the pre-sense circuit BGS. The sense amplifier 105c differentially amplifies complementary data 304p and 304n stored in the second memory cell 202.

  The row decoder 102b selects the word line WL of the third memory cell 203 according to the row address RA. Note that the row decoder 102b may be common with the row decoder 102a. Each of the third memory cells 203 is a 2T2C type memory cell and stores a column address CAP and a voltage detection flag FLG. The write amplifier 305 c amplifies the write data and outputs the amplified write data to the 2T2C type third memory cell 203. The sense amplifier 105b amplifies the output voltage of the third memory cell 203.

  When the power supply voltage is detected and the power supply voltage is lower than the threshold, the voltage detection unit 207 outputs a voltage detection flag FLG of “1” indicating that the power supply voltage is low, and the power supply voltage is higher than the threshold. In this case, a voltage detection flag FLG of “0” indicating that the power supply voltage is a standard voltage is output.

  FIG. 8 is a diagram showing a write operation when the power supply voltage is a low voltage. When the control unit 106 inputs a write request to the first row address RA and the first column address CA, the third memory selected by the first row address RA when the power supply voltage is lower than the threshold value. A first column address CA (column address CAP) and a voltage detection flag FLG indicating a low voltage are written in the cell 203. In addition, the control unit 106 writes the 1-bit data 302 and the reference data 303H and 303L to the first memory cell 201 selected by the first row address RA and the first column address CA, and the first row address The complementary 2-bit data 304p and 304n are written in the second memory cell 202 selected by RA.

  FIG. 9 is a diagram showing a write operation when the power supply voltage is a standard voltage. When the control unit 106 inputs a write request to the first row address RA and the first column address CA, the third memory selected by the first row address RA when the power supply voltage is higher than the threshold value. The column address CA and the voltage detection flag FLG stored in the cell 203 are maintained. Then, the control unit 106 writes the 1-bit data 302 and the reference data 303H and 303L to the first memory cell 201 selected by the first row address RA and the first column address CA, and the first row address Each 2-bit data 304p, 304n of the second memory cell 202 selected by RA is maintained.

  FIG. 10 is a diagram illustrating a read operation. The read operation is performed in one stage (one cycle). The control unit 106 inputs a read request for the row address RA and the column address CA. The row decoder 102a selects the word lines WL of the first memory cell 201 and the second memory cell 202 according to the row address RA. The column selector 301 selects the bit line BL of the first memory cell 201 according to the column address CA. Data 302 and reference data 303H and 303L stored in the first memory cell 201 selected by the word line WL and the bit line BL are read to the pre-sense circuit BGS. The pre-sense circuit BGS converts the data 302 and the reference data 303H and 303L from electric charge to voltage and outputs them to the sense amplifier 105a. The sense amplifier 105a differentially amplifies each 16-bit data 302 and reference data 303H, differentially amplifies each 16-bit data 302 and reference data 303L, and outputs binary 16-bit data D. Also, complementary data 304p and 304n stored in the second memory cell 202 selected by the word line WL are read to the sense amplifier 105c. The sense amplifier 105c differentially amplifies the 16-bit complementary data 304p and 304n and outputs binary 16-bit data D.

  The row decoder 102b selects the word line WL of the third memory cell 203 according to the row address RA. The column address CAP and the voltage detection flag FLG stored in the third memory cell 203 selected by the word line WL are read to the sense amplifier 105b. The sense amplifier 105b amplifies the column address CAP and the voltage detection amplifier FLG. The exclusive OR circuit 401 detects whether or not the column address CA and the column address CAP are the same. When the voltage detection flag FLG indicates a standard voltage, or when the column address CA is different from the column address CAP, it indicates that the data is written at the standard voltage, so that the selector 701 outputs the data output from the sense amplifier 105a. Select D and output. Further, when the voltage detection flag FLG indicates a low voltage and the column address CA is the same as the column address CAP, it indicates that the data is written at the time of the low voltage. The data D to be output is selected and output.

  As described above, when the control unit 106 inputs a read request from the first row address RA and the first column address CA, it is stored in the third memory cell 203 selected by the first row address RA. When the detected voltage detection flag FLG indicates a low voltage and the column address CAP stored in the third memory cell 203 selected by the first row address RA is the same as the first column address CA Outputs the read data D based on the complementary 2-bit data 304p and 304n stored in each second memory cell 202 selected by the first row address RA.

  In addition, the control unit 106 selects the voltage detection flag FLG stored in the third memory cell 203 selected by the first row address RA indicating the standard voltage, or is selected by the first row address RA. When the column address CAP stored in the third memory cell 203 is different from the first column address CA, each first memory cell selected by the first row address RA and the first column address CA Read data D is output based on each 1-bit data 302 and reference data 303H and 303L stored in 201.

  Next, the rewriting operation after reading in FIG. 10 will be described. When the power supply voltage is lower than the threshold, the voltage detection unit 207 outputs a voltage detection flag FLG of “1” indicating that the power supply voltage is a low voltage. In that case, the control unit 106 writes the input column address CA (column address CAP) and the voltage detection flag FLG of the voltage detection unit 207 to the third memory cell 203. Then, the control unit 106 writes back the read data 302 and the reference data 303H and 303L to the first memory cell 201, and based on the read data 302, the complementary data 304p and 304n are transferred to the second memory cell 202. Write.

  Further, when the power supply voltage is higher than the threshold value, the voltage detection unit 207 outputs a voltage detection flag FLG of “0” indicating that the power supply voltage is a standard voltage. In that case, the control unit 106 writes back the read column address CAP and voltage detection flag FLG to the third memory cell 203. Then, the control unit 106 writes the read data 302 and the reference data 303H and 303L back to the first memory cell 201, and writes the read complementary data 304p and 304n back to the second memory cell 202. The control unit 106 sets the initial value when the voltage detection flag FLG stored in the third memory cell 203 is “1” and the column address CAP is the same as the input column address CA. The column address CAP and the voltage detection flag FLG of “0” may be written in the third memory cell 203.

(Third embodiment)
FIG. 11 is a diagram illustrating a configuration example of the memory cell array 104 according to the third embodiment. Hereinafter, the points of the present embodiment different from the first embodiment will be described. The voltage detection unit 207 detects whether the power supply voltage is lower than a threshold value. Each of the first memory cells 201 is a 1T1C type memory cell, and stores 16-bit data and error correction information (1ECC) that can correct 16-bit data by 1-bit error. Each of the second memory cells 202 is a 1T1C type memory cell, and stores error correction information (4ECC) capable of correcting the 16-bit data of the first memory cell by 4-bit error. The third memory cell 203 is a 1T1C type memory cell, and stores a column address CAP, a voltage detection flag FLG, and error correction information (4ECC) capable of correcting them by 4 bits. Note that the third memory cell 203 may be a 2T2C type memory cell in order to enable low voltage operation.

  When the power supply voltage at the time of writing is a standard voltage, the control unit 106 can perform highly reliable writing to the first memory cell 201, and when the power supply voltage at the time of writing is a low voltage. Therefore, highly reliable writing to the first memory cell 201 cannot be performed. The data storage reliability of the first memory cell 201 written at the standard voltage is high, and the data storage reliability of the first memory cell 201 written at the low voltage is low.

  Error correction information (1ECC) capable of correcting 1-bit error has a low error correction capability but a small amount of information. Conversely, error correction information (4ECC) that can correct a 4-bit error has a large amount of information, but has a high error correction capability. Error correction information (4ECC) that can correct 4-bit errors has higher error correction capability than error correction information (1ECC) that can correct 1-bit errors. Therefore, when the power supply voltage is a standard voltage, the control unit 106 performs error correction using error correction information (1ECC) that can correct a 1-bit error in the first memory cell 201. In addition, when the power supply voltage is low, the control unit 106 performs error correction using error correction information (4ECC) that can correct the 4-bit error of the second memory cell 202, and the reliability of data reading Increase sex.

  FIG. 12 is a diagram for explaining an example of error correction information (1ECC) that can correct a 1-bit error. The first memory cell 201 stores 16-bit data D0 to DF and 5-bit parity P0 to P4. The 5-bit parity P0 to P4 is error correction information (1ECC) that can correct 16-bit data D0 to DF by 1-bit error. First, the 1ECC unit sets the 5-bit parities P0 to P4 so that the sum of the 16-bit data D0 to DF and the 5-bit parities P0 to P4 is an even number in the horizontal direction of each of the five error events Q0 to Q4. Generate. Next, the control unit 106 writes the 16-bit data D0 to DF and the 5-bit parity P0 to P4 in the first memory cell 201. Next, the control unit 106 reads 16-bit data D0 to DF and 5-bit parity P0 to P4 from the first memory cell 201. Next, the 1 ECC unit checks whether or not the sum of the 16-bit data D0 to DF and the 5-bit parity P0 to P4 is an even number in the horizontal direction of each of the five error events Q0 to Q4.

  The 1ECC unit has no error in the 16-bit data D0 to DF when the sum of the 16-bit data D0 to DF and the 5-bit parity P0 to P4 is an even number in all the five error events Q0 to Q4. Therefore, the 16-bit data D0 to DF are output as they are.

  In addition, for example, the 1 ECC unit indicates that there is an error in the data D0 when the sum of the 16-bit data D0 to DF and the 5-bit parity P0 to P4 is odd only in the two error events Q0 and Q1. As shown, the data D0 is bit-inverted for error correction, and 16-bit data D0 to DF are output. In the area 1201, in the case of two error events, if the sum of the 16-bit data D0 to DF and the 5-bit parity P0 to P4 is an odd number, any one of the data D0 to D9 can be error-corrected. It is. In the area 1202, in the case of three error events, if the sum of the 16-bit data D0 to DF and the 5-bit parity P0 to P4 is an odd number, one of the data DA to DF has an error. It can be corrected. Further, in the area 1203, when one of the error events, the sum of the 16-bit data D0 to DF and the 5-bit parity P0 to P4 is an odd number, the parity of any one of the parities P0 to P4 is determined as an error. It can be corrected.

  Next, error correction information (4ECC) that can correct a 4-bit error will be described. The first memory cell 201 stores 16-bit data and 5-bit parity. The third memory cell 203 stores a 4-bit column address CAP and a 1-bit voltage detection flag FLG. The 4ECC unit 1302 generates error correction information (4ECC) that can correct a 4-bit error for a total of 21-bit data of 16-bit data and 5-bit parity. In this case, error correction information that can correct a 4-bit error is a 17-bit parity. The 4ECC unit 1306 generates error correction information (4ECC) that allows 4-bit error correction for the 4-bit column address CAP and the 1-bit voltage detection flag FLG. In this case, error correction information that can correct a 4-bit error is a 12-bit parity. As a result, errors within 4 bits can be independently corrected.

  FIG. 13 is a diagram showing a configuration example of a part of the ferroelectric memory device according to the third embodiment. First, the write operation will be described. The selector 1305 selects the 16-bit data 16b from the input circuit and outputs it to the 1ECC unit 1301. The 1ECC unit 1301 generates 5 bit parity 5p capable of correcting 1 bit error based on the 16 bit data 16b, and outputs the 16 bit data 16b and the 5 bit parity 5p to the write amplifier 305a. The write amplifier 305 a amplifies the 16-bit data 16 b and the 5-bit parity 5 p and outputs the amplified data to the first memory cell 201. In the first memory cell 201, 16-bit data 16b and 5-bit parity 5p are written according to the row address RA and the column address CA.

  When the power supply voltage is lower than the threshold, the voltage detection unit 207 outputs a voltage detection flag FLG indicating that the power supply voltage is low. In that case, the 4ECC unit 1302 generates 17-bit parity 17p capable of 4-bit error correction for the 16-bit data 16b and the 5-bit parity 5p output from the 1ECC unit 1301. In addition, the 4ECC unit 1307 generates a 12-bit parity 12p capable of 4-bit error correction based on the input column address CA (column address CAP) and the voltage detection flag FLG of the voltage detection unit 207. The selector 1303 selects the 17-bit parity 17p, the column address CAP, the voltage detection flag FLG, and the 12-bit parity 12p for the data, and outputs them to the write amplifier 305b. The write amplifier 305b amplifies the 17-bit parity 17p, the column address CAP, the voltage detection flag FLG and the 12-bit parity 12p, outputs the 17-bit parity 17p to the second memory cell 202, and outputs the column address CAP and the voltage detection flag. The FLG and its 12-bit parity 12p are output to the third memory cell 203. In the second memory cell 202, 17-bit parity 17p capable of 4-bit error correction is written according to the row address RA. In the third memory cell 203, the column address CAP, the voltage detection flag FLG indicating a low voltage, and its 12-bit parity 12p are written according to the row address RA.

  When the power supply voltage is higher than the threshold, the voltage detection unit 207 outputs a voltage detection flag FLG indicating that the power supply voltage is a standard voltage. In that case, writing is not performed on the second memory cell 202 and the third memory cell 203 and the memory state is maintained. The initial value of the voltage detection flag FLG of the third memory cell 203 indicates a standard voltage.

  As described above, the plurality of first memory cells 201 are selected by the row address RA and the column address CA, and store the 16-bit data 16b and the error correction information (parity) 5p of the first number of bits (5 bits). To do. The plurality of second memory cells 202 are selected by the row address RA and store error correction information (parity) 17p having a second bit number (17 bits) larger than the first bit number. The third memory cell 203 is selected by the row address RA, and stores a column address CAP, a voltage detection flag FLG indicating a standard voltage of an initial value, and its 12-bit parity 12p. The voltage detection unit 207 detects whether the power supply voltage is lower than a threshold value.

  When the control unit 106 inputs a write request to the first row address RA and the first column address CA, the third memory selected by the first row address RA when the power supply voltage is lower than the threshold value. A first column address CA, a voltage detection flag FLG indicating a low voltage, and its 12-bit parity 12p are written in the cell 203. Then, the control unit 106 writes the 16-bit data 16b and the error correction information 5p of the first number of bits into the first memory cell 201 selected by the first row address RA and the first column address CA, The error correction information 17p having the second number of bits is written into the second memory cell 202 selected by the one row address RA.

  In addition, when the controller 106 inputs a write request to the first row address RA and the first column address CA, when the power supply voltage is higher than the threshold value, the control unit 106 selects the third row address RA selected by the first row address RA. The column address CA and voltage detection flag FLG stored in the memory cell 203 and the 12-bit parity 12p thereof are maintained. Then, the control unit 106 writes the 16-bit data 16b and the error correction information 5p of the first number of bits into the first memory cell 201 selected by the first row address RA and the first column address CA, The error correction information 17p of the second number of bits of the second memory cell 202 selected by one row address RA is maintained.

  Next, the reading operation will be described. The first memory cell 201 outputs 16-bit data 16b and 5-bit parity 5p to the sense amplifier 105a according to the row address RA and the column address CA. The sense amplifier 105a amplifies the 16-bit data 16b and the 5-bit parity 5p and outputs them to the 1ECC unit 1301 and the 4ECC unit 1302. The 1 ECC unit 1301 performs error correction on the 16-bit data 16b using the 5-bit parity 5p, and outputs the error-corrected 16-bit data 16b to the selector 1304.

  The second memory cell 202 outputs the 17-bit parity 17p to the sense amplifier 105b according to the row address RA. The third memory cell 203 outputs the column address CAP, the voltage detection flag FLG, and its 12-bit parity 12p to the sense amplifier 105b according to the row address RA. The sense amplifier 105b amplifies the 17-bit parity 17p and outputs it to the 4ECC unit 1302. The 4ECC unit 1302 performs error correction on the 16-bit data 16b and the 5-bit parity 5p using the 17-bit parity 17p. Then, the 4ECC unit 1302 outputs the error-corrected 16-bit data 16b to the selector 1304. The sense amplifier 105b amplifies the 4-bit column address CAP, the 1-bit voltage detection flag FLG, and the 12-bit parity 12p, and outputs the amplified signal to the 4ECC unit 1306. The 4ECC unit 1306 corrects the column address CAP and the voltage detection flag FLG using the 12-bit parity 12p, so that the column address coincidence can be reliably determined even when writing is performed at a low voltage.

  When the error detection voltage detection flag FLG indicates a low voltage and the column address CAP after error correction is the same as the input column address CA, the selector 1304 outputs the error correction output from the 4ECC unit 1302 The 16-bit data 16b is selected and output as read data. In addition, the selector 1304 displays a post-error correction output from the 1ECC unit 1301 when the error detection voltage detection flag FLG indicates a standard voltage, or when the post-error correction column address CAP is different from the input column address CA. 16-bit data 16b is selected and output as read data.

  As described above, the 1ECC unit 1301 and the 4ECC units 1302, 1306, and 1307 are error correction units. When the 4ECC unit 1302 receives a read request from the first row address RA and the first column address CA, the voltage detection flag stored in the third memory cell 203 selected by the first row address RA. When FLG indicates a low voltage and the column address CAP stored in the third memory cell 203 selected by the first row address RA is the same as the first column address CA, the first Selected by the 16-bit data 16b and the first bit number of error correction information 5p stored in the first memory cell 201 selected by the row address RA and the first column address CA, and the first row address RA. 16 bit data based on the second bit number of error correction information 17p stored in the second memory cell 202. 16b to correct the error.

  When the 1ECC unit 1301 receives a read request from the first row address RA and the first column address CA, the voltage detection flag stored in the third memory cell 203 selected by the first row address RA. If FLG indicates a standard voltage, or if the column address CAP stored in the third memory cell 203 selected by the first row address RA is different from the first column address CA, the first row address The 16-bit data 16b is error-corrected based on the 16-bit data 16b stored in the first memory cell 201 selected by the address RA and the first column address CA and the error correction information 5p of the first number of bits. .

  Next, the rewriting operation after reading will be described. The selector 1305 selects the read 16-bit data 16b output from the selector 1304 and outputs it to the 1ECC unit 1301. The 1ECC unit 1301 generates 5 bit parity 5p capable of correcting 1 bit error based on the 16 bit data 16b, and outputs the 16 bit data 16b and the 5 bit parity 5p to the write amplifier 305a. The write amplifier 305 a amplifies the 16-bit data 16 b and the 5-bit parity 5 p and outputs the amplified data to the first memory cell 201. In the first memory cell 201, 16-bit data 16b and 5-bit parity 5p are written according to the row address RA and the column address CA.

  When the power supply voltage is lower than the threshold, the voltage detection unit 207 outputs a voltage detection flag FLG indicating that the power supply voltage is low. In this case, the 4ECC unit 1302 generates 17-bit parity 17p that can correct the 16-bit data 16b and the 5-bit parity 5p output from the 1ECC unit 1301 by 4-bit error correction. In addition, the 4ECC unit 1307 generates a 12-bit parity 12p capable of 4-bit error correction based on the input column address CA (column address CAP) and the voltage detection flag FLG of the voltage detection unit 207. The selector 1303 selects the 17-bit parity 17p, the column address CAP, the voltage detection flag FLG, and the 12-bit parity 12p and outputs them to the write amplifier 305b. The write amplifier 305b amplifies the 17-bit parity 17p, the column address CAP and the voltage detection flag FLG and the 12-bit parity 12p, outputs the 17-bit parity 17p to the second memory cell 202, and outputs the column address CAP and the voltage detection flag. The FLG and its 12-bit parity 12p are output to the third memory cell 203. In the second memory cell 202, 17-bit parity 17p capable of 4-bit error correction is written according to the row address RA. In the third memory cell 203, the column address CAP, the voltage detection flag FLG indicating a low voltage, and its 12-bit parity 12p are written according to the row address RA.

  When the power supply voltage is higher than the threshold, the voltage detection unit 207 outputs a voltage detection flag FLG indicating that the power supply voltage is a standard voltage. In that case, the selector 1303 selects the read 17-bit parity 17p, the column address CAP, the voltage detection flag FLG, and the 12-bit parity 12p output from the sense amplifier 105b and outputs them to the write amplifier 305b. The write amplifier 305b amplifies the 17-bit parity 17p, the column address CAP, the voltage detection flag FLG, and the 12-bit parity 12p, outputs the amplified 17-bit parity 17p to the second memory cell 202, and amplifies the column address. The CAP and voltage detection flag FLG and its 12-bit parity 12p are output to the third memory cell 203. The second memory cell 202 is rewritten with 17-bit parity 17p. The third memory cell 203 is rewritten with the column address CAP, the voltage detection flag FLG, and its 12-bit parity 12p. As in the first embodiment, when the voltage detection flag FLG at the time of reading is a low voltage and the column address CAP at the time of reading is the same as the input column address CA, the third memory cell In 203, an initial value column address CAP, a voltage detection flag FLG indicating a standard voltage, and its 12-bit parity 12p are written.

(Fourth embodiment)
FIG. 14 is a diagram showing a configuration example of a part of the ferroelectric memory device according to the fourth embodiment. In the third embodiment, the second memory cell 202 stores 17-bit parity 17p. On the other hand, in the fourth embodiment, the second memory cell 202 stores 16-bit parity 16p. The 4ECC unit 1302 generates a 16-bit parity 16p that can correct a 4-bit error based on the 16-bit data 16b. That is, the 5-bit parity 5p is not subject to 4-bit error correction. Hereinafter, differences of the present embodiment from the third embodiment will be described. The 4-bit column address CAP and the 1-bit voltage detection flag FLG are written in the second memory cell 203 of 2T2C without the ECC 12-bit parity 12p, thereby taking measures against low voltage. The third memory cell 203 is a 2T2C type memory cell.

  First, a write operation and a rewrite operation will be described. The 1 ECC unit 1301 outputs the 16-bit data 16b and the 5-bit parity 5p to the write amplifier 305a, and outputs the 16-bit data 16b to the 4 ECC unit 1302. The 4ECC unit 1302 generates a 16-bit parity 16p that can correct a 4-bit error based on the 16-bit data 16b. The write amplifier 305 b amplifies the 16-bit parity 16 p and outputs it to the second memory cell 202. In the second memory cell 202, 16-bit parity 16p is written according to the row address RA. In the third memory cell 203, the column address CAP and the voltage detection flag FLG are written according to the row address RA.

  Next, the reading operation will be described. The second memory cell 202 outputs 16-bit parity 16p to the sense amplifier 105b according to the row address RA. The sense amplifier 105b amplifies the 16-bit parity 16p and outputs the amplified 16-bit parity 16p to the 4ECC unit 1302. The 4ECC unit 1302 uses the 16-bit parity 16p to error-correct the 16-bit data 16b, and outputs the error-corrected 16-bit data 16b to the selector 1304. The 4ECC unit 1302 may further correct the error-corrected 16-bit data 16b using the 5-bit parity 5p and output the error-corrected 16-bit data 16b to the selector 1304. The third memory cell 203 outputs the column address CAP and the voltage detection flag FLG to the sense amplifier 105d according to the row address RA. The sense amplifier 105d amplifies the column address CAP and the voltage detection flag FLG. The selector 1304 selects the 16-bit data 16b after error correction output by the 4ECC unit 1302 when the voltage detection flag FLG indicates a low voltage and the column address CAP is the same as the input column address CA. And output as read data. Further, when the voltage detection flag FLG indicates a standard voltage, or when the column address CAP is different from the input column address CA, the selector 1304 receives the 16-bit data 16b after error correction output from the 1ECC unit 1301. Select and output as read data.

  According to the present embodiment, since the 5-bit parity 5p is not subjected to 4-bit error correction, the number of bits of the 4-bit error correction information (16-bit parity 16p) can be reduced. Further, the column address CAP is added to the third memory cell 203 of the 5 bit 2T2C (10 cells in terms of 1T1C) type without adding the 4 ECC 12 bit parity 12p for the 4 bit column address CAP and the 1 bit voltage detection flag FLG. And the voltage detection flag FLG is written. According to the first to fourth embodiments, both high reliability of data storage and a small area can be achieved.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

101 Address latch 102 Row decoder 103 Column decoder 104 Memory cell array 105 Amplifier 106 Control unit 107 External terminal 201 First memory cell 202 Second memory cell 203 Third memory cell 207 Voltage detection unit

Claims (9)

A plurality of first memory cells each selected by a row address and a column address, each storing 1-bit data by one transistor and one capacitor;
A plurality of second memory cells selected by the row address, each storing 1-bit data with one transistor and one capacitor;
A plurality of third memory cells selected by the row address and storing a column address and a voltage detection bit indicating a standard voltage or a low voltage;
A voltage detector for detecting whether the power supply voltage is lower than a threshold;
When a write request to the first row address and the first column address is input, if the power supply voltage is lower than a threshold value, the first memory address selected by the first row address is stored in the first memory cell. A column address and a voltage detection bit indicating a low voltage are written, a first 1-bit data is written to a first memory cell selected by the first row address and the first column address, and the first row When the second 1-bit data of the logical inversion of the first 1-bit data is written into the second memory cell selected by the address, and the power supply voltage is higher than a threshold, the first row address is selected. Maintaining the column address and the voltage detection bit indicating the standard voltage stored in the third memory cell, the first row address and the first A controller that writes the first 1-bit data to the first memory cell selected by the column address and maintains the 1-bit data of the second memory cell selected by the first row address. A memory device. The controller is
When a read request from the first row address and the first column address is input, the voltage detection bit stored in the third memory cell selected by the first row address indicates a low voltage, When the column address stored in the third memory cell selected by the first row address is the same as the first column address, the first row address and the first row address The first 1-bit data stored in the first memory cell selected by the column address and the second 1-bit stored in the second memory cell selected by the first row address Read data based on data and output data
When the voltage detection bit stored in the third memory cell selected by the first row address indicates a standard voltage, or stored in the third memory cell selected by the first row address If the column address being set is different from the first column address, the first 1 stored in the first memory cell selected by the first row address and the first column address 2. The memory device according to claim 1, wherein read data is output based on the bit data. A plurality of first memory cells each selected by a row address and a column address, each storing 1-bit data by one transistor and one capacitor;
A plurality of second memory cells selected by the row address, each storing 1-bit data with one transistor and one capacitor;
A plurality of third memory cells selected by the row address and storing a column address and a voltage detection bit of a standard voltage or a low voltage;
When a read request from the first row address and the first column address is input, the voltage detection bit stored in the third memory cell selected by the first row address indicates a low voltage, and When the column address stored in the third memory cell selected by the first row address is the same as the first column address, the first row address and the first column address The logic of the first 1-bit data stored in the first memory cell selected by the first memory cell and the first 1-bit data stored in the second memory cell selected by the first row address Read data is output based on the inverted second 1-bit data, and stored in the third memory cell selected by the first row address. When the pressure detection bit indicates a standard voltage, or when the column address stored in the third memory cell selected by the first row address is different from the first column address, the first And a control section for outputting read data based on the first 1-bit data stored in the first memory cell selected by the row address and the first column address. apparatus. A plurality of first memory cells each selected by a row address and a column address, each storing 1-bit data by one transistor and one capacitor;
A plurality of second memory cells that are selected by the row address and each store complementary 2-bit data by two transistors and two capacitors;
A plurality of third memory cells selected by the row address and storing a column address and a voltage detection bit indicating a standard voltage or a low voltage;
A voltage detector for detecting whether the power supply voltage is lower than a threshold;
When a write request to the first row address and the first column address is input, if the power supply voltage is lower than a threshold value, the first memory address selected by the first row address is stored in the first memory cell. Write a column address and a voltage detection bit indicating a low voltage, write 1-bit data to a first memory cell selected by the first row address and the first column address, and select by the first row address When complementary 2-bit data is written in the second memory cell and the power supply voltage is higher than the threshold value, the column address stored in the third memory cell selected by the first row address and A voltage detection bit indicating a standard voltage is maintained, and a first memory selected by the first row address and the first column address is used. Writing 1-bit data in the cell, the memory device characterized by a control unit to maintain the 2-bit data of the second memory cells selected by said first row address. The controller is
When a read request from the first row address and the first column address is input, the voltage detection bit stored in the third memory cell selected by the first row address indicates a low voltage, When the column address stored in the third memory cell selected by the first row address is the same as the first column address, the first address selected by the first row address Read data is output based on the complementary 2-bit data stored in the two memory cells,
When the voltage detection bit stored in the third memory cell selected by the first row address indicates a standard voltage, or stored in the third memory cell selected by the first row address If the column address being set is different from the first column address, the 1-bit data stored in the first memory cell selected by the first row address and the first column address is stored. 5. The memory device according to claim 4, wherein read data is output based on the read data. A plurality of first memory cells each selected by a row address and a column address, each storing 1-bit data by one transistor and one capacitor;
A plurality of second memory cells that are selected by the row address and each store complementary 2-bit data by two transistors and two capacitors;
A plurality of third memory cells selected by the row address and storing a column address and a voltage detection bit of a standard voltage or a low voltage;
When a read request from the first row address and the first column address is input, the voltage detection bit stored in the third memory cell selected by the first row address indicates a low voltage, and If the column address stored in the third memory cell selected by the first row address is the same as the first column address, the second address selected by the first row address Read data is output based on the complementary 2-bit data stored in the memory cell, and the voltage detection bit stored in the third memory cell selected by the first row address has a standard voltage. Or the column address stored in the third memory cell selected by the first row address is the first column address. A controller that outputs read data based on the 1-bit data stored in the first memory cell selected by the first row address and the first column address, if different A memory device. A plurality of first memory cells selected by a row address and a column address and storing data and error correction information of a first number of bits;
A plurality of second memory cells selected by the row address and storing error correction information having a second number of bits greater than the first number of bits;
A plurality of third memory cells selected by the row address and storing a column address and a voltage detection bit indicating a standard voltage or a low voltage;
A voltage detector for detecting whether the power supply voltage is lower than a threshold;
When a write request to the first row address and the first column address is input, if the power supply voltage is lower than a threshold value, the first memory address selected by the first row address is stored in the first memory cell. Write a column address and a voltage detection bit indicating a low voltage, and write data and error correction information of the first number of bits to the first memory cell selected by the first row address and the first column address. The error correction information of the second number of bits is written in the second memory cell selected by the first row address, and when the power supply voltage is higher than a threshold value, it is selected by the first row address. Maintaining a column address and a voltage detection bit indicating a standard voltage stored in the third memory cell, the first row address and the first The data and the error correction information of the first number of bits are written in the first memory cell selected by the column address, and the second number of bits of the second memory cell selected by the first row address And a control unit for maintaining the error correction information.   Further, when a read request from the first row address and the first column address is input, the voltage detection bit stored in the third memory cell selected by the first row address has a low voltage. And the column address stored in the third memory cell selected by the first row address is the same as the first column address, the first row address and the first row address Data stored in a first memory cell selected by one column address and error correction information of the second number of bits stored in a second memory cell selected by the first row address The data is error-corrected based on the data, and the voltage detection bit stored in the third memory cell selected by the first row address is a standard. When the voltage indicates a voltage, or when the column address stored in the third memory cell selected by the first row address is different from the first column address, the first row address and the An error correction unit for correcting an error of the data based on the data stored in the first memory cell selected by the first column address and the error correction information of the first number of bits is provided. The memory device according to claim 7. A plurality of first memory cells selected by a row address and a column address and storing data and error correction information of a first number of bits;
A plurality of second memory cells selected by the row address and storing error correction information having a second number of bits greater than the first number of bits;
A plurality of third memory cells selected by the row address and storing a column address and a voltage detection bit of a standard voltage or a low voltage;
When a read request from the first row address and the first column address is input, the voltage detection bit stored in the third memory cell selected by the first row address indicates a low voltage, and When the column address stored in the third memory cell selected by the first row address is the same as the first column address, the first row address and the first column address And the error correction information of the second number of bits stored in the second memory cell selected by the first row address and the data stored in the first memory cell selected by the first row address. When data is error-corrected and the voltage detection bit stored in the third memory cell selected by the first row address indicates a standard voltage Alternatively, when the column address stored in the third memory cell selected by the first row address is different from the first column address, the first row address and the first column address And an error correction unit that corrects the error of the data based on the data stored in the first memory cell selected by the error correction information of the first number of bits.

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